Datasheet LTC1840 Datasheet (LINEAR TECHNOLOGY)

FEATURES

■

Two 8-Bit Current DACs

■

DACs Guaranteed Monotonic

■

Known IC State on Power-Up

■

Serial Interface Watchdog Timer with Disable

■

2-Wire Serial Interface Compatible with I2C
and SMBus

■

2 Programmable Fan Tachometer Interfaces

■

4 Programmable General Purpose I/Os

■

Small 16-Pin SSOP Package

■

Single 2.7V to 5.75V Supply Operation

■

Fault Output Signal

■

Status Register

■

Fan Blasting Function

■

Nine Addresses Using Two Programming Lines

U

APPLICATIO S

■

Servers

■

Desktop Computers

■

Power Supplies

■

Cooling Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

I2C is a trademark of Philips Electronics N.V.

TM

LTC1840

Dual Fan Controller

with 2-Wire Interface

U

DESCRIPTIO

The LTC®1840 is a fan controller with two 8-bit current
output DACs, two tachometer interfaces, and four general
purpose I/O (GPIO) pins. It operates from a single supply
with a range of 2.7V to 5.75V. A current output DAC is used
to control an external switching regulator, which controls
the fan speed. A current output DAC and tachometer allow
a controller to form a closed control loop on fan velocity.
The GPIO pins can be used as digital inputs or open drain
pull-down outputs.

The part features a simple 2-wire I2C and SMBus compat­ible serial interface that allows communication between
many devices. The interface includes a fault status register
that reflects the state of the part and which can be polled
to find the cause of a fault condition. Other operational
characteristics of the part, such as DAC output currents,
GPIO modes, and tachometer frequency, are also pro­grammed through the serial interface. Two address pins
provide nine possible device addresses.

The BLAST pin is provided to force the DAC output
currents to program the maximum regulator output
voltages through a single pin and gate the operation of the
serial access timer.

TYPICAL APPLICATIO

3.3V

3.3V

3.3V

130Ω

LED2

10k

TO

MASTER

3.3V

NC

130Ω

NC

LED1

ADDRESS = 1110010
(8 OTHERS POSSIBLE)

FAULT

SDA

SCL

A0

A1

GPI01

GPI02

V

CC

IDACOUTA

LTC1840

IDACOUTB

GND

U

Low Parts Count, High Efficiency Dual Fan Control

C

FB1

100pF

C

FB2

100pF

12V

RUN/SS

LTC1771

I

TH

V

FB

12V

RUN/SS

LTC1771

I

TH

V

FB

GND

GND

V

V

IN

SENSE

PGATE

IN

SENSE

PGATE

MODE

MODE

R

R

SENSE1

0.05Ω

SENSE2

0.05Ω

GPI04

BLAST

GPI03

TACHB

TACHA

+

10µF

SYSTEM
RESET

R
10k

R
10k

0.1µF

C1

C

C1

220pF

C2

C

C2

220pF

+

Si6447DQ

L1 47µH

UPS5817

+

Si6447DQ

L2 47µH

UPS5817

C

VIN1

22µF

R

FB1A

75k

+

R

FB1B

28k

2-NMB 6820PL-04W-B29-D50 FANS

1.1A NOM AT 12V

C

VIN2

22µF

R

FB2A

75k

+

R

FB2B

28k

C

OUT1

150µF

C

OUT2

150µF

FAN

FAN

3.3V

DC

10k

TACH

OUT

3.3V

DC

10k

TACH

OUT

1840 TA01

1840f

1

LTC1840

TOP VIEW

GN PACKAGE

16-LEAD PLASTIC SSOP

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

SCL

SDA

A1

A0
FAULT
GPIO1
GPIO2

GND

V

CC

I

DACOUTA

I

DACOUTB

BLAST
TACHB
TACHA
GPIO4
GPIO3

WW

W

ABSOLUTE AXI U RATI GS

U

UUW

PACKAGE/ORDER I FOR ATIO

(Note 1)

VCC to GND .................................................... –0.3 to 6V

A0, A1.............................................–0.3 to (V

I

DACOUTA

, I

DACOUTB

.............................

–0.3 to (V

+ 0.3V)

CC

+ 0.75V)

CC

All other pins ................................................. –0.3 to 6V

ORDER PART

NUMBER

LTC1840CGN
LTC1840IGN

Operating Temperature

LTC1840C ............................................... 0°C to 70°C

LTC1840I.............................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

GN PART

MARKING

Lead Temperature (Soldering, 10 sec).................. 300°C

1840

T

= 125°C, θJA = 110°C/W

JMAX

Consult LTC marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 3V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DACs

n Resolution 8 Bits
DNL Differential Nonlinearity V
INL Integral Nonlinearity V
ZSE Zero-Scale Error V

Output Voltage Rejection 1.1V< V
Output Voltage Rejection VCC = 5.75V, 1.1V < V

I

DACOUTA(FS),

I

DACOUTB(FS)

Power Supply

V

CC

I

CC

V

UVLO

V

UVHYS

Oscillator Performance

f

OSC

PSRR Supply Sensitivity 2.7V < VCC < 5.75V 0.1 0.5 %/V

GPIO Performance

I

O

V
V
V
I

LEAK

IL

IH

IHYST

Full-Scale Current Sinking 97 103 µA

Positive Supply Voltage ● 2.7 5.75 V
Supply Current VCC = 3V, A0 and A1 Floating 400 600 µA

UVLO/POR Voltage ● 2.1 2.4 2.69 V
UVLO/POR Voltage Hysteresis (Note 2) 20 90 160 mV

Oscillator Frequency ● 47 50 53 kHz

Output Current Sink V
Digital Input Low Voltage Internal Pull-Down Disabled ● 0.3V
Digital Input High Voltage Internal Pull-Down Disabled ● 0.7V
Input Hysteresis (Note 2) 50 mV
Leakage Internal Pull-Down Disabled ±1 µA

= 1.1V, Guaranteed Monotonic ● ±0.9 LSB

DACOUT

= 1.1V ± 4LSB

DACOUT

= 1.1V –0.2 0.1 2 µA

DACOUT

< 3.75V ±1LSB

DACOUT

< 6.5V ±2LSB

DACOUT

V

= 1.1V ● 95 105 µA

DACOUT

V

= 5V, A0 and A1 Floating 500 750 µA

CC

= 0.7V, Internal Pull-Down Enabled ● 10 mA

GPIOX

CC

1840I

CC

1840f

2

V
V

LTC1840

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 3V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Inputs SCL, SDA

V

IH

V

IL

V

LTH

I

LEAK

C

IN

Digital Output SDA

V

OL

Digital Output FAULT

V

OL

Digital Inputs TACHA, TACHB

V

IH

V

IL

I

LEAK

Digital Input BLAST

V

LTH

V

IHYST

I

LEAK

Address Inputs A0, A1

V

IH

V

IL

I

IN

Timing Characteristics

f

I2C

t

BUF

t

hD, STA

t

su, STA

t

su, STO

t

hD, DAT

t

su, DAT

t

LOW

t

HIGH

t

f

t

r

Note 1: Absolute Maximum Ratings are those values beyond
which the life of a device may be impaired.

Digital Input High Voltage ● 1.4 V
Digital Input Low Voltage ● 0.6 V
Logic Threshold Voltage (Note 2) 1 V
Digital Input Leakage VCC = 5V and 0V, VIN = GND to V

CC

±1 µA

Digital Input Capacitance (Note 2) 10 pF

Digital Output Low Voltage I

Digital Output Low Voltage I

Digital Input High Voltage ● 0.7V
Digital Input Low Voltage ● 0.3V
Digital Input Leakage VCC = 5V and 0V, VIN = GND to V

= 3mA ● 0.4 V

PULL-UP

= 1mA ● 0.4 V

PULL-UP

CC

CC

CC

±1 µA

Logic Threshold Voltage Measured on BLAST Falling Edge 0.95 1.0 1.05 V
Input Hysteresis (Note 2), Measured on Rising Edge 20 mV
Digital Input Leakage VCC = 5V and 0V, VIN = GND to V

Input High Voltage ● 0.9V

CC

CC

Input Low Voltage ● 0.1V

±1 µA

CC

Input Current AX Shorted to GND or VCC, VCC = 5V ±100 µA

I2C Operating Frequency (Note 2) 0 100 kHz
Bus Free Time Between (Note 2) 4.7 µs

Stop and Start Condition
Hold Time after (Repeated) (Note 2) 4 µs

Start Condition
Repeated Start Condition (Note 2) 4.7 µs

Setup Time
Stop Condition Setup Time (Note 2) 4 µs
Data Hold Time 300 ns
Data Setup Time (Note 2) 250 ns
Clock Low Period (Note 2) 4.7 µs
Clock High Period (Note 2) 4.0 µs
Clock, Data Fall Time (Note 2) 300 ns
Clock, Data Rise Time (Note 2) 1000 ns

Note 2: Guaranteed by design not subject to test.

V
V

V
V

1840f

3

LTC1840

V

DACOUT

(V)

I

DACOUT

(µA)

100.5

100.3

100.1

99.9

99.7

99.5

99.3

99.1

1840 G06

0

1

23456

TA = 25°C

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Temperature

Supply Current vs Supply Voltage

550

TA = 25°C

500

(µA)

CC

I

450

450

440

430

(µA)

420

CC

I

410

400

(VCC = 3V)

100.10

100.05

(µA)

100.00

DACOUT

I

99.95

I

Full Scale vs VCC,

DACOUT

V

DACOUT

TA = 25°C

= 1.1V

400

2.5

I

DACOUT

3.5

FS vs V

at VCC = 3V to 5V

120

TA = 25°C

100

80

(µA)

60

DACOUT

I

40

20

0

0

I

DACOUT

234

1

AC Supply Rejection at

Full Scale, VCC = 3V DC

20

TA = 25°C

VCC (V)

V

DACOUT

4.5

DACOUT

(V)

5.5

56

1840 G01

1840 G04

6.5

390

–50

I

DACOUT

02550

–25

TEMPERATURE (°C)

FS vs V

DACOUT

at VCC = 3V

100.10
TA = 25°C

100.05

100.00

99.95

(µA)

99.90

DACOUT

I

99.85

99.80

99.75

0.5

1.5 2.5 4.5
V

(V)

DACOUT

DAC Zero Scale Error at VCC = 3V,
V

10

DACOUT

= 1.1V

3.5

75 100

1840 G02

1840 G05

99.90

2.5

I

DACOUT

3.5

FS vs V

4.5

VCC (V)

DACOUT

at VCC = 5V

DAC DNL vs Code at VCC = 3V

0.2
TA = 25°C

5.5

6.5

1840 G03

15

(µA/V)

CC

10

/V

DACOUT

I

5

0

1

4

10
FREQUENCY (kHz)

100

1840 G07

1000

5

DAC ZSE (nA)

0

–50

–25 0

50 100 125

25 75

TEMPERATURE (°C)

1840 G08

0.1

0

DNL (LSB)

–0.1

–0.2

1

CODE

255

1840 G09

1840f

UW

TYPICAL PERFOR A CE CHARACTERISTICS

DAC INL at VCC = 3V

0.4
TA = 25°C

0.3

0.2

0.1

0

BEST FIT INL (LSB)

–0.1

–0.2

0

CODE

255

1840 G10

1.011

1.010

1.009

1.008

1.007

1.006

1.005

BLASTB THRESHOLD (V)

1.004

1.003

1.002

BLAST Falling Threshold
at VCC = 3V

–50 –25 25 75

0 100

TEMPERATURE (°C)

50

LTC1840

1840 G11

U

UU

PI FU CTIO S

SCL (Pin 1): Serial Clock Input. The 2-wire bus master
device clocks this pin at a frequency between 0kHz and
100kHz to enable serial bus communications. Data at the
SDA pin is shifted in or out on rising SCL edges. SCL has
a logic threshold of 1V and an external pull-up resistor or
current source is normally required.

SDA (Pin 2): Serial Data Input. This is a bidirectional data
pin which normally has an external pull-up resistor or
current source and can be pulled down by the open drain
device on the LTC1840 or by external devices. The master
controls SDA during addressing, the writing of data, and
read acknowledgment, while the LTC1840 controls SDA
when data is being read back and during write acknowl­edgment. SDA data is shifted in or out on rising SCL edges.
SDA has a logic threshold of 1V.

A1 (Pin 3): Three State Address Programming Input. This
pin can cause three different logic states internally, de­pending upon whether it is pulled to supply, pulled to
ground, or not connected (NC). Combined with the A0 pin,
this provides for nine different possible two-wire bus
addresses for the LTC1840 (see Table 1).

A0 (Pin 4): Three State Address Programming Input. See
A1.

FAULT (Pin 5): Fault Indicator Pull-Down Output. This pin
has an open drain pull-down that is used to signal various

fault conditions on the LTC1840. An external 10k pull-up
is recommended.

GPIO1, GPIO2, GPIO3, GPIO4 (Pins 6, 7, 9, 10): General
Purpose Inputs/Outputs. These pins can be used as digital
inputs with CMOS logic thresholds or digital outputs/LED
drivers with open drain pull-downs that can be pro­grammed to blink. GPIO pins can be programmed to
produce faults due to changes in their logic states, and
these faults can only be cleared by software or powering
the LTC1840 down. All GPIOs default to nonfaulting logic
inputs upon power-up and their functionality is changed
through the serial interface.

GND (Pin 8): Ground. Connect to analog ground plane.
TACHA (Pin 11): Tachometer Input A. This pin is a digital

input that is designed to interface to the tachometer output
from a 3-wire fan. Internal logic counts between rising
TACHA edges at serially programmable frequencies of
25kHz, 12.5kHz, 6.25kHz or 3.125kHz and the most re­cently completed count is stored in a register accessible
through the serial interface. The maximum count is 255
and the LTC1840 is programmable to produce faults when
a count exceeds this number. This pin has CMOS thresh­olds and the default conditions are to count at 3.125kHz
and to not produce faults.

TACHB (Pin 12): Tachometer Input B. See TACHA

1840f

5

LTC1840

U

UU

PI FU CTIO S

BLAST (Pin 13): Blast/Timer Function Input. This is a
multifunction digital input pin that controls blast and timer
operation. If this pin is in a logic high state at power-up or
is transitioned from high to low, it will “blast” the current
DAC outputs to full scale (100µA) no matter what their
previous state was and set a fault condition. In addition, if
BLAST is in a logic high state, the serial access timer is
active; this circuit measures time between serial commu­nications to the LTC1840 and forces a blast and trips a fault
if the part hasn’t been accessed for about 1.5 minutes. This
pin has a 1V logic threshold.

I

DACOUTB

(Pin 14): Current DAC Output B. This is a high

impedance output with a sinking current output of 0µA to

W

BLOCK DIAGRA

SCL

I

DACOUTAIDACOUTB

15

14 5 13

II

8-BIT

IDACs

1

FAULT

FAULT

DETECT

100µA. This current can be programmed to one of 256
values through the serial interface or it can be “blasted”
immediately to full scale using the BLAST pin or by the
serial access timer if it is enabled and the LTC1840 is not
accessed for about 1.5 minutes. This pin will maintain the
programmed current to a very tight tolerance from as low
as 1.1V to at least 0.75V above VCC. The current DAC is
guaranteed to be monotonic over its full 8-bit range.

I

DACOUTA

(Pin 15): Current DAC Output A. See I

DACOUTB

VCC (Pin 16): Positive Supply. This pin must be closely
decoupled to ground (pin 8). A 10µF tantalum and a 0.1µF
ceramic capacitor in parallel are recommended.

BLAST

GPIO1

6

SERIAL

INTERFACE

2

SDA

A1

3

4

A0

8

GND

UWW

TI I G DIAGRA

SDA

t

LOW

SCL

t

hD, STA

START

CONDITION

t

GPIO2

GPI/O

INTERFACE

8-BIT

COUNTER

REF

t

su, DAT

t

HIGH

r

OSC

t

hD, DAT

t

f

÷ 2, 4,

8, 16

TACHB

REPEATED START

CONDITION

12

COUNTER

TACHA

t

su, STA

8-BIT

11

t

hD, STA

t

su, STO

STOP

CONDITION

t

BUF

7

9

10

1840 BD

1840 TD01

START

CONDITION

GPIO3

GPIO4

1840f

6

OPERATIO

SDA

LTC1840

U

Typical 2-Wire Serial I2C or SMBus Transmission

SCL

CONDITION

S

START

ADDRESS ACK ACK ACKR/W

81-7 9 81-7 9 81-7 9

DATA DATA

Serial Interface

• Simple 2-wire interface

• Multiple devices on same bus

• Idle bus must have SDA and SCL lines high

• LTC1840 is read/write

• Master controls bus

• Devices listen for unique address that precedes data

The START and STOP Conditions

When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.

Acknowledge

The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge (LOW active)
generated by the slave lets the master know that the latest
byte of information was received. The acknowledge­related clock pulse is generated by the master. The trans­mitter master releases the SDA line (HIGH) during the
acknowledge clock pulse. The slave receiver must pull
down the SDA line during the acknowledge clock pulse so

P

STOP

1840 TD02

CONDITION

that it remains stable LOW during the HIGH period of this
clock pulse.

When a slave receiver doesn’t acknowledge the slave
address (for example, it’s unable to receive because it’s
performing some real-time function), the data line must be
left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer.

If a slave receiver acknowledges the slave address, but
some time later in the transfer cannot receive any more
data bytes, the master must again abort the transfer. This
is indicated by the slave generating the “not acknowledge”
on the first byte to follow. The slave leaves the data line
HIGH and the master generates the STOP condition.

Commands Supported

The LTC1840 supports read byte, write byte, read word
(the second data byte will be all ones) and write word (the
second data byte will be ignored) commands.

Data Transfer Timing for Write Commands

In order to help assure that bad data is not written into the
LTC1840, data from a write command is only stored after
a valid acknowledge has been performed. The part will
detect that SDA is low on the rising edge of SCL that marks
the end of the period in which the LTC1840 acknowledges
the data write and then latch the data during the following
SCL low period.

LTC1840 Write Byte Protocol

1

START 1 1 1 B4 B3 B2 B1 X X X X X R2 R1 R0

7

SLAVE

ADDRESS

11

WR ACK

S
0

0

88

REGISTER
ADDRESS

111

D7 D6 D5 D4 D3 D2 D1 D0

ACK

S

0

LTC1840 Read Byte Protocol

111 1

START 1 1 1 B4 B3 B2 B1 X X X X X R2 R1 R0

7

SLAVE

ADDRESS

WR ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP

S
0

8 8

REGISTER
ADDRESS

11

START 1 1 1 B4 B3 B2 B1

S
0

7

SLAVE

ADDRESS

ACK STOP

DATA
BYTE

111

ACK

RD

S
0

1

S

0

DATA
BYTE

M
10

1840 TD03

1840f

7

LTC1840

OPERATIO

U

LTC1840 Device Addressing

It is possible to configure the part to operate with any one
of nine separate addresses through the three state A0 and
A1 pins. Table 1 shows the correspondence of addresses
to the states of the pins:

Table 1. Device Addressing

LTC1840 2-Wire Bus Slave Address Bits

Device Address (B7,B6,B5 = 111)

A0 A1 B4 B3 B2 B1

LNC0000
NCH0001
NCNC0010

HNC0011

LL0100

HH0101

NCL0110

HL0111

LH1000

Register Addresses and Contents

Fault conditions are cleared by the action of writing to the
fault register, but the data byte from the write command is
not actually loaded into the register.

A TACHA/B FLT (fault) bit will be high if the corresponding
TACHA/B FLTEN bit in the status register has been set high
and the corresponding TACHA/B counter has overflowed
its maximum count of 255. These faults are latched
internally and must be cleared by writing to the fault
register or by setting TACHA/B FLTEN low. The fault will be
reasserted if the counter is still in overflow after a write to
the fault register. The TACH FLT bits power-up in the low
state.

The blast and timer bits become high after blasting and
serial access time-out events, respectively.

A high GPIOX FLT bit reflects that the GPIOX pin has
caused a fault condition; to do so, the pin must be enabled
as fault producing in the GPIO setup register (GPIOX

For the A0 and A1 lines, L refers to a grounded pin, H is a
pin shorted to VCC and NC is no connect. The pin voltage
will be set to approximately VCC/2 when not connected.
Bits B7, B6 and B5 of the address are hardwired to 111.

FLTEN set high) and the logic state of the pin must change
after the enable. The fault is latched internally and must be
cleared through software by writing to the fault register or
by setting GPIOX FLTEN low; a change in the state of the
GPIOX pin from its state at the point of the fault register

Table 2. LTC1840 Register Address and Contents

Register Register

Name Address Data Byte
(R/W) R2 R1 R0 D7 D6 D5 D4 D3 D2 D1 D0

FAULT 000 TACHA FLT TACHB FLT Blast Timer GPI04 FLT GPI03 FLT GPI02 FLT GPI01 FLT

(0) (0) (0) (0) (0) (0) (0) (0)

STATUS 001 TACHA FLTEN TACHB FLTEN DIV1 DIV0 *See Note 2

(0) (0) (0) (0) (0/1) (0) (0) (1)

DACA 010 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB

(0) (0) (0) (0) (0) (0) (0) (0)

DACB 011 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB

(0) (0) (0) (0) (0) (0) (0) (0)

TACHA 100 Cnt A7 Cnt A6 Cnt A5 Cnt A4 Cnt A3 Cnt A2 Cnt A1 Cnt A0

(1) (1) (1) (1) (1) (1) (1) (1)

TACHB 101 Cnt B7 Cnt B6 Cnt B5 Cnt B4 Cnt B3 Cnt B2 Cnt B1 Cnt B0

(1) (1) (1) (1) (1) (1) (1) (1)

GPIO Data 110 GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIO4 Reg GPIO3 Reg GPIO2 Reg GPIO1 Reg

(N/A) (N/A) (N/A) (N/A) (1) (1) (1) (1)

GPIO Setup 111 GPIO4 BLNK GPIO3 BLNK GPIO2 BLNK GPIO1 BLNK GPIO4 FLTEN GPIO3 FLTEN GPIO2 FLTEN GPIO1 FLTEN

(0) (0) (0) (0) (0) (0) (0) (0)

Note 1: Number in ( )signifies default bit status upon power-up.

being written will cause another fault to be signalled.

Note 2: State of bit depends on slave address used.

1840f

8

OPERATIO

LTC1840

U

DIV1 and DIV0 program the ratio by which the internal
50kHz oscillator frequency is divided down to produce the
tachometer clocks (2, 4, 8, or 16). The DIV bits power-up
low, which corresponds to a frequency division of 16. For
example, if DIV1 and DIV0 are both high, the divide ratio
is set to 2. If DIV1 is high and DIV0 is low, the divide ratio
is set to 4. If DIV1 is low and DIV0 is high, the divide ratio
is set to 8.

The TACHA and TACHB registers will be set to all ones
by a UVLO condition. The tach counters count between
rising edges on the TACHA and TACHB pins. If a counter
overflows its maximum count of 255, the latch holding the
count results is immediately set to 255 without waiting for
the next edge on its TACH pin. This is done so that a
suddenly stopped or locked rotor will be easily detectable
by reading its corresponding tach register; otherwise, the
register would merely hold the previous count and be
waiting for a tach signal edge that isn’t coming to update
the overflow count.

The GPIOX pin bits in the GPIO data register reflect the
logic state of the pin itself, while the GPIOX register bits
reflect the data that is stored in the register that controls
the gate of the internal pull-down for the pin. The logic
polarities of the GPIOX bits are the same as those of the
GPIOX pins assuming an appropriately sized pull-up resis­tor (for example, a 1 value for the GPIO1 register bit will
force the internal N-channel MOSFET pull-down to an off­state, resulting in a 1 value at the GPIO1 pin). For a GPIO
to be used as a digital input, the GPIOX register bit is set
high, which turns off the internal pull-down N-channel
MOSFET, and the state of the pin can be controlled
externally and read back via the GPIOX pin bit. The GPIO
register bits power-up in the high state.

The GPIOX BLNK bits in the GPIO setup register control
whether the internal pull-down on a GPIO shuts on and off
at about 1.5Hz when the GPIOX register bit is low, and the
GPIOX FLTEN bits control whether a GPIO pin can trigger
a fault condition by a change in state. The GPIO FLTEN and
GPIO BLNK bits power-up in the low state.

Serial Interface Example

In this example, an LTC1840 has both address pins open
(NC) and the output current of DACA will be programmed
to half of full-scale (50µA current sink).

Provide a start condition on the bus by pulling SDA from
high to low while SCL is high and then write the SDA bit
stream 1110010 to the part for the LTC1840 slave
address, followed by a 0 to indicate that a write operation
will follow. All SDA transitions must happen when SCL is
low, or a start or stop condition will be interpreted. The
LTC1840 will then pull the SDA line low during the next
SCL clock phase to indicate that it is responding to the
communication attempt. To write to the DACA output
register, write 00000010 to the LTC1840 and wait for the
LTC1840 to acknowledge again on the following SCL cycle
by pulling SDA low. Next, send the LTC1840 the value
indicating the DACA current; writing the SDA data stream
10000000 sets the DAC to sink 50µA. The LTC1840 will
then acknowledge a third time by pulling SDA low for the
next SCL cycle. Then the data will be written into the
internal DACA register and I
Now generate a stop condition by forcing SDA from low to
high while SCL is high.

Tachometer Interface Operation

It is common for fans to have tachometer outputs that
produce two pulses per blade revolution. The LTC1840
provides two inputs that interface to circuits that count
between rising edges on these pulses. The frequency at
which the counting is done is programmable via the serial
interface to 25kHz, 12.5kHz, 6.25kHz, and 3.125kHz,
equivalent to divide by 2, 4, 8, and 16 operations on the
internal 50kHz oscillator. The count values corresponding
to these two inputs can also be read via the serial interface.
The output registers storing these counts power-up to all
ones, and they will also be loaded with all ones whenever
a counter overflows between two rising edges to allow for
the detection of a suddenly stopped rotor. The part can
also be configured to produce a fault as soon as the
counter overflows. However, the default state is to not
produce such faults, so as to prevent unnecessary fault
conditions while the fan is spinning up at start-up.

Multiple fans with open drain tachometer output signals
can be connected to a single LTC1840 tachometer input in
a wired-OR fashion, as long as the fans are not active at the
same time. If the fans happen to be spinning simulta­neously, the counts in the tach registers will not be
meaningful.

DACOUTA

pin will sink 50µA.

1840f

9

LTC1840

OPERATIO

U

GPIO Operation

The GPIO circuits feature N-channel MOSFET open drain
pull-downs that can drive LEDs and readback circuitry to
allow the logic states of the GPIO pins to be accessed
through the serial interface. The circuits that read the logic
states of the pins have standard CMOS thresholds. The
user must take care to minimize the power dissipation in
the pull-downs. LEDs should have series resistors added
to limit current and to limit the voltage drop across the
internal pull-down if their forward drop is less than about
VCC minus 0.7V. The N-channel MOSFET pull-downs can
sink 10mA at 0.7V drop to drive LEDs. A series resistor is
usually required to limit LED current and the LTC1840
internal power dissipation. See Table 3 for resistor values.

Table 3. Recommended LED Resistor Values

Recommended

LED Current (mA) Series Resistor (Ω)

V

= 3V VCC = 5V

CC

11k3k
3 270 910
5 120 510

10 30 240

Note: LED forward voltage drop assumed to be 2V.

FAULT Operation

Normally, the FAULT pin internal pull-down is only en­abled if one of the fault bits in the fault register is high. But
it is also enabled if the part is shut down by the POR block
due to low VCC supply. This POR fault does not have a
corresponding fault register bit.

BLAST and Serial Interface Watchdog Timer
Operation

The BLAST pin is used to force the DAC output currents to
full value instantaneously and also to gate the operation of
the serial interface watchdog timer. A blast will occur if the
BLAST pin is high when the part comes out of POR or if
there is a high to low transition on BLAST after POR. The
threshold of the BLAST pin is about 1V, independent of
VCC. The serial interface watchdog timer, which will signal
a fault condition if the part has not been addressed via the
serial interface for about a minute and a half, is only active

if the BLAST pin is high. If neither blasts nor an active serial
interface watchdog timer are desired, this pin should be
tied to ground. If timer operation is desired without having
a blast occur at power-up, the pin should be pulled above
1V after the part’s supply has ramped up. The blast state
is cleared by writing to the fault register.

Current Output DAC Interface to Switching Regulator

The output of a current DAC is used to control the output
voltage of a switching regulator that powers a fan, which
determines the rotational speed of the fan. The resistor
divider from the output of the regulator to the feedback pin
to ground should be ratioed to give the minimum desired
voltage from the fan, which corresponds to the minimum
fan speed. The size of the resistor from the output to the
feedback pin is then chosen by dividing the difference
between the maximum and minimum desired fan voltages
by the nominal maximum current output of the DAC, which
is 100µA. The value of the resistor from the feedback pin
to ground is then derived from the divider ratio and the
resistor value just calculated.

For example, if the feedback pin of the regulator is at 1.25V
with respect to ground and the minimum desired fan
voltage is 5V, the top resistor in the divider should be
(5V – 1.25V)/1.25V = 3 times larger than the resistor from
the feedback node to ground. If the maximum desired fan
voltage is 12V, the top resistor value is then (12V – 5V)/
100µA = 69.8k, and the bottom resistor is 69.8k/3 = 23.2k.
See Figure 1.

If the feedback pin voltage of a regulator is lower than the

1.1V compliance voltage of either of the LTC1840’s cur­rent output DACs, the resistor from the regulator output to
the feedback pin can be divided into two resistors, giving
the DAC more room to operate. See Figure 2.

If more than one fan is controlled by one regulator output,
small differences in the actual rotational speeds of the fans
may result in audible beat frequencies, which can be very
annoying. To avoid this problem, the actual voltages
applied to the fans can be varied by adding resistors or
diodes in series with some of the fans, resulting in larger
differences between their rotational speeds and less
noticeable beating. See Figure 3.

10

1840f

OPERATIO

LTC1840

U

V

OUT

(5V TO 12V)

REGULATOR

R1

69.8k
I

DAC

V

FB

1.25V

FB

R2

23.2k

LTC1840*

I

DACOUTA

(I

DACOUTB

15(14)

*ADDITIONAL DETAILS
OMITTED FOR CLARITY

)

1840 F01

Figure 1. Feedback Divider for 1.25V Reference

V

OUT

FAN 1 FAN 2

FAN 1, FAN 2: NMB 6820PL-04W-B49-D50

Figure 3. Series Diode to Avoid Beat Frequencies

BYS10-25

V

OUT

(5V TO 12V)

REGULATOR

R3

69.8k
I

DAC

1.3V
R1

V

FB

10k

0.8V

FB

R2
15k

LTC1840*

I

DACOUTA

(I

DACOUTB

15(14)

*ADDITIONAL DETAILS
OMITTED FOR CLARITY

Figure 2. Feedback Divider for 0.8V Reference

1840 F03

)

1840 F02

PACKAGE DESCRIPTIO

0.007 – 0.0098
(0.178 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

U

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

16

0.229 – 0.244

(5.817 – 6.198)

12

0.015

± 0.004

(0.38 ± 0.10)

0° – 8° TYP

× 45°

0.053 – 0.068

(1.351 – 1.727)

0.008 – 0.012

(0.203 – 0.305)

0.189 – 0.196*
(4.801 – 4.978)

15

14

13

4

3

12 11 10

5

678

0.0250
(0.635)

9

0.150 – 0.157**

0.004 – 0.0098

(0.102 – 0.249)

BSC

GN16 (SSOP) 1098

0.009

(0.229)

REF

(3.810 – 3.988)

1840f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

11

LTC1840

TYPICAL APPLICATIO

U

Controlling Fan Pair with Automatic Blast Redundancy
and Fan Pair with Automatic Tach Muxing

12V

L1 = SUMIDA CDRH125-15OMC

, C

, = PANASONIC EEV-FC1C471P

C

IN

OUT

R1, R2 = 1% METAL FILM

3.3V

LTC1840

LTC1840

SCL

SDA

10k

FAULT

3.3V

10k

TO AUTOMATICALLY MUX TACHB BETWEEN THE

TWO PARALLEL FANS, SET GPIO2 TO BLINK

1

2

3

NC

130Ω

4

NC

LED1

5

6

-A-

7

8

ADDRESS = 1110010

(8 OTHERS POSSIBLE)

SCL

SDA

A1

A0

FAULT

GPIO1

GPIO2

GND

I

DACOUTA

I

DACOUTB

BLAST

TACHB

TACHA

GPIO4

GPIO3

V

CC

16

15

14

13

12

11

10

9

0.1µF

+

10µF

SYSTEM
RESET

10k

+ +

IN4148

TN0205A

+

C

IN1B

470µF

10k
CC1B
470pF

CF1B
100pF

C

IN1

470µF

10k
CC1
470pF

CF1
100pF

C

IN2B

470µF

LTC1625

1

EXTV

CC

2

SYNC

3

RUN/SS

4

FCB

5

I

B00ST

TH

CC2B

6

220pF

+

C

IN2

470µF

CC2
220pF

7

8

1

2

3

4

5

6

7

8

SGND

V

OSENSE

V

PROG

LTC1625

EXTV

SYNC

RUN/SS

FCB

I

TH

SGND

V

OSENSE

V

PROG

INTV

PGND

CC

B00ST

INTV

PGND

4.7k

16

V

IN

15

TK

14

SW

13

TG

CBB, 0.22µF

12

11

CMDSH-3

CC

10

BG

+

CV

CCB

9

4.7µF

4.7k

16

V

IN

15

TK

14

SW

13

TG

CB, 0.22µF

12

11

CMDSH-3

CC

10

BG

+

CV

9

CC

4.7µF

Si4410DY

L1B

15µH

MBRS140T3

Si4410DY

Si4410DY

L1

15µH

MBRS140T3

Si4410DY

CV

INB

0.1µF

CV

IN

0.1µF

(4.5V TO 12V)

R1

75k

R2

27k

R1B
75k

R2B
27k

C

OUT1

470µF

TP0101TS

TACH

OUT

TACH

OUT

3.3V

10k

1840 TA03

(4.5V TO 12V)

DC

DC

FAN

+

C

OUT1B

470µF
×2

3.3V

10k 10k

-A-

DC

+

×2

FAN

TACH
OUT

2- NMB 5920PL-04W-B29-D50 FANS

FAN

2- NMB 5910PL-04W-B59-D50 FANS

2.1A NOM AT 12V

BYS10-25

DC
FAN

TACH
OUT

2.2A NOM AT 12V

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and ThinSOT are trademarks of Linear Technology Corporation.

SENSE

Linear Technology Corporation

12

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

TM

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●

www.linear.com

LT/TP 0402 2K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2001

1840f