LINEAR TECHNOLOGY LTC1603 Technical data

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FEATURES

LTC1603

High Speed, 16-Bit, 250ksps

Sampling A/D Converter

with Shutdown

U

DESCRIPTIO

■

A Complete, 250ksps 16-Bit ADC

■

90dB S/(N+D) and –100dB THD (Typ)

■

Power Dissipation: 220mW (Typ)

■

Nap (7mW) and Sleep (10µW) Shutdown Modes

■

No Pipeline Delay

■

No Missing Codes over Temperature

■

Operates with Internal 15ppm/°C Reference
or External Reference

■

True Differential Inputs Reject Common Mode Noise

■

5MHz Full Power Bandwidth

■

±2.5V Bipolar Input Range

■

Pin Compatible with LTC1604 and LTC1608

■

36-Pin SSOP Package

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APPLICATIO S

■

Telecommunications

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

High Speed Data Acquisition

■

Spectrum Analysis

■

Imaging Systems

The LTC®1603 is a 250ksps, 16-bit sampling A/D con­verter that draws only 220mW from ±5V supplies. This
high performance device includes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel output. Two digitally selectable power shutdown
modes provide power savings for low power systems.

The LTC1603’s full-scale input range is ±2.5V. Outstand­ing AC performance includes 90dB S/(N+D) and –100dB
THD at a sample rate of 250ksps.

The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 15MHz
bandwidth. The 68dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.

The ADC has µP compatible,16-bit parallel output port.
There is no pipeline delay in conversion results. A separate
convert start input and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessors.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

+

47µF

DIFFERENTIAL

ANALOG INPUT

±2.5V

REFCOMP

4

1

A

2

A

U

IN

IN

3

V

+

–

2.2µF

REF

4.375V

1.75X

+

SAMPLING

–

AGND

10µF

16-BIT

ADC

5

+

36

AV

DDAVDD

AGND

6

10Ω

7.5k

AGND

10µF

5V

+ +

35

2.5V
REF

B15 TO B0

AGND

8

7

V

–5V

5V

SS

34

10µF

10

9

DVDDDGND

CONTROL

LOGIC

AND

TIMING

OUTPUT

BUFFERS

10µF

+

SHDN

CONVST

BUSY
OV

OGND

D15 TO D0

CS

RD

DD

33
32
31
30
27

29

28

16-BIT
PARALLEL
BUS

11 TO 26

1603 TA01

µP
CONTROL
LINES

+

10µF

5V OR
3V

1603f

1

LTC1603

WW

W

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ABSOLUTE MAXIMUM RATINGS

AVDD = DVDD = OVDD = V

Supply Voltage (VDD)................................................ 6V

Negative Supply Voltage (VSS) ............................... – 6V

Total Supply Voltage (VDD to VSS) .......................... 12V

Analog Input Voltage

(Note 3) .........................(VSS – 0.3V) to (VDD + 0.3V)

V

Voltage (Note 4) ................. –0.3V to (VDD + 0.3V)

REF

REFCOMP Voltage (Note 4) .........–0.3V to (VDD + 0.3V)

Digital Input Voltage (Note 4) ....................–0.3V to 10V

Digital Output Voltage.................. –0.3V to (VDD + 0.3V)

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC1603C .............................................. 0°C to 70°C

LTC1603I............................................ –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

(Notes 1, 2)

DD

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W

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PACKAGE/ORDER INFORMATION

TOP VIEW

+

A
A

V

REF

REFCOMP

AGND
AGND
AGND
AGND

DV

DGND

D15 (MSB)

D14
D13
D12
D11
D10

1

IN

–

2

IN

3
4
5
6
7
8
9

DD

10
11
12
13
14
15
16
17

D9

18

D8

36-LEAD PLASTIC SSOP

T

JMAX

G PACKAGE

= 125°C, θJA = 95°C/W

36

AV

DD

35

AV

DD

34

V

SS

33

SHDN

32

CS

31

CONV

30

RD

29

OV

DD

28

OGND

27

BUSY

26

D0

25

D1

24

D2

23

D3

22

D4

21

D5

20

D6

19

D7

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ORDER

PART NUMBER

LTC1603CG
LTC1603IG

U

CO

VERTER

CCHARA TERIST

temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 16 16 Bits
Integral Linearity Error (Note 7) ● ±1 ±3 LSB
Transition Noise (Note 8) 0.7 LSB
Offset Error (Note 9) ● ±0.05 ±0.125 %
Offset Tempco (Note 9) 0.5 ppm/°C
Full-Scale Error Internal Reference ±0.125 ±0.25 %

Full-Scale Tempco I

A

U

LOG

IA

U
PUT

The ● denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

IN

C

IN

t

ACQ

t

AP

t

jitter

CMRR Analog Input Common Mode Rejection Ratio –2.5V < (A

Analog Input Range (Note 2) 4.75 ≤ VDD ≤ 5.25V, –5.25 ≤ VSS ≤ –4.75V, ±2.5 V

Analog Input Leakage Current CS = High ● ±1 µA
Analog Input Capacitance Between Conversions 43 pF

Sample-and-Hold Acquisition Time 380 ns
Sample-and-Hold Acquisition Delay Time –1.5 ns
Sample-and-Hold Acquisition Delay Time Jitter 5 ps

The ● denotes the specifications which apply over the full operating

ICS

External Reference ±0.25 %

(Reference) = 0, Internal Reference ±15 ppm/°C

OUT

–

≤ (A

V

SS

+

, A

) ≤ AV

IN

IN

DD

During Conversions 5 pF

–

+

= A

IN

) < 2.5V 68 dB

IN

RMS

1603f

2

LTC1603

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DY A IC ACCURACY

otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/N Signal-to-Noise Ratio 5kHz Input Signal ● 87 90 dB

S/(N + D) Signal-to-(Noise + Distortion) Ratio 5kHz Input Signal 90 dB

THD Total Harmonic Distortion 5kHz Input Signal – 100 dB

Up to 5th Harmonic 100kHz Input Signal
SFDR Spurious Free Dynamic Range 100kHz Input Signal 96 dB
IMD Intermodulation Distortion f

Full Power Bandwidth 5 MHz

Full Linear Bandwidth (S/(N + D) ≥ 84dB 350 kHz

The ● denotes the specifications which apply over the full operating temperature range,

100kHz Input Signal 90 dB

100kHz Input Signal (Note 10)

= 29.37kHz, f

IN1

= 32.446kHz –88 dB

IN2

● 84 89 dB

● –94 –88 dB

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I TER AL REFERE CE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

V

Output Voltage I

REF

V

Output Tempco I

REF

V

Line Regulation 4.75 ≤ VDD ≤ 5.25V 0.01 LSB/V

REF

V

Output Resistance 0 ≤ I

REF

REFCOMP Output Voltage I

= 0 2.475 2.500 2.515 V

OUT

= 0 ±15 ppm/°C

OUT

–5.25V ≤ V

= 0 4.375 V

OUT

≤ –4.75V 0.01 LSB/V

SS

 ≤ 1mA 7.5 kΩ

OUT

(Note 5)

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DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

OZ

C

OZ

I

SOURCE

I

SINK

High Level Input Voltage VDD = 5.25V ● 2.4 V
Low Level Input Voltage VDD = 4.75V ● 0.8 V
Digital Input Current VIN = 0V to V
Digital Input Capacitance 5pF
High Level Output Voltage VDD = 4.75V, I

= 4.75V, I

V

DD

Low Level Output Voltage VDD = 4.75V, I

V

= 4.75V, I

DD

Hi-Z Output Leakage D15 to D0 V
Hi-Z Output Capacitance D15 to D0 CS High (Note 11) ● 15 pF
Output Source Current V
Output Sink Current V

OUT

OUT

OUT

DD

OUT
OUT

OUT
OUT

= 0V to VDD, CS High ● ±10 µA

= 0V –1 0 mA
= V

DD

The ● denotes the specifications which apply over the

● ±10 µA

= –10µA 4.5 V
= –400µA ● 4.0 V

= 160µA 0.05 V
= 1.6mA ● 0.10 0.4 V

10 mA

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3

LTC1603

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POWER REQUIRE E TS

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

V

SS

I

DD

I

SS

P

D

Positive Supply Voltage (Notes 12, 13) 4.75 5.25 V
Negative Supply Voltage (Note 12) –4.75 –5.25 V
Positive Supply Current CS = RD = 0V ● 18 30 mA

Nap Mode CS = 0V, SHDN = 0V 1.5 2.4 mA
Sleep Mode CS = 5V, SHDN = 0V 1 100 µA

Negative Supply Current CS = RD = 0V ● 26 40 mA

Nap Mode CS = 0V, SHDN = 0V 1 100 µA
Sleep Mode CS = 5V, SHDN = 0V 1 100 µA

Power Dissipation CS = RD = 0V ● 220 350 mW

Nap Mode CS = 0V, SHDN = 0V 7.5 12 mW
Sleep Mode CS = 5V, SHDN = 0V 0.01 1 mW

The ● denotes the specifications which apply over the full operating temperature

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SMPL(MAX)

t

CONV

t

ACQ

t

ACQ+CONV

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

Maximum Sampling Frequency ● 250 kHz
Conversion Time ● 2.2 3.3 3.8 µs
Acquisition Time (Note 11) ● 480 ns
Throughput Time (Acquisition + Conversion) ● 4 µs
CS to RD Setup Time (Notes 11, 12) ● 0ns
CS↓ to CONVST↓ Setup Time (Notes 11, 12) ● 10 ns
SHDN↓ to CS↑ Setup Time (Notes 11, 12) ● 10 ns
SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) 400 ns
CONVST Low Time (Note 12) ● 40 ns
CONVST to BUSY Delay CL = 25pF 36 ns

Data Ready Before BUSY↑ 60 ns

Delay Between Conversions (Note 12) ● 200 ns
Wait Time RD↓ After BUSY↑ (Note 12) ● –5 ns
Data Access Time After RD↓ CL = 25pF 40 50 ns

Bus Relinquish Time 50 60 ns

RD Low Time (Note 12) ● t
CONVST High Time (Note 12) ● 40 ns
Aperture Delay of Sample-and-Hold 2 ns

The ● denotes the specifications which apply over the full operating temperature

● 80 ns

● 32 ns

● 60 ns

CL = 100pF 45 60 ns

● 75 ns

LTC1603C
LTC1603I

● 70 ns

● 75 ns

10

ns

4

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TI I G CHARACTERISTICS

LTC1603

(Note 5)

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND

and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V

or above VDD, they

SS

will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.

Note 4: When these pin voltages are taken below V

, they will be clamped

SS

by internal diodes. This product can handle input currents greater than
100mA below V

Note 5: V

without latchup. These pins are not clamped to VDD.

SS

= 5V, VSS = –5V, f

DD

= 250kHz, and tr = tf = 5ns unless

SMPL

otherwise specified.
Note 6: Linearity, offset and full-scale specification apply for a single-

ended A

+

input with A

IN

–

grounded.

IN

Note 8: Typical RMS noise at the code transitions. See Figure 17 for
histogram.

Note 9: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.

Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).

Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns

high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.

Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.

UW

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity vs
Output Code

2.0

1.5

1.0

0.5

0.0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

–32768 –16384 0 16384 32767

CODE

1603 G11

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

DNL (LSB)

–0.4
–0.6
–0.8
–1.0

–32768 –16384 16384 32767

Differential Nonlinearity vs
Output Code

0

CODE

1603 G10

1603f

5

LTC1603

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PIN FUNCTIONS

+

A

(Pin 1): Positive Analog Input. The ADC converts the

IN

difference voltage between A
tial range of ±2.5V. A

–

A

is grounded.

IN

–

A

(Pin 2): Negative Analog Input. Can be grounded, tied

IN

IN

to a DC voltage or driven differentially with A

V

(Pin 3): 2.5V Reference Output. Bypass to AGND with

REF

2.2µF tantalum in parallel with 0.1µF ceramic.
REFCOMP (Pin 4): 4.375V Reference Compensation Pin.

Bypass to AGND with 47µF tantalum in parallel with 0.1µF
ceramic.

AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground
plane.

DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND
with 10µF tantalum in parallel with 0.1µF ceramic.

DGND (Pin 10): Digital Ground for Internal Logic. Tie to
analog ground plane.

D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
is the Most Significant Bit.

BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.

+

and A

IN

+

has a ±2.5V input range when

–

with a differen-

IN

+

.

IN

OGND (Pin 28): Digital Ground for Output Drivers.
OVDD (Pin 29): Digital Power Supply for Output Drivers.

Bypass to OGND with 10µF tantalum in parallel with 0.1µF
ceramic.

RD (Pin 30): Read Input. A logic low enables the output
drivers when CS is low.

CONVST (Pin 31): Conversion Start Signal. This active
low signal starts a conversion on its falling edge when CS
is low.

CS (Pin 32): The Chip Select Input. Must be low for the
ADC to recognize CONVST and RD inputs.

SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.

VSS (Pin 34): –5V Negative Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.

AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic.

AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic and
connect this pin to Pin 35 with a 10Ω resistor.

6

1603f

LTC1603

UU

FU CTIO AL BLOCK DIAGRA

1.75X

+

SAMPLING

–

AGND

10µF

16-BIT

ADC

AGND

5

47µF

DIFFERENTIAL

ANALOG INPUT

±2.5V

2.2µF

3

V

REF

REFCOMP

4

+

4.375V

+

A

1

IN

–

A

2

IN

W

+

AV

V

–5V

SS

34

10µF

5V

9

DV

DD

CONTROL

LOGIC

AND

TIMING

OUTPUT

BUFFERS

+

10µF

10
DGND

D15 TO D0

SHDN

CONVST

RD

BUSY
OV

OGND

CS

DD

33
32
31
30
27

29

28

16-BIT
PARALLEL
BUS

11 TO 26

1603 TA01

µP
CONTROL
LINES

5V OR

+

3V

10µF

10µF

5V

10Ω

AV

7.5k

AGND

35

DD

B15 TO B0

7

+ +

2.5V
REF

AGND

8

36

DD

6

TEST CIRCUITS

Load Circuits for Access Timing

1k

(A) Hi-Z TO VOH AND VOL TO V

C

Load Circuits for Output Float Delay

5V

1k

DNDN

L

(B) Hi-Z TO VOL AND VOH TO V

OH

C

L

OL

1603 TC01

1k

(A) VOH TO Hi-Z

C

L

5V

DNDN

(B) VOL TO Hi-Z

1k

C

1603 TC02

L

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7

LTC1603

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APPLICATIONS INFORMATION

CONVERSION DETAILS

The LTC1603 uses a successive approximation algorithm
and internal sample-and-hold circuit to convert an analog
signal to a 16-bit parallel output. The ADC is complete with
a sample-and-hold, a precision reference and an internal
clock. The control logic provides easy interface to micro­processors and DSPs. (Please refer to the Digital Interface
section for the data format.)

Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) resets. Once a conversion
cycle has begun it cannot be restarted.

During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the A
acquired during the acquire phase and the comparator
offset is nulled by the zeroing switches. In this acquire
phase, a duration of 480ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
transferring the differential analog input charge onto the

+

and A

IN

capacitors to ground,

SMPL

IN

–

inputs are

summing junctions. This input charge is successively
compared with the binary-weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the A

IN

+

and A

IN

–

input
charges. The SAR contents (a 16-bit data word) which
represent the difference of A

IN

+

and A

–

are loaded into

IN

the 16-bit output latches.

DIGITAL INTERFACE

The A/D converter is designed to interface with micropro­cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con­version.

Internal Clock

The A/D converter has an internal clock that runs the A/D
conversion. The internal clock is factory trimmed to achieve
a typical conversion time of 3.3µs and a maximum conver-
sion time of 3.8µs over the full temperature range. No
external adjustments are required. The guaranteed maxi­mum acquisition time is 480ns. In addition, a throughput
time (acquisition + conversion) of 4µs and a minimum
sampling rate of 250ksps are guaranteed.

A

IN

A

IN

8

C

HOLD

HOLD

–V

DAC

C

+C

–C

SMPL

SMPL

DAC

DAC

ZEROING SWITCHES

HOLD

HOLD

+

COMP

–

16

SAR

OUTPUT

LATCHES

D15

•

•

•
D0

1603 F01

SAMPLE

+

SAMPLE

–

+V

DAC

Figure 1. Simplified Block Diagram

3V Input/Output Compatible

The LTC1603 operates on ±5V supplies, which makes the
device easy to interface to 5V digital systems. This device
can also talk to 3V digital systems: the digital input pins
(SHDN, CS, CONVST and RD) of the LTC1603 recognize
3V or 5V inputs. The LTC1603 has a dedicated output
supply pin (OVDD) that controls the output swings of the
digital output pins (D0 to D15, BUSY) and allows the part
to talk to either 3V or 5V digital systems. The output is
two’s complement binary.

Power Shutdown

The LTC1603 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The Nap
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode all bias

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LTC1603

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APPLICATIONS INFORMATION

SHDN

t

3

CS

Figure 2a. Nap Mode to Sleep Mode Timing

SHDN

t

4

CONVST

Figure 2b. SHDN to CONVST Wake-Up Timing

CS

t

2

CONVST

t

1

RD

Figure 3. CS to CONVST Setup Timing

4

3

2

CHANGE IN DNL (LSB)

1

0

0

500 1000

Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion

t

CONV

CONVST LOW TIME, t

20001500

2500 3000

5

(ns)

1603 F02a

1603 F02b

1603 F03

t

ACQ

3500 4000

1603 F04

currents are shut down and only leakage current remains
(about 1µA). Wake-up time from Sleep mode is much
slower since the reference circuit must power up and
settle. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 160ms with the recommended 47µF
capacitor.

Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.

Timing and Control

Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.

We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in
Figures 5 and 6. A narrow low or high CONVST pulse
prevents the rising edge of the CONVST pulse from upset­ting the critical bit decisions during the conversion time.
Figure 4 shows the change of the differential nonlinearity
error versus the low time of the CONVST pulse. As shown,
if CONVST returns high early in the conversion (e.g.,
CONVST low time <500ns), accuracy is unaffected. Simi­larly, if CONVST returns high after the conversion is over
(e.g., CONVST low time >t

), accuracy is unaffected.

CONV

For best results, keep t5 less than 500ns or greater than
t

.

CONV

Figures 5 through 9 show several different modes of
operation. In modes 1a and 1b (Figures 5 and 6), CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.

In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are in

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9

LTC1603

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APPLICATIONS INFORMATION

t

CS = RD = 0

CONVST

BUSY

DATA

CS = RD = 0

CONVST

t

5

t

6

DATA (N – 1)

D15 TO D0

Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled

(CONVST = )

t

13

t

6

CONV

t

CONV

t

5

t

8

t

7

DATA N

D15 TO D0

t

8

t

6

DATA (N + 1)

D15 TO D0

1603 F05

BUSY

DATA

t

7

DATA (N – 1)

D15 TO D0

DATA N

D15 TO D0

Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled

(CONVST = )

t

CS = 0

CONVST

BUSY

RD

DATA

t

CONV

t

5

t

6

13

t

8

t

9

t

12

t

10

t

DATA N

D15 TO D0

11

DATA (N + 1)

D15 TO D0

1603 F06

1603 F07

10

Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD

1603f

LTC1603

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APPLICATIONS INFORMATION

10

t

t

CONV

DATA (N – 1)

D5 TO D0

Figure 8. Mode 2. Slow Memory Mode Timing

t

CONV

6

t

10

t

DATA (N – 1)

D15 TO D0

11

CS = 0

RD = CONVST

BUSY

DATA

RD = CONVST

CS = 0

BUSY

DATA

t

6

t

t

7

DATA N

D15 TO D0

t

8

t

11

DATA N

D15 TO D0

t

8

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

1603 F08

1603 F09

Figure 9. ROM Mode Timing

three-state until read by the MPU with the RD signal. Mode
2 can be used for operation with a shared data bus.

In slow memory and ROM modes (Figures 8 and 9) CS is
tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the com­bined CONVST-RD signal. Conversions are started by the
MPU or DSP (no external sample clock is needed).

In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (=CONVST) back
high and reads the new conversion data.

In ROM mode, the processor takes RD (=CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.

DIFFERENTIAL ANALOG INPUTS

Driving the Analog Inputs

The differential analog inputs of the LTC1603 are easy to
drive. The inputs may be driven differentially or as a single­ended input (i.e., the A

–

A

inputs are sampled at the same instant. Any un-

IN

–

input is grounded). The A

IN

IN

+

and

wanted signal that is common mode to both inputs will be
reduced by the common mode rejection of the sample­and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1603
inputs can be driven directly. As source impedance in­creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion

1603f

11

LTC1603

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APPLICATIONS INFORMATION

10

1

0.1

ACQUISITION TIME (µs)

0.01
1 10 100 1k 10k

SOURCE RESISTANCE (Ω)

1603 F10

Figure 10. t

starts (settling time must be 200ns for full throughput
rate).

Choosing an Input Amplifier

vs Source Resistance

ACQ

LT®1007: Low Noise Precision Amplifier. 2.7mA supply
current, ±5V to ±15V supplies, gain bandwidth product
8MHz, DC applications.

LT1097: Low Cost, Low Power Precision Amplifier. 300µA
supply current, ±5V to ±15V supplies, gain bandwidth
product 0.7MHz, DC applications.

LT1227: 140MHz Video Current Feedback Amplifier. 10mA
supply current, ±5V to ±15V supplies, low noise and low
distortion.

LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA sup­ply current, ±5V to ±15V supplies, good AC/DC specs.

LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA sup­ply current, good AC/DC specs.

LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback
Amplifiers. 6.3mA supply current per amplifier, good AC/
DC specs.

Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (< 100Ω) at the closed-loop band­width frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 15MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.

The best choice for an op amp to drive the LTC1603 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifi­cations are most critical and time domain applications
where DC accuracy and settling time are most critical.
The following

list is a summary of the op amps that are
suitable for driving the LTC1603. More detailed informa­tion is available in the Linear Technology databooks, the
LinearViewTM CD-ROM and on our web site at:
www.linear-tech. com.

Input Filtering

The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1603 noise and distortion. The small-signal band­width of the sample-and-hold circuit is 15MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 11 shows a 3000pF
capacitor from A

+

to ground and a 100Ω source resistor

IN

to limit the input bandwidth to 530kHz. The 3000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam­pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.

12

LinearView is a trademark of Linear Technology Corporation.

1603f

LTC1603

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APPLICATIONS INFORMATION

ANALOG INPUT

100Ω

3000pF

47µF

Figure 11. RC Input Filter

Input Range

The ±2.5V input range of the LTC1603 is optimized for low
noise and low distortion. Most op amps also perform well
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla­tion circuitry.

Some applications may require other input ranges. The
LTC1603 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.

1

2

3

4

5

+

A

IN

–

A

IN

LTC1603

V

REF

REFCOMP

AGND

1603 F11

R1

7.5k

BANDGAP

REFERENCE

LTC1603

1603 F12a

4.375V

2.500V

47µF

V

3

REFCOMP

4

AGND

5

REF

REFERENCE

R2

12k

R3

16k

AMP

Figure 12a. LTC1603 Reference Circuit

5V

V

IN

LT1019A-2.5

V

OUT

ANALOG

INPUT

+

1

+

A

IN

2

–

A

IN

3

V

REF

LTC1603

4

REFCOMP

0.1µF10µF

5

AGND

1603 F12b

Figure 12b. Using the LT1019-2.5 as an External Reference

Internal Reference

The LTC1603 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.500V. It is connected internally to a refer­ence amplifier and is available at V

(Pin 3) (see Figure

REF

12a). A 7.5k resistor is in series with the output so that it
can be easily overdriven by an external reference or other
circuitry (see Figure 12b). The reference amplifier gains
the voltage at the V

pin by 1.75 to create the required

REF

internal reference voltage. This provides buffering
between the V

pin and the high speed capacitive DAC.

REF

The reference amplifier compensation pin (REFCOMP,
Pin 4) must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 22µF or
greater. For the best noise performance a 47µF ceramic
or 47µF tantalum in parallel with a 0.1µF ceramic is
recommended.

The V

pin can be driven with a DAC or other means

REF

shown in Figure 13. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1603 reference amplifier will limit
the bandwidth and settling time of this circuit. A settling
time of 20ms should be allowed for after a reference
adjustment.

Differential Inputs

The LTC1603 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of A

IN

+

– A

–

independent of the

IN

common mode voltage (see Figure 15a). The common
mode rejection holds up to extremely high frequencies
(see Figure 14a). The only requirement is that both inputs

1603f

13

LTC1603

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APPLICATIONS INFORMATION

1

+

A

ANALOG INPUT

2V TO 2.7V

DIFFERENTIAL

LTC1450

Figure 13. Driving V

80

70

60

50

40

30

20

COMMON MODE REJECTION (dB)

10

0

1k

2V TO 2.7V

47µF

REF

10k 100k

INPUT FREQUENCY (Hz)

Figure 14a. CMRR vs Input Frequency

IN

2

–

A

IN

LTC1603

3

V

REF

4

REFCOMP

5

AGND

with a DAC

1603 G14a

1M

1603 F13

1
2

3

4

5

+

A

IN

–

A

IN

V

REF

LTC1603

REFCOMP

AGND

1603 F14b

±2.5V

ANALOG INPUT

0V TO
5V

+

–

10µF

Figure 14b. Selectable 0V to 5V or ±2.5V Input Range

Full-Scale and Offset Adjustment

Figure 15a shows the ideal input/output characteristics
for the LTC1603. The code transitions occur midway
between successive integer LSB values (i.e., –FS +

0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,
FS –

0.5LSB). The output is two’s complement binary with

1LSB = FS – (–FS)/65536 = 5V/65536 = 76.3µV.
In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 15b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the A

–

input. For zero offset error apply

IN

can not exceed the AVDD or VSS power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin­earity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
as the inputs approach either power supply rail, from 96dB
with a common mode of 0V to 86dB with a common mode
of 2.5V or –2.5V.

Differential inputs allow greater flexibility for accepting
different input ranges. Figure 14b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.

14

011...111

011...110

000...001

000...000

111...111

OUTPUT CODE

111...110

100...001

100...000

–(FS – 1LSB)

INPUT VOLTAGE (A

FS – 1LSB

+

–

– A

IN

)

IN

1603 F15a

Figure 15a. LTC1603 Transfer Characteristics

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APPLICATIONS INFORMATION

–5V

R8

50k

R5

R7

47k

50k

+

47µF

Figure 15b. Offset and Full-Scale Adjust Circuit

–38µV (i.e., –0.5LSB) at A

–

A

input by varying R8 until the output code flickers

IN

between 0000 0000 0000 0000 and 1111 1111 1111 1111.
For full-scale adjustment, an input voltage of 2.499886V
(FS/2 – 1.5LSBs) is applied to A
the output code flickers between 0111 1111 1111 1110
and 0111 1111 1111 1111.

BOARD LAYOUT AND GROUNDING

Wire wrap boards are not recommended for high resolu­tion or high speed A/D converters. To obtain the best
performance from the LTC1603, a printed circuit board
with ground plane is required. Layout should ensure that
digital and analog signal lines are separated as much as
possible. Particular care should be taken not to run any
digital track alongside an analog signal track or under­neath the ADC.The analog input should be screened by
AGND.

An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other
analog grounds should be connected to this single analog
ground point. The REFCOMP bypass capacitor and the
DVDD bypass capacitor should also be connected to this

R3

24k

R6
24k

0.1µF

ANALOG

INPUT

R4
100Ω

IN

+

1

+

A

IN

2

–

A

IN

LTC1603

3

V

REF

4

REFCOMP

5

AGND

and adjust the offset at the

+

and R7 is adjusted until

IN

1603 F15b

analog ground plane. No other digital grounds should be
connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active micropro­cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com­parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.

The LTC1603 has differential inputs to minimize noise
coupling. Common mode noise on the A
will be rejected by the input CMRR. The A
used as a ground sense for the A

IN

+

and A

IN

–

IN

+

input; the LTC1603
will hold and convert the difference voltage between A
and A

–

. The leads to A

IN

+

(Pin 1) and A

IN

–

(Pin 2) should

IN

–

leads

IN

input can be

+

IN

be kept as short as possible. In applications where this is
not possible, the A

IN

+

and A

–

traces should be run side

IN

by side to equalize coupling.

SUPPLY BYPASSING

High quality, low series resistance ceramic, 10µF or 47µF
bypass capacitors should be used at the VDD and REFCOMP
pins as shown in Figure 16 and in the Typical Application
on the first page of this data sheet. Surface mount ceramic
capacitors such as Murata GRM235Y5V106Z016 provide
excellent bypassing in a small board space. Alternatively,
10µF tantalum capacitors in parallel with 0.1µF ceramic
capacitors can be used. Bypass capacitors must be lo­cated as close to the pins as possible. The traces connect­ing the pins and the bypass capacitors must be kept short
and should be made as wide as possible.

1603f

15

LTC1603

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APPLICATIONS INFORMATION

1

+

A

IN

–

A

IN

ANALOG

INPUT

CIRCUITRY

V

REFCOMP

REF

+
–

3

2.2µF

AGND

4

5 TO 8234 29

47µF

Figure 16. Power Supply Grounding Practice

DC PERFORMANCE

The noise of an ADC can be evaluated in two ways: signal­to-noise raio (SNR) in frequency domain and histogram in
time domain. The LTC1603 excels in both. Figure 18a
demonstrates that the LTC1603 has an SNR of over 90dB
in frequency domain. The noise in the time domain histo­gram is the transition noise associated with a high resolu­tion ADC which can be measured with a fixed DC signal
applied to the input of the ADC. The resulting output codes
are collected over a large number of conversions. The
shape of the distribution of codes will give an indication of
the magnitude of the transition noise. In Figure 17 the
distribution of output codes is shown for a DC input that
has been digitized 4096 times. The distribution is Gaussian
and the RMS code transition noise is about 0.66LSB. This
corresponds to a noise level of 90.9dB relative to full scale.
Adding to that the theoretical 98dB of quantization error
for 16-bit ADC, the resultant corresponds to an SNR level
of 90.1dB which correlates very well to the frequency
domain measurements in DYNAMIC PERFORMANCE
section.

DYNAMIC PERFORMANCE

The LTC1603 has excellent high speed sampling capabil­ity. Fast fourier transform (FFT) test techniques are used
to test the ADC’s frequency response, distortions and
noise at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figures 18a and 18b
show typical LTC1603 FFT plots.

V

SS

10µF3610µF

LTC1603

DD

DIGITAL
SYSTEM

OV

DGNDAV

DV

AV

DD

35

10µF

DD

9

10µF

2500

2000

1500

COUNT

1000

500

0

OGND

DD

2810

10µF

1603 F16

–5–4–3 –2 –1 0 1 2 3 4 5

CODE

1603 F17

Figure 17. Histogram for 4096 Conversions

0

–20

–40

–60

–80

AMPLITUDE (dB)

–100

–120

–140

0

20 40 80 100 120

FREQUENCY (kHz)

60

f

= 250kHz

SAMPLE

= 9.959kHz

f

IN

SINAD = 90.2dB
THD = –103.2dB

1603 F18a

Figure 18a. This FFT of the LTC1603’s Conversion of a
Full-Scale 10kHz Sine Wave Shows Outstanding Response
with a Very Low Noise Floor When Sampling at 250ksps

16

1603f

LTC1603

FREQUENCY (Hz)

1k

EFFECTIVE BITS

SINAD (dB)

16

15

14

13

12

11

10

9

8

98

92

86

80

74

68

62

56

50

10k 100k 1M

1603 F19

U

WUU

APPLICATIONS INFORMATION

Signal-to-Noise Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 18a shows a typical spectral content
with a 250kHz sampling rate and a 5kHz input. The
dynamic performance is excellent for input frequencies up
to and beyond the Nyquist limit of 125kHz.

Effective Number of Bits

The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:

N = [S/(N + D) – 1.76]/6.02

where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 250kHz the LTC1603 maintains above 14 bits up to
the Nyquist input frequency of 125kHz (refer to Figure 19).

0

f

= 250kHz

SAMPLE

f

= 97.152kHz

IN

–20

SINAD = 89dB
THD = –96dB

–40

–60

–80

AMPLITUDE (dB)

–100

–120

–140

06020 40 80 100 120

FREQUENCY (kHz)

1603 F18b

Figure 18b. Even with Inputs at 100kHz, the LTC1603’s
Dymanic Linearity Remains Robust

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:

222 2

VVV Vn

+++

THD Log

=

20

234

V

1

...

where V1 is the RMS amplitude of the fundamental fre­quency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 20. The LTC1603 has good distortion
performance up to the Nyquist frequency and beyond.

Figure 19. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

–110

1k

10k

INPUT FREQUENCY (Hz)

100k 1M

THD
3RD

2ND

1603 F20

Figure 20. Distortion vs Input Frequency

17

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LTC1603

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APPLICATIONS INFORMATION

Intermodulation Distortion

If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.

If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func­tion can create distortion products at the sum and differ­ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,

0

–20

–40

–60

–80

AMPLITUDE (dB)

–100

–120

–140

020

Figure 21. Intermodulation Distortion Plot

40 60 120
FREQUENCY (kHz)

f

SAMPLE

= 29.3kHz

f

IN1

= 32.4kHz

f

IN2

80 100

= 250kHz

1603 F21

etc. For example, the 2nd order IMD terms include
(fa – fb). If the two input sine waves are equal in magni­tude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:

IMD fa fb Log

±

()

=±20

Amplitude

Amplitude at fa

at (fa fb)

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec­tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.

The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 84dB (13.66 effective bits).
The LTC1603 has been designed to optimize input band­width, allowing the ADC to undersample input signals with
frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.

18

1603f

PACKAGE DESCRIPTION

U

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

1.25 ±0.12

12.50 – 13.10*
(.492 – .516)

LTC1603

2526 22 21 20 19232427282930313233343536

7.8 – 8.2

0.42 ±0.03 0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60**
(.197 – .221)

0.09 – 0.25

(.0035 – .010)
NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

0.55 – 0.95

(.022 – .037)

MILLIMETERS

(INCHES)

0

5.3 – 5.7

° – 8°

12345678 9 10 11 12 14 15 16 17 1813

0.65

(.0256)

BSC

0.22 – 0.38

(.009 – .015)

7.40 – 8.20

(.291 – .323)

2.0

(.079)

0.05

(.002)

G36 SSOP 0802

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

1603f

19

LTC1603

TYPICAL APPLICATION

Using the LTC1603 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System

U

CH0

CH7

CH0

CH7

+

–

10µF

1.75X

16-BIT

SAMPLING

ADC

5

5V 10µF5V

10Ω

+

AV

DD

678

AV

7.5k

B15 TO B0

3536

DD

+ +

2.5V
REF

AGNDAGNDAGNDAGND

V

–5V

SS

34

10µF

9
DV

CONTROL

LOGIC

AND

TIMING

OUTPUT

BUFFERS

+

DD

10µF

10
DGND

D15 TO D0

SHDN

CONVST

BUSY

OV

OGND

LTC1603

1603 TA03

CS

RD

DD

33
32
31
30
27

29

28

16-BIT
PARALLEL
BUS

11 TO 26

µP
CONTROL
LINES

+

10µF

5V OR
3V

5V

LTC1391

1

+

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

LTC1391

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

D

GND

D

GND

OUT

D

CLK

OUT

D

CLK

V

D

V

IN

CS

V

D

V

IN

CS

2

3

4

5

6

7

8

+

1

–

2

3

4

5

6

7

8

–

+

16

+

15

14

–

13

12

11

10

9

5V

16

+

15

14

–

13

12

11

10

9

1µF

–5V

1µF

+

+

47µF

3000pF

1µF

–5V

3000pF

+

D

IN

µP
CONTROL

CS

LINES

CLK

4

1

2

2.2µF

3

V

REF

REFCOMP

4.375V

+

A

IN

–

A

IN

RELATED PARTS

SAMPLING ADCs

PART NUMBER DESCRIPTION COMMENTS

LTC1410 12-Bit, 1.25Msps, ±5V ADC 71.5dB SINAD at Nyquist, 150mW Dissipation
LTC1415 12-Bit, 1.25Msps, Single 5V ADC 55mW Power Dissipation, 72dB SINAD
LTC1418 14-Bit, 200ksps, Single 5V ADC 15mW, Serial/Para llel ±10V
LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LTC1604 16-Bit, 333ksps, ±5V ADC Pin Compatible with LTC1603
LTC1605 16-Bit, 100ksps, Single 5V ADC ±10V Inputs, 55mW, Byte or Parallel I/O
LTC1608 16-Bit, 500ksps, ±5V ADC Pin Compatible with LTC1603

DACs

PART NUMBER DESCRIPTION COMMENTS

LTC1592 16-Bit Serial SoftSpanTM DAC ±1LSB Max INL/DNL, Software-Selectable Output Spans
LTC1595 16-Bit Serial Multiplying I
LTC1596 16-Bit Serial Multiplying I
LTC1597 16-Bit Parallel, Multiplying DAC ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650 16-Bit Serial V

DAC Low Power, Low Gritch, 4-Quadrant Multiplication

OUT

SoftSpan is a trademark of Linear Technolology Corporation.

Linear Technology Corporation

20

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade

OUT

DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade

OUT

LT/TP 0503 1K • PRINTED IN USA

●

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 LINEAR TECHNOLOGY CORPORATION 2003

1603f