LINEAR TECHNOLOGY LTC1603 Technical data

查询LTC1597-1ACN供应商

FEATURES

LTC1603

High Speed, 16-Bit, 250ksps

Sampling A/D Converter

with Shutdown

U

DESCRIPTIO

■

A Complete, 250ksps 16-Bit ADC

■

90dB S/(N+D) and –100dB THD (Typ)

■

Power Dissipation: 220mW (Typ)

■

Nap (7mW) and Sleep (10µW) Shutdown Modes

■

No Pipeline Delay

■

No Missing Codes over Temperature

■

Operates with Internal 15ppm/°C Reference
or External Reference

■

True Differential Inputs Reject Common Mode Noise

■

5MHz Full Power Bandwidth

■

±2.5V Bipolar Input Range

■

Pin Compatible with LTC1604 and LTC1608

■

36-Pin SSOP Package

U

APPLICATIO S

■

Telecommunications

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

High Speed Data Acquisition

■

Spectrum Analysis

■

Imaging Systems

The LTC®1603 is a 250ksps, 16-bit sampling A/D con­verter that draws only 220mW from ±5V supplies. This
high performance device includes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel output. Two digitally selectable power shutdown
modes provide power savings for low power systems.

The LTC1603’s full-scale input range is ±2.5V. Outstand­ing AC performance includes 90dB S/(N+D) and –100dB
THD at a sample rate of 250ksps.

The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 15MHz
bandwidth. The 68dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.

The ADC has µP compatible,16-bit parallel output port.
There is no pipeline delay in conversion results. A separate
convert start input and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessors.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

+

47µF

DIFFERENTIAL

ANALOG INPUT

±2.5V

REFCOMP

4

1

A

2

A

U

IN

IN

3

V

+

–

2.2µF

REF

4.375V

1.75X

+

SAMPLING

–

AGND

10µF

16-BIT

ADC

5

+

36

AV

DDAVDD

AGND

6

10Ω

7.5k

AGND

10µF

5V

+ +

35

2.5V
REF

B15 TO B0

AGND

8

7

V

–5V

5V

SS

34

10µF

10

9

DVDDDGND

CONTROL

LOGIC

AND

TIMING

OUTPUT

BUFFERS

10µF

+

SHDN

CONVST

BUSY
OV

OGND

D15 TO D0

CS

RD

DD

33
32
31
30
27

29

28

16-BIT
PARALLEL
BUS

11 TO 26

1603 TA01

µP
CONTROL
LINES

+

10µF

5V OR
3V

1603f

1

LTC1603

WW

W

U

ABSOLUTE MAXIMUM RATINGS

AVDD = DVDD = OVDD = V

Supply Voltage (VDD)................................................ 6V

Negative Supply Voltage (VSS) ............................... – 6V

Total Supply Voltage (VDD to VSS) .......................... 12V

Analog Input Voltage

(Note 3) .........................(VSS – 0.3V) to (VDD + 0.3V)

V

Voltage (Note 4) ................. –0.3V to (VDD + 0.3V)

REF

REFCOMP Voltage (Note 4) .........–0.3V to (VDD + 0.3V)

Digital Input Voltage (Note 4) ....................–0.3V to 10V

Digital Output Voltage.................. –0.3V to (VDD + 0.3V)

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC1603C .............................................. 0°C to 70°C

LTC1603I............................................ –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

(Notes 1, 2)

DD

U

W

U

PACKAGE/ORDER INFORMATION

TOP VIEW

+

A
A

V

REF

REFCOMP

AGND
AGND
AGND
AGND

DV

DGND

D15 (MSB)

D14
D13
D12
D11
D10

1

IN

–

2

IN

3
4
5
6
7
8
9

DD

10
11
12
13
14
15
16
17

D9

18

D8

36-LEAD PLASTIC SSOP

T

JMAX

G PACKAGE

= 125°C, θJA = 95°C/W

36

AV

DD

35

AV

DD

34

V

SS

33

SHDN

32

CS

31

CONV

30

RD

29

OV

DD

28

OGND

27

BUSY

26

D0

25

D1

24

D2

23

D3

22

D4

21

D5

20

D6

19

D7

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ORDER

PART NUMBER

LTC1603CG
LTC1603IG

U

CO

VERTER

CCHARA TERIST

temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 16 16 Bits
Integral Linearity Error (Note 7) ● ±1 ±3 LSB
Transition Noise (Note 8) 0.7 LSB
Offset Error (Note 9) ● ±0.05 ±0.125 %
Offset Tempco (Note 9) 0.5 ppm/°C
Full-Scale Error Internal Reference ±0.125 ±0.25 %

Full-Scale Tempco I

A

U

LOG

IA

U
PUT

The ● denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

IN

C

IN

t

ACQ

t

AP

t

jitter

CMRR Analog Input Common Mode Rejection Ratio –2.5V < (A

Analog Input Range (Note 2) 4.75 ≤ VDD ≤ 5.25V, –5.25 ≤ VSS ≤ –4.75V, ±2.5 V

Analog Input Leakage Current CS = High ● ±1 µA
Analog Input Capacitance Between Conversions 43 pF

Sample-and-Hold Acquisition Time 380 ns
Sample-and-Hold Acquisition Delay Time –1.5 ns
Sample-and-Hold Acquisition Delay Time Jitter 5 ps

The ● denotes the specifications which apply over the full operating

ICS

External Reference ±0.25 %

(Reference) = 0, Internal Reference ±15 ppm/°C

OUT

–

≤ (A

V

SS

+

, A

) ≤ AV

IN

IN

DD

During Conversions 5 pF

–

+

= A

IN

) < 2.5V 68 dB

IN

RMS

1603f

2

LTC1603

UW

DY A IC ACCURACY

otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/N Signal-to-Noise Ratio 5kHz Input Signal ● 87 90 dB

S/(N + D) Signal-to-(Noise + Distortion) Ratio 5kHz Input Signal 90 dB

THD Total Harmonic Distortion 5kHz Input Signal – 100 dB

Up to 5th Harmonic 100kHz Input Signal
SFDR Spurious Free Dynamic Range 100kHz Input Signal 96 dB
IMD Intermodulation Distortion f

Full Power Bandwidth 5 MHz

Full Linear Bandwidth (S/(N + D) ≥ 84dB 350 kHz

The ● denotes the specifications which apply over the full operating temperature range,

100kHz Input Signal 90 dB

100kHz Input Signal (Note 10)

= 29.37kHz, f

IN1

= 32.446kHz –88 dB

IN2

● 84 89 dB

● –94 –88 dB

UU U

I TER AL REFERE CE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

V

Output Voltage I

REF

V

Output Tempco I

REF

V

Line Regulation 4.75 ≤ VDD ≤ 5.25V 0.01 LSB/V

REF

V

Output Resistance 0 ≤ I

REF

REFCOMP Output Voltage I

= 0 2.475 2.500 2.515 V

OUT

= 0 ±15 ppm/°C

OUT

–5.25V ≤ V

= 0 4.375 V

OUT

≤ –4.75V 0.01 LSB/V

SS

 ≤ 1mA 7.5 kΩ

OUT

(Note 5)

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

OZ

C

OZ

I

SOURCE

I

SINK

High Level Input Voltage VDD = 5.25V ● 2.4 V
Low Level Input Voltage VDD = 4.75V ● 0.8 V
Digital Input Current VIN = 0V to V
Digital Input Capacitance 5pF
High Level Output Voltage VDD = 4.75V, I

= 4.75V, I

V

DD

Low Level Output Voltage VDD = 4.75V, I

V

= 4.75V, I

DD

Hi-Z Output Leakage D15 to D0 V
Hi-Z Output Capacitance D15 to D0 CS High (Note 11) ● 15 pF
Output Source Current V
Output Sink Current V

OUT

OUT

OUT

DD

OUT
OUT

OUT
OUT

= 0V to VDD, CS High ● ±10 µA

= 0V –1 0 mA
= V

DD

The ● denotes the specifications which apply over the

● ±10 µA

= –10µA 4.5 V
= –400µA ● 4.0 V

= 160µA 0.05 V
= 1.6mA ● 0.10 0.4 V

10 mA

1603f

3

LTC1603

WU

POWER REQUIRE E TS

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

V

SS

I

DD

I

SS

P

D

Positive Supply Voltage (Notes 12, 13) 4.75 5.25 V
Negative Supply Voltage (Note 12) –4.75 –5.25 V
Positive Supply Current CS = RD = 0V ● 18 30 mA

Nap Mode CS = 0V, SHDN = 0V 1.5 2.4 mA
Sleep Mode CS = 5V, SHDN = 0V 1 100 µA

Negative Supply Current CS = RD = 0V ● 26 40 mA

Nap Mode CS = 0V, SHDN = 0V 1 100 µA
Sleep Mode CS = 5V, SHDN = 0V 1 100 µA

Power Dissipation CS = RD = 0V ● 220 350 mW

Nap Mode CS = 0V, SHDN = 0V 7.5 12 mW
Sleep Mode CS = 5V, SHDN = 0V 0.01 1 mW

The ● denotes the specifications which apply over the full operating temperature

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SMPL(MAX)

t

CONV

t

ACQ

t

ACQ+CONV

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

Maximum Sampling Frequency ● 250 kHz
Conversion Time ● 2.2 3.3 3.8 µs
Acquisition Time (Note 11) ● 480 ns
Throughput Time (Acquisition + Conversion) ● 4 µs
CS to RD Setup Time (Notes 11, 12) ● 0ns
CS↓ to CONVST↓ Setup Time (Notes 11, 12) ● 10 ns
SHDN↓ to CS↑ Setup Time (Notes 11, 12) ● 10 ns
SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) 400 ns
CONVST Low Time (Note 12) ● 40 ns
CONVST to BUSY Delay CL = 25pF 36 ns

Data Ready Before BUSY↑ 60 ns

Delay Between Conversions (Note 12) ● 200 ns
Wait Time RD↓ After BUSY↑ (Note 12) ● –5 ns
Data Access Time After RD↓ CL = 25pF 40 50 ns

Bus Relinquish Time 50 60 ns

RD Low Time (Note 12) ● t
CONVST High Time (Note 12) ● 40 ns
Aperture Delay of Sample-and-Hold 2 ns

The ● denotes the specifications which apply over the full operating temperature

● 80 ns

● 32 ns

● 60 ns

CL = 100pF 45 60 ns

● 75 ns

LTC1603C
LTC1603I

● 70 ns

● 75 ns

10

ns

4

1603f

UW

TI I G CHARACTERISTICS

LTC1603

(Note 5)

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND

and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V

or above VDD, they

SS

will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.

Note 4: When these pin voltages are taken below V

, they will be clamped

SS

by internal diodes. This product can handle input currents greater than
100mA below V

Note 5: V

without latchup. These pins are not clamped to VDD.

SS

= 5V, VSS = –5V, f

DD

= 250kHz, and tr = tf = 5ns unless

SMPL

otherwise specified.
Note 6: Linearity, offset and full-scale specification apply for a single-

ended A

+

input with A

IN

–

grounded.

IN

Note 8: Typical RMS noise at the code transitions. See Figure 17 for
histogram.

Note 9: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.

Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).

Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns

high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.

Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.

UW

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity vs
Output Code

2.0

1.5

1.0

0.5

0.0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

–32768 –16384 0 16384 32767

CODE

1603 G11

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

DNL (LSB)

–0.4
–0.6
–0.8
–1.0

–32768 –16384 16384 32767

Differential Nonlinearity vs
Output Code

0

CODE

1603 G10

1603f

5

LTC1603

UUU

PIN FUNCTIONS

+

A

(Pin 1): Positive Analog Input. The ADC converts the

IN

difference voltage between A
tial range of ±2.5V. A

–

A

is grounded.

IN

–

A

(Pin 2): Negative Analog Input. Can be grounded, tied

IN

IN

to a DC voltage or driven differentially with A

V

(Pin 3): 2.5V Reference Output. Bypass to AGND with

REF

2.2µF tantalum in parallel with 0.1µF ceramic.
REFCOMP (Pin 4): 4.375V Reference Compensation Pin.

Bypass to AGND with 47µF tantalum in parallel with 0.1µF
ceramic.

AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground
plane.

DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND
with 10µF tantalum in parallel with 0.1µF ceramic.

DGND (Pin 10): Digital Ground for Internal Logic. Tie to
analog ground plane.

D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
is the Most Significant Bit.

BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.

+

and A

IN

+

has a ±2.5V input range when

–

with a differen-

IN

+

.

IN

OGND (Pin 28): Digital Ground for Output Drivers.
OVDD (Pin 29): Digital Power Supply for Output Drivers.

Bypass to OGND with 10µF tantalum in parallel with 0.1µF
ceramic.

RD (Pin 30): Read Input. A logic low enables the output
drivers when CS is low.

CONVST (Pin 31): Conversion Start Signal. This active
low signal starts a conversion on its falling edge when CS
is low.

CS (Pin 32): The Chip Select Input. Must be low for the
ADC to recognize CONVST and RD inputs.

SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.

VSS (Pin 34): –5V Negative Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.

AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic.

AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic and
connect this pin to Pin 35 with a 10Ω resistor.

6

1603f