Datasheet LTC1588, LTC1589, LTC1592 Datasheet (LINEAR TECHNOLOGY)

with Programmable Output Range

FEATURES

■

Six Programmable Output Ranges

Unipolar Mode: 0V to 5V, 0V to 10V
Bipolar Mode: ±5V, ±10V, ±2.5V, –2.5V to 7.5V

■

1LSB Max DNL and INL Over the Industrial
Temperature Range

■

Glitch Impulse < 2nV-s

■

16-Lead SSOP Package

■

Power-On Reset to 0V

■

Asynchronous Clear to 0V for All Ranges

U

APPLICATIO S

■

Process Control and Industrial Automation

■

Precision Instrumentation

■

Direct Digital Waveform Generation

■

Software-Controlled Gain Adjustment

■

Automatic Test Equipment

LTC1588/LTC1589/LTC1592

12-/14-/16-Bit SoftSpan DACs

U

DESCRIPTIO

The LTC®1588/LTC1589/LTC1592 are serial input 12-/14­/16-bit multiplying current output DACs that operates
from a single 5V supply. These SoftSpanTM DACs can be
software-programmed for either unipolar or bipolar mode
through a 3-wire SPI interface. In either mode, the voltage
output range can also be software-programmed. Two
output ranges in unipolar mode and four output ranges in
bipolar mode are available.

INL and DNL are accurate to 1LSB over the industrial
temperature range in both unipolar and bipolar modes.
True 16-bit 4-quadrant multiplication is achieved with
on-chip four quadrant multiplication resistors. The
LTC1588/LTC1589/LTC1592 are available in a 16-lead
SSOP package.

These devices include an internal deglitcher circuit that
reduces the glitch impulse to less than 2nV-s (typ).

The asynchronous clear pin resets the LTC1588/LTC1589/
LTC1592 to 0V in unipolar or bipolar mode.

, LTC and LT are registered trademarks of Linear Technology Corporation.

SoftSpan is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

Programmable Output Range 16-Bit SoftSpan DAC

V

REF

5V

5

+

1/2 LT®1469

6

–

1

2

R

R1

9

5V

0.1µF

V

CC

14

CLR

13

CS/LD

12

SCK

11

SDI

10

SDO

COM

R1

16-BIT DAC WITH SPAN ADJUST

C2

150pF

R2

7

LTC1592

U

LTC1592 Integral Nonlinearity

1.0
V

= 5V

REF

0.8

ALL OUTPUT RANGES

0.6

0.4

3

15

16

R2

REF

4

R

R

FB

OFS

I

OUT1

I

OUT2

AGND

GND

1588992 TA01

C1
15pF

5

2

3

6
7
8

15V

8

–

1/2 LT1469

+

4

–15V

0.1µF

0.1µF

1

V

OUT

0.2

0
–0.2
–0.4
–0.6

INTEGRAL NONLINEARITY (LSB)

–0.8
–1.0

0

32768

16384

DIGITAL INPUT CODE

49152

65535

1588992 TA02

1588992fa

1

LTC1588/LTC1589/LTC1592

PACKAGE/ORDER I FOR ATIO

UU

W

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

VCC to AGND, GND ......................................–0.3V to 7V

AGND to GND .............................. –0.3V to (VCC + 0.3V)

GND to AGND .............................. –0.3V to (VCC + 0.3V)

R

to AGND, GND ................................ –0.3V to 12V

COM

REF to AGND, GND ................................................ ±15V

R

, RFB, R1, R2 to AGND, GND .......................... ±15V

OFS

Digital Inputs to AGND, GND ....... –0.3V to (VCC + 0.3V)

I

, I

OUT1

Maximum Junction Temperature .......................... 150°C

Operating Temperature Range

LTC1588C/LTC1589C/LTC1592C ........... 0°C to 70°C

LTC1588I/LTC1589I/LTC1592I........... –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

to AGND, GND.......... –0.3V to (VCC + 0.3V)

OUT2

ORDER PART

TOP VIEW

1

R

COM

2

R1

3

R

OFS

4

R

FB

5

I

OUT1

6

I

OUT2

7

AGND

8

GND

G PACKAGE

16-LEAD PLASTIC SSOP

T

= 150°C, θJA = 125°C/ W

JMAX

Consult LTC Marketing for parts specified with wider operating temperature ranges.

16

R2

15

REF

14

CLR

13

CS/LD

12

SCK

11

SDI

10

SDO

9

V

CC

NUMBER

LTC1588CG
LTC1588IG
LTC1589CG
LTC1589IG
LTC1592ACG
LTC1592AIG
LTC1592BCG
LTC1592BIG

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = T
VCC = 5V, V

SYMBOL PARAMETER CONDITIONS TEMPERATURE MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Accuracy

INL Integral (Notes 2, 3) TA = 25°C ±1 ±1 ±2 ±0.3 ±1LSB

DNL Differential Guaranteed T

GE Gain Error All Output Ranges TA = 25°C –0.20 ±3 –1.0 ±4–3±16 –2 ±16 LSB

BZE Bipolar Zero Error All Bipolar Ranges TA = 25°C ±1 ±2.5 ±10 ±5LSB

I

LKG

PSRR Power Supply VCC = 5V ±10% ● ±0.01±0.15 ±0.05 ±0.5 ±2 ±0.2 ±2 LSB/V

= 5V, I

REF

Resolution ● 12 14 16 16 Bits

Nonlinearity T

Nonlinearity Monotonic (Note 3)

Gain Temperature ∆Gain/∆Temperature ● 3 3 3 1 3 ppm/°C
Coefficient (Note 4)

I

Leakage (Note 5) TA = 25°C ±5 ±5 ±5 ±5nA

OUT1

Current T

Rejection

= AGND = GND = 0V.

OUT2

(Note 3) T

(Note 3) T

MIN

MIN

MIN

MIN

MIN

to T
to T

to T

to T

to T

MAX

MAX

MAX

MAX

MAX

LTC1588 LTC1589 LTC1592B LTC1592A

● ±1 ±1 ±2 ±0.4 ±1LSB

● ±1 ±1 ±1 ±0.2 ±1LSB

● –0.22 ±3 –1.3 ±6–4±24 –3 ±16 LSB

● ±1 ±4.0 ±16 ±8LSB

● ±15 ±15 ±15 ±15 nA

MIN

to T

MAX

,

2

1588992fa

LTC1588/LTC1589/LTC1592

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are TA = T

The ● denotes specifications which apply over the full operating

MIN

to T

, VCC = 5V, V

MAX

REF

= 5V, I

= AGND = GND = 0V.

OUT2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Input

R

REF

DAC Input Resistance (Unipolar) (Note 6) ● 5710 kΩ

R1, R2 R1, R2 Resistance (Notes 6, 11) ● 10 14 20 kΩ
R

OFS

R

FB

Offset Resistance (Bipolar) ±5V, ±10V, ±2.5V Ranges ● 10 14 20 kΩ

–2.5V to 7.5V Range

● 20 28 40 kΩ

Feedback Resistance (Unipolar) 5V Range ● 5710 kΩ

10V Range

● 10 14 20 kΩ

Feedback Resistance (Bipolar) ±5V and –2.5V to 7.5V Ranges ● 10 14 20 kΩ

±10V Range
±2.5V Range

● 20 28 40 kΩ

● 5710 kΩ

Analog Outputs (Note 4)

C

OUT

Output Capacitance (I

) DAC Load All 1s 160 pF

OUT1

DAC Load All 0s 100 pF

AC Performance (Note 4)

Settling Time 5V Range, 0V to 5V Step with LT1468 (Note 7) 2 µs
Midscale Glitch Impulse (Note 10) 2 nV-s
Multiplying Feedthrough Error V

= ±10V, 10kHz Sine Wave 1 mV

REF

P-P

THD Total Harmonic Distortion (Note 8) Multiplying –108 dB

Output Noise Voltage Density (Note 9) At I

OUT1

11 nV/√Hz

Digital Inputs

V

IH

V

IL

I

IN

C

IN

Digital Input High Voltage ● 2.4 V
Digital Input Low Voltage ● 0.8 V
Digital Input Current ● ±1 µA
Digital Input Capacitance VIN = 0V (Note 4) ● 8pF

Digital Outputs

V

OH

V

OL

Digital Output High Voltage IOH = 200µA ● 4V
Digital Output Low Voltage IOL = 1.6mA ● 0.4 V

Timing Characteristics

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

Serial Input Valid to SCK Setup Time ● 60 ns
Serial Input Valid to SCK Hold Time ● 0ns
SCK Pulse Width High ● 35 ns
SCK Pulse Width Low ● 35 ns
CS/LD Pulse High Width ● 360 ns
LSB SCK High to CS/LD High ● 35 ns
CS/LD Low to SCK High ● 0ns
SCK to SDO Propagation Delay C

= 50pF ● 20 180 ns

LOAD

SCK Low to CS/LD Low ● 35 ns
Clear Pulse Low Width ● 100 ns
CS/LD High to SCK Positive Edge ● 35 ns
SCK Frequency Non-Daisy Chain (Note 12) ● 14.2 MHz

Daisy Chain (Note 13) 4.1 MHz

1588992fa

3

LTC1588/LTC1589/LTC1592

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are TA = T

The ● denotes specifications which apply over the full operating

MIN

to T

, VCC = 5V, V

MAX

REF

= 5V, I

= AGND = GND = 0V.

OUT2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply

V

CC

I

CC

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale
(LTC1592). ±1LSB = ±0.006% of full scale = ±61.2ppm of full scale
(LTC1589). ±1LSB = 0.024% of full scale = ±244.8ppm of full scale
(LTC1588).

Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: I
Note 6: Typical temperature coefficient is 100ppm/°C.
Note 7: To 0.0015% for a full-scale change, measured from the falling

edge of LD for the LTC1592 only.
Note 8: REF = 6V

Supply Voltage ● 4.5 5 5.5 V
Supply Current, V

CC

Digital Inputs = 0V or V

CC

● 10 µA

Note 9: Calculation from en = √4kTRB where: k = Boltzmann constant
(1.38E-23 J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth
(Hz).

Note 10: Midscale transition code: 32767 to 32768 for the LTC1592, 8191
to 8192 for the LTC1589, 2047 to 2048 for the LTC1588.

Note 11: R1 and R2 are measured between R1 and R

, R2 and R

COM

COM

Note 12: If a continuous clock is used with data changing on the rising

, t2) will limit the maximum clock

1

with DAC register loaded to all 0s.

OUT1

edge of SCK, setup and hold time (t
frequency. If data changes on the falling edge of SCK then the setup time
will limit the maximum clock frequency to 8MHz (continuous 50% duty
cycle clock).

, t1) limit the

8

at 1kHz. DAC register loaded with all 1s. Output

RMS

Note 13: SDO propagation delay and SDI setup time (t
maximum clock frequency for daisy chaining.

.

amplifier = LT1468.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Midscale Glitch Impulse

40

USING AN LT1468

= 30pF

C

FEEDBACK

30

V

= 10V

REF

20

10

0

–10

OUTPUT VOLTAGE (mV)

–20

–30

–40

0

1nV-s TYPICAL

0.2 0.4 0.8

TIME (µs)

0.6

1.0

1588992 G03

Supply Current vs Input Voltage

5

VCC = 5V
ALL DIGITAL INPUTS
TIED TOGETHER

4

3

2

SUPPLY CURRENT (mA)

1

0

1

0

INPUT VOLTAGE (V)

3

2

4

(LTC1588/LTC1589/LTC1592)

Logic Threshold vs Supply Voltage

3.0

2.5

2.0

1.5

1.0

LOGIC THRESHOLD (V)

0.5

0

1588992 G09

5

0

234

1

SUPPLY VOLTAGE (V)

576

1588992 G10

4

1588992fa

LTC1588/LTC1589/LTC1592

UW

TYPICAL PERFOR A CE CHARACTERISTICS

(LTC1588)

Integral Nonlinearity Differential Nonlinearity

(LTC1589)

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

INTEGRAL NONLINEARITY (LSB)

–0.8
–1.0

800

0

DIGITAL INPUT CODE

2400 3200 4095

1600

1588992 G11

Integral Nonlinearity Differential Nonlinearity

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

INTEGRAL NONLINEARITY (LSB)

–0.8
–1.0

0

4112

8224 12336 16383

DIGITAL INPUT CODE

1588992 G13

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

DIFFERENTIAL NONLINEARITY (LSB)

–0.8
–1.0

0

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

DIFFERENTIAL NONLINEARITY (LSB)

–0.8
–1.0

0

800

1600

DIGITAL INPUT CODE

4112

8224 12336 16383

DIGITAL INPUT CODE

2400 3200 4095

1588992 G12

1588992 G14

(LTC1592)

Integral Nonlinearity (INL)

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

INTEGRAL NONLINEARITY (LSB)

–0.8
–1.0

0

16384

DIGITAL INPUT CODE

32768

49152

1588992 G01

65535

Differential Nonlinearity (DNL)

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

DIFFERENTIAL NONLINEARITY (LSB)

–0.8
–1.0

0

16384

32768

DIGITAL INPUT CODE

49152

65535

1588992 G02

Integral Nonlinearity
vs Reference Voltage
in Unipolar Mode

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

INTEGRAL NONLINEARITY (LSB)

–0.8
–1.0

–6

–4

–8 8

–10

–2

0

REFERENCE VOLTAGE (V)

2

4

6

10

1588992 G05

1588992fa

5

LTC1588/LTC1589/LTC1592

UW

TYPICAL PERFOR A CE CHARACTERISTICS

(LTC1592)

Integral Nonlinearity
vs Reference Voltage
in Bipolar Mode

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

INTEGRAL NONLINEARITY (LSB)

–0.8
–1.0

–6

–4

–8 8

–10

–2

0

REFERENCE VOLTAGE (V)

Differential Nonlinearity
vs Reference Voltage
in Bipolar Mode

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

DIFFERENTIAL NONLINEARITY (LSB)

–0.8
–1.0

–6

–4

–8 8

–10

–2

0

REFERENCE VOLTAGE (V)

Differential Nonlinearity
vs Reference Voltage
in Unipolar Mode

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

DIFFERENTIAL NONLINEARITY (LSB)

–0.8

2

4

6

10

1588992 G06

–1.0

–6

–4

–8 8

–10

–2

REFERENCE VOLTAGE (V)

2

4

6

0

10

1588992 G07

Full-Scale Settling Waveform

LD PULSE

5V/DIV

GATED

SETTLING

WAVEFORM

500µV/DIV

500ns/DIV

USING LT1468 OP AMP

= 20pF

C

2

4

6

10

1588992 G08

FEEDBACK

0V TO 10V STEP

1592 G04

U

UU

PI FU CTIO S

R

(Pin 1): Center Tap Point of the Two Bipolar Resis-

COM

tors R1 and R2. Normally tied to the inverting input of an
external amplifier. When these resistors are not used,
connect this pin to ground. The absolute maximum volt­age range on this pin is –0.3V to 12V.

R1 (Pin 2): Bipolar Resistor R1. The main reference input
V

, typically 5V. Accepts up to ±15V. Normally tied to

REF

R

(Pin 3) and the reference input voltage V

OFS

REF

(5V).

When not used connect this pin to ground.

6

R

(Pin 3): Bipolar Offset Network. This pin provides the

OFS

offset of the output voltage range for bipolar modes.
Accepts up to ±15V. Normally tied to R1 and the reference
input voltage V
driven from a different voltage than V

(5V). Alternatively, this pin may be

REF

.

REF

RFB (Pin 4): Feedback Network. Normally tied to the output
of the current to voltage converter op amp. Range limited
to ±15V.

1588992fa

LTC1588/LTC1589/LTC1592

U

UU

PI FU CTIO S

I

(Pin 5): True DAC Current Output. Tied to the

OUT1

inverting input of the current-to-voltage op amp.

I

(Pin 6): Complement of DAC Current Output. Nor-

OUT2

mally tied to AGND pin.
AGND (Pin 7): Analog Ground. Tie to the system’s analog

ground plane.
GND (Pin 8): Ground. Tie to the system’s analog ground

plane.
VCC (Pin 9): Positive Supply Input. 4.5V ≤ VCC ≥ 5.5V.

Requires a 0.1µF bypass capacitor to ground.
SDO (Pin 10): Serial Data Output. Data at this pin is shifted

out on the rising edge of SCK.
SDI (Pin 11): Serial Data Input.

U

U

FU CTIO TABLE

SCK (Pin 12): Serial Interface Clock. Data on the SDI pin
is shifted into the input shift register on rising edge of SCK.

CS/LD (Pin 13): Chip Select Input. When CS/LD is low,
SCK is enabled for shifting data into the input shift register.
When CS/LD is pulled high, SCK is disabled and the control
logic executes the control word (the first 4 bits of the input
data stream as shown in Table 1).

CLR (Pin 14): When CLR is taken to a logic low, it sets the
DAC output to 0V and all internal registers to zero code.

REF (Pin 15): DAC Reference Input. Typically 5V, accepts
up to ±15V.

R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC
reference input REF (Pin 15) and the output of the inverting
amplifier tied to R

COM

(Pin 1).

Table 1

Internal Register Status

COMMAND

EACH COMMAND IS EXECUTED

C0

C1

C2

C3

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

0

0

1

0

1

1

0

1

1

0

0

0

1

0

0

1

1

0

1

1

0

1

0

1

1

0

1

1

1

1

1

1

1

1

Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code.

Copy Data Word Dn in SReg to Buf1

1

Copy the Data in Buf1 to Buf2

0

Copy Data Word Dn in SReg to Buf1 and Buf2

1

Reserved (Do Not Use)

0

Reserved (Do Not Use)

1

Reserved (Do Not Use)

0

Reserved (Do Not Use)

1

Reserved (Do Not Use)

0

Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2

1

Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2

0

Set Range to ±5V. Copy Dn in SReg to Buf1 and Buf2

1

Set Range to ±10V. Copy Dn in SReg to Buf1 and Buf2

0

Set Range to ±2.5V. Copy Dn in SReg to Buf1 and Buf2

1

Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2

0

Reserved (Do Not Use)

1

No Operation

ON THE RISING EDGE OF CS/LD

OPERATION

SREG
DATA WORD
Dn IN INPUT

SHIFT REGISTER

Dn

X

Dn

Dn
Dn
Dn
Dn
Dn
Dn

X

BUF1

INPUT

BUFFER

Dn
Dn
Dn

Dn
Dn
Dn
Dn
Dn
Dn

No Change

(DAC OUTPUT)

No Change

No Change

BUF2

DAC

BUFFER

Dn
Dn

Dn
Dn
Dn
Dn
Dn
Dn

DAC

OUTPUT

RANGE

No Change
No Change
No Change

5V

10V

±5V

±10V

±2.5V

–2.5V to 7.5V

No Change

1588992fa

7

LTC1588/LTC1589/LTC1592

W

BLOCK DIAGRA

SDI

SCK

SDO

CS/LD

UWW

TI I G DIAGRA

SCK

SREG

24-BIT

SHIFT

REGISTER

8-BIT

SHIFT

REGISTER

12-/14-/16-BIT

DATA WORD

4 BIT

COMMAND

WORD

t

1

t

BUF2BUF1

BITS

BUFFER12/14/16

t

4

BITS

DECODER

BUFFER

t

3

Dn

2

1 2 23 24

12-/14-/16-BIT DAC12/14/16

SPAN ADJUST

1588992 BD

t

6

SDI

CS/LD

SDO

t

9

t

5

t

7

t

8

t

11

1588992 TD

8

1588992fa

U

OPERATIO

INPUT WORD (LTC1588)

COMMAND DON’T CARE DATA (12 BITS + 4 DON’T-CARE BITS)

LTC1588/LTC1589/LTC1592

C3

INPUT WORD (LTC1589)

C3

INPUT WORD (LTC1592)

C3

C1

C2

COMMAND DON’T CARE DATA (14 BITS + 2 DON’T-CARE BITS)

C1

C2

COMMAND DON’T CARE DATA (16 BITS)

C1

C2

C0

C0

C0

X

X

X

X

X

X

X

X

X

X

D11 D10 D9 D8

MSB

X

X

D13

MSB

MSB

D12

D11 D10 D9 D8

D12

D13D14D15

Serial Interface

When the CS/LD is brought to a logic low, the data on the
SDI input is loaded into the shift register on the rising edge
of the clock. A 4-bit command word (C3 C2 C1 C0),
followed by four “don’t care” bits and 16 data bits
(MSB-first) is the minimum loading sequence required for
the LTC1588/LTC1589/LTC1592. When the CS/LD is
brought to a logic high, the clock is disabled internally and
the command word is executed.

If no daisy-chaining is required, the input stream can be
24-bit wide as shown in Figure 1a. The first four bits are the
command word, followed by four “don’t care” bits, then a
16-bit data word. The last four bits (LSBs) of this 16-bit
data word are don’t cares for the LTC1588. For the
LTC1589, the last 2 bits of the 16-bit data word are don’t
cares.

D6

D7

D11 D10 D9 D8

D5 D4 D3 D2 D1

D6

D7

D5 D4 D3 D2 D1

D6

D7

D0 X XXX

LSB

D0 X X

LSB

D5 D4 D3 D2 D1

1588992 TD4

1588992 TD3

D0

LSB

1588992 TD2

clocked to all ICs, then the CS/LD signal is pulled high to
update all of them simultaneously.

Power-On Reset and Clear

When the power supply is first turned on, the LTC1588/
LTC1589/LTC1592 will power up in 5V unipolar mode (C3
C2 C1 C0 = 1000). All the internal registers are set to zeros
and the DAC is set to zero code.

The LTC1588/LTC1589/LTC1592 must first be pro­grammed in either unipolar or bipolar mode. There are six
operating modes available and can be software-pro­grammed by the command word. When a CLR signal is
brought to low, it clears all internal registers to zero. The
DAC output voltage goes to zero volts. If an update DAC
command (C3 C2 C1 C0 = 0001) is issued immediately
after the CLR signal, the DAC output remains at zero volts.

If daisy-chaining is required or the input needs to be
written in two 16-bit wide segments, then the input stream
must be 32-bit wide and the first 8 bits loaded are “don’t
care” bits. The remaining bits work the same as a 24-bit
stream which is described in the previous paragraph. The
output of the internal 32-bit shift register is available on the
SDO pin 32 clock cycles later.

Multiple LTC1588/LTC1589/LTC1592s may be daisy­chained together by connecting the SDO pin to the SDI pin
of the next IC. The clock and CS/LD signals should remain
common to all ICs in the daisy-chain. The serial data is

If a CLR signal is given within a 100ns interval immediately
after CS/LD goes high, the user should reload the output
range.

Output Range Programming

There are two output ranges available in unipolar mode
and four output ranges available in bipolar mode. See
Function Table for details. All output ranges are with re­spect to a 5V reference input. When changing the LTC1588/
LTC1589/LTC1592 to a new mode, the command word
and data are given at the same time (24 or 32 bit). When

1588992fa

9

LTC1588/LTC1589/LTC1592

U

OPERATIO

1588992 F01a

24

23

22

21

WORD

CURRENT

32-BIT INPUT

1588992 F01b

20

19

18

17

16

15

14

13

12

11

10

24-BIT DATA STREAM (CANNOT BE DAISY-CHAINED)

9

8

7

6

5

DATA WORD Dn

(RESERVED)

Figure 1a. LTC1592 24-Bit Load Sequence (Minimum Input Word)

4

3

2

C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3

1

CONTROL WORD DON’T CARE

LTC1589 SDI Data Word = 14-Bit Input Code + 2 Don’t Care Bits at LSB Positions

24 25 26 27 28 29 30 31 32

23

22

21

20

19

18

17

16

15

32-BIT DATA STREAM (CAN BE DAISY-CHAINED)

LTC1588 SDI Data Word = 12-Bit Input Code + 4 Don’t Care Bits at LSB Positions

14

13

12

11

10

C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX

9

8

7

6

5

C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX

CONTROL WORD DON’T CARE DATA WORD Dn

18

D14

4

t

2

t

17

t

1

t

SCK

PREVIOUS 32-BIT INPUT WORD

PREVIOUS D14PREVIOUS D15

3

8

t

D15

SDI

SDO

Figure 1b. LTC1592 32-Bit Load Sequence (Required for Daisy-Chain Operation)

LTC1589 SDI/SDO Data Word = 14-Bit Input Code + 2 Don’t Care Bits at LSB Positions

LTC1588 SDI/SDO Data Word = 12-Bit Input Code + 4 Don’t Care Bits at LSB Positions

10

CS/LD

SCK

SDI

CS/LD

4

3

2

1

SCK

SDI

DON’T CARE

SDO

1588992fa

OPERATIO

LTC1588/LTC1589/LTC1592

U

CS/LD goes high, the mode changes and the DAC output
goes to a value corresponding to the data code.

Examples using the LTC1592:

1. Using a 24-bit loading sequence, load the unipolar
range of 0V to 10V with the DAC output at zero volt:

a) CS/LD
b) Clock SDI = 1001 XXXX 0000 0000 0000 0000

c) CS/LD ; then V

2. Using a 24-bit loading sequence, load the bipolar range
of ±5V and the DAC output at zero volt:

a) CS/LD
b) Clock SDI = 1010 XXXX 1000 0000 0000 0000

c) CS/LD ; then V

= 0V

OUT

= 0V on the ±5V range

OUT

WUUU

APPLICATIO S I FOR ATIO

3. Using a 32-bit load sequence, load the bipolar range of

±10V with the DAC output voltage at 5V initially. Then
change the DAC output to –5V:

a) CS/LD
b) Clock SDI = XXXX XXXX 1011 XXXX 1100 0000 0000

0000

c) CS/LD ; then V
Next, the bipolar range of ±10V is retained and the DAC

output voltage is changed to V
a) CS/LD

b) Clock SDI = XXXX XXXX 0010 XXXX 0100 0000 0000

0000

c) CS/LD ; then V

= 5V on the ±10V range

OUT

= –5V:

OUT

= –5V on the ±10V range

OUT

Op Amp Selection

Because of the extremely high accuracy of the 16-bit
LTC1592, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.

Tables 2 and 3 contain equations for evaluating the effects
of op amp parameters on the LTC1592’s accuracy when
programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the INL, DNL,
unipolar offset, unipolar gain error, bipolar zero and bipo­lar gain error. Tables 2 and 3 can also be used to determine
the effects of op amp parameters on the LTC1589 and the
LTC1588. However, the results obtained from Tables 2
and 3 are in 16-bit LSBs. Divide these results by 4
(LTC1589) and 16 (LTC1588) to obtain the correct LSB
sizing.

Table 4 contains a partial list of LTC precision op amps
recommended for use with the LTC1592. The easy-to-use
design equations simplify the selection of op amps to meet
the system’s specified error budget. Select the amplifier
from Table 4 and insert the specified op amp parameters
in Table 3. Add up all the errors for each category to
determine the effect the op amp has on the accuracy of the
LTC1592. Arithmetic summation gives an (unlikely) worst­case effect. A root-sum-square (RMS) summation pro­duces a more realistic estimate.

Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on INL and DNL. For the
LTC1592, a 250µV op amp offset will cause about 0.65LSB
INL degradation and 0.15LSB DNL degradation with a 10V
full-scale range (20V range in bipolar). For the LTC1592
programmed in a unipolar mode, the same 250µV op amp
offset will cause a 3.3LSB zero-scale error and a 3.3LSB
gain error with a 10V full-scale range.

1588992fa

11

LTC1588/LTC1589/LTC1592

WUUU

APPLICATIO S I FOR ATIO

While not directly addressed by the simple equations in
Tables 2 and 3, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp’s data sheet to find the worst-case VOS and I
over temperature. Then, plug these numbers in the V
and IB equations from Table 3 and calculate the tempera­ture induced effects.

For applications where fast settling time is important, Appli­cation Note 74, entitled “

Component and Measurement

Advances Ensure 16-Bit DAC Settling Time

ough discussion of 16-bit DAC settling time and op amp
selection.

B

Precision Voltage Reference Considerations

OS

Much in the same way selecting an operational amplifier
for use with the LTC1592 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC1592
is directly affected by the voltage reference; thus, any

Table 2. Variables for Each Output Range That Adjust the
Equations in Table 3

OUTPUT RANGE A1 A2 A3 A4 A5

5V 1.1 2 1

10V 2.2 3 1.5

±5V 2 2 1.2 1 1.5

±10V 4 4 1.2 1 2.5

±2.5V 1 1 1.6 1 1

–2.5V to 7.5V 1.9 3 1 0.5 1.5

Table 3. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges

OP AMP

V

OS1

I

B1

A

VOL1

V

OS2

I

B2

A

VOL2

(mV)

(nA)

(V/V)

(mV)

(mV)

(V/V)

INL (LSB)

V

OS1

• 0.0003 •

I

B1

A1 •

0

0

0

DNL (LSB)

5V

• 2.4 •

()

V

()

V

16.5k

()

A

VOL1

REF

5V

REF

V

OS1

• 0.00008 •

I

B1

A2 •

0

0

0

5V

• 0.6 •

()

V

REF

5V

()

V

REF

1.5k

()

A

VOL1

UNIPOLAR

OFFSET (LSB)

V

• 13.2 •

OS1

• 0.13 •

I

B1

0

0

0

0

voltage reference error will appear as a DAC output voltage
error.

There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit applica­tions: output voltage initial tolerance, output voltage tem­perature coefficient and output voltage noise.

Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference

BIPOLAR ZERO

ERROR (LSB)

5V

V
5V

REF

REF

A3 • V

A4 • V

A4 • I

()

()

V

• 19.8 •

OS1

• 0.01 •

I

B1

0

OS2

()

• 0.05 •

B2

()

A4 •

()

V

5V

()

V

REF

• 13.1 •

()

V
5V

()

V

REF

66k

()

A

VOL2

5V

REF

I

5V

REF

UNIPOLAR GAIN

V

OS1

B1

V

OS2

I

,” offers a thor-

BIPOLAR GAIN

I

V

B1

V

ERROR (LSB)

• 13.2 •

OS1

• 0.0018 •

A5 •

• 26.2 •

OS2

I

• 0.1 •

B2

()

5V

()

V

REF

5V

()

V

REF

131k

()

A

VOL1

5V

()

V

REF

5V

()

V

REF

131k

A

VOL2

ERROR (LSB)

• 13.2 •

• 0.0018 •

A5 •

• 26.2 •

• 0.1 •

B2

()

5V

()

V

REF

5V

()

V

REF

131k

()

A

VOL1

5V

()

V

REF

5V

()

V

REF

131k

A

VOL2

Table 4. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC1588/LTC1589/LTC1592,
with Relevant Specifications

AMPLIFIER SPECIFICATIONS

VOLTAGE CURRENT SLEW GAIN BANDWIDTH t

V

AMPLIFIER µV nA V/mV nV/√Hz pA/√Hz V/µs MHz µsmW

LT1001 25 2 800 10 0.12 0.25 0.8 120 46
LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11
LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp
LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp
LT1468 75 10 5000 5 0.6 22 90 2.5 117
LT1469 (Dual) 125 10 2000 5 0.6 22 90 2.5 123/Op Amp

OS

I

B

A

OL

NOISE NOISE RATE PRODUCT with LTC1592 DISSIPATION

SETTLING

POWER

1588992fa

12

WUUU

APPLICATIO S I FOR ATIO

LTC1588/LTC1589/LTC1592

with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the refer­ence; however, a calibration sequence that corrects for
system zero- and full-scale error is always recommended.

A reference’s output voltage temperature coefficient af­fects not only the full-scale error, but can also affect the
circuit’s INL and DNL performance. If a reference is
chosen with a loose output voltage temperature coeffi­cient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient condi­tions. Minimizing the error due to reference temperature
coefficient can be achieved by choosing a precision
reference with a low output voltage temperature coeffi­cient and/or tightly controlling the ambient temperature
of the circuit to minimize temperature gradients.

As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib­ute a dominant share of the system’s noise floor. This in
turn can degrade system dynamic range and signal-to­noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practical
for the system resolution desired. Precision voltage refer­ences, like the LT1236, produce low output noise in the

0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V

or 10V full-scale systems. However, as the circuit band­widths increase, filtering the output of the reference may
be required to minimize output noise.

Table 5. Partial List of LTC Precision References Recommended
for Use with the LTC1588/LTC1589/LTC1592 with Relevant
Specifications

INITIAL TEMPERATURE 0.1Hz to 10Hz

REFERENCE TOLERANCE DRIFT NOISE

LT1019A-5, ±0.05% 5ppm/°C12µV
LT1019A-10

LT1236A-5, ±0.05% 5ppm/°C3µV
LT1236A-10

LT1460A-5, ±0.075% 10ppm/°C20µV
LT1460A-10

LT1790A-2.5 ±0.05% 10ppm/°C12µV

P-P

P-P

P-P

P-P

Grounding

As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding techniques should be used. I

must be tied

OUT2

to the star ground with as low a resistance as possible.
When it is not possible to locate star ground close to I

OUT2

,
a low resistance trace should be used to route this pin to
star ground. This minimizes the voltage drop from this pin
to ground caused by the code dependent current flowing
to ground. When the resistance of this circuit board trace
becomes greater than 1Ω, a force/sense amplified con­figuration should be used to drive this pin (see Figure 2).
This preserves the excellent accuracy (1LSB INL and DNL)
of the LTC1588/LTC1589/LTC1592.

An Isolated 16-Bit Subsystem Using the LTC1592

The circuit in Figure 4 is a complete example of an optically
isolated analog output subsystem that supports most of
the legacy ranges that are still common in industrial
environments. This circuit uses only two optoisolators,
the load pulse (CS/LD) being derived from a series of
transitions on the data line (SDI) after the clock (SCK) is
halted high. If a single chip microcontroller with an auto­mated SPI interface is to be used, the SPI port can transfer
the 24 bits as three bytes. Subsequently, the data output
port pin can be reassigned to general purpose port opera­tion and exercised to produce a number of transitions to
generate the load pulse. Alternatively, the entire sequence
can be programmed bit by bit with a general purpose port.
Figure 5 shows the timing.

The DC/DC converter, Figure 3 based on the LT®3439
ultralow noise transformer driver provides a compact
means of powering this circuit, and allows the output to
deliver output current that is only limited by the LT1468
capabilities. The output capability of the DC/DC converter
itself is 80mA at ±12V and is available as demo board
DC511A. This circuit as shown requires approximately
130mA of the 5V supply (no load). The total surface area
required is less than 2 square inches.

1588992fa

13

LTC1588/LTC1589/LTC1592

WUUU

APPLICATIO S I FOR ATIO

ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE

6

I

OUT2

ZETEX

BAT54S

V

REF

5V

1

23

6

LT1468

5

6

–

2

3

+

+

1/2 LT1469

–

C3**

150pF

200Ω

200Ω

1000pF

–

2

I

OUT2

7

*SCHOTTKY BARRIER DIODE

6

1

23

LT1001

ZETEX*
BAT54S

3

+

V

±5%

SHDN

SYNC

GND

T1

••

••

R3
15k

16

3

15

R2

REF

MMBD914

MMBD914

MMBD914

MMBD914

4

R

R

FB

OFS

I

OUT1

I

6

OUT2

7

AGND

8

GND

1588992 F02

DAC with Two Optional Circuits

OUT

LT1121-5

D1

D2

R10

10k

D3

D4

C2
15pF

15V

8

C3
22µF
25V
CER

C4
22µF
25V
CER

–

2

1/2 LT1469

3

+

2.2µF

LT1761

IN OUT

GND ADJ

GND ADJ

LT1964

2

IN OUT

4

–15V

5V

3

BYP

24

14

BYP

3

5

R5

49.9k

R6

49.9k

5

0.1µF

0.1µF

51

R4

442k

R7

442k

1

C7

0.01µF

+

+

C8

0.01µF

V

C5
33µF
25V
TANT

C6
33µF
25V
TANT

1588992 F03

OUT

12V

AGND

–12V

1

2

R

R1

9

5V

V

CC

0.1µF

14

CLR

13

CS/LD

12

SCK

11

SDI

10

SDO

**FOR MULTIPLYING APPLICATIONS C3 = 15pF

COM

R1

R2

12-/14-/16-BIT DAC WITH SPAN ADJUST

LTC1588/LTC1589/LTC1592

Figure 2. Basic Connections for SoftSpan V
for Driving I

E1

IN

5V

E5

E7

E6

R9
10k

V

IN

C1

4.7µF

6.3V

C2
820pF

R1
1M

R2

16.9k

11

5

6
7

from AGND with a Force/Sense Amplifier

OUT2

13

V

SYNC

LT3439

CT
RT

10 1 16

IN

PGNDPGNDGND

COLASHDN

COLB

RSL

CTX02-16030

3

14
4

14

C22

2.2nF
1kV

Figure 3. Isolated Power Supplies for the Circuit of Figure 4

1588992fa

PACKAGE DESCRIPTIO

U

G Package

16-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

1.25 ±0.12

LTC1588/LTC1589/LTC1592

5.90 – 6.50*
(.232 – .256)

14 13 12 11 10 91516

7.8 – 8.2

0.42 ±0.03 0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60**
(.197 – .221)

0.09 – 0.25

(.0035 – .010)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

0.55 – 0.95

(.022 – .037)

MILLIMETERS

(INCHES)

5.3 – 5.7

° – 8°

0

0.65

(.0256)

BSC

12345678

0.22 – 0.38

(.009 – .015)

7.40 – 8.20

(.291 – .323)

2.0

(.079)

0.05

(.002)

G16 SSOP 0802

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

1588992fa

15

LTC1588/LTC1589/LTC1592

WUUU

APPLICATIO S I FOR ATIO

OPTIONAL CIRCUIT FOR 2-WIRE INTERFACE.
FOR A 3-WIRE INTERFACE (SPI), ADD A 3RD
OPTOISOLATOR TO DRIVE CS/LD WITH THE
WAVEFORMS OF FIGURE 1

74HC161
A

B
C
D
CLK
ENP
ENT
LD
CLR

RCO

14

ISOLATED

QA

CS/LD

13

QB

12

QC

11

QD

15

µCONTROLLER

3

GND

4
5
6

2

HCPL2300

2

V

CC

R1

7.5k

3

SCK

TO

V

CC

SDI

R2

7.5k

HCPL2300

2

3

8

5V

7
6

5

8

5V

7
6

5

7

10

9
1

5V

ISOLATED SCK

ISOLATED SDI

0.1µF

5V REF

10µF

12V
7

2

3

1

2
R1

R

V

CC

CLR
CS/LD
SCK
SDI
SDO

COM

R1

12-/14-/16-BIT DAC WITH SPAN ADJUST

5V

9

14
13
12
11
10

0.1µF

–

LT1468

+

4

–12V

6

10µF

0.1µF

150pF

R2

LTC1588/LTC1589/LTC1592

16

R2

15
REF

+

3

4

R

R

OFS

FB

10µF

I

OUT1

I

OUT2

AGND

GND

4

12V

LT1027-5

5

6
7
8

2

3

8

2

15pF

–

+

12V

7

LT1468

4

–12V

10µF

0.1µF

10µF

0.1µF

AGND

6

AGND

1588992 F04

V

OUT

Figure 4. Optically Isolated 16-Bit SoftSpan System

SCK

SDI

CS/LD

C3 C2 C1 C0 X D2 D1 D0

1588992 F05

Figure 5. Timing Diagram for the Circuit of Figure 4

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1591/LTC1597 Parallel 14-/16-Bit Current Output DACs On-Chip 4-Quadrant Resistors
LTC1595/LTC1596 Serial 16-Bit Current Output DACs Low Glitch, ±1LSB Maximum INL, DNL
LTC1599 2-Byte, 16-Bit Current Output DAC On-Chip 4-Quadrant Resistors
LTC1821 Parallel 16-Bit Voltage Outupt DAC Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610 Octal 16-/14-/12-Bit DACs Single Supply, µPower in Narrow SSOP16

LTC2620

16

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

1588992fa

LT/TP 0503 1K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2001