High Power Buck Converter from 5V or 3.3V
Main Power
■
Adjustable Current Limit in S0-8 with
Topside FET R
■
No External Sense Resistor Required
■
Hiccup Mode Current Limit Protection
■
Adjustable, Fixed 1.9V, 2.5V, 2.8V and 3.3V Output
■
All N-Channel MOSFET Synchronous Driver
■
Excellent Output Regulation: ±2% over Line, Load
DS(ON)
Sensing
and Temperature Variations
■
High Efficiency: Over 95% Possible
■
Fast Transient Response
■
Fixed 300kHz Frequency Operation
■
Internal Soft-Start Circuit
■
Quiescent Current: 1mA, 45µA in Shutdown
U
APPLICATIO S
LTC1530
High Power Synchronous
Switching Regulator Controller
U
DESCRIPTIO
The LTC®1530 is a high power synchronous switching
regulator controller optimized for 5V to 1.3V-3.5V output
applications. Its synchronous switching architecture drives
two external N-channel MOSFET devices to provide high
efficiency. The LTC1530 contains a precision trimmed
reference and feedback system that provides worst-case
output voltage regulation of ±2% over temperature, load
current and line voltage shifts. Current limit circuitry
senses the output current through the on-resistance of
the topside N-channel MOSFET, providing an adjustable
current limit without requiring an external low value sense
resistor.
The LTC1530 includes a fixed frequency PWM oscillator
that free runs at 300kHz, providing greater than 90%
efficiency in converter designs from 1A to 20A of output
current. Shutdown mode drops the LTC1530 supply current to 45µA.
■
Power Supply for Pentium® II, AMD-K6®-2, SPARC,
ALPHA and PA-RISC Microprocessors
■
High Power 5V to 1.3V-3.5V Regulators
U
TYPICAL APPLICATIO
V
IN
5V
MBR0530T1 MBR0530T1
0.1µF
+
10µF
G1
I
G2
V
OUT
†
COILTRONICS CTX02-13198
OR PANASONIC ETQP6F2R5HA
††
AVX TPSE337M006R0100
20Ω
FB
0.22µF
Q1*
Q2*
COILTRONICS (561) 241-7876
C1
150pF
0.022µF
2.7k
PV
I
CC
MAX
COMP
R
LTC1530-3.3
C
10k
C
C
GND
Figure 1. Single 5V to 3.3V Supply
The LTC1530 is specified for commercial and industrial
temperature ranges and is available in the S0-8 package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corp.
AMD-K6 is a registered trademark of Advanced Micro Devices, Inc.
The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at –40°C ≤ TA ≤ 85°C.
PVCC = 12V unless otherwise noted. (Note 3)
Internal Soft-Start Wake-Up TimeFigure 4, COMP Pulls High to G1↑ (Note 10)3.5ms
Driver Rise and Fall TimeFigure 4●90140ns
Driver Nonoverlap TimeFigure 4●30100ns
Maximum G1 Duty CycleFigure 4●8186%
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: If I
is taken below GND, it is clamped by an internal diode. This
FB
pin handles input currents ≤ 100mA below GND without latch-up. In the
positive direction, it is not clamped to PVCC.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: The LTC1530 is tested in an op amp feedback loop which
regulates V
SENSE
based on V
OUT
= 2V for the error amplifier.
COMP
or V
Note 5: The Open-loop DC gain and transconductance from the VFB pin to
the COMP pin are G
ERR
and g
versions, the actual open-loop DC gain and transconductance are G
and g
multiplied by the ratio 1.235/V
mERR
respectively. For fixed output voltage
mERR
.
OUT
ERR
Note 6: The total voltage from the PV
pin to the GND pin must be ≥8V
CC
for the current limit protection circuit to be active.
Note 7: G1 and G2 begin to switch once PV
is ≥ the undervoltage
CC
lockout threshold voltage.
Note 8: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This current varies
with the LTC1530 operating frequency, supply voltage and the external
FETs used.
Note 9: The LTC1530 enters shutdown if COMP is pulled low.
Note 10: Slew rate is measured at the COMP pin on the transition from
shutdown to active mode.
3
LTC1530
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0
0.3
4
2
LOAD CURRENT (A)
LTC1530-1.9 V
1.930
1.925
1.920
1.915
1.910
1.905
(V)
1.900
OUT
V
1.895
1.890
1.885
1.880
1.875
1.870
–55
–35
5
–15
TEMPERATURE (°C)
TA = 25°C
REFER TO FIGURE 10
8
6
OUT
25
10
vs Temperature
45 65 85 105 125
12
1530 G01
1530 G04
14
Load Regulation
2.510
TA = 25°C
2.508
REFER TO FIGURE 2
2.506
2.504
2.502
2.500
2.498
2.496
OUTPUT VOLTAGE (V)
2.494
2.492
2.490
0123456
OUTPUT CURRENT (A)
LTC1530-2.5 V
2.55
2.54
2.53
2.52
2.51
(V)
2.50
OUT
V
2.49
2.48
2.47
2.46
2.45
–355
–55
–15
TEMPERATURE (°C)
vs Temperature
OUT
85
45125
25
65
1530 G02
105
1530 G05
LTC1530 V
1.260
1.255
1.250
1.245
1.240
(V)
1.235
SENSE
V
1.230
1.225
1.220
1.215
1.210
–55
LTC1530-2.8 V
2.85
2.84
2.83
2.82
2.81
2.80
(V)
OUT
2.79
V
2.78
2.77
2.76
2.75
2.74
–55
–15
–355
–35
–15
vs Temperature
SENSE
45125
25
TEMPERATURE (°C)
5
TEMPERATURE (°C)
65
vs Temperature
OUT
25
45 65 85 105 125
85
105
1530 G03
1530 G06
4
(V)
OUT
V
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
3.23
LTC1530-3.3 V
–35
–55
–15
TEMPERATURE (°C)
vs Temperature
OUT
5
25
45 65 85 105 125
1530 G06
Undervoltage Lockout Threshold
Voltage vs Temperature
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.3
–355
–55
–15
25
TEMPERATURE (°C)
45125
65
Error Amplifier Transconductance
vs Temperature
2.8
2.6
2.4
2.2
2.0
1.8
1.6
ERROR AMPLIFIER TRANSCONDUCTANCE (millimho)
–355
–55
85
105
1530 G08
–15
25
TEMPERATURE (°C)
85
45125
105
65
1530 G09
AMBIENT TEMPERATURE (°C)
–55
MAXIMUM G1 DUTY CYCLE (%)
92
90
88
86
84
82
80
78
–15
25
45125
1530 G12
–355
65
85
105
THERMAL SHUTDOWN OCCURS
BEYOND THESE POINTS
G1, G2
CAPACITANCE
= 1000pF
PVCC = 12V
f
OSC
= 300kHz
7700pF
5500pF
3300pF
2200pF
TEMPERATURE (°C)
–55
80
75
70
65
60
55
50
45
40
35
30
–15
25
45125
1530 G15
–355
65
85
105
PVCC = 12V
PV
CC
SHUTDOWN CURRENT (µA)
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1530
Error Amplifier Open-Loop Gain
vs Temperature
60
55
50
45
ERROR AMPLIFIER OPEN-LOOP DC GAIN (dB)
SINK CURRENT (µA)
MAX
I
40
300
280
260
240
220
200
180
160
140
120
–15
–355
–55
I
Sink Current vs Temperature
MAX
PVCC = 12V
G1, G2 ARE NOT SWITCHING
–15
–355
–55
25
TEMPERATURE (°C)
25
TEMPERATURE (°C)
85
45125
65
85
45125
65
105
105
1530 G10
1530 G13
Oscillator Frequency
vs Temperature
350
340
330
320
310
300
290
280
270
OSCILLATOR FREQUENCY (kHz)
260
250
–355
–55
–15
25
TEMPERATURE (°C)
PVCC Supply Current
vs Gate Capacitance
70
PVCC = 12V
= 25°C
T
A
60
GATE CAPACITANCE = C
50
40
30
SUPPLY CURRENT (mA)
20
CC
PV
10
0
1357
0
248
GATE CAPACITANCE (nF)
85
45125
= C
G1
105
65
1530 G11
G2
6
1530 G14
Maximum G1 Duty Cycle
vs Ambient Temperature
PVCC Shutdown Supply Current
vs Temperature
Shutdown Threshold Voltage
vs TemperatureOutput Overcurrent Protection
250
PVCC = 12V
MEASURED AT
COMP PIN
200
150
100
50
SHUTDOWN THRESHOLD VOLTAGE (mV)
0
–355
–55
–15
TEMPERATURE (°C)
45125
25
Transient Response
3.0
2.5
PVCC = 12V
T
= 25°C
A
2.0
REFER TO
FIGURE 2
1.5
1.0
OUTPUT VOLTAGE (V)
SHORT-CIRCUIT
CURRENT
0.5
85
105
65
1530 G16
0
213579
0
OUTPUT CURRENT (A)
6
4
8
1530 G17
50mV/DIV
2A/DIV
50µs/DIV1530 G18
10
5
LTC1530
U
UU
PI FU CTIO S
PVCC (Pin 1): Power Supply for G1, G2 and Logic. PV
must connect to a potential of at least VIN + V
GS(ON)Q1
VIN = 5V, generate PVCC using a simple charge pump
connected to the switching node between Q1 and Q2 (see
Figure 1) or connect PVCC to a 12V supply. Bypass PV
properly or erratic operation will result. A low ESR 10µF
capacitor or larger bypass capacitor along with a 0.1µF
surface mount ceramic capacitor in parallel is recommended from PVCC directly to GND to minimize switching
ripple. Switching ripple should be ≤100mV at the PV
pin.
GND (Pin 2): Power and Logic Ground. GND is connected
to the internal gate drive circuitry and the feedback circuitry. To obtain good output voltage regulation, use
proper ground techniques between the LTC1530 GND and
bottom-side FET source and the negative terminal of the
output capacitor. See the Applications Information section
for more details on PCB layout techniques.
V
SENSE/VOUT
(Pin 3): Feedback Voltage Pin. For the adjust-
able LTC1530, use an external resistor divider to set the
required output voltage. Connect the tap point of the
resistor divider network to V
and the top of the
SENSE
divider network to the output voltage. For fixed output
voltage versions of the LTC1530, the resistor divider is
internal and the top of the resistor divider network is
brought out to V
. In general, the resistor divider
OUT
network for each fixed output voltage version sinks approximately 30µA. Connect V
to the output voltage
OUT
either at the output capacitors or at the actual point of load.
V
SENSE/VOUT
is sensitive to switching noise injected into
the pin. Isolate high current switching traces from this pin
and its PCB trace.
COMP (Pin 4): External Compensation. The COMP pin is
connected to the error amplifier output and the input of the
PWM comparator. An RC + C network is typically used at
CC
. If
CC
CC
COMP to compensate the feedback loop for optimum
transient response. To shut down the LTC1530, pull this
pin below 0.1V with an open-collector or open-drain
transistor. Supply current is typically reduced to 45µA in
shutdown. An internal 4µA pullup ensures start-up.
I
(Pin 5): Current Limit Threshold. Current limit is set
MAX
by the voltage drop across an external resistor connected
between the drain of Q1 and I
pared with the voltage across the R
. This voltage is com-
MAX
of the high side
DS(ON)
MOSFET. The LTC1530 contains a 200µA internal pull-
down at I
to set current limit. This 200µA current
MAX
source has a positive temperature coefficient to provide
first order correction for the temperature coefficient of the
external N-channel MOSFET’s R
DS(ON)
.
IFB (Pin 6): Current Limit Sense Pin. Connect IFB to the
switching node between Q1’s source and Q2’s drain. If I
drops below I
with G1 on, the LTC1530 enters current
MAX
FB
limit. Under this condition, the internal soft-start capacitor
is discharged and COMP is pulled low slowly. Duty cycle
is reduced and output power is limited. The current limit
circuitry is only activated if PVCC ≥ 8V. This action eases
start-up considerations as PVCC is ramping up because
the MOSFET’s R
can be significantly higher than
DS(ON)
what is measured under normal operating conditions. The
current limit circuit is disabled by floating I
and short-
MAX
ing IFB to PVCC.
G2 (Pin 7): Gate Drive for the Low Side N-Channel MOSFET,
Q2. This output swings from PVCC to GND. It is always low
if G1 is high or if the output is disabled. To prevent
undershoot during a soft-start cycle, G2 is held low until
G1 first transitions high.
G1 (Pin 8): Gate Drive for the Topside N-Channel MOSFET,
Q1. This output swings from PVCC to GND. It is always low
if G2 is high or if the output is disabled.
The LTC1530 is a voltage feedback, synchronous switching regulator controller (see Block Diagram) designed for
use in high power, low voltage step-down (buck) converters. It includes an on-chip soft-start capacitor, a PWM
generator, a precision reference trimmed to ±1%, two high
power MOSFET gate drivers and all the necessary feedback and control circuitry to form a complete switching
regulator circuit running at 300kHz.
The LTC1530 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as a
current sensing element, eliminating the need for an
external sense resistor. If the current comparator, CC,
detects an overcurrent condition, the duty cycle is reduced
by discharging the internal soft-start capacitor through a
voltage-controlled current source. Under severe overloads or output short-circuit conditions, the soft-start
capacitor is pulled to ground and a start-up cycle is
initiated. If the short circuit or overload persists, the chip
repeats soft-start cycles and prevents damage to external
components.
THEORY OF OPERATION
Primary Feedback Loop
The LTC1530 compares the output voltage with the internal reference at the error amplifier inputs. The error
amplifier outputs an error signal to the PWM comparator.
This signal is compared to the fixed frequency oscillator
sawtooth waveform to generate the PWM signal. The
PWM signal drives the external MOSFETs at the G1 and G2
pins. The resulting chopped waveform is filtered by LO and
C
which closes the loop. Loop frequency compensa-
OUT
tion is typically accomplished with an external RC + C
network at the COMP pin, which is the output node of the
transconductance error amplifier.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the error
amplifier cannot respond quickly enough. MIN compares
the feedback signal to a voltage 3% below the internal
reference. If the signal is below the comparator threshold,
the MIN comparator overrides the error amplifier and
forces the loop to maximum duty cycle, typically 86%.
Similarly, the MAX comparator forces the output to 0%
duty cycle if the feedback signal is greater than 3% above
the internal reference. To prevent these two comparators
from triggering due to noise, the MIN and MAX comparators’ response times are deliberately delayed by two to
three microseconds. These comparators help prevent
extreme output perturbations with fast output load current
transients, while allowing the main feedback loop to be
optimally compensated for stability.
Thermal Shutdown
The LTC1530 has a thermal protection circuit that disables
both internal gate drivers if activated. G1 and G2 are held
low and the LTC1530 supply current drops to about 1mA.
8
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