The LTC®1344 features six software-selectable
multiprotocol cable terminators. Each terminator can be
configured as an RS422 (V.11) 100Ω minimum differen-
tial load, V.35 T-network load or an open circuit for use
with RS232 (V.28) or RS423 (V.10) transceivers that
provide their own termination. When combined with the
LTC1343, the LTC1344 forms a complete software-selectable multiprotocol serial port. A data bus latch feature
allows sharing of the select lines between multiple interface ports.
The LTC1344 is available in a 24-lead SSOP.
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Data Networking
■
CSU and DSU
■
Data Routers
TYPICAL APPLICATION
Daisy-Chained Control Outputs
U
1
LTC1344
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
G PACKAGE
24-LEAD PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
M0
V
EE
R1C
R1B
R1A
R2A
R2B
R2C
R3A
R3B
R3C
GND
M1
M2
DCE/DTE
LATCH
R6B
R6A
R5A
R5B
R4A
R4B
V
CC
GND
WW
W
U
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Positive Supply Voltage (VCC)................................... 7V
Negative Supply Voltage (VEE) ........................... –13.2V
Input Voltage (Logic Inputs) .... VEE – 0.3V to VCC + 0.3V
Input Voltage (Load Inputs) .................................. ±18V
Operating Temperature Range
LTC1344C ............................................... 0°C to 70°C
LTC1344I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
/
PACKAGE
T
JMAX
Consult factory for Military grade parts.
O
RDER IFORATIO
= 150°C, θJA = 100°C/W
WU
ORDER PART
NUMBER
LTC1344CG
LTC1344IG
U
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°.
V
= 5V ±5%, VEE = –5V ±5%, T
CC
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
Supplies
I
CC
Terminator Pins
R
V.35
R
V.11
I
LEAK
Logic Inputs
V
IH
V
IL
I
IN
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are reference to ground unless otherwise
specified.
LATCH (Pin 21): TTL Level Logic Signal Latch Input. When
it is low the input buffers on M0, M1, M2 and DCE/DTE are
transparent. When it is high the logic pins are latched into
their respective input buffers. The data latch allows the
select lines to be shared between multiple I/O ports.
DCE/DTE (Pin 22): TTL Level Mode Select Input. The DCE
mode is selected when it is high and DTE mode when low.
The data on DCE/DTE is latched when LATCH is high.
M2 (Pin 23): TTL Level Mode Select Input 1. The data on
M2 is latched when LATCH is high.
M1 (Pin 24): TTL Level Mode Select Input 2. The data on
M1 is latched when LATCH is high.
TEST CIRCUITS
A
Ω
B
Figure 1. Differential V.11 or V.35 Impedance MeasurementFigure 2. V.35 Common Mode Impedance Measurement
S1
ON
±7V OR ±2V
V
R1
51.5Ω
R2
51.5Ω
S2
OFF
R1
C
R3
124Ω
1344 F01
A, B
Ω
51.5Ω
S1
ON
R2
51.5Ω
±2V
V
S2
ON
C
R3
124Ω
1344 F02
4
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