Datasheet LTC1272-8CCN, LTC1272-8ACS, LTC1272-3CCS, LTC1272-3CCN, LTC1272-3ACS Datasheet (Linear Technology)

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LTC1272

FREQUENCY (kHz)

–140

AMPLITUDE (dB)

20 40 60 80

LTC1272 • TA02

–120

–100

–80

–60

–40

–20

100 120

(N+D)

= 72.1

12-Bit, 3µs, 250kHz

Sampling A/D Converter

EATU

■

AD7572 Pinout

■

12-Bit Resolution

■

3µs and 8µs Conversion Times

■

On-Chip Sample-and-Hold

■

Up to 250kHz Sample Rates

■

5V Single Supply Operation

■

No Negative Supply Required

■

On-Chip 25ppm/°C Reference

■

75mW (Typ) Power Consumption

■

24-Pin Narrow DIP and SOL Packages

■

ESD Protected on All Pins

PPLICATI

■

High Speed Data Acquisition

■

Digital Signal Processing (DSP)

■

Multiplexed Data Acquisition Systems

■

Single Supply Systems

U S

DUESCRIPTIO

The LTC1272 is a 3µs, 12-bit, successive approximation sampling A/D converter. It has the same pinout as the industry standard AD7572 and offers faster conversion time, on-chip sample-and-hold, and single supply operation. It uses LTBiCMOSTM switched-capacitor technology to combine a high speed 12-bit ADC with a fast, accurate sample-and-hold and a precision reference.

The LTC1272 operates with a single 5V supply but can also accept the 5V/–15V supplies required by the AD7572 (Pin 23, the negative supply pin of the AD7572, is not connected on the LTC1272). The LTC1272 has the same 0V to 5V input range as the AD7572 but, to achieve single supply operation, it provides a 2.42V reference output instead of the –5.25V of the AD7572. It plugs in for the AD7572 if the reference capacitor polarity is reversed and a 1µ s sampleand-hold acquisition time is allowed between conversions.

The output data can be read as a 12-bit word or as two 8-bit bytes. This allows easy interface to both 8-bit and higher processors. The LTC1272 can be used with a crystal or an external clock and comes in speed grades of 3µs and 8µs.

LTBiCMOS is a trademark of Linear Technology Corporation

PPLICATITYPICAL

Single 5V Supply, 3µs, 12-Bit Sampling ADC

ANALOG INPUT

2.42V V 

REF

OUTPUT

(0V TO 5V)

0.1µF

8 OR 12-BIT

PARALLEL

BUS

10µF



LTC1272

REF

AGND D11 (MSB) D10 D9 D8 D7 D6 D5 D4 DGND

BUSY

HBEN

CLK OUT

CLK IN

D0/8 D1/9

D2/10

D3/11

10 F

P

CONTROL LINES

LTC1272 • TA01

1024 Point FFT, fS = 250kHz, fIN = 10kHz

0.1 F

LTC1272

LUTEXI T

WUW

ARB

U G

(Notes 1 and 2)

Supply Voltage (VDD)................................................. 6V

Analog Input Voltage (Note 3) ...................–0.3V to 15V

Digital Input Voltage ..................................–0.3V to 12V

Digital Output Voltage.................... –0.3V to VDD + 0.3V

Power Dissipation.............................................. 500mW

PACKAGE

REF

AGND

(MSB) D11

D10

5 6

D8 D7 D6

DGND

24-LEAD PLASTIC DIP

JMAX

= 110°C, θJA = 100°C/W

RDER I FOR ATIO

TOP VIEW

BUSY

N PACKAGE

20 19 18 178 16 15 14 1312

CS RD HBEN CLK OUT CLK IN D0/8 D1/9 D2/10 D3/11

(MSB) D11

REF

AGND

3 4

D10

5 6

D8 D7 D6

DGND

JMAX

TOP VIEW

S PACKAGE

24-LEAD PLASTIC SOL

= 110°C, θJA = 130°C/W

Operating Temperature Range

LTC1272-XAC, CC ................................. 0°C to 70°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART NUMBER

V 23 22 21 20 19 18 178 16 15 14 1312

BUSY

HBEN

CLK OUT

CLK IN

D0/8

D1/9

D2/10

D3/11

CONVERSION CONVERSION TIME = 3µs TIME = 8µs

LTC1272-3ACN LTC1272-8ACN LTC1272-3CCN LTC1272-8CCN

S PACKAGE ONLY

LTC1272-3ACS LTC1272-8ACS LTC1272-3CCS LTC1272-8CCS

Consult factory for Industrial and Military grade parts.

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 12 Bits Integral Linearity Error (Note 5) ● ±1/2 ±1 LSB Differential Linearity Error ● ±1 ±1 LSB Offset Error ±3 ±4 LSB

Gain Error ±10 ±15 LSB Full-Scale Tempco I

VERTER

CCHARA TERIST

(Reference) = 0 ● ±5 ±25 ±10 ±45 ppm/°C

OUT

ICS

With Internal Reference (Note 4)

LTC1272-XA LTC1272-XC

● ±4 ±6 LSB

LTC1272

UUU

I TER AL REFERE CE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Output Voltage (Note 6) I

REF

Output Tempco I

REF

Line Regulation 4.75V ≤ VDD ≤ 5.25V, I

REF

Load Regulation (Sourcing Current) 0 ≤ I

REF

= 0 2.400 2.420 2.440 2.400 2.420 2.440 V

OUT

= 0 ● 5 25 10 45 ppm/°C

OUT

= 0 0.01 0.01 LSB/V

OUT

 ≤ 1mA 2 2 LSB/mA

OUT

(Note 4)

LTC1272-XA LTC1272-XC

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SOURCE

SINK

High Level Input Voltage CS, RD, HBEN, CLK IN VDD = 5.25V ● 2.4 V Low Level Input Voltage CS, RD, HBEN, CLK IN VDD = 4.75V ● 0.8 V Input Current CS, RD, HBEN VIN = 0V to V Input Current CLK IN VIN = 0V to V High Level Output Voltage All Logic Outputs VDD = 4.75V I

I Low Level Output Voltage All Logic Outputs VDD = 4.75V, I High-Z Output Leakage D11-D0/8 V High-Z Output Capacitance (Note 7) ● 15 pF Output Source Current V Output Sink Current V Positive Supply Current CS = RD = VDD, AIN = 5V ● 15 30 mA Power Dissipation 75 mW

OUT

= –10µA 4.7 V

OUT

= –200µA ● 4.0 V

OUT

= 1.6mA ● 0.4 V

OUT

= 0V to V

= 0V –10 mA = V

(Note 4)

LTC1272-XA/C

● ±10 µA

● ±20 µA

● ±10 µA

10 mA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion Ratio 10kHz Input Signal 72 dB THD Total Harmonic Distortion (Up to 5th Harmonic) 10kHz Input Signal –82 dB

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V IINInput Current ● 3.5 mA C t

LOG

ACQ

ACCURACY

Peak Harmonic or Spurious Noise 10kHz Input Signal – 82 dB

U PUT

Input Voltage Range 4.75V ≤ VDD ≤ 5.25V ● 05V

Input Capacitance 50 pF Sample-and-Hold Acquisition Time ● 0.45 1 µs

(Note 4)

(Note 4) f

= 250kHz (LTC1272-3), 111kHz (LTC1272-8)

SAMPLE

LTC1272-XA/C

LTC1272-XA/B/C

LTC1272

CCHARA TERIST

GTI

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CONV

CS to RD Setup Time ● 0ns RD to BUSY Delay CL = 50pF 80 190 ns

Data Access Time After RD↓ CL = 20pF 50 90 ns

RD Pulse Width t

CS to RD Hold Time ● 0ns Data Setup Time After BUSY 40 70 ns

Bus Relinquish Time 20 30 75 ns

HBEN to RD Setup Time ● 0ns HBEN to RD Hold Time ● 0ns Delay Between RD Operations ● 200 ns Delay Between Conversions 1 µs Aperture Delay of Sample and Hold Jitter <50ps 25 ns CLK to BUSY Delay 80 170 ns

Conversion Time ● 12 13 CLK

ICS

(Note 8)

LTC1272-XA/C

COM Grade ● 230 ns

COM Grade ● 110 ns

CL = 100pF 70 125 ns

COM Grade ● 150 ns

COM Grade ● t

COM Grade ● 90 ns

COM Grade ● 20 85 ns

COM Grade ● 220 ns

3 3

ns ns

CYCLES

The ● indicates specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C.

Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND and AGND wired together, unless otherwise noted.

Note 3: When the analog input voltage is taken below ground it will be clamped by an internal diode. This product can handle, with no external diode, input currents of greater than 60mA below ground without latch-up.

VDD = 5V, f

Note 4: LTC1272-8, t performance, the LTC1272 clock should be synchronized to the RD and CS control inputs with at least 40ns separating convert start from the nearest clock edge.

= 4MHz for LTC1272-3, and 1.6MHz for

CLK

= tf = 5ns unless otherwise specified. For best analog

Note 5: Linearity error is specified between the actual end points of the A/D transfer curve.

Note 6: The LTC1272 has the same 0V to 5V input range as the AD7572 but, to achieve single supply operation, it provides a 2.42V reference output instead of the –5.25V of the AD7572. This requires that the polarity of the reference bypass capacitor be reversed when plugging an LTC1272 into an AD7572 socket.

Note 7: Guaranteed by design, not subject to test. Note 8: V

ensure compliance. All input control signals are specified with t (10% to 90% of 5V) and timed from a voltage level of 1.6V. See Figures 13 through 17.

= 5V. Timing specifications are sample tested at 25°C to

= tf = 5ns

LTC1272

AIN (Pin 1): Analog Input, 0V to 5V Unipolar Input. V

an AD7572 socket, reverse the reference bypass capacitor polarity and short the 10Ω series resistor.

AGND (Pin 3): Analog Ground. D11 to D4 (Pins 4-11): Three-State Data Outputs. DGND (Pin 12): Digital Ground. D3/11 to D0/8 (Pins 13-16): Three-State Data Outputs. CLK IN (Pin 17): Clock Input. An external TTL/CMOS

compatible clock may be applied to this pin or a crystal can be connected between CLK IN and CLK OUT.

CLK OUT (Pin 18): Clock Output. An inverted CLK IN signal appears at this pin.

FUUC

(Pin 2): 2.42V Reference Output. When plugging into

REF

U S

HBEN (Pin 19): High Byte Enable Input. This pin is used to multiplex the internal 12-bit conversion result into the lower bit outputs (D7 to D0/8). See table below. HBEN also disables conversion starts when HIGH.

RD (Pin 20): Read Input. This active low signal starts a conversion when CS and HBEN are low. RD also enables the output drivers when CS is low.

CS (Pin 21): The Chip Select Input must be low for the ADC to recognize RD and HBEN inputs.

BUSY (Pin 22): The BUSY Output is low when a conversion is in progress.

NC (Pin 23): Not Connected Internally. The LTC1272 does not require negative supply. This pin can accommodate the –15V required by the AD7572 without problems.

VDD (Pin 24): Positive Supply, 5V.

Data Bus Output, CS and RD = LOW

Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16

MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8

*D11...D0/8 are the ADC data output pins.

DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.

LPER

ATYPICA

INL ERROR (LSBs)

CCHARA TERIST

Integral Nonlinearity

1.0 VDD = 5V

= 4MHz

CLK

0.5

–0.5

ICS

–1.0

512 1024 4096

1536 2048 2560 3072 3584

CODE

LTC1272 • TPC01

LTC1272

TEMPERATURE (°C)

–55

CLOCK FREQUENCY (MHz)

–25 25 50 125

LT1272 • TPC05

0 75 100

LPER

ATYPICA

VDD Supply Current vs Minimum Clock Frequency vs Maximum Clock Frequency vs Temperature Temperature Temperature

VDD = 5V

= 4MHz

CLK

(mA)

CCHARA TERIST

Differential Nonlinearity

1.0 VDD = 5V

= 4MHz

CLK

0.5

INL ERROR (LSBs)

–0.5

–1.0

512 1024 4096

600

VDD = 5V

500

400

ICS

1536 2048 2560 3072 3584

CODE

LTC1272 • TPC02

SUPPLY CURRENT, I

–55

0 75 100

–25 25 50 125

TEMPERATURE (°C)

REF

2.435

2.430

2.425

(V)

2.420

REF

2.415

2.410

2.405 –5

vs I

–4 –2 –1 2

LT1272 • TPC03

(mA) LTC1272 ENOBs* vs Frequency

LOAD

–3 0 1

IL (mA)

300

200

CLOCK FREQUENCY (kHz)

100

–25 25 50 125

–55

LT1272 • TPC06

0 75 100

TEMPERATURE (°C)

LT1272 • TPC04

*EFFECTIVE NUMBER OF BITS, ENOBs =

12 11

ENOBs*

9 8

7 6 5 4 3 2

fS = 250kHz

= 5V

40 100

20 60 80 120

fIN (kHz)

LT1272 • TPC07

S/(N + D) – 1.76dB

6.02

LTC1272

DAC

LTC1272 • TA07

–

DAC

300Ω

SAMPLE

HOLD

SAMPLE

2.7k

S A R

12-BIT LATCH

COMPARATOR

SAMPLE

FREQUENCY (kHz)

–110

AMPLITUDE (dB)

–90

–70

–50

–30

–10

20 40 80 120

LTC1272 • TA23

–20

–40

–60

–80

–100

60 100

PPLICATI

I FOR ATIO

Conversion Details

Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approximation register (SAR) is reset and the three-state data outputs are enabled. Once a conversion cycle has begun it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor through a 300Ω/2.7kΩ divider. The voltage divider allows the LTC1272 to convert 0V to 5V input signals while operating from a 4.5V supply. The conversion has two phases: the sample phase and the convert phase. During the sample phase, the comparator offset is nulled by the feedback switch and the analog input is stored as a charge on the sample-and-hold capacitor, C

SAMPLE

. This phase lasts from the end of the previous conversion until the next conversion is started. A minimum delay between conversions (t10) of 1µs allows enough time for the analog input to be acquired. During the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. The sample-and-hold capacitor is switched to ground injecting the analog input charge onto the comparator summing junction. This input charge is successively compared to binary weighted charges supplied by the capacitive DAC. Bit decisions are made by the comparator (zero crossing detector) which checks the addition of each successive weighted bit from the DAC output. The MSB decision is made 50ns (typically) after the second falling edge of CLK IN following a conversion start. Similarly, the succeeding bit decisions are made approximately 50ns after a CLK IN edge until the conversion is finished. At the end of a conversion, the DAC output balances the AIN output charge. The SAR contents (12-bit data word) which represent the AIN input signal are loaded into a 12-bit latch.

Sample-and-Hold and Dynamic Performance

Traditionally A/D converters have been characterized by such specs as offset and full-scale errors, integral

Figure 1. AIN Input

nonlinearity and differential nonlinearity. These specs are useful for characterizing an ADC’s DC or low frequency signal performance.

These specs alone are not adequate to fully specify the LTC1272 because of its high speed sampling ability. FFT (Fast Fourrier Transform) test techniques are used to characterize the LTC1272’s frequency response, distortion and noise at the rated throughput.

By applying a low distortion sine wave and analyzing the digital output using a FFT algorithm, the LTC1272’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1272 FFT plot.

Figure 2. LTC1272 Non-Averaged, 1024 Point FFT Plot. fS = 250kHz, fIN = 10kHz

LTC1272

PPLICATI

I FOR ATIO

Signal-to-Noise Ratio

The Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. This includes distortion as well as noise products and for this reason it is sometimes referred to as Signal-to-Noise + Distortion [S/(N + D)]. The output is band limited to frequencies from DC to one half the sampling frequency. Figure 2 shows spectral content from DC to 125kHz which is 1/2 the 250kHz sampling rate.

Effective Number of Bits

The effective number of bits (ENOBs) is a measurement of the resolution of an A/D and is directly related to the S/(N + D) by the equation:

N = [S/(N + D) –1.76]/6.02, where N is the effective number of bits of resolution and

S/(N + D) is expressed in dB. At the maximum sampling rate of 250kHz the LTC1272 maintains 11.5 ENOBs or better to 20kHz. Above 20kHz the ENOBs gradually decline, as shown in Figure 3, due to increasing second harmonic distortion. The noise floor remains approximately 90dB. The dynamic differential nonlinearity remains good out to 120kHz as shown in Figure 4.

1.0

0.5

ERROR (LSB)

–0.5

–1.0

Figure 4. LTC1272 Dynamic DNL. f fS = 250kHz, fIN = 122.25342kHz, VCC = 5V

CODE (THOUSANDS)

LTC1272 • TA24

= 4MHz,

CLK

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The harmonics are limited to the frequency band between DC and one half the sampling frequency. THD is

expressed as: 20 LOG [√V

+ V

+ ... + V

/V1] where

V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics.

Clock and Control Synchronization

12 11

9 8

7 6

ENOBs*

5 4 3 2

fS = 250kHz

= 5V

Figure 3. LTC1272 Effective Number of Bits (ENOBs) vs Input Frequency. fS = 250kHz

40 100

20 60 80 120

fIN (kHz)

LT1272 • TPC07

For best analog performance, the LTC1272 clock should be synchronized to the CS and RD control inputs as shown in Figure 5, with at least 40ns separating convert start from the nearest CLK IN edge. This ensures that transitions at CLK IN and CLK OUT do not couple to the analog input and get sampled by the sample-and-hold. The magnitude of this feedthrough is only a few millivolts, but if CLK and convert start (CS and RD) are asynchronous, frequency components caused by mixing the clock and convert signals may increase the apparent input noise.

When the clock and convert signals are synchronized, small endpoint errors (offset and full-scale) are the most that can be generated by clock feedthrough. Even these errors (which can be trimmed out) can be eliminated by ensuring that the start of a conversion (CS and RD’s falling edge) does not occur within 40ns of a clock edge, as in

LTC1272

PPLICATI

I FOR ATIO

CS & RD

BUSY

CLK IN

UNCERTAIN CONVERSION TIME FOR 30ns < t



THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES.

≥ 40ns*

Figure 5. RD and CLK IN for Synchronous Operation

(MSB)

Figure 5. Nevertheless, even without observing this guideline, the LTC1272 is still compatible with AD7572 synchronization modes, with no increase in linearity error. This means that either the falling or rising edge of CLK IN may be near RD’s falling edge.

Driving the Analog Input

The analog input of the LTC1272 is much easier to drive than that of the AD7572. The input current is not modulated by the DAC as in the AD7572. It has only one small current spike from charging the sample-and-hold capacitor at the end of the conversion. During the conversion the analog input draws only DC current. The only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion is started. Any op amp that settles in 1µs to small current transients will allow maximum speed operation. If slower op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the LTC1272 AIN input include the LT1006 and LT1007 op amps.

Internal Clock Oscillator

CONV

DB1DB10DB11

< 180ns

NOTES: LTC1272-3 – 4MHz CRYSTAL/CERAMIC RESONATOR LTC1272-8 – 1.6MHz CRYSTAL/CERAMIC RESONATOR

CLK OUT

CLK IN

Figure 6. LTC1272 Internal Clock Circuit

DB0

(LSB)

LTC1272 • TA06

LTC1272

CLOCK

LTC1272 • TA09

connected to CLK IN. For an external clock the duty cycle is not critical. An inverted CLK IN signal will appear at the CLK OUT pin as shown in the operating waveforms of Figure 7. Capacitance on the CLK OUT pin should be minimized for best analog performance.

Internal Reference

The LTC1272 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.42V ±1%. It is internally connected to the DAC and is also available at pin 2 to provide up to 1mA current to an external load.

Figure 6 shows the LTC1272 internal clock circuit. A crystal or ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18) to provide a clock oscillator for ADC timing. Alternatively the crystal/resonator may be omitted and an external clock source may be

For minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10µF tantalum in parallel with a

0.1µF ceramic). A simplified schematic of the reference with its recommended decoupling is shown in Figure 8.

LTC1272

PPLICATI

CURVATURE CORRECTED

REFERENCE

Figure 8. LTC1272 Internal 2.42V Reference

BANDGAP

I FOR ATIO

CS & RD

BUSY

CLK IN

CLK OUT

Figure 7. Operating Waveforms Using an External Clock Source for CLK IN

–

AGND

LTC1272

0.1µF

10µF

REF

LTC1272 • TA10

(MSB)

TO DAC

50ns TYP

DB1DB10DB11

11...111

11...110

11...101

OUTPUT CODE

00...011

00...010

00...001

00...000

DB0

(LSB)

LTC1272 • TA08

FULL-SCALE TRANSITION

FS = 5V

FS

1LSB =

–––– 4096

1FS

LSB

LSBs

AIN, INPUT VOLTAGE (IN TERMS OF LSBs)

FS – 1LSB

LT1272 • TA11

Figure 9. LTC1272 Ideal Input/Output Transfer Characteristic

Unipolar Operation

Figure 9 shows the ideal input/output characteristic for the 0V to 5V input range of the LTC1272. The code transitions occur midway between successive integer LSB values (i.e., 1/2LSB, 3/2LSBs, 5/2LSBs . . . FS – 3/2LSBs). The output code is natural binary with 1 LSB = FS/4096 = (5/4096)V = 1.22mV.

Unipolar Offset and Full-Scale Error Adjustment

In applications where absolute accuracy is important, then offset and full-scale error can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figure 10 shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset of the op amp driving AIN (i.e., A1 in Figure 10). For zero offset error apply 0.61mV (i.e., 1/2LBS) at VIN and adjust the op amp offset voltage until the ADC output code flickers between 0000 0000 0000 and 0000 0000 0001.

For zero full-scale error apply an analog input of 4.99817V (i.e., FS – 3/2LSBs or last code transition) at VIN and adjust R1 until the ADC output code flickers between 1111 1111 1110 and 1111 1111 1111.

LTC1272

PPLICATI

0V TO 5V

ANALOG

Figure 10. Unipolar 0V to 5V Operation with Gain Error Adjust

INPUT

A1

LT1007

–

*ADDITIONAL PINS OMITTED FOR CLARITY

I FOR ATIO

R3

15Ω

R1 200Ω

R2

20k

LTC1272

AGND

LTC1272 • TA12

Application Hints

Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1272 a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the LTC1272. The analog input should be screened by AGND.

A single point analog ground separate from the logic system ground should be established with an analog ground plane at pin 3 (AGND) or as close as possible to the LTC1272, as shown in Figure 11. Pin 12 (LTC1272 DGND) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and

the foil width for these tracks should be as wide as possible.

Noise: Input signal leads to AIN and signal return leads from AGND (pin 3) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible, a shielded cable between source and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible.

In applications where the LTC1272 data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get LSB errors in conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion (see Slow Memory Mode interfacing), or by using three-state buffers to isolate the LTC1272 data bus.

Timing and Control

Conversion start and data read operations are controlled by three LTC1272 digital inputs; HBEN, CS and RD. Figure 12 shows the logic structure associated with these inputs. The three signals are internally gated so that a logic “0” is required on all three inputs to initiate a conversion. Once initiated it cannot be restarted until conversion is complete. Converter status is indicated by the BUSY output, and this is low while conversion is in progress.

ANALOG

INPUT

CIRCUITRY

–

AGND

3 2 24 12

Figure 11. Power Supply Grounding Practice

LTC1272

REF

ANALOG GROUND PLANE

C3 C4

DGND

DIGITAL SYSTEM

GROUND CONNECTION TO DIGITAL CIRCUITRY

LTC1272 • TA13

LTC1272

PPLICATI

I FOR ATIO

There are two modes of operation as outlined by the timing diagrams of Figures 13 to 17. Slow Memory Mode is designed for microprocessors which can be driven into a Wait state, a Read operation brings CS and RD low which initiates a conversion and data is read when conversion is complete.

LTC1272

HBEN



D11....D0/8 ARE THE ADC DATA OUTPUT PINS

DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS

ACTIVE HIGH

The second is the ROM Mode which does not require microprocessor Wait states. A Read operation brings CS and RD low which initiates a conversion and reads the previous conversion result.

CONVERSION START (RISING EDGE TRIGGER)

FLIP

FLOP

CLEAR

BUSY

ENABLE THREE-STATE OUTPUTS

D11....D0/8 = DB11....DB0

ENABLE THREE-STATE OUTPUTS

D11....D8 = DB11....DB8

D7....D4 = LOW

D3/11....D0/8 = DB11....DB8

LTC1272 • TA14

Figure 12. Internal Logic for Control Inputs CS, RD and HBEN

CS & RD

BUSY

≥ 40ns*

CLK IN

(MSB)



UNCERTAIN CONVERSION TIME FOR 30ns < t *

THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES. SEE “DIGITAL INTERFACE” TEXT.

< 180ns

CONV

DB1DB10DB11

DB0

(LSB)

LTC1272 • TA15

Figure 13. RD and CLK IN for Synchronous Operation

Table 1. Data Bus Output, CS and RD = Low

PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 PIN 10 PIN 11 PIN 13 PIN 14 PIN 15 PIN 16

Data Outputs* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = Low DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = High DB11 DB10 DB9 DB8 Low Low Low Low DB11 DB10 DB9 DB8

Note: *D11 . . . D0/8 are the ADC data output pins

DB11 . . . DB0 are the 12-bit conversion results, DB11 is the MSB

LTC1272

PPLICATI

Table 2. Slow Memory Mode, Parallel Read Data Bus Status

Data Outputs D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8

Read DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

I FOR ATIO

RDCSRD

BUSY

DATA

HOLD

TRACK

Figure 14. Slow Memory Mode, Parallel Read Timing Diagram

OLD DATA DB11-DB0

CONV

NEW DATA

DB11-DB0

LTC1272 • TA16

Data Format

The output data format can be either a complete parallel load for 16-bit microprocessors or a two byte load for 8-bit microprocessors. Data is always right justified (i.e., LSB is the most right-hand bit in a 16-bit word). For a two byte read, only data outputs D7. . . D0/8 are used. Byte selection is governed by the HBEN input which controls an internal digital multiplexer. This multiplexes the 12 bits of conversion data onto the lower D7. . . D0/8 outputs (4MSBs or 8LSBs) where it can be read in two read cycles. The 4MSBs always appear on D11 . . . D8 whenever the three-state output drives are turned on.

Slow Memory Mode, Parallel Read (HBEN = Low)

Figure 14 and Table 2 show the timing diagram and data bus status for Slow Memory Mode, Parallel Read. CS and RD going low triggers a conversion and the LTC1272 acknowledges by taking BUSY low. Data from the previous conversion appears on the three-state data outputs. BUSY returns high at the end of conversion when the output latches have been updated and the conversion result is placed on data outputs D11 . . . D0/8.

Slow Memory Mode, Two Byte Read

For a two byte read, only 8 data outputs D7 . . . D0/8 are used. Conversion start procedure and data output status for the first read operation is identical to Slow Memory Mode, Parallel Read. See Figure 15 timing diagram and Table 3 data bus status. At the end of conversion the low data byte (DB7 . . . DB0) is read from the ADC. A second Read operation with HBEN high, places the high byte on data outputs D3/11 . . . D0/8 and disables conversion start. Note the 4MSBs appear on data outputs D11 . . . D8 during the two Read operations above.

ROM Mode, Parallel Read (HBEN = Low)

The ROM Mode avoids placing a microprocessor into a Wait state. A conversion is started with a Read operation and the 12 bits of data from the previous conversion is available on data outputs D11 . . . D0/8 (see Figure 16 and Table 4). This data may be disregarded if not required. A second Read operation reads the new data (DB11 . . . DB0) and starts another conversion. A delay at least as long as the LTC1272 conversion time plus the 1µs minimum delay between conversions must be allowed between Read operations.

LTC1272

PPLICATI

HBEN

BUSY

DATA

HOLD

TRACK

I FOR ATIO

Figure 15. Slow Memory Mode, Two Byte Read Timing Diagram

CONV

OLD DATA

DB7-DB0

NEW DATA

DB7-DB0

NEW DATA

DB11-DB8

LTC1272 • TA17

Table 3. Slow Memory Mode, Two Byte Read Data Bus Status

Data Outputs D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8

First Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Second Read Low Low Low Low DB11 DB10 DB9 DB8

BUSY

DATA

HOLD

TRACK

OLD DATA DB11-DB0

CONV

NEW DATA

DB11-DB0

CONV

LTC1272 • TA18

Figure 16. ROM Mode, Parallel Read Timing Diagram

Table 4. ROM Mode, Parallel Read Data Bus Status

Data Outputs D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8

First Read (Old Data) DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Second Read DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LTC1272

PPLICATI

HBEN

BUSY

DATA

HOLD

TRACK

I FOR ATIO

OLD DATA

DB7-DB0

CONV

NEW DATA DB11-DB8

NEW DATA

DB7-DB0

LTC1272 • TA19

Figure 17. ROM Mode, Two Byte Read Timing Diagram

Table 5. ROM Mode, Two Byte Read Data Bus Status

Data Outputs D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8

First Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Second Read Low Low Low Low DB11 DB10 DB9 DB8 Third Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ROM Mode, Two Byte READ

As previously mentioned for a two byte read, only data outputs D7 . . . D0/8 are used. Conversion is started in the normal way with a Read operation and the data output status is the same as the ROM Mode, Parallel Read. See Figure 17 timing diagram and Table 5 data bus status. Two more Read operations are required to access the new

Microprocessor Interfacing

The LTC1272 is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. The HBEN input serves as a data byte select for 8-bit processors and is normally connected to the micropro-

cessor address bus. conversion result. A delay equal to the LTC1272 conversion time must be allowed between conversion start and the second data Read operation. The second Read operation, with HBEN high, disables conversion start and places the high byte (4 MSBs) on data outputs D3/11 . . . DO18. A third read operation accesses the low data byte (DB7 . . . DB0) and starts another conversion. The 4 MSB’s

MC68000 Microprocessor

Figure 18 shows a typical interface for the MC68000. The

LTC1272 is operating in the Slow Memory Mode. Assum-

ing the LTC1272 is located at address C000, then the

following single 16-bit Move instruction both starts a

conversion and reads the conversion result: appear on data outputs D11 . . . D8 during all three read

operations above.

Move.W $C000,D0

LTC1272

DATA BUS

LTC1272 • TA22

PORT ADDRESS BUS

D11

DEN

PA0

PA2

TMS32010

ADDRESS

DECODE

D0/8

D11

HBEN

LTC1272

LINEAR CIRCUITRY OMITTED FOR CLARITY

PPLICATI

A23

MC68000

DTACK

R/W

D11

ADDITIONAL PINS OMITTED FOR CLARITY

U S

I FOR ATIO

ADDRESS BUS

ADDRESS

DECODE

DATA BUS

CS BUSY

RD D11

D0/8

LTC1272

HBEN

LTC1272 • TA20

Figure 18. LTC1272 MC68000 Interface

At the beginning of the instruction cycle when the ADC address is selected, BUSY and CS assert DTACK, so that the MC68000 is forced into a Wait state. At the end of conversion BUSY returns high and the conversion result is placed in the D0 register of the microprocessor.

is accomplished with the single 16-bit Load instruction

below.

For the 8085A LHLD (B000) For the Z80 LDHL, (B000)

This is a two byte read instruction which loads the ADC

data (address B000) into the HL register pair. During the

first read operation, BUSY forces the microprocessor to

Wait for the LTC1272 conversion. No Wait states are

inserted during the second read operation when the mi-

croprocessor is reading the high data byte.

TMS32010 Microcomputer

Figure 20 shows an LTC1272 TMS32010 interface. The

LTC1272 is operating in the ROM Mode. The interface is

designed for a maximum TMS32010 clock frequency of

18MHz but will typically work over the full TMS32010

clock frequency range.

8085A, Z80 Microprocessor

Figure 19 shows a LTC1272 interface for the Z80 and 8085A. The LTC1272 is operating in the Slow Memory Mode and a two byte read is required. Not shown in the figure is the 8-bit latch required to demultiplex the 8085A common address/data bus. A0 is used to assert HBEN, so that an even address (HBEN = LOW) to the LTC1272 will start a conversion and read the low data byte. An odd address (HBEN = HIGH) will read the high data byte. This

A15

MREQ

Z80

8085A

WAIT

LINEAR CIRCUITRY OMITTED FOR CLARITY

D7 D0

Figure 19. LTC1272 8085A/Z80 Interface

ADDRESS BUS

ADDRESS

DECODE

DATA BUS

CS BUSY

RD D7

D0/8

HBEN

LTC1272

LTC1272 • TA21

The LTC1272 is mapped at a port address. The following

I/O instruction starts a conversion and reads the previous

conversion result into data memory.

IN A,PA (PA = PORT ADDRESS)

When conversion is complete, a second I/O instruction

reads the up-to-date data into memory and starts another

conversion. A delay at least as long as the ADC conversion

time must be allowed between I/O instructions.

Figure 20. LTC1272 TMS32010 Interface

LTC1272

PPLICATI

I FOR ATIO

Compatibility with the AD7572

Figure 21 shows the simple, single 5V configuration recommended for new designs with the LTC1272. If an AD7572 replacement or upgrade is desired, the LTC1272 can be plugged into an AD7572 socket with minor modifications. It can be used as a replacement or to upgrade with sample-and-hold, single supply operation and reduced power consumption.

The LTC1272, while consuming less power overall than the AD7572, draws more current from the 5V supply (it draws no power from the –15V supply). Also, a 1µs

LTC1272

2.42V V 

REF

OUTPUT

ANALOG INPUT

(0V TO 5V)

0.1µF

8 OR 12-BIT

PARALLEL

BUS

10µF



REF

AGND D11 (MSB) D10 D9 D8 D7 D6 D5 D4

DGND

BUSY

HBEN

CLK OUT

CLK IN

D0/8 D1/9

D2/10

D3/11

minimum time between conversions must be provided to allow the sample-and-hold to reacquire the analog input. Figure 22 shows that if the clock is synchronous with CS and RD, it is only necessary to short out the 10Ω series resistor and reverse the polarity of the 10µF bypass capacitor on the V

pin. The –15V supply is not required

REF

and can be removed, or, because there is no internal connection to pin 23, it can remain unmodified. The clock can be considered synchronous with CS and RD in cases where the LTC1272 CLK IN signal is derived from the same clock as the microprocessor reading the LTC1272.

10 F

µP CONTROL LINES

0.1 F*

FOR GROUNDING AND BYPASSING HINTS

SEE FIGURE 11 AND APPLICATION HINTS SECTION

Figure 21. Single 5V Supply, 3µs, 12-Bit Sampling ADC

LTC1272 • TA03

LTC1272

PPLICATI

2.42V V 

REF

OUTPUT

ANALOG INPUT

(0V TO 5V)

10µF

I FOR ATIO

LTC1272

REF

AGND D11 (MSB) D10 D9 D8 D7 D6 D5 D4 DGND

0.1µF

DATA

BUS

Ω

P

BUSY

HBEN

CLK OUT

CLK IN**

D0/8 D1/9

D2/10

D3/11

✝

P

CONTROL LINES

–15V

10 F

†

0.1 F

THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V

REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE 10 RESISTOR.Ω

THE ADC CLOCK SHOULD BE SYNCHRONIZED TO THE CONVERSION START SIGNALS (CS, RD) OR 1-2 LSBs OF OUTPUT CODE NOISE MAY OCCUR. DERIVING THE ADC CLOCK FROM THE P CLOCK IS ADEQUATE.

✝

THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.

0.1 F

10 F

LTC1272 • TA04

Figure 22. Plugging the LTC1272 into an AD7572 Socket Case 1: Clock Synchronous with CS and RD

If the clock signal for the AD7572 is derived from a separate crystal or other signal which is not synchronous with the microprocessor clock, then the signals need to be synchronized for the LTC1272 to achieve best analog performance (see Clock and Control Synchronization). The best way to synchronize these signals is to drive the CLK IN pin of the LTC1272 with a derivative of the processor clock, as mentioned above and shown in Figure

22. Another way, shown in Figure 23, is to use a flip-flop to synchronize the RD to the LTC1272 with the CLK IN signal. This method will work but has two disavantages

over the first: because the RD is delayed by the flip-flop, the actual conversion start and the enabling of the LTC1272’s BUSY and data outputs can take up to one CLK IN cycle to respond to a RD↓ convert command from the processor. The sampling of the analog input no longer occurs at the processor’s falling RD edge but may be delayed as much as one CLK IN cycle. Although the LTC1272 will still exhibit excellent DC performance, the flip-flop will introduce jitter into the sampling which may reduce the usefulness of this method for AC systems.

LTC1272

PPLICATI

2.42V V 

REF

OUTPUT

I FOR ATIO

ANALOG INPUT

(0V TO 5V)

10µF

0.1µF

P

DATA

BUS

THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V

REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE 10 RESISTOR.Ω

THE D FLIP-FLOP SYNCHRONIZES THE CONVERSION START SIGNAL (RD ) TO THE

ADC CLK SIGNAL TO PREVENT OUTPUT CODE NOISE WHICH OCCURS WITH

OUT

AN ASYNCHRONOUS CLOCK.

✝

THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.

Ω

REF

AGND D11 (MSB) D10 D9 D8 D7 D6 D5 D4 DGND

LTC1272

CLK OUT

CLK IN

V NC

BUSY

HBEN

D0/8 D1/9

D2/10

D3/11

✝

CS RD

ASYNCHRONOUS

0.1 F

EXTERNAL

CLOCK

➞

1/2

74HC74

CLK

D**

–15V

10 F

0.1 F

†

P

LTC1272 • TA05

CONTROL LINES

74HC04

➞

Figure 23. Plugging the LTC1272 into an AD7572 Socket Case 2: Clock Not Synchronous with CS and RD

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1272

PACKAGEDESCRIPTI

Dimensions in inches (millimeters) unless otherwise noted.

N Package

24-Lead Plastic DIP

1.265*

(32.131)

0.260 ± 0.010* (6.604 ± 0.254)

123456

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.025

0.325 –0.015

+0.635

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).

0.015

(0.381)

MIN

(3.175)

0.125

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.050 – 0.085

(1.27 – 2.159)

(2.540 ± 0.254)

24-Lead Plastic SOL

2223

0.100 ± 0.010

SO Package

0.045 – 0.065

(1.143 – 1.651)

2324

89101911 12

0.598 – 0.614

(15.190 – 15.600)

22 21 20 19 18

(NOTE 2)

151718

0.018 ± 0.003

(0.457 ± 0.076)

16 15

131416

0.065

(1.651)

TYP

N24 0594

1314

0.291 – 0.299

(7.391 – 7.595)

0.005

(0.127)

RAD MIN

0.009 – 0.013

(0.229 – 0.330)

(NOTE 2)

0.010 – 0.029

(0.254 – 0.737)

NOTE 1

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.

2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).

× 45°

0.016 – 0.050

(0.406 – 1.270)

0° – 8° TYP

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487

(408) 432-1900

●

FAX

: (408) 434-0507

●

TELEX

: 499-3977

NOTE 1

0.093 – 0.104

(2.362 – 2.642)

0.050

(1.270)

2345678

TYP

0.014 – 0.019

(0.356 – 0.482)

0.394 – 0.419

(10.007 – 10.643)

910

11 12

0.037 – 0.045

(0.940 – 1.143)

0.004 – 0.012

(0.102 – 0.305)

SOL24 0392

LT/GP 0694 5K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1994

Datasheet LTC1272-8CCN, LTC1272-8ACS, LTC1272-3CCS, LTC1272-3CCN, LTC1272-3ACS Datasheet (Linear Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual