Linear Technology LTC1272-8CCN, LTC1272-8ACS, LTC1272-3CCS, LTC1272-3CCN, LTC1272-3ACS Datasheet

LTC1272

FREQUENCY (kHz)

0

–140

AMPLITUDE (dB)

20 40 60 80

LTC1272 • TA02

–120

–100

–80

–60

–40

–20

0

100 120

S

(N+D)

= 72.1

12-Bit, 3µs, 250kHz

Sampling A/D Converter

EATU

F

■

AD7572 Pinout

■

12-Bit Resolution

■

3µs and 8µs Conversion Times

■

On-Chip Sample-and-Hold

■

Up to 250kHz Sample Rates

■

5V Single Supply Operation

■

No Negative Supply Required

■

On-Chip 25ppm/°C Reference

■

75mW (Typ) Power Consumption

■

24-Pin Narrow DIP and SOL Packages

■

ESD Protected on All Pins

PPLICATI

A

■

High Speed Data Acquisition

■

Digital Signal Processing (DSP)

■

Multiplexed Data Acquisition Systems

■

Single Supply Systems

RE

S

O

U
S

DUESCRIPTIO

The LTC1272 is a 3µs, 12-bit, successive approximation
sampling A/D converter. It has the same pinout as the
industry standard AD7572 and offers faster conversion
time, on-chip sample-and-hold, and single supply opera­tion. It uses LTBiCMOSTM switched-capacitor technology to
combine a high speed 12-bit ADC with a fast, accurate
sample-and-hold and a precision reference.

The LTC1272 operates with a single 5V supply but can also
accept the 5V/–15V supplies required by the AD7572 (Pin
23, the negative supply pin of the AD7572, is not connected
on the LTC1272). The LTC1272 has the same 0V to 5V input
range as the AD7572 but, to achieve single supply opera­tion, it provides a 2.42V reference output instead of the
–5.25V of the AD7572. It plugs in for the AD7572 if the
reference capacitor polarity is reversed and a 1µ s sample­and-hold acquisition time is allowed between conversions.

The output data can be read as a 12-bit word or as two
8-bit bytes. This allows easy interface to both 8-bit and
higher processors. The LTC1272 can be used with a
crystal or an external clock and comes in speed grades of
3µs and 8µs.

LTBiCMOS is a trademark of Linear Technology Corporation

A

PPLICATITYPICAL

Single 5V Supply, 3µs, 12-Bit Sampling ADC

ANALOG INPUT

2.42V
V 

REF

OUTPUT

(0V TO 5V)

+

0.1µF

8 OR 12-BIT

PARALLEL

BUS

10µF



LTC1272

A

IN

V

REF

AGND
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND

O

V

NC

BUSY

RD

HBEN

CLK OUT

CLK IN

D0/8
D1/9

D2/10

D3/11

U

DD

CS

µ

10 F

P

µ

CONTROL
LINES

+

LTC1272 • TA01

1024 Point FFT, fS = 250kHz, fIN = 10kHz

5V

µ

0.1 F

1

LTC1272

A

W

O

LUTEXI T

S

A

WUW

ARB

U
G

I

S

(Notes 1 and 2)

Supply Voltage (VDD)................................................. 6V

Analog Input Voltage (Note 3) ...................–0.3V to 15V

Digital Input Voltage ..................................–0.3V to 12V

Digital Output Voltage.................... –0.3V to VDD + 0.3V

Power Dissipation.............................................. 500mW

PACKAGE

1

A

IN

2

V

REF

AGND

3

(MSB) D11

4

D10

5
6

D9

7

D8
D7
D6

9

10

D5

11

D4

DGND

24-LEAD PLASTIC DIP

T

JMAX

= 110°C, θJA = 100°C/W

/

O

RDER I FOR ATIO

TOP VIEW

24

V

DD

23

NC

22

BUSY

21

N PACKAGE

20
19
18
178
16
15
14
1312

CS
RD
HBEN
CLK OUT
CLK IN
D0/8
D1/9
D2/10
D3/11

(MSB) D11

WU

1

A

IN

2

V

REF

AGND

3
4

D10

5
6

D9

7

D8
D7
D6

9

10

D5

11

D4

DGND

T

JMAX

U

TOP VIEW

S PACKAGE

24-LEAD PLASTIC SOL

= 110°C, θJA = 130°C/W

Operating Temperature Range

LTC1272-XAC, CC ................................. 0°C to 70°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART NUMBER

24

V
23
22
21
20
19
18
178
16
15
14
1312

DD

NC

BUSY

CS

RD

HBEN

CLK OUT

CLK IN

D0/8

D1/9

D2/10

D3/11

CONVERSION CONVERSION
TIME = 3µs TIME = 8µs

LTC1272-3ACN LTC1272-8ACN
LTC1272-3CCN LTC1272-8CCN

S PACKAGE ONLY

LTC1272-3ACS LTC1272-8ACS
LTC1272-3CCS LTC1272-8CCS

Consult factory for Industrial and Military grade parts.

U

CO

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 12 Bits
Integral Linearity Error (Note 5) ● ±1/2 ±1 LSB
Differential Linearity Error ● ±1 ±1 LSB
Offset Error ±3 ±4 LSB

Gain Error ±10 ±15 LSB
Full-Scale Tempco I

VERTER

CCHARA TERIST

(Reference) = 0 ● ±5 ±25 ±10 ±45 ppm/°C

OUT

ICS

With Internal Reference (Note 4)

LTC1272-XA LTC1272-XC

● ±4 ±6 LSB

2

LTC1272

UUU

I TER AL REFERE CE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

V

Output Voltage (Note 6) I

REF

V

Output Tempco I

REF

V

Line Regulation 4.75V ≤ VDD ≤ 5.25V, I

REF

V

Load Regulation (Sourcing Current) 0 ≤ I

REF

= 0 2.400 2.420 2.440 2.400 2.420 2.440 V

OUT

= 0 ● 5 25 10 45 ppm/°C

OUT

= 0 0.01 0.01 LSB/V

OUT

 ≤ 1mA 2 2 LSB/mA

OUT

(Note 4)

LTC1272-XA LTC1272-XC

U

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

V

OH

V

OL

I

OZ

C

OZ

I

SOURCE

I

SINK

I

DD

P

D

High Level Input Voltage CS, RD, HBEN, CLK IN VDD = 5.25V ● 2.4 V
Low Level Input Voltage CS, RD, HBEN, CLK IN VDD = 4.75V ● 0.8 V
Input Current CS, RD, HBEN VIN = 0V to V
Input Current CLK IN VIN = 0V to V
High Level Output Voltage All Logic Outputs VDD = 4.75V I

I
Low Level Output Voltage All Logic Outputs VDD = 4.75V, I
High-Z Output Leakage D11-D0/8 V
High-Z Output Capacitance (Note 7) ● 15 pF
Output Source Current V
Output Sink Current V
Positive Supply Current CS = RD = VDD, AIN = 5V ● 15 30 mA
Power Dissipation 75 mW

OUT

OUT

OUT

DD

DD

= –10µA 4.7 V

OUT

= –200µA ● 4.0 V

OUT

= 1.6mA ● 0.4 V

OUT

= 0V to V

= 0V –10 mA
= V

DD

DD

(Note 4)

LTC1272-XA/C

● ±10 µA

● ±20 µA

● ±10 µA

10 mA

W

U

IC

DY

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion Ratio 10kHz Input Signal 72 dB
THD Total Harmonic Distortion (Up to 5th Harmonic) 10kHz Input Signal –82 dB

U

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V
IINInput Current ● 3.5 mA
C
t

LOG

IN

IN

ACQ

ACCURACY

Peak Harmonic or Spurious Noise 10kHz Input Signal – 82 dB

U
PUT

IA

Input Voltage Range 4.75V ≤ VDD ≤ 5.25V ● 05V

Input Capacitance 50 pF
Sample-and-Hold Acquisition Time ● 0.45 1 µs

(Note 4)

(Note 4) f

= 250kHz (LTC1272-3), 111kHz (LTC1272-8)

SAMPLE

LTC1272-XA/C

LTC1272-XA/B/C

3

LTC1272

UW

CCHARA TERIST

GTI

I

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

CONV

CS to RD Setup Time ● 0ns
RD to BUSY Delay CL = 50pF 80 190 ns

Data Access Time After RD↓ CL = 20pF 50 90 ns

RD Pulse Width t

CS to RD Hold Time ● 0ns
Data Setup Time After BUSY 40 70 ns

Bus Relinquish Time 20 30 75 ns

HBEN to RD Setup Time ● 0ns
HBEN to RD Hold Time ● 0ns
Delay Between RD Operations ● 200 ns
Delay Between Conversions 1 µs
Aperture Delay of Sample and Hold Jitter <50ps 25 ns
CLK to BUSY Delay 80 170 ns

Conversion Time ● 12 13 CLK

ICS

(Note 8)

LTC1272-XA/C

COM Grade ● 230 ns

COM Grade ● 110 ns

CL = 100pF 70 125 ns

COM Grade ● 150 ns

COM Grade ● t

COM Grade ● 90 ns

COM Grade ● 20 85 ns

COM Grade ● 220 ns

3
3

ns
ns

CYCLES

The ● indicates specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND and
AGND wired together, unless otherwise noted.

Note 3: When the analog input voltage is taken below ground it will be
clamped by an internal diode. This product can handle, with no external
diode, input currents of greater than 60mA below ground without latch-up.

VDD = 5V, f

Note 4:
LTC1272-8, t
performance, the LTC1272 clock should be synchronized to the RD and
CS control inputs with at least 40ns separating convert start from the
nearest clock edge.

r

= 4MHz for LTC1272-3, and 1.6MHz for

CLK

= tf = 5ns unless otherwise specified. For best analog

Note 5: Linearity error is specified between the actual end points of the
A/D transfer curve.

Note 6: The LTC1272 has the same 0V to 5V input range as the AD7572
but, to achieve single supply operation, it provides a 2.42V reference
output instead of the –5.25V of the AD7572. This requires that the polarity
of the reference bypass capacitor be reversed when plugging an LTC1272
into an AD7572 socket.

Note 7: Guaranteed by design, not subject to test.
Note 8: V

ensure compliance. All input control signals are specified with t
(10% to 90% of 5V) and timed from a voltage level of 1.6V. See Figures 13
through 17.

= 5V. Timing specifications are sample tested at 25°C to

DD

= tf = 5ns

r

4

LTC1272

U

PI

AIN (Pin 1): Analog Input, 0V to 5V Unipolar Input.
V

an AD7572 socket, reverse the reference bypass capacitor
polarity and short the 10Ω series resistor.

AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 4-11): Three-State Data Outputs.
DGND (Pin 12): Digital Ground.
D3/11 to D0/8 (Pins 13-16): Three-State Data Outputs.
CLK IN (Pin 17): Clock Input. An external TTL/CMOS

compatible clock may be applied to this pin or a crystal can
be connected between CLK IN and CLK OUT.

CLK OUT (Pin 18): Clock Output. An inverted CLK IN signal
appears at this pin.

FUUC

(Pin 2): 2.42V Reference Output. When plugging into

REF

TI

O

U
S

HBEN (Pin 19): High Byte Enable Input. This pin is used to
multiplex the internal 12-bit conversion result into the
lower bit outputs (D7 to D0/8). See table below. HBEN also
disables conversion starts when HIGH.

RD (Pin 20): Read Input. This active low signal starts a
conversion when CS and HBEN are low. RD also enables
the output drivers when CS is low.

CS (Pin 21): The Chip Select Input must be low for the ADC
to recognize RD and HBEN inputs.

BUSY (Pin 22): The BUSY Output is low when a conver­sion is in progress.

NC (Pin 23): Not Connected Internally. The LTC1272 does
not require negative supply. This pin can accommodate
the –15V required by the AD7572 without problems.

VDD (Pin 24): Positive Supply, 5V.

Data Bus Output, CS and RD = LOW

Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16

MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8

*D11...D0/8 are the ADC data output pins.

DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.

UW

LPER

F

O

R

ATYPICA

INL ERROR (LSBs)

CCHARA TERIST

E

C

Integral Nonlinearity

1.0
VDD = 5V

= 4MHz

f

CLK

0.5

0

–0.5

ICS

–1.0

0

512 1024 4096

0

1536 2048 2560 3072 3584

CODE

LTC1272 • TPC01

5

LTC1272

TEMPERATURE (°C)

–55

2

CLOCK FREQUENCY (MHz)

3

4

5

6

7

8

–25 25 50 125

LT1272 • TPC05

0 75 100

UW

LPER

F

O

R

ATYPICA

VDD Supply Current vs Minimum Clock Frequency vs Maximum Clock Frequency vs
Temperature Temperature Temperature

30

VDD = 5V

= 4MHz

f

CLK

25

(mA)

DD

20

CCHARA TERIST

E

C

Differential Nonlinearity

1.0
VDD = 5V

= 4MHz

f

CLK

0.5

0

INL ERROR (LSBs)

–0.5

–1.0

0

512 1024 4096

0

600

VDD = 5V

500

400

ICS

1536 2048 2560 3072 3584

CODE

LTC1272 • TPC02

15

10

SUPPLY CURRENT, I

DD

5

V

0

–55

0 75 100

–25 25 50 125

TEMPERATURE (°C)

V

REF

2.435

2.430

2.425

(V)

2.420

REF

V

2.415

2.410

2.405
–5

vs I

–4 –2 –1 2

LT1272 • TPC03

(mA) LTC1272 ENOBs* vs Frequency

LOAD

–3 0 1

IL (mA)

300

200

CLOCK FREQUENCY (kHz)

100

0

–25 25 50 125

–55

LT1272 • TPC06

0 75 100

TEMPERATURE (°C)

LT1272 • TPC04

*EFFECTIVE NUMBER OF BITS, ENOBs =

12
11

10

ENOBs*

9
8

7
6
5
4
3
2

fS = 250kHz

1

= 5V

V

DD

0

0

40 100

20 60 80 120

fIN (kHz)

LT1272 • TPC07

S/(N + D) – 1.76dB

6.02

6