The LT®8330 is a current mode DC/DC converter capable
of generating either positive or negative output voltages
using a single feedback pin. It can be configured as a
boost, SEPIC or inverting converter consuming as low as
6µA of quiescent current. Low ripple Burst Mode opera
tion maintains high efficiency down to very low output
currents while keeping
the output
ripple below 15mV in
a typical application. The internally compensated current
mode architecture results in stable operation over a wide
range of input and output voltages. Integrated soft-start
and frequency foldback functions are included to control
inductor current during start-up. The 2MHz operation
combined with small package options, enables low cost,
area efficient solutions.
L, LT, LTC , LT M, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
DDB PACKAGE
θ
Operating Junction Temperature (Note 3)
LT8330E, LT8330I ............................. –40°C to 125°C
LT8330H ............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
TOP VIEW
1
SW
2
GND
3
FBX
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
= 125°C/W, θJC = 102°C/W
θ
JA
6
V
5
INTV
4
EN/UVLO
IN
CC
orDer inForMaTion
(http://www.linear.com/product/LT8330#orderinfo)
LEAD FREE FINISHTAPE AND REELPART MARKINGPACKAGE DESCRIPTIONTEMPERATURE RANGE
LT8330ES6#PBFLT8330ES6#TRPBFLTGMQ6-Lead Plastic TSOT-23–40°C to 125°C
LT8330IS6#PBFLT8330IS6#TRPBFLTGMQ6-Lead Plastic TSOT-23–40°C to 125°C
LT8330HS6#PBFLT8330HS6#TRPBFLTGMQ6-Lead Plastic TSOT-23–40°C to 150°C
LT8330EDDB#PBFLT8330EDDB#TRPBFLGRC8-Lead (3mm × 2mm) Plastic DFN–40°C to 125°C
LT8330IDDB#PBFLT8330IDDB#TRPBFLGRC8-Lead (3mm × 2mm) Plastic DFN–40°C to 125°C
LT8330HDDB#PBFLT8330HDDB#TRPBFLGRC8-Lead (3mm × 2mm) Plastic DFN–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
8330fa
For more information www.linear.com/LT8330
Page 3
LT8330
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, EN/UVLO = 12V unless otherwise noted.
PARAMETERCONDITIONSMINTYPMAXUNITS
Operating Voltage Range
V
IN
Quiescent Current at ShutdownV
V
IN
V
Quiescent CurrentSleep Mode, Not Switching
IN
EN/UVLO
V
EN/UVLO
= 0.2V
= 1.5V
Active Mode, Not Switching
FBX Regulation
FBX Regulation VoltageFBX > 0V
FBX < 0V
FBX Line RegulationFBX > 0V, 3V < V
FBX < 0V, 3V < V
< 40V
IN
< 40V
IN
FBX Pin CurrentFBX = 1.6V, –0.8V
Oscillator
Switching Frequency (f
Minimum On-TimeV
Minimum Off-TimeV
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: INTV
cannot be externally driven. No additional components or
CC
loading is allowed on this pin.
Note 3: The LT8330E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8330I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT8330H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
Note 4: The IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime.
For more information www.linear.com/LT8330
8330fa
3
Page 4
LT8330
VIN = 12V
JUNCTION TEMPERATURE (°C)
–50
–250255075
100
125
150
175
1.570
1.580
1.590
1.600
1.610
1.620
1.630
8330 G01
VIN = 12V
JUNCTION TEMPERATURE (°C)
–50
–250255075
100
125
150
175
–0.815
–0.810
–0.805
–0.800
–0.795
–0.790
–0.785
8330 G02
VIN = 24V
JUNCTION TEMPERATURE (°C)
–50
–250255075
100
125
150
175
1.90
1.92
1.94
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
8330 G04
VIN (V)
0510152025303540
45
1.85
1.90
1.95
2.00
2.05
2.10
2.15
8330 G05
VIN = 24V
FBX VOLTAGE (V)
–0.8
–0.4
0.0
0.4
0.8
1.2
1.6
0255075100
125
NORMALIZED SWITCHING FREQUENCY (%)
8330 G06
VIN = 12V
DUTY CYCLE (%)
020406080
100
1.00
1.10
1.20
1.30
1.40
SWITCH CURRENT LIMIT (A)
8330 G07
VIN = 24V
JUNCTION TEMPERATURE (°C)
–50
–250255075
100
125
150
175
30
40
50
60
70
80
90
100
8330 G08
VIN = 24V
JUNCTION TEMPERATURE (°C)
–50
–250255075
100
125
150
1753035
4045505560
MINIMUM OFF–TIME (ns)
8330 G09
VIN = 12V
EN/UVLO RISING (TURN-ON)
EN/UVLO FALLING (TURN-OFF)
JUNCTION TEMPERATURE (°C)
–50
–250255075
100
125
150
175
1.54
1.56
1.58
1.60
1.62
1.64
1.66
1.68
1.70
1.72
1.74
EN/UVLO PIN VOLTAGE (V)
8330 G03
Typical perForMance characTerisTics
FBX Positive Regulation Voltage
vs Temperature
FBX Negative Regulation Voltage
vs Temperature
Switching Frequency
vs TemperatureSwitching Frequency vs V
EN/UVLO Pin Thresholds
vs Temperature
Normalized Switching Frequency
IN
vs FBX Voltage
Switch Current Limit vs Duty
Cycle
4
Switch Minimum On-Time
vs Temperature
For more information www.linear.com/LT8330
Switch Minimum Off-Time
vs Temperature
8330fa
Page 5
Typical perForMance characTerisTics
VIN = 12V
JUNCTION TEMPERATURE (°C)
–50
–250255075
100
125
150
175
0
1.25
2.50
3.75
5.00
6.25
7.50
8.75
10.00
V
8330 G10
VIN = 12V
JUNCTION TEMPERATURE (°C)
–50
–250255075
100
125
150
175
600
650
700
750
800
850
900
950
1000
V
8330 G11
VIN = 12V
V
OUT
= 48V
FRONT PAGE APPLICATION
LOAD CURRENT (mA)
010203040
50
0
0.5
1.0
1.5
2.0
2.5
8330 G12
VIN = 12V, V
OUT
= 48V, I
LOAD
= 135mA
1µs/DIV
FRONT PAGE APPLICATION
VSW20V/DIV
I
L
500mA/DIV
8330 G13
VIN = 12V, V
OUT
= 48V, I
LOAD
= 20mA
1µs/DIV
FRONT PAGE APPLICATION
VSW20V/DIV
8330 G14
I
L
500mA/DIV
VIN = 12V, V
OUT
= 48V, I
LOAD
= 2mA
1µs/DIV
FRONT PAGE APPLICATION
VSW20V/DIV
8330 G15
I
L
500mA/DIV
FRONT PAGE APPLICATION
VIN = 12V
V
OUT
= 48V
100µs/DIV
V
OUT
500mV/DIV
I
L
100mA/DIV
8330 G16
FRONT PAGE APPLICATION
VIN = 12V
V
OUT
= 48V
100µs/DIV
V
OUT
500mV/DIV
I
L
100mA/DIV
8330 G17
LT8330
Pin Current (Sleep Mode, Not
V
IN
Switching) vs Temperature
Switching Waveforms
(in CCM)
VIN Pin Current (Active Mode, Not
Switching) vs TemperatureBurst Frequency vs Load Current
Switching Waveforms
(in DCM/Light Burst Mode)
Switching Waveforms
(in Deep Burst Mode)
V
Transient Response: Load
OUT
Current Transients from 67.5mA to
135mA to 67.5mA
V
OUT
Current Transients from 5mA to
135mA to 5mA
For more information www.linear.com/LT8330
Transient Response: Load
8330fa
5
Page 6
LT8330
pin FuncTions
EN/UVLO: Shutdown and Undervoltage Detect Pin. The
LT8330 is shut down when this pin is low and active
when this pin is high. Below an accurate 1.6V threshold
the part enters undervoltage lockout and stops switching.
This allows an undervoltage lockout (UVLO) threshold to
be programmed for system input voltage by resistively
dividing down system input voltage to the EN/UVLO pin.
An 80mV pin hysteresis ensures part switching resumes
when the pin exceeds 1.68V. EN/UVLO pin voltage below
0.2V reduces V
UVLO features are not required, the pin can be tied directly
to system input.
FBX: Voltage Regulation Feedback Pin for Positive or
Negative Outputs. Connect this pin to a resistor divider
between the output and GND. FBX reduces the switching
frequency during start-up and fault conditions when FBX
is close to GND.
current below 1µA. If shutdown and
IN
GND: Ground Connection for the LT8330. The DFN pack
age has the best thermal performance due to an exposed
pad (Pin
pad must be soldered to a ground plane. Pin 5 of the DFN
package (and Pin 2 of the TSOT package) should also be
connected to a ground plane. The ground plane should be
connected to large copper layers to spread heat dissipated
by the LT8330.
INTV
INTV
ceramic capacitor to ground. No additional components
or loading is allowed on this pin.
NC: No Internal Connection. Tie directly to local ground.
SW: The Output of Internal Power Switch. Minimize the
metal trace area connected to this pin to reduce EMI.
V
IN
sure to place the positive terminal of the input capacitor as
close as possible to the V
as close as possible to the GND pin.
9) on the bottom of the package. This exposed
: Regulated 3V Supply for Internal Loads. The
CC
pin must be bypassed with a minimum 1µF low ESR
CC
: Input Supply. This pin must be locally bypassed. Be
pin, and the negative terminal
IN
-
6
8330fa
For more information www.linear.com/LT8330
Page 7
block DiagraM
LT8330
M1
R
SW
INTV
SENSE
D
V
OUT
C
OUT
CC
C
VCC
A3
A4
L
DRIVER
–
+
+
–
I
LIMIT
V
IN
R4
OPT
INTERNAL
REFERENCE
UVLO
A6
UVLO
TJ > 170°C
INTV
CC
UVLO
FREQUENCY
FOLDBACK
ERROR AMP
SELECT
ERROR
AMP
+
R1
V
OUT
FBX
R2
1.6V
–0.8V
–
+
–
A1
ERROR
A2
AMP
1.68V(+)
+
1.6V(–)
–
R3
OPT
EN/UVLO
SLOPE
VC
OSCILLATOR
2MHz
BURST
DETECT
SLOPE
C
IN
3V REGULATOR
–
A5
+
PWM COMPARATOR
V
IN
SWITCH
LOGIC
UVLO
SOFT-START
M2
For more information www.linear.com/LT8330
GND
8330 BD
8330fa
7
Page 8
LT8330
VIN = 12V
V
OUT
= 48V
FRONT PAGE APPLICATION
LOAD CURRENT (mA)
010203040
50
0
0.5
1.0
1.5
2.0
2.5
8330 F01
operaTion
The LT8330 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block
.
Diagram
An internal 2MHz oscillator turns on the internal
power switch at the beginning of each clock cycle. Current
in the inductor then increases until the current comparator
trips and turns off the power switch. The peak inductor
current at which the switch turns off is controlled by the
voltage on the internal VC node. The error amplifier servos
the VC node by comparing the voltage on the FBX pin with
an internal reference voltage (1.60V or –0.80V, depending
on the chosen topology). When the load current increases
it causes a reduction in the FBX pin voltage relative to
the internal reference. This causes the error amplifier to
increase the VC voltage until the new load current is satis
fied. In this manner, the error amplifier sets the correct
peak switch current level to keep the output in regulation.
LT8330 is capable of generating either a positive or
The
negative output voltage with a single FBX pin. It can be
configured as a boost or SEPIC converter to generate a
positive output voltage, or as an inverting converter to
generate a negative output voltage. When configured as
a boost converter, as shown in the Block Diagram, the
FBX pin is pulled up to the internal bias voltage of 1.60V
by a voltage divider (R1 and R2) connected from V
OUT
to GND. Amplifier A2 becomes inactive and amplifier A1
performs (inverting) amplification from FBX to VC. When
the LT8330 is in an inverting configuration, the FBX pin
is pulled down to –0.80V by a voltage divider from V
OUT
to GND. Amplifier A1 becomes inactive and amplifier A2
performs (non-inverting) amplification from FBX to VC.
If the EN/UVLO pin voltage is below 1.6V, the LT8330
enters undervoltage lockout (UVLO), and stops switching.
When the EN/UVLO pin voltage is above 1.68V (typical),
IN
.
the LT8330 resumes switching. If the EN/UVLO pin volt
age is below 0.2V, the LT8330 only draws 1µA from V
To optimize efficiency at light loads, the LT8330 operates
in Burst Mode operation in light load situations. Between
bursts, all circuitry associated with controlling the output
switch is shut down, reducing the input supply current
to 6µA.
applicaTions inForMaTion
ACHIEVING ULTRALOW QUIESCENT CURRENT
To enhance efficiency at light loads the LT8330 uses
a low ripple Burst Mode architecture. This keeps the
output capacitor charged to the desired output voltage
while minimizing the input quiescent current and output
ripple. In Burst Mode operation the LT8330 delivers single
small pulses of current to the output capacitor followed
by sleep periods where the output power is supplied by
the output capacitor. While in sleep mode the LT8330
consumes only 6µA.
As the output load decreases, the frequency of single cur
rent pulses decreases (see Figure 1) and the percentage
of time the LT8330
is in sleep mode increases, resulting
in much higher light load efficiency than for typical con
verters. To optimize the quiescent current performance
at light loads, the current in the feedback resistor divider
must be minimized as it appears to the output as load
current. In addition, all possible leakage currents from
-
-
the output should also be minimized as they all add to the
equivalent output load. The largest contributor to leakage
current can be due to the reverse biased leakage of the
Schottky diode (see Diode Selection in the Applications
Information section).
Figure 1. Burst Frequency vs Load Current
8330fa
8
For more information www.linear.com/LT8330
Page 9
applicaTions inForMaTion
5µs/DIV
V
OUT
5mV/DIV
I
L
200mA/DIV
8330 F02
LT8330
While in Burst Mode operation the current limit of the
switch is approximately 240mA resulting in the output
voltage ripple shown in Figure 2. Increasing the output
capacitance will decrease the output ripple proportionally.
As the output load ramps upward from zero the switch
-
ing frequency will increase but only up to the fixed 2MHz
1.
defined by the internal oscillator as shown in Figure
The
output load at which the LT8330 reaches the fixed 2MHz
frequency varies based on input voltage, output voltage,
and inductor choice.
Figure 2. Burst Mode Operation
PROGRAMMING INPUT TURN-ON AND TURN-OFF
THRESHOLDS WITH EN/UVLO PIN
The EN/UVLO pin voltage controls whether the LT8330 is
enabled or is in a shutdown state. A 1.6V reference and a
comparator A6 with built-in hysteresis (typical 80mV) allow
the user to accurately program the system input voltage
at which the IC turns on and off (see the Block Diagram).
The typical input falling and rising threshold voltages can
be calculated by the following equations:
V
IN(FALLING,UVLO(–))
V
IN(RISING, UVLO(+))
current is reduced below 1µA when the EN/UVLO pin
V
IN
= 1.60 • (R3+R4)/R4
= 1.68 • (R3+R4)/R4
voltage is less than 0.2V. The EN/UVLO pin can be connected directly to the input supply V
for always-enabled
IN
operation. A logic input can also control the EN/UVLO pin.
When operating in Burst Mode operation for light load
currents, the current through the R3 and R4 network can
easily be greater than the supply current consumed by the
LT8330. Therefore, R3 and R4 should be large enough to
minimize their effect on efficiency at light loads.
INTV
A low dropout (LDO) linear regulator, supplied from V
produces a 3V supply at the INTV
REGULATOR
CC
pin. A minimum 1µF
CC
IN
,
low ESR ceramic capacitor must be used to bypass the
INTV
pin to ground to supply the high transient currents
CC
required by the internal power MOSFET gate driver.
No additional components or loading is allowed on this
pin. The INTV
switching) is typically 2.6V. The INTV
rising threshold (to allow soft start and
CC
falling threshold
CC
(to stop switching and reset soft start) is typically 2.5V.
DUTY CYCLE CONSIDERATION
The LT8330 minimum on-time, minimum off-time and
switching frequency (f
) define the allowable minimum
OSC
and maximum duty cycles of the converter (see Minimum
On-Time, Minimum Off-Time, and Switching Frequency
in the Electrical Characteristics table).
Minimum Allowable Duty Cycle =
Minimum On-Time
(MAX)
• f
OSC(MAX)
Maximum Allowable Duty Cycle =
1 – Minimum Off-Time
(MAX)
• f
OSC(MAX)
The required switch duty cycle range for a Boost converter
operating in continuous conduction mode (CCM) can be
calculated as:
D
MIN
D
MAX
where V
= 1– V
IN(MAX)
= 1– V
is the diode forward voltage drop. If the above
D
IN(MIN)
/(V
/(V
OUT
OUT
+ VD)
+ VD)
duty cycle calculations for a given application violate the
minimum and/or maximum allowed duty cycles for the
LT8330, operation in discontinuous conduction mode
(DCM) might provide a solution. For the same V
levels, operation in DCM does not demand as low a
V
OUT
and
IN
duty cycle as in CCM. DCM also allows higher duty cycle
operation than CCM. The additional advantage of DCM is
the removal of the limitations to inductor value and duty
cycle required to avoid sub-harmonic oscillations and the
right half plane zero (RHPZ). While DCM provides these
benefits, the trade-off is higher inductor peak current, lower
available output power and reduced efficiency.
8330fa
For more information www.linear.com/LT8330
9
Page 10
LT8330
500µs/DIV
I
L
500mA/DIV
V
OUT
20V/DIV
8330 F03
applicaTions inForMaTion
SETTING THE OUTPUT VOLTAGE
The output voltage is programmed with a resistor divider
from the output to the FBX pin. Choose the resistor values
for a positive output voltage according to:
R1 = R2 • (V
/1.60V – 1)
OUT
Choose the resistor values for a negative output voltage
according to:
R1 = R2 • (|V
|/0.80V – 1)
OUT
The locations of R1 and R2 are shown in the Block Diagram. 1%
resistors are recommended to maintain output
voltage accuracy.
Higher-value FBX divider resistors result in the lowest input
quiescent current and highest light-load efficiency. FBX
divider resistors R1 and R2 are usually in the range from
25k to 1M. Most applications use a phase-lead capacitor
from V
to FBX in combination with high-value FBX
OUT
divider resistors (see Compensation in the Applications
Information section).
SOFT-START
The LT8330 contains several features to limit peak switch
currents and output voltage (V
) overshoot during
OUT
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since V
is far from its final value,
OUT
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
will reset the internal soft-start function and will pull down
VC. Once all faults are removed, the LT8330 will soft-start
VC and hence inductor peak current.
FREQUENCY FOLDBACK
During start-up or fault conditions in which V
OUT
is very
low, extremely small duty cycles may be required to
maintain control of inductor peak current. The minimum
on-time limitation of the power switch might prevent these
low duty cycles from being achievable. In this scenario
inductor current rise will exceed inductor current fall during
each cycle, causing inductor current to ‘walk up’ beyond
the switch current limit. The LT8330 provides protection
from this by folding back switching frequency whenever
FBX pin is close to GND (low V
levels). This frequency
OUT
foldback provides a larger switch-off time, allowing inductor
current to fall enough each cycle (see Normalized Switch
ing Frequency vs FBX Voltage in the Typical Performance
Characteristics section).
The LT8330 addresses this mechanism with an internal
soft-start function. As shown in the Block Diagram, the
soft-start function controls the ramp of the power switch
current by controlling the ramp of VC through M2. This
allows the output capacitor to be charged gradually toward
its final value while limiting the start-up peak currents.
Figure 3
the first page T
shows the output voltage and supply current for
ypical Application. It can be seen that both
the output voltage and supply current come up gradually.
10
THERMAL LOCKOUT
If the LT8330 die temperature reaches 170°C (typical),
the part will stop switching and go into thermal lockout.
When the die temperature has dropped by 5°C (nominal),
the part will resume switching with a soft-started inductor
peak current.
For more information www.linear.com/LT8330
8330fa
Page 11
applicaTions inForMaTion
LT8330
SWITCHING FREQUENCY AND INDUCTOR SELECTION
The LT8330 switches at 2MHz, allowing small value induc-
H to
tors to be used. 0.68µ
10µH will usually suffice. Choose
an inductor that can handle at least 1.4A without saturating,
and ensure that the inductor has a low DCR (copper-wire
2
resistance) to minimize I
R power losses. Note that in
some applications, the current handling requirements of
the inductor can be lower, such as in the SEPIC topology
where each inductor only carries one-half of the total
switch current. For better efficiency, use similar valued
inductors with a larger volume. Many different sizes and
shapes are available from various manufacturers. Choose
a core material that has low losses at 2MHz, such as a
ferrite core. The final value chosen for the inductor should
not allow peak inductor currents to exceed 1A in steady
state at maximum load. Due to tolerances, be sure to ac
count for minimum possible inductance value, switching
frequency and converter efficiency
Table 1. Inductor Manufacturers
Sumida(847) 956-0666www.sumida.com
TDK(847) 803-6100www.tdk.com
Murata(714) 852-2001www.murata.com
Coilcraft(847) 639-6400www.coilcraft.com
Würth(605) 886-4385www.we-online.com
.
INPUT CAPACITOR
Bypass the input of the LT8330 circuit with a ceramic capacitor of X7R or X5R type placed as close as possible to
the V
and GND pins. Y5V types have poor performance
IN
over temperature and applied voltage, and should not be
used. A 4.7µF to 10µF ceramic capacitor is adequate to
bypass the LT8330 and will easily handle the ripple cur
rent. If the input power source has high impedance, or
there is significant inductance due to long wires or cables,
additional bulk capacitance may be necessar
y. This can
be provided with a low performance electrolytic capacitor.
A precaution regarding the ceramic input capacitor con
cerns the maximum input voltage rating of the LT8330.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality
(
under damped) tank cir
cuit. If the LT8330 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possibly
exceeding the LT8330’s voltage rating. This situation is
easily avoided (see Application Note 88).
OUTPUT CAPACITOR AND OUTPUT RIPPLE
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they are small and have extremely low ESR. Use X5R or
X7R types. This choice will provide low output ripple and
good transient response. A 4.7µF to 15µF output capacitor
is sufficient for most applications, but systems with very
low output currents may need only a 1µF or 2.2µF output
capacitor. Solid tantalum or OS-CON capacitor can be
used, but they will occupy more board area than a ceramic
and will have a higher ESR. Always use a capacitor with a
sufficient voltage rating.
COMPENSATION
The LT8330 is internally compensated. The decision to
use either low ESR (ceramic) capacitors or the higher
ESR (tantalum or OS-CON) capacitors, for the output
capacitor, can affect the stability of the overall system.
The ESR of any capacitor, along with the capacitance
itself, contributes a zero to the system. For the tantalum
and OS-CON capacitors, this zero is located at a lower
frequency due to the higher value of the ESR, while the
zero of a ceramic capacitor is at a much higher frequency
and can generally be ignored.
A phase lead zero can be intentionally introduced by placing
a capacitor in parallel with the resistor between V
OUT
and
FBX. By choosing the appropriate values for the resistor and
capacitor, the zero frequency can be designed to improve
the phase margin of the overall converter. The typical target
value for the zero frequency is between 30kHz to 60kHz.
A practical approach to compensation is to start with one
of the circuits in this data sheet that is similar to your ap
plication. Optimize performance by adjusting the output
capacitor and/
or the feed forward capacitor (connected
across the feedback resistor from output to FBX pin).
For more information www.linear.com/LT8330
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CERAMIC CAPACITORS
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT8330 due to their piezoelectric nature.
When in Burst Mode operation, the LT8330’s switching
frequency depends on the load current, and at very light
loads the LT8330 can excite the ceramic capacitor at audio
frequencies, generating audible noise. Since the LT8330
operates at a lower current limit during Burst Mode op
eration, the noise is typically very quiet to a casual ear.
If this is unacceptable, use a high performance tantalum
or electrolytic capacitor at the output. Low noise ceramic
capacitors are also available.
Table 2. Ceramic Capacitor Manufacturers
Taiyo Yuden(408) 573-4150www.t-yuden.com
AVX(803) 448-9411www.avxcorp.com
Murata(714) 852-2001www.murata.com
DIODE SELECTION
A Schottky diode is recommended for use with the LT8330.
Low leakage Schottky diodes are necessary when low
quiescent current is desired at low loads. The diode leakage
appears as an equivalent load at the output and should be
minimized. Choose Schottky diodes with sufficient reverse
voltage ratings for the target applications.
Table 3. Recommended Schottky Diodes
AVERAGE
FORWARD
CURRENT
PART NUMBER
PMEG6010CEJ≤1000≤6050NXP
PMEG6030EP≤3000≤60200NXP
(mA)
REVERSE
VOLTAGE
(V)
REVERSE
CURRENT
(µA)MANUFACTURER
LAYOUT HINTS
The high speed operation of the LT8330 demands careful attention to board layout. Careless layout will result in
formance degradation
per
. Figure 4a shows the recommended component placement for the ThinSOT package.
Figure 4b
shows the recommended component placement
for the DFN package. Note the vias under the exposed pad.
These should connect to a local ground plane for better
thermal performance.
V
OUT
D1
V
OUT
C2
GND
L1
1
2
3
FB
C3
6
5
4
R2
R1
C1
V
IN
C2
(VIN)
R4
R3
8330 F04a8330 F04b
V
OUT
GND
C3
V
OUT
FB
D1
L1
C4
R1
R2
1
8
2
7
3
6
4
5
R3
R4
(VIN)
C2
V
C1
IN
(a)(b)
Figure 4. Suggested Layout – (a) ThinSOT, (b) DFN
8330fa
12
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Page 13
applicaTions inForMaTion
V
V
IN
D
V
V
V
V
L1
L2
V
OUT
VINSW
FBX
GND
EN/UVLO
LT8330
V
IN
VCCINT
D1
CINC
OUT
C
DC
8330 F05
LT8330
THERMAL CONSIDERATIONS
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LT8330. The DFN package has the
best thermal performance due to an exposed pad (Pin 9)
on the bottom of the package. This exposed pad must be
soldered to a ground plane. Pin 5 of the DFN package (and
Pin 2 of the TSOT package) should also be connected to a
ground plane. The ground plane should be connected to
large copper layers to spread heat dissipated by the LT8330
and to further reduce the thermal resistance (θ
) values
JA
listed in the Pin Configuration section. Power dissipation
within the LT8330 (P
DISS_LT8330
) can be estimated by
subtracting the inductor and Schottky diode power losses
from the total power losses calculated in an efficiency
measurement. The junction temperature of LT8330 can
then be estimated by,
(LT8330) = TA + θJA • P
T
J
DISS_LT8330
ADDITIONAL TOPOLOGIES : SEPIC AND INVERTING
In addition to the Boost topology, the LT8330 can be
configured in a SEPIC or Inverting topology. SEPIC and
Inverting converters are analyzed below.
voltage (V
), the input voltage (VIN) and the diode
OUT
forward voltage (VD).
The maximum duty cycle (D
) occurs when the converter
MAX
operates at the minimum input voltage:
+
D
=
MAX
V
IN(MIN)
OUT
Conversely, the minimum duty cycle (D
+ V
OUT
D
+ V
D
) occurs when
MIN
the converter operates at the maximum input voltage:
+
+ V
D
OUT
MAX
+ V
D
and D
(MAX)
obey:
MIN
• f
OSC(MAX)
D
=
MIN
V
OUT
IN(MAX)
Be sure to check that D
< 1-Minimum Off-Time
D
MAX
and
> Minimum On-Time
D
MIN
where Minimum Off-Time, Minimum On-Time and f
(MAX)
• f
OSC(MAX)
OSC
are specified in the Electrical Characteristics table.
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
SEPIC CONVERTER APPLICATIONS
The LT8330 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 5. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
+
OUT
D
V
=
1−D
in continuous conduction mode (CCM).
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
As shown in Figure 5, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but can
Figure 5. LT8330 Configured in a SEPIC Topology
8330fa
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13
Page 14
LT8330
D
I
I
I
MAX
1
MAX
V
OSC
V
OSC
applicaTions inForMaTion
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
I
L1(MAX)(AVE)=IIN(MAX)(AVE)
I
L2(MAX)(AVE)
=I
O(MAX)
=I
O(MAX)
•
1−D
MAX
MAX
In a SEPIC converter, the switch current is equal to IL1 +
when the power switch is on, therefore, the maximum
I
L2
average switch current is defined as:
SW(MAX)(AVE)
=I
O(MAX)
•
=
1
1−D
L1(MAX)(AVE)
+
L2(MAX)(AVE)
and the peak switch current is:
⎛
⎞
c
I
SW(PEAK)
= 1+
⎜
⎝
• I
⎟
O(MAX)
⎠
2
•
1−D
The constant c in the preceding equations represents
the percentage peak-to-peak ripple current in the switch,
relative to I
SW(MAX)(AVE)
switch ripple current ∆I
SW
= c • I
SW(MAX)(AVE)
∆I
, as shown in Figure 6. Then, the
can be calculated by:
SW
The inductor ripple currents ∆IL1 and ∆IL2 are identical:
∆I
= ∆IL2 = 0.5 • ∆I
L1
SW
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
requires large inductances and reduces the current
∆I
L
loop gain (the converter will approach voltage mode).
Accepting larger values of ∆I
allows the use of low in-
L
ductances, but results in higher input current ripple and
greater core losses.
It is recommended that c falls in the
range of 0.2 to 0.6.
Due to the current limit of its internal power switch, the
LT8330 should be used in a SEPIC converter whose
maximum output current (I
) is less than the output
O(MAX)
current capability by a sufficient margin (10% or higher
is recommended):
I
O(MAX)
< (1 – D
) • (1A – 0.5 •∆ISW) • (0.9)
MAX
Given an operating input voltage range, and having chosen ripple current in the inductor, the inductor value (L1
2
and L
are independent) of the SEPIC converter can be
determined using the following equation:
L1= L2 =
IN(MIN)
0.5 • ∆ISW• f
• D
MAX
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 47µH.
By making L1 = L2, and winding them on the same core, the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
I
SW
I
SW(MAX)(AVE)
DT
S
Figure 6. The Switch Current Waveform of the SEPIC Converter
14
∆I
SW = χ • ISW(MAX)(AVE)
T
S
L =
IN(MIN)
∆ISW• f
This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:
t
= I
= I
8330 F06
I
I
L1(PEAK)
L2(PEAK)
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
For more information www.linear.com/LT8330
• D
L1(MAX)
L2(MAX)
MAX
+ 0.5 •∆I
+ 0.5 •∆I
L1
L2
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V
V
IN
D
applicaTions inForMaTion
V
V
V
V
+
LT8330
Based on the preceding equations, the user should choose
the inductors having sufficient saturation and RMS current ratings.
SEPIC Converter
T
o maximize efficiency, a fast switching diode with a low
: Output Diode Selection
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
It is recommended that the peak repetitive reverse voltage
rating V
is higher than V
RRM
OUT
+ V
IN(MAX)
by a safety
margin (a 10V safety margin is usually sufficient).
The power dissipated by the diode is:
P
D
= I
O(MAX)
• V
D
where VD is diode’s forward voltage drop, and the diode
junction temperature is:
= TA + PD • R
T
J
The R
used in this equation normally includes the R
θJA
θJA
θJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. T
must not
J
exceed the diode maximum junction temperature rating.
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPIC converter are similar to those of the boost converter.
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (C
DC
,
as shown in Figure 5) should be larger than the maximum
input voltage:
CDC
> V
IN(MAX)
V
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through C
approximately –I
flows during the on-time. The RMS
O
is IIN, while
DC
rating of the coupling capacitor is determined by the following equation:
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C
DC
.
INVERTING CONVERTER APPLICATIONS
The LT8330 can be configured as a dual-inductor inverting
topology, as shown in Figure 7. The V
−
OUT
D
V
= −
1−D
to VIN ratio is:
OUT
in continuous conduction mode (CCM).
C
SW
LT8330
+
GND
DC
L2
–
–
C
OUT
D1
V
OUT
+
+
8330 F07
L1
V
IN
C
IN
Figure 7. A Simplified Inverting Converter
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (V
The maximum duty cycle (D
) and the input voltage (VIN).
OUT
) occurs when the converter
MAX
has the minimum input voltage:
−
D
IN(MIN)
) occurs when
MIN
D
=
MAX
V
OUT
OUT
− VD− V
Conversely, the minimum duty cycle (D
the converter operates at the maximum input voltage :
−
D
IN(MAX)
OUT
OUT
− VD− V
D
=
MIN
V
+ V
V
I
RMS(CDC)>IO(MAX)
OUT
•
V
IN(MIN)
D
8330fa
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15
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LT8330
applicaTions inForMaTion
Be sure to check that D
< 1-Minimum Off-Time
D
MAX
MAX
and D
(MAX)
obey :
MIN
• f
OSC(MAX)
and
> Minimum On-Time
D
MIN
where Minimum Off-Time, Minimum On-Time and f
(MAX)
• f
OSC(MAX)
OSC
are specified in the Electrical Characteristics table.
Inverting Converter: Inductor, Output Diode and Input
Capacitor Selections
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those of
the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
converters for similar output ripples. This is due to the fact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
output capacitors are continuous. The output ripple voltage
is produced by the ripple current of L2 flowing through
the ESR and bulk capacitance of the output capacitor:
∆V
OUT(P–P)
⎛
= ∆IL2• ESR
⎜
⎝
COUT
+
8 • f • C
⎞
1
⎟
⎠
OUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output voltage ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
I
RMS(COUT)
> 0.3 •∆I
L2
Inverting Converter: Selecting the DC Coupling
Capacitor
The DC voltage rating of the DC coupling capacitor (C
DC
,
as shown in Figure 7) should be larger than the maximum
input voltage minus the output voltage (negative voltage):
V
CDC
> V
IN(MAX)
– V
OUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the following equation:
D
I
RMS(CDC)>IO(MAX)
MAX
•
1−D
MAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C
Please refer to http://www.linear.com/product/LT8330#packaging for the most recent package drawings.
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
0.61 ±0.05
(2 SIDES)
0.70 ±0.05
2.55 ±0.05
1.15 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
LT8330
3.00 ±0.10
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
2.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
0 – 0.05
R = 0.115
TYP
TYP
0.56 ±0.05
(2 SIDES)
0.25 ±0.05
BOTTOM VIEW—EXPOSED PAD
2.15 ±0.05
(2 SIDES)
0.40 ±0.10
85
14
0.50 BSC
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
(DDB8) DFN 0905 REV B
For more information www.linear.com/LT8330
8330fa
21
Page 22
LT8330
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
package DescripTion
Please refer to http://www.linear.com/product/LT8330#packaging for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
3.85 MAX
0.62
MAX
2.62 REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.95
REF
1.22 REF
1.4 MIN
0.20 BSC
DATUM ‘A’
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
0.30 – 0.50 REF
2.80 BSC
0.09 – 0.20
(NOTE 3)
1.50 – 1.75
(NOTE 4)
1.00 MAX
0.95 BSC
0.80 – 0.90
2.90 BSC
(NOTE 4)
PIN ONE ID
0.30 – 0.45
6 PLCS (NOTE 3)
0.01 – 0.10
1.90 BSC
S6 TSOT-23 0302
22
8330fa
For more information www.linear.com/LT8330
Page 23
LT8330
revision hisTory
REVDATEDESCRIPTIONPAGE NUMBER
A03/16Corrected V
Corrected Typographic Errors
Quiescent Current
IN
3
2, 22, 23
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.