CTRL Pin Adjusts High Side Current Sense Threshold
n
Low Shutdown Current: <1µA
n
Programmable Soft-Start
n
Available in the 36-Lead (5mm × 6mm) QFN Package
applicaTions
n
High Power LED
n
Battery Charger
n
Accurate Current Limited Voltage Regulator
80VIN, 80V
OUT
Constant-Current,
Constant-Voltage Converter
DescripTion
The LT®3956 is a DC/DC converter designed to operate as
a constant-current source and constant-voltage regulator.
It is ideally suited for driving high current LEDs. It features
an internal low side N-channel power MOSFET rated for
84V at 3.3A and driven from an internal regulated 7.15V
supply. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages. A ground referenced voltage FB pin
serves as the input for several LED protection features,
and also makes it possible for the converter to operate
as a constant-voltage source. A frequency adjust pin
allows the user to program the frequency from 100kHz
to 1MHz to optimize efficiency, performance or external
component size.
The LT3956 senses output current at the high side of the
LED string. High side current sensing is the most flexible
scheme for driving LEDs, allowing boost, buck mode or
buck-boost mode configuration. The PWM input provides
LED dimming ratios of up to 3000:1, and the CTRL input
provides additional analog dimming capability.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
True Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 7199560 and 7321203.
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, CTRL = 2V, PWM = 5V, unless otherwise noted.
PARAMETERCONDITIONSMINTYPMAXUNITS
VIN Minimum Operating VoltageVIN Tied to INTV
VIN Shutdown I
VIN Operating IQ (Not Switching)PWM = 0V1.41.7mA
V
REF
V
REF
Voltage–100µA ≤ I
Line Regulation4.5V ≤ VIN ≤ 80V0.006%/V
l
l
1.9652.002.045V
VREF
CC
≤ 0µA
Q
EN/UVLO = 0V
EN/UVLO = 1.15V
–40°C to 125°C
–40°C to 125°C
4.5V
0.11
5
µA
µA
3956f
2
Page 3
LT3956
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, CTRL = 2V, PWM = 5V, unless otherwise noted.
PARAMETERCONDITIONSMINTYPMAXUNITS
SW Pin LeakageSW = 48V510µA
SW Pin Current Limit
SW Pin Voltage DropI(SW) = 2A220mV
SS Pull-Up CurrentCurrent Out of Pin81013µA
Error Amplifier
Full-Scale Current Sense Threshold ( V
Current Sense Threshold at CTRL = 1V ( V
Current Sense Threshold at CTRL = 0.5V ( V
Current Sense Threshold at CTRL = 0.1V ( V
CTRL Range for Current Sense Threshold Adjustment01.1V
CTRL Input Bias CurrentCurrent Out of Pin, CTRL = 0V50100nA
Current Sense Amplifier Input Common Mode
Range ( V
ISP/ISN Short-Circuit Threshold (V
ISP/ISN Short-Circuit Fault Sensing Common Mode
Range ( V
ISP/ISN Input Bias Current (Combined)PWM = 5V (Active), ISP = ISN = 48V
LED Current Sense Amplifier g
VC Output Impedance1V < VC < 2V15000kΩ
VC Standby Input Bias CurrentPWM = 0V–2020nA
FB Regulation Voltage (VFB)ISP = ISN = 0V, 48V
FB Amplifier g
FB Pin Input Bias CurrentCurrent Out of Pin, FB = 1V40100nA
FB Voltage Loop Active ThresholdVMODE FallingV
INTVCC Regulation Voltage77.157.3V
Dropout (VIN – INTVCC)I
INTVCC Undervoltage Lockout
INTVCC Current Limit141725mA
INTVCC Current in ShutdownEN/UVLO = 0V, INTVCC = 7V812µA
ISN
ISN
)
(ISP–ISN)
)
m
m
)FB = 0V, ISP = 48V, CTRL ≥ 1.2V
(ISP–ISN)
)CTRL = 1V, FB = 0V, ISP = 48V
(ISP–ISN)
)CTRL = 0.5V
(ISP–ISN)
)CTRL = 0.1V, FB = 0V, ISP = 48V
(ISP–ISN)
)ISN = 0V300335370mV
PWM = 0V (Standby), ISP = ISN = 48V
FB = VFB, ISP = ISN480µS
RT = 10k
= –10mA, VIN = 7V1V
INTVCC
l
l
l
l
l
l
l
l
3.33.94.6A
240250257mV
217225231mV
96100103mV
–2.504.5mV
2.980V
03V
80
0
120µS
1.220
1.232
FB
65mV
90
925
1.250
1.250
–
V
–
FB
50mV
60mV
100
1000
4.14.4V
0.1
1.270
1.265
V
–
FB
40mV
VFB +
80mV
125
1050
µA
µA
V
V
V
V
kHz
kHz
3956f
3
Page 4
LT3956
CTRL VOLTAGE (V)
0
–50
V
(ISP– ISN)
THRESHOLD (mV)
50
150
250
0.511.5
300
0
100
200
2
3956 G01
ISP VOLTAGE (V)
0
97
V
(ISP– ISN)
THRESHOLD (mV)
99
101
20408060
103
98
100
102
3956 G02
CTRL = 0.5V
242
246
250
256
254
244
248
252
3956 G03
V
(ISP– ISN)
THRESHOLD (mV)
TEMPERATURE (°C)
–500
50
75
–25
25
100
125
CTRL = 2V
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, CTRL = 2V, PWM = 5V, unless otherwise noted.
PARAMETERCONDITIONSMINTYPMAXUNITS
Logic Inputs/Outputs
PWM Threshold Voltage
PWM Pin Resistance to GND4560kΩ
EN/UVLO Threshold Voltage Falling
EN/UVLO Rising Hysteresis20mV
EN/UVLO Input Low VoltageI
Drops Below 1µA0.4V
VIN
EN/UVLO Pin Bias Current LowEN/UVLO = 1.15V1.72.12.5µA
EN/UVLO Pin Bias Current HighEN/UVLO = 1.30V10100nA
VMODE Output Low (VOL)I
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3956E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3956I is guaranteed to meet performance specifications over the –40°C
to 125°C operating junction temperature range.
Note 3: For VIN below 6V, the EN/UVLO pin must not exceed VIN for proper
operation.
l
0.851.351.8V
l
1.1851.2201.245V
0.05
V
Typical perForMance characTerisTics
4
V
(ISP–ISN)
Threshold vs V
TA = 25°C, unless otherwise noted.
V
(ISP–ISN)
CTRL
with Reduced CTRL Voltage
Threshold vs V
ISP
V
(ISP–ISN)
Full-Scale Threshold
vs Temperature
3956f
Page 5
LT3956
RT (k)
SWITCHING FREQUENCY (kHz)
3956 G07
10000
1000
100
10
10100
3956 G04
V
FB
(V)
TEMPERATURE (°C)
–500
50
75
–25
25
100
125
1.20
1.22
1.24
1.26
1.28
1.21
1.23
1.25
1.27
3956 G05
V
REF
(V)
TEMPERATURE (°C)
–500
50
75
–25
25
100
125
1.96
1.98
2.00
2.02
2.04
1.97
1.99
2.01
2.03
VIN (V)
1.96
V
REF
(V)
1.98
2.00
2.02
2.04
1.97
1.99
2.01
2.03
3956 G06
020408060
3956 G08
SWITCHING FREQUENCY (kHz)
TEMPERATURE (°C)
–500
50
75
–25
25
100
125
300
400
500
350
450
RT = 26.7k
3956 G09
TEMPERATURE (°C)
–500
50
75
–25
25
100
125
1.6
I
EN/UVLO
(µA)
2.0
2.4
1.8
2.2
3956 G12
EN/UVLO VOLTAGE (V)
TEMPERATURE (°C)
1.18
1.22
1.28
1.20
1.24
1.26
EN/UVLO RISING
EN/UVLO FALLING
–500
50
75
–25
25
100
125
VIN (V)
0
V
IN
CURRENT (mA)
1.0
2.0
0.5
1.5
3956 G10
020408060
PWM = 0V
CURRENT LIMIT (A)
4.2
4.0
3.8
3.6
4.4
3956 G11
TEMPERATURE (°C)
–500
50
75
–25
25
100
125
Typical perForMance characTerisTics
FB Regulation Voltage (VFB)
vs TemperatureV
Switching Frequency vs R
T
Voltage vs TemperatureV
REF
Switching Frequency
vs Temperature
TA = 25°C, unless otherwise noted.
Voltage vs V
REF
IN
EN/UVLO Hysteresis Current
vs Temperature
Quiescent Current vs V
SW Pin Current Limit
IN
vs Temperature
EN/UVLO Threshold
vs Temperature
3956f
5
Page 6
LT3956
0
4
8
12
2
6
10
3956 G13
V
IN
CURRENT (mA)
SWITCHING FREQUENCY (kHz)
0400
800
200
600
1000
3956 G14
INTV
CC
CURRENT LIMIT (mA)
TEMPERATURE (°C)
10
14
20
12
16
18
–500
50
75
–25
25
100
125
NOT SWITCHING
3956 G15
INTV
CC
(V)
TEMPERATURE (°C)
–500
50
75
–25
25
100
125
7.0
7.2
7.4
7.1
7.3
DUTY CYCLE (%)
2.5
SW PIN CURRENT LIMIT (A)
3.5
4.5
3.0
4.0
3956 G16
0255075100
FB VOLTAGE (V)
3956 G17
1.21.221.241.261.28
0
125.0
312.5
62.50
187.5
250.0
V
(ISP–ISN)
THRESHOLD (mV)
V
CTRL
= 2V
LDO CURRENT (mA)
0
–2.5
LDO DROPOUT (V)
–2.0
–1.5
–1.0
–0.5
0
3
691215
3956 G18
–40°C
25°C
125°C
CTRL (V)
0
INPUT BIAS CURRENT (µA)
40
80
20
60
3956 G19
00.511.52
ISP
ISN
TEMPERATURE (°C)
–50
ON-RESISTANCE (mΩ)
120
140
160
100
80
–252505075100 125
20
0
60
180
40
3956 G20
200ns/DIV
PWM
INPUT
PWMOUT
5V/DIV
3956 G21
C
PWMOUT
= 2.2nF
Typical perForMance characTerisTics
Quiescent Current
vs Switching Frequency
SW Pin Current Limit
vs Duty Cycle
INTVCC Current Limit
vs TemperatureINTVCC Voltage vs Temperature
LED Current Sense Threshold
vs FB Voltage
TA = 25°C, unless otherwise noted.
INTVCC Dropout Voltage
vs INTVCC Current
ISP/ISN Input Bias Current
vs CTRL Voltage
6
Switch On-Resistance
vs Temperature
PWMOUT Waveform
3956f
Page 7
pin FuncTions
LT3956
NC: No Internal Connection. These pins may be left floating
or connected to an adjacent pin.
EN/UVLO: Shutdown and Undervoltage Detect Pin. An
accurate 1.22V falling threshold with externally programmable hysteresis detects when power is OK to enable
switching. Rising hysteresis is generated by the external
resistor divider and an accurate internal 2.1µA pull-down
current. Above the 1.24V (nominal) threshold (but below
6V), EN/UVLO input bias current is sub-µA. Below the
falling threshold, a 2.1µA pull-down current is enabled so
the user can define the hysteresis with the external resistor selection. An undervoltage condition resets soft-start.
Tie to 0.4V, or less, to disable the device and reduce VIN
quiescent current below 1µA.
INTVCC: Regulated supply for internal loads, GATE driver
and PWMOUT driver. Supplied from VIN and regulates to
7.15V (typical). INTVCC must be bypassed with a 4.7µF
capacitor placed close to the pin. Connect INTVCC directly
to VIN if VIN is always less than or equal to 7V.
GND: Ground. The exposed pad, Pin 37, is ground and
must be soldered directly to the ground plane.
VIN: Input Supply Pin. Must be locally bypassed with
a 0.22µF (or larger) capacitor to PGND placed close to
the IC.
FB: Voltage Loop Feedback Pin. FB is intended for constant-voltage regulation or for LED protection/open LED
detection. The internal transconductance amplifier with
output VC will regulate FB to 1.25V (nominal) through the
DC/DC converter. If the FB input is regulating the loop, the
VMODE pull-down is asserted. This action may signal an
open LED fault. If FB is driven above the FB threshold (by
an external power supply spike, for example), the VMODE
pull-down will be de-asserted and the PWMOUT pin will
be driven low to protect the LEDs from an overcurrent
event. Do not leave the FB pin open. If not used, connect
to GND.
ISN: Connection point for the negative terminal of the
current feedback resistor. If ISN is greater than 2.9V, the
LED current can be programmed by I
when V
if V
CTRL
CTRL
> 1.2V or I
LED
= (V
CTRL
< 1V. Input bias current is typically 20µA. Below
= 250mV/R
LED
–100mV)/(4 • R
LED
LED
)
3V, ISN is an input to the short-circuit protection feature
that forces GATE to 0V if ISP exceeds ISN by more than
350mV (typ).
ISP: Connection point for the positive terminal of the current
feedback resistor. Input bias current for this pin depends
on CTRL pin voltage, as shown in the Typical Performance
Characteristics. ISP is an input to the short-circuit protection feature when ISN is less than 3V.
SW: The exposed pad, Pin 38, is the drain of the switching N-channel MOSFET and must be connected to the
external inductor.
PGND: Source terminal of switch and the GND input to
the switch current comparator. Kelvin connect to the GND
plane close to the IC using Pin 12. Pins 13 to 17 should be
connected externally to the PGND terminals of components
in the switching path. See the Board Layout section.
PWMOUT: Buffered Version of the PWM Signal. This pin is
used to drive the LED load disconnect N-channel MOSFET
or level shift. This pin also serves in a protection function
for the FB overvoltage condition—will toggle if the FB
input is greater than the FB regulation voltage (VFB) plus
60mV (typical). The PWMOUT pin is driven from INTVCC.
Use of a MOSFET with gate cut-off voltage higher than
1V is recommended.
VC: Transconductance Error Amplifier Output Pin. This pin
is used to stabilize the voltage loop with an RC network.
This pin is high impedance when PWM is low, a feature
that stores the demand current state variable for the next
PWM high transition. Connect a capacitor between this
pin and GND; a resistor in series with the capacitor is
recommended for fast transient response.
CTRL: Current Sense Threshold Adjustment Pin. Regulating threshold V
for 0V < V
CTRL
(ISP – ISN)
< 1V. For V
is 0.25 • V
> 1.2V the current sense
CTRL
plus an offset
CTRL
threshold is constant at the full-scale value of 250mV. For
1V < V
threshold upon V
< 1.2V, the dependence of the current sense
CTRL
transitions from a linear function
CTRL
to a constant value, reaching 98% of full-scale value by
V
= 1.1V. Connect CTRL to V
CTRL
for the 250mV default
REF
threshold. Do not leave this pin open.
3956f
7
Page 8
LT3956
+
–
+
–
+
–
+
–
+
–
+
+
–
A1
A3
A6
+
+
–
FREQ
PROG
1.25V
SSCLAMP
1.1V
CTRL
V
REF
EN/UVLO
ISP
ISN
Q2
350mV
20k
170k
140µA
2.1µA
CTRL
BUFFER
g
m
EAMP
PWM
COMPARATOR
DRIVER
1mA (MAX)
I
SENSE
A4
g
m
A10
A5
OVFB
COMPARATOR
1.25V
FB
SHORT-CIRCUIT
DETECT
SCILMB
SCILMB
5k
PWMOUT PWM
1.25V
V
IN
INTV
CC
VC
+
–
+
–
A2
RQ
S
RAMP
GENERATOR
100kHz TO 1MHz
OSCILLATOR
+
–
+
–
A8
7.15V
LDO
SW
PGND
3956 BD
VMODE
GND
1.2V
FB
+
–
1.22V
+
–
2V
1.31V
RTSS
SHDN
A7
10µA
10µA AT
FB = 1.25V
VC
TSD
165°C
FAULT
LOGIC
10µA
10µA AT
A1+ = A1
–
pin FuncTions
V
: Voltage Reference Output Pin (typically 2V). This
REF
pin drives a resistor divider for the CTRL pin, either for
analog dimming or for temperature limit/compensation
of LED load. Can supply up to 100μA.
PWM: A signal low turns off switcher, idles oscillator and
disconnects VC pin from all internal loads. PWMOUT pin
follows PWM pin. PWM has an internal pull-down resistor.
If not used, connect to INTVCC.
VMODE: An open-collector pull-down on VMODE asserts
if the FB input is greater than the FB regulation threshold
minus 50mV (typical). To function, the pin requires an
external pull-up resistor. When the PWM input is low
and the DC/DC converter is idle, the VMODE condition is
latched to the last valid state when the PWM input was
high. When PWM input goes high again, the VMODE pin
will be updated. This pin may be used to report an open
LED fault. Use a pull-up current less than 1mA.
SS: Soft-Start Pin. This pin modulates oscillator frequency and compensation pin voltage (VC) clamp. The
soft-start interval is set with an external capacitor. The
pin has a 10µA (typical) pull-up current source to an
internal 2.5V rail. The soft-start pin is reset to GND by
an undervoltage condition (detected by EN/UVLO pin)
or thermal limit.
RT: Switching Frequency Adjustment Pin. Set the frequency using a resistor to GND (for resistor values, see
the Typical Performance curve or Table 1). Do not leave
the RT pin open.
block DiagraM
8
3956f
Page 9
operaTion
LT3956
The LT3956 is a constant-frequency, current mode
converter with a low side N-channel MOSFET switch.
The switch and PWMOUT pin drivers, and other chip
loads, are powered from INTVCC, which is an internally
regulated supply. In the discussion that follows, it will be
helpful to refer to the Block Diagram of the IC. In normal
operation, with the PWM pin low, the power switch is
turned off and the PWMOUT pin is driven to GND, the
VC pin is high impedance to store the previous switching
state on the external compensation capacitor, and the ISP
and ISN pin bias currents are reduced to leakage levels.
When the PWM pin transitions high, the PWMOUT pin
transitions high after a short delay. At the same time, the
internal oscillator wakes up and generates a pulse to set
the PWM latch, turning on the internal power MOSFET
switch. A voltage input proportional to the switch current,
sensed by an internal current sense resistor, is added to
a stabilizing slope compensation ramp and the resulting
switch-current sense signal is fed into the positive terminal of the PWM comparator. The current in the external
inductor increases steadily during the time the switch is
on. When the switch-current sense voltage exceeds the
output of the error amplifier, labeled VC, the latch is reset
and the switch is turned off. During the switch off phase,
the inductor current decreases. At the completion of each
oscillator cycle, internal signals such as slope compensation return to their starting points and a new cycle begins
with the set pulse from the oscillator.
Through this repetitive action, the PWM control algorithm
establishes a switch duty cycle to regulate a current or
voltage in the load. The VC signal is integrated over many
switching cycles and is an amplified version of the difference between the LED current sense voltage, measured
between ISP and ISN, and the target difference voltage
set by the CTRL pin. In this manner, the error amplifier
sets the correct peak switch-current level to keep the
LED current in regulation. If the error amplifier output
increases, more current is demanded in the switch; if it
decreases, less current is demanded. The switch current
is monitored during the on-phase and is not allowed to
exceed the current limit threshold of 3.9A (typical). If the
SW pin exceeds the current limit threshold, the SR latch is
reset regardless of the output state of the PWM compara-
tor. Likewise, at an ISP/ISN common mode voltage less
than 3V, the difference between ISP and ISN is monitored
to determine if the output is in a short-circuit condition. If
the difference between ISP and ISN is greater than 335mV
(typical), the SR latch will be reset regardless of the PWM
comparator. These functions are intended to protect the
power switch, as well as various external components in
the power path of the DC/DC converter.
In voltage feedback mode, the operation is similar to that
described above, except the voltage at the VC pin is set by
the amplified difference of the internal reference of 1.25V
(nominal) and the FB pin. If FB is lower than the reference
voltage, the switch current will increase; if FB is higher
than the reference voltage, the switch demand current
will decrease. The LED current sense feedback interacts
with the FB voltage feedback so that FB will not exceed
the internal reference and the voltage between ISP and
ISN will not exceed the threshold set by the CTRL pin.
For accurate current or voltage regulation, it is necessary
to be sure that under normal operating conditions, the
appropriate loop is dominant. To deactivate the voltage
loop entirely, FB can be connected to GND. To deactivate
the LED current loop entirely, the ISP and ISN should be
tied together and the CTRL input tied to V
Two LED specific functions featured on the LT3956 are
controlled by the voltage feedback pin. First, when the
FB pin exceeds a voltage 50mV lower (–4%) than the FB
regulation voltage, the pull-down driver on the VMODE pin
is activated. This function provides a status indicator that
the load may be disconnected and the constant-voltage
feedback loop is taking control of the switching regulator.
When the FB pin exceeds the FB regulation voltage by 60mV
(5% typical), the PWMOUT pin is driven low, ignoring the
state of the PWM input. In the case where the PWMOUT
pin drives a disconnect NFET, this action isolates the
LED load from GND, preventing excessive current from
damaging the LEDs. If the FB input exceeds the overvoltage threshold (1.31V typical), then an externally driven
overvoltage event may have caused the FB pin to be too
high and the VMODE pull-down will be deactivated until
the FB pin drops below the overvoltage threshold.
REF
.
3956f
9
Page 10
LT3956
V
RR
R
IN FALLING,
.•=+1 22
12
2
VµA RV
IN RISINGIN FALLING,,
.•=+2 11
EN/UVLO
LT3956
V
IN
R2
3956 F01
R1
I
VmV
R
LED
CTRL
LED
=
− 100
4•
I
mV
R
LED
LED
=
250
applicaTions inForMaTion
INTVCC Regulator Bypassing and Operation
The INTVCC pin requires a capacitor for stable operation
and to store the charge for the switch driver and PWMOUT
pin switching currents. Choose a 10V rated low ESR, X7R
or X5R ceramic capacitor for best performance. A 4.7µF
capacitor will be adequate for many applications. Place
the capacitor close to the IC to minimize the trace length
to the INTVCC pin and also to the IC ground.
An internal current limit on the INTVCC output protects
the LT3956 from excessive on-chip power dissipation.
The INTVCC pin has its own undervoltage disable (UVLO)
set to 4.1V (typical) to protect the internal MOSFET from
excessive power dissipation caused by not being fully enhanced. If the INTVCC pin drops below the UVLO threshold,
the PWMOUT pin will be forced to 0V, the power switch
turned off and the soft-start pin will be reset.
If the input voltage, VIN, will not exceed 7V, then the INTVCC
pin could be connected to the input supply. This action
allows the LT3956 to operate from as low as 4.5V. Be aware
that a small current (less than 12μA) will load the INTVCC
in shutdown. Otherwise, the minimum operating VIN value
is determined by the dropout voltage of the linear regulator
and the 4.4V (4.1V typical) INTVCC undervoltage lockout
threshold mentioned above.
Programming the Turn-On and Turn-Off Thresholds
With the EN/UVLO Pin
LED Current Programming
The LED current is programmed by placing an appropriate value current sense resistor, R
, between the ISP
LED
and ISN pins. Typically, sensing of the current should
be done at the top of the LED string. If this option is not
available, then the current may be sensed at the bottom
of the string, but take caution that the minimum ISN value
does not fall below 3V, which is the lower limit of the LED
current regulation function. The CTRL pin should be tied
to a voltage higher than 1.2V to get the full-scale 250mV
(typical) threshold across the sense resistor. The CTRL pin
can also be used to dim the LED current to zero, although
relative accuracy decreases with the decreasing voltage
sense threshold. When the CTRL pin voltage is less than
1V, the LED current is:
When the CTRL pin voltage is between 1V and 1.2V
the LED current varies with CTRL, but departs from the
previous equation by an increasing amount as the CTRL
voltage increases. Ultimately, above CTRL = 1.2V, the LED
current no longer varies with CTRL. At CTRL = 1.1V, the
actual value of I
When V
is higher than 1.2V, the LED current is regu-
CTRL
is ~98% of the equation’s estimate.
LED
lated to:
The falling UVLO value can be accurately set by the resistor
divider. A small 2.1µA pull-down current is active when
EN/UVLO is below the falling threshold. The purpose of
this current is to allow the user to program the rising
hysteresis. The following equations should be used to
determine the values of the resistors:
10
The CTRL pin should not be left open (tie to V
REF
if not
used). The CTRL pin can also be used in conjunction with
a thermistor to provide overtemperature protection for
the LED load, or with a resistor divider to VIN to reduce
output power and switching current when VIN is low.
The presence of a time varying differential voltage signal
(ripple) across ISP and ISN at the switching frequency
is expected. The amplitude of this signal is increased by
high LED load current, low switching frequency and/or a
smaller value output filter capacitor. Some level of ripple
signal is acceptable: the compensation capacitor on the
VC pin filters the signal so the average difference between
ISP and ISN is regulated to the user-programmed value.
Ripple voltage amplitude (peak-to-peak) in excess of
Figure 1
3956f
Page 11
applicaTions inForMaTion
IA
V
V
OUT MAX
IN MIN
OUT MAX
()
()
()
.≤ 2 5
IA
V
VV
OUT MAX
IN MIN
OUT MAXIN MIN
()
()
()()
.
()
≤+2 5
FB
LT3956
V
OUT
R4
3956 F02
R3
FB
LT3956
100k
V
OUT
C
OUT
R4
3956 F03
R3
LED
ARRAY
R
LED
+
–
V
RR
R
OUT
=+1 25
34
4
.•
VV
R
R
OUTBE
=+ 1 25
3
4
.•
LT3956
20mV should not cause misoperation, but may lead to
noticeable offset between the average value and the userprogrammed value.
Output Current Capability
An important consideration when using a switch with a
fixed current limit is whether the regulator will be able
to supply the load at the extremes of input and output
voltage range. Several equations are provided to help
determine this capability. Some margin to data sheet
limits is included.
For boost converters:
For buck mode converters:
I
OUT(MAX)
≤ 2.5A
For SEPIC and buck-boost mode converters:
Programming Output Voltage (Constant-Voltage
Regulation) or Open LED/Overvoltage Threshold
For a boost or SEPIC application, the output voltage can
be set by selecting the values of R3 and R4 (see Figure 2)
according to the following equation:
For a boost type LED driver, set the resistor from the output
to the FB pin such that the expected voltage level during
normal operation will not exceed 1.1V. For an LED driver
of buck mode or a buck-boost mode configuration, the
output voltage is typically level-shifted to a signal with
respect to GND as illustrated in Figure 3. The output can
be expressed as:
These equations assume the inductor value and switching frequency have been selected so that inductor ripple
current is ~600mA. Ripple current higher than this value
will reduce available output current. Be aware that current
limited operation at high duty cycle can greatly increase
inductor ripple current, so additional margin may be
required at high duty cycle.
If some level of analog dimming is acceptable at minimum
supply levels, then the CTRL pin can be used with a resistor
divider to VIN (as shown on page 1) to provide a higher
output current at nominal VIN levels.
Figure 2. Feedback Resistor Connection
for Boost or SEPIC LED Drivers
Figure 3. Feedback Resistor Connection for
Buck Mode or Buck-Boost Mode LED Driver
ISP/ISN Short-Circuit Protection Feature for SEPIC
The ISP and ISN pins have a protection feature independent of the LED current sense feature that operates at
ISN below 3V. The purpose of this feature is to provide
continuous current sensing when ISN is below the LED
current sense common mode range (during start-up or
an output short-circuit fault) to prevent the development
of excessive switching currents that could damage the
power components in a SEPIC converter. The action
threshold (335mV, typ) is above the default LED current
sense threshold, so that no interference will occur over
the ISN voltage range where these two functions overlap.
This feature acts in the same manner as switch-current
limit—it prevents switch turn-on until the ISP/ISN difference falls below the threshold.
3956f
11
Page 12
LT3956
0
100
200
300
50
150
250
3956 F04
TIME (ns)
TEMPERATURE (°C)
–500
50
75
–25
25
100
125
MINIMUM ON-TIME
MINIMUM OFF-TIME
applicaTions inForMaTion
Dimming Control
There are two methods to control the current source for
dimming using the LT3956. One method uses the CTRL
pin to adjust the current regulated in the LEDs. A second
method uses the PWM pin to modulate the current source
between zero and full current to achieve a precisely programmed average current. To make this method of current
control more accurate, the switch demand current is stored
on the VC node during the quiescent phase when PWM is
low. This feature minimizes recovery time when the PWM
signal goes high. To further improve the recovery time, a
disconnect switch may be used in the LED current path to
prevent the ISP node from discharging during the PWM
signal low phase. The minimum PWM on or off time will
depend on the choice of operating frequency through the
RT input. For best overall performance, the minimum PWM
low or high time should be at least six switching cycles
(6μs for fSW = 1MHz).
Programming the Switching Frequency
Duty Cycle Considerations
Switching duty cycle is a key variable defining converter
operation, therefore, its limits must be considered when
programming the switching frequency for a particular
application. The fixed minimum on-time and minimum
off-time (see Figure 4) and the switching frequency define
the minimum and maximum duty cycle of the switch,
respectively. The following equations express the minimum/maximum duty cycle:
Min Duty Cycle = (minimum on-time) • switching
frequency
Max Duty Cycle = 1 – (minimum off-time) • switching
frequency
When calculating the operating limits, the typical values
for on/off-time in the data sheet should be increased by at
least 60ns to allow margin for PWM control latitude and
SW node rise/fall times.
The RT frequency adjust pin allows the user to program
the switching frequency from 100kHz to 1MHz to optimize
efficiency/performance or external component size. Higher
frequency operation yields smaller component size but
increases switching losses and gate driving current, and
may not allow sufficiently high or low duty cycle operation.
Lower frequency operation gives better performance at the
cost of larger external component size. For an appropriate
RT resistor value see Table 1. An external resistor from the
RT pin to GND is required—do not leave this pin open.
Figure 4. Typical Switch Minimum On
and Off Pulse Width vs Temperature
Thermal Considerations
The LT3956 is rated to a maximum input voltage of 80V.
Careful attention must be paid to the internal power dissipation of the IC at higher input voltages to ensure that a
junction temperature of 125°C is not exceeded. This junction
limit is especially important when operating at high ambient
temperatures. If the LT3956’s junction temperature reaches
165°C (typ), the power switch will be turned off and the
soft-start (SS) pin will be discharged to GND. Switching
3956f
12
Page 13
applicaTions inForMaTion
CI
V
V
T
µF
A µs
IN µFLED A
OUT
IN
SW µs( )( )( )
•••
•
=
1
CIT
µF
A µs
IN µFLED ASW µs( )( )( )
••
.
•
=
4 7
I
IN(RMS)
=
()
IDD
LED
•–•1
LT3956
will be enabled after the device temperature drops 10°C.
This function is intended to protect the device during
momentary overload conditions.
The major contributors to internal power dissipation are
the current in the linear regulator to drive the switch, and
the ohmic losses in the switch. The linear regulator power
is proportional to VIN and switching frequency, so at high
VIN the switching frequency should be chosen carefully
to ensure that the IC does not exceed a safe junction
temperature. The internal junction temperature of the IC
can be estimated by:
TJ = TA + [VIN • (IQ + fSW • 7nC) + I
• θ
JA
2
• 0.14Ω • DSW]
SW
where TA is the ambient temperature, IQ is the quiescent
current of the part (maximum 1.7mA) and θJA is the
package thermal impedance (43°C/W for the 5mm × 6mm
QFN package). For example, an application with T
85°C, V
IN(MAX)
= 60V, fSW = 400kHz, and having an average
A(MAX)
=
switching current of 2.5A at 70% duty cycle, the maximum
IC junction temperature will be approximately:
The Exposed Pads on the bottom of the package must be
soldered to a plane. These should then be connected to internal copper planes with thermal vias placed directly under
the package to spread out the heat dissipated by the IC.
Open LED Detection
The LT3956 provides an open-drain status pin, VMODE,
that pulls low when the FB pin is within ~50mV of its 1.25V
regulated voltage. If the open LED clamp voltage is programmed correctly using the FB pin, then the FB pin should
never exceed 1.1V when LEDs are connected, therefore, the
only way for the FB pin to be within 50mV of the regulation
voltage is for an open LED event to have occurred.
Input Capacitor Selection
The input capacitor supplies the transient input current for
the power inductor of the converter and must be placed
and sized according to the transient current requirements.
The switching frequency, output current and tolerable input
voltage ripple are key inputs to estimating the capacitor
value. An X7R type ceramic capacitor is usually the best
choice since it has the least variation with temperature and
DC bias. Typically, boost and SEPIC converters require a
lower value capacitor than a buck mode converter. Assuming that a 100mV input voltage ripple is acceptable,
the required capacitor value for a boost converter can be
estimated as follows:
Therefore, a 4.7µF capacitor is an appropriate selection
for a 400kHz boost regulator with 12V input, 48V output
and 1A load.
With the same VIN voltage ripple of 100mV, the input capacitor for a buck converter can be estimated as follows:
A 10µF input capacitor is an appropriate selection for a
400kHz buck mode converter with a 1A load.
In the buck mode configuration, the input capacitor has
large pulsed currents due to the current returned through
the Schottky diode when the switch is off. In this buck
converter case it is important to place the capacitor as
close as possible to the Schottky diode and to the PGND
return of the switch. It is also important to consider the
ripple current rating of the capacitor. For best reliability,
this capacitor should have low ESR and ESL and have an
adequate ripple current rating. The RMS input current for
a buck mode LED driver is:
The selection of the output capacitor depends on the load
and converter configuration, i.e., step-up or step-down
and the operating frequency. For LED applications, the
equivalent resistance of the LED is typically low and the
output filter capacitor should be sized to attenuate the
current ripple. Use of an X7R type ceramic capacitor is
recommended.
To achieve the same LED ripple current, the required filter
capacitor is larger in the boost and buck-boost mode applications than that in the buck mode applications. Lower
operating frequencies will require proportionately higher
capacitor values.
Soft-Start Capacitor Selection
For many applications, it is important to minimize the
inrush current at start-up. The built-in soft-start circuit
significantly reduces the start-up current spike and output
voltage overshoot. The soft-start interval is set by the softstart capacitor selection according to the equation:
it is important to consider diode leakage, which increases
with the temperature, from the output during the PWM
low interval. Therefore, choose the Schottky diode with
sufficiently low leakage current. Table 3 has some recommended component vendors.
Table 3. Schottky Rectifier Manufacturers
VENDORWEB SITE
On Semiconductorwww.onsemi.com
Diodes, Inc.www.diodes.com
Central Semiconductorwww.centralsemi.com
Inductor Selection
The inductor used with the LT3956 should have a saturation
current rating appropriate to the maximum switch current
of 4.6A. Choose an inductor value based on operating
frequency, input and output voltage to provide a current
mode signal of approximately 0.6A magnitude. The following equations are useful to estimate the inductor value
(TSW = 1/f
OSC
):
A typical value for the soft-start capacitor is 0.01µF. The
soft-start pin reduces the oscillator frequency and the
maximum current in the switch. The soft-start capacitor
is discharged when EN/UVLO falls below its threshold,
during an overtemperature event or during an INTVCC undervoltage event. During start-up with EN/UVLO, charging
of the soft-start capacitor is enabled after the first PWM
high period.
Schottky Rectifier Selection
The power Schottky diode conducts current during the
interval when the switch is turned off. Select a diode rated
for the maximum SW voltage of the application and the
RMS diode current. If using the PWM feature for dimming,
Table 4 provides some recommended inductor vendors.
The LT3956 uses an internal transconductance error amplifier whose VC output compensates the control loop. The
external inductor, output capacitor and the compensation
resistor and capacitor determine the loop stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor at VC are selected to optimize control loop
response and stability. For typical LED applications, a 4.7nF
compensation capacitor at VC is adequate, and a series resistor should always be used to increase the slew rate on
the VC pin to maintain tighter regulation of LED current during fast transients on the input supply to the converter.
Board Layout
The high speed operation of the LT3956 demands careful
attention to board layout and component placement. The
exposed pads of the package are important for thermal
management of the IC. It is crucial to achieve a good electrical and thermal contact between the GND exposed pad and
the ground plane of the board. To reduce electromagnetic
interference (EMI), it is important to minimize the area of
the high dV/dt switching node between the inductor, SW
pin and anode of the Schottky rectifier. Use a ground plane
under the switching node to eliminate interplane coupling
to sensitive signals. The lengths of the high dI/dt traces:
1) from the switch node through the switch to PGND, and
2) from the switch node through the Schottky rectifier and
filter capacitor to PGND, should be minimized. The ground
points of these two switching current traces should come
to a common point then connect to the ground plane at the
PGND pin of the LT3956 through a separate via to Pin 12,
as shown in the suggested layout (Figure 5). Likewise, the
ground terminal of the bypass capacitor for the INTVCC
regulator should be placed near the GND of the IC. The
ground for the compensation network and other DC control
signals should be star connected to the GND Exposed Pad
of the IC. Do not extensively route high impedance signals
such as FB and VC, as they may pick up switching noise.
Since there is a small variable DC input bias current to
the ISN and ISP inputs, resistance in series with these
pins should be minimized to avoid creating an offset in
the current sense threshold.
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
1
363530 31 3233 34
28
20
21
23
24
25
27
2
3
4
6
8
9
10
121314151617
BOTTOM VIEW—EXPOSED PAD
2.00 REF
1.50 REF
0.75 p 0.05
R = 0.125
TYP
R = 0.10
TYP
PIN 1 NOTCH
R = 0.30 OR
0.35 s 45o
CHAMFER
0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UHE28MA) QFN 0110 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 p0.05
4.10 p 0.05
5.50 p 0.05
PACKAGE OUTLINE
1.88 p 0.10
1.53 p 0.10
2.00 REF
1.50 REF
5.10 p 0.05
6.50 p 0.05
UHE Package
Variation: UHE28MA
36-Lead Plastic QFN (5mm s 6mm)
(Reference LTC DWG # 05-08-1836 Rev C)
3.00 p 0.10
3.00 p 0.10
0.12
p 0.10
1.88
p 0.05
1.53
p 0.05
3.00 p 0.053.00 p 0.05
0.48 p 0.05
0.12
p 0.05
0.48 p 0.10
0.25 p0.05
0.50 BSC
101234689
17
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30
31
32
33
34
35
36
12
13
14
15
16
LT3956
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.