LINEAR TECHNOLOGY LT3825 Technical data
LT3825
Isolated No-Opto
Synchronous Flyback Controller
FEATURES
■
Senses Output Voltage Directly from Primary Side
Winding—No Optoisolator Required
■
Synchronous Driver for High Efficiency
■
Input Voltage Limited Only by External
Power Components
■
Accurate Output Regulation Without User Trims
■
Switching Frequency from 50kHz to 250kHz
■
Synchronizable
■
Load Compensation
■
Programmable Undervoltage Lockout
■
Available in a Thermally Enhanced 16-Lead
TSSOP Package
U
APPLICATIO S
■
Isolated Medium Power (10W to 60W) Supplies
■
Isolated Telecom, Medical Converters
■
Instrumentation Power Supplies
■
Isolated Power over Ethernet Supplies
with Wide Input Supply Range
U
DESCRIPTIO
The LT®3825 is an isolated switching regulator controller
designed for medium power flyback topologies. A typical
application is 10W to 60W with input voltage limited only
by external power path components. A third transformer
winding provides output voltage feedback.
The LT3825 is a current mode controller that regulates
output voltage based on sensing secondary voltage via a
transformer winding during flyback. This allows for tight
output regulation without the use of an optoisolator,
improving dynamic response and reliability. Synchronous
rectification increases converter efficiency and improves
output cross regulation in multiple output converters.
The LT3825 operates in forced continuous conduction
mode which improves cross regulation in multiple winding
applications. Switching frequency is user programmable
and can be externally synchronized. The part also has load
compensation, undervoltage lockout and soft-start circuity.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6948466, 5841643.
TYPICAL APPLICATIO
48V to 3.3V at 12A Isolated Supply
+
V
IN
36V TO 72V
28.7k
T1
20Ω
•
2.2µF
402k
15k
3.01k
UVLO
PGDLY
tONSYNC
100k12k
FB
R
CMP
47µF
V
CC
LT3825
ENDLY OSC
2.1k 150k
47pF
+
47k
SGSGPG
GND SFST
U
0.22µF
0.1µF
SENSE
SENSE
C
CMP
92
Efficiency
90
36V
IN
48V
88
86
+
V
OUT
3.3V
•
100pF
20Ω
+
–
V
C
0.02Ω
100k
10nF
T1
•
SG
330Ω
0.1µF
•
470µF
12A
×4
47Ω
×2
1µF
15Ω
2.2nF
•
10k
3825 TA01a
84
EFFICIENCY (%)
82
80
78
2
3
3.43
3.38
3.33
3.28
OUTPUT (V)
3.23
3.18
3.13
2
3
IN
72V
IN
5
6
4
LOAD CURRENT (A)
Regulation
5
6
4
LOAD CURRENT (A)
810
7
36V
IN
48V
IN
72V
IN
7
810
12
9
11
3825 TA01b
12
9
11
3825 TA01c
3825f
1
LT3825
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
VCC to GND
Low Impedance Source ........................ –0.3V to 18V
Current Fed
(VCC has Internal 19.5V Clamp) .......... 30mA into V
UVLO, SYNC Pin Voltage .......................... – 0.3V to V
SENSE–, SENSE+ Pin Voltage ................... – 0.5V, +0.5V
FB Pin Current ...................................................... ±2mA
V
Pin Current ..................................................... ±1mA
C
Operating Junction Temperature Range
(Notes 2, 3) .......................................... – 40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
CC
CC
UU
W
PACKAGE/ORDER I FOR ATIO
TOP VIEW
1
SG
2
V
CC
3
t
ON
4
ENDLY
SYNC
SFST
OSC
FB
16-LEAD PLASTIC TSSOP
T
= 125°C, θJA = 40°C/ W, θJC = 10°C/ W
JMAX
EXPOSED PAD (PIN 17) IS GND,MUST BE SOLDERED TO PCB
5
6
7
8
FE PACKAGE
17
ORDER PART NUMBER FE PART MARKING
LT3825EFE
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
PG
16
PGDLY
15
R
14
C
13
SENSE
12
SENSE
11
UVLO
10
V
9
CMP
CMP
+
–
C
3825EFE
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
= 14V; PG, SG Open; VC = 1.5V, V
V
CC
PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VCC Turn-On Voltage
VCC Turn-Off Voltage
VCC Hysteresis V
VCC Shunt Clamp V
VCC Supply Current (Note 5) (ICC)V
VCC Start-Up Current VCC = 10V
Feedback Amplifier
Feedback Regulation Voltage (VFB)
Feedback Pin Input Bias Current R
Feedback Amplifier Transconductance ∆IC = ±10µA
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage VFB = 0.9V 2.56 V
Reference Voltage Line Regulation 12V ≤ VCC ≤ 18V
Feedback Amplifier Voltage Gain VC = 1.2V to 1.7V 1400 V/V
Soft-Start Charging Current V
Soft-Start Discharge Current V
Control Pin Threshold (VC) Duty Cycle = Min 1.0 V
SENSE
–
= 0V; R
= 1k, R
CMP
CC(ON)
UVLO
= Open
C
Open 200 nA
CMP
= 1.4V 0.84 V
V
FB
= 0V 16 20 25 µA
SFST
= 1.5V, V
SFST
tON
– V
= 0V, I
= 90k, R
CC(OFF)
= 15mA
VCC
= 0V 0.8 1.3 mA
UVLO
PGDLY
= 27.4k, R
= 90k, unless otherwise specified.
ENDLY
●
14.0 15.3 16.0 V
●
●
●
●
●
●
●
●
●
8 9.7 11 V
4.0 5.6 6.5 V
19.5 20.5 V
4 6.4 10 mA
180 400 µA
1.220 1.237 1.251 V
700 1000 1400 µmho
25 55 90 µA
0.005 0.02 %/V
2
3825f
LT3825
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
= 14V; PG, SG Open; VC = 1.5V, V
V
CC
PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Outputs
PG, SG Output High Level
PG, SG Output Low Level
PG, SG Output Shutdown Strength V
PG Rise Time CPG = 1nF 11 ns
SG Rise Time CSG = 1nF 15 ns
PG, SG Fall Time CPG, CSG = 1nF 10 ns
Current Amplifier
Switch Current Limit at Maximum V
∆V
/∆V
SENSE
C
Sense Voltage Overcurrent Fault Voltage V
Timing
Switching Frequency (f
)C
OSC
Oscillator Capacitor Value (C
Minimum Switch On Time (t
Flyback Enable Delay Time (tED) 265 ns
PG Turn-On Delay Time (t
PGDLY
Maximum Switch Duty Cycle
SYNC Pin Threshold
SYNC Pin Input Resistance 40 kΩ
Load Compensation
Load Comp to V
Offset Voltage V
SENSE
Feedback Pin Load Compensation Current V
UVLO Function
UVLO Pin Threshold (V
UVLO
UVLO Pin Bias Current V
Note 1: Absolute Maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LT3825E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
C
) (Note 6) 33 200 pF
OSC
) 200 ns
ON(MIN)
) 200 ns
)
SENSE
–
= 0V; R
CMP
V
= 1k, R
UVLO
SENSE
= 90k, R
tON
PGDLY
= 0V; IPG, ISG = 20mA
+
= 27.4k, R
= 90k, unless otherwise specified.
ENDLY
●
6.6 7.4 8.0 V
●
●
●
88 98 110 mV
0.01 0.05 V
1.4 1.8 V
0.07 V/V
+
, V
SENSE
OSC
RCMP
SENSE
UVLO
V
UVLO
= 100pF
< 1V
SFST
with V
+
= 20mV, VFB = 1.230V 20 µA
+
= 0V 1 mV
SENSE
= 1.2V –0.25 0 ±0.25 µA
= 1.3V –4.50 –3.4 –2.50 µA
Note 4: T
dissipation P
is calculated from the ambient temperature TA and power
J
according to the following formula:
D
= TA + (PD • 40°C/W)
T
J
●
●
84 100 110 kHz
●
85 88 %
●
●
1.215 1.240 1.265 V
206 230 mV
1.53 2.1 V
Note 5: Supply current does not include gate charge current to the
MOSFETs. See Applications Information.
Note 6: Component value range guaranteed by design.
3825f
3
LT3825
TEMPERATURE (°C)
–50
8
9
25 75
3825 G03
7
6
–25 0
50 100 125
5
4
3
10
I
VCC
(mA)
DYNAMIC CURRENT CPG = 1nF,
C
SG
= 1nF, f
OSC
= 100kHz
STATIC PART CURRENT
VCC = 14V
TEMPERATURE (°C)
–50
90
f
OSC
(kHz)
92
96
98
100
110
104
0
50
75
3825 G06
94
106
108
102
–25
25
100
125
C
OSC
= 100pF
TEMPERATURE (°C)
–50
V
FB
RESET (V)
1.03
25
3825 G09
1.00
0.98
–25 0 50
0.97
0.96
1.04
1.02
1.01
0.99
75 100 125
UW
TYPICAL PERFOR A CE CHARACTERISTICS
V
CC(ON)
vs Temperature
16
15
14
13
(V)
12
CC
V
11
10
9
8
–25 0 50
–50
and V
CC(OFF)
V
CC(ON)
V
CC(OFF)
25
TEMPERATURE (°C)
75 100 125
3825 G01
(µA)
VCC
I
Start-Up Current
V
CC
vs Temperature
300
250
200
150
100
50
0
–50
–25 0
50 100 125
25 75
TEMPERATURE (°C)
3825 G02
V
Current vs Temperature
CC
110
108
106
104
102
100
98
96
SENSE VOLTAGE (mV)
94
92
90
–50
1.240
1.239
1.238
1.237
1.236
(V)
1.235
FB
V
1.234
1.233
1.232
1.231
1.230
4
SENSE Voltage vs Temperature
FB = 1.1V
SENSE = V
WITH V
–25
vs Temperature
V
FB
–50
–25
+
SENSE
–
= 0V
SENSE
50
25
0
TEMPERATURE (°C)
50
25
0
TEMPERATURE (°C)
75
100
3825 G04
75
100
125
3825 G07
125
SENSE Fault Voltage
vs Temperature
220
SENSE = V
WITH V
215
210
205
200
195
SENSE VOLTAGE (mV)
190
185
180
–25 0 50
–50
+
SENSE
–
= 0V
SENSE
25
TEMPERATURE (°C)
Feedback Pin Input Bias
vs Temperature
300
R
OPEN
CMP
250
200
150
100
FEEDBACK PIN INPUT BIAS (nA)
50
0
–50
–25 0
25 75
TEMPERATURE (°C)
Oscillator Frequency
vs Temperature
75 100 125
3825 G05
VFB Reset vs Temperature
50 100 125
3825 G08
3825f
UW
TEMPERATURE (°C)
–50
3.4
3.5
3.7
25 75
3825 G15
3.3
3.2
–25 0
50 100 125
3.1
3.0
3.6
I
UVLO
(µA)
TEMPERATURE (°C)
–50 –25
19.0
V
CC
(V)
20.0
21.5
0
50
75
3825 G18
19.5
21.0
20.5
25
100
125
ICC = 10mA
TYPICAL PERFOR A CE CHARACTERISTICS
LT3825
Feedback Amplifier Output
Current vs V
70
50
30
10
(µA)
VC
I
–10
–30
–50
–70
0.9
FB
125°C
1
1.1
1.2
VFB (V)
1.3
Feedback Amplifier Voltage Gain
vs Temperature
1700
1650
1600
1550
1500
1450
1400
(V/V)
V
A
1350
1300
1250
1200
1150
1100
–25 0 50
–50
25
TEMPERATURE (°C)
25°C
–40°C
1.5
1.4
3825 G10
75 100 125
3825 G13
Feedback Amplifier Source and
Sink Current vs Temperature
70
65
60
(µA)
55
VC
I
50
45
40
–50
–25 0
SOURCE CURRENT
25 75
TEMPERATURE (°C)
= 1.1V
V
FB
50 100 125
SINK
CURRENT
= 1.4V
V
FB
3825 G11
UVLO vs Temperature I
1.250
1.245
1.240
1.235
UVLO (V)
1.230
1.225
1.220
–50
–25 0
TEMPERATURE (°C)
50 100 125
25 75
3825 G14
Feedback Amplifier g
vs Temperature
1100
1050
1000
(µmho)
m
g
950
900
–50
–25 0 25 50
TEMPERATURE (°C)
Hysteresis vs Temperature
UVLO
m
75 100 125
3825 G12
Soft-Start Charge Current
vs Temperature
23
22
21
20
19
18
17
SFST CHARGE CURRENT (µA)
16
15
–25 0 50
–50
TEMPERATURE (°C)
PG, SG Rise and Fall Times
vs Load Capacitance
80
TA = 25°C
70
60
50
40
TIME (ns)
30
20
10
0
0
75 100 125
3825 G16
25
FALL TIME
RISE TIME
246 107135 9
CAPACITANCE (nF)
8
3825 G17
VCC Clamp Voltage
vs Temperature
3825f
5
LT3825
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum PG On Time
vs Temperature
340
R
tON(MIN)
330
320
310
(ns)
300
ON(MIN)
t
290
280
270
260
–25 0 50
–50
U
= 158k
25
TEMPERATURE (°C)
75 100 125
3825 G19
UU
PG Delay Time vs Temperature
300
250
200
(ns)
150
PGDLY
t
100
50
0
–50
–25 25
R
R
0
TEMPERATURE (°C)
PI FU CTIO S
SG (Pin 1): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchronous switch. Large dynamic currents may flow during
voltage transitions. See the Applications Information for
details.
V
(Pin 2): Supply Voltage Pin. Bypass this pin to ground
CC
with a 4.7µF capacitor or more. This pin has a 19.5V clamp
to ground. V
turns the part on when V
at 9.7V. In a conventional “trickle-charge” bootstrapped
configuration, the V
cantly during turn-on causing a benign relaxation oscillation action on the VCC pin if the part does not start
normally.
(Pin 3): Pin for external programming resistor to set
t
ON
the minimum time that the primary switch is on for each
cycle. Minimum turn-on facilitates the isolated feedback
method. See Applications Information for details.
has an undervoltage lockout function that
CC
is approximately 15.3V and off
CC
supply current increases signifi-
CC
Enable Delay Time vs Temperature
260
R
= 90k
ENDLY
PGDLY
PGDLY
= 27.4k
= 16.9k
50
75
100 125
3825 G20
240
(ns)
ED
t
180
140
220
200
160
–50
–25 0
50 100 125
25 75
TEMPERATURE (°C)
SYNC (Pin 5): Pin for synchronizing the internal oscillator
with an external clock. The positive edge on a pulse causes
the oscillator to discharge causing PG to go low (off) and
SG high (on). The sync threshold is typically 1.6V. See
Applications Information for details. Tie to ground if
unused.
SFST (Pin 6): This pin, in conjunction with a capacitor to
ground, controls the ramp-up of peak primary current as
sensed through the sense resistor. This is used to control
converter inrush current at start-up. The VC pin voltage
cannot exceed the SFST pin voltage, so as SFST increases,
the maximum voltage on VC increases commensurately,
allowing higher peak currents. Total V
ramp time is
C
approximately 70ms per µF of capacitance. Leave pin open
if not using the soft-start function.
OSC (Pin 7): This pin in conjunction with an external
capacitor defines the controller oscillator frequency. The
frequency is approximately 100kHz • 100/C
OSC
(pF).
3825 G21
ENDLY (Pin 4): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifier for a fixed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for flyback voltage sensing.
See Applications Information for details.
6
FB (Pin 8): Pin for the feedback node for the power supply
feedback amplifier. Feedback is usually sensed via a third
winding and enabled during the flyback period. This pin
also sinks additional current to compensate for load
current variation as set by the R
pin. Keep the Thevenin
CMP
equivalent resistance of the feedback divider at roughly 3k.
3825f
LT3825
U
UU
PI FU CTIO S
VC (Pin 9): Pin used for frequency compensation for the
switcher control loop. It is the output of the feedback
amplifier and the input to the current comparator. Switcher
frequency compensation components are normally placed
on this pin to ground. The voltage on this pin is proportional to the peak primary switch current. The feedback
amplifier output is enabled during the synchronous switch
on time.
UVLO (Pin 10): A resistive divider from V
an undervoltage lockout based upon V
When the UVLO pin is below its threshold, the gate drives
are disabled, but the part draws its normal quiescent
current from VCC. The VCC undervoltage lockout supersedes this function so V
the part.
The bias current on this pin has hysteresis such that the
bias current is sourced when the UVLO threshold is
exceeded. This introduces a hysteresis at the pin equivalent to the bias current change times the impedance of the
upper divider resistor. The user can control the amount of
hysteresis by adjusting the impedance of the divider. See
the Applications Information for details. Tie the UVLO pin
to V
SENSE– (Pin 11), SENSE+ (Pin 12): These pins are used
to measure primary side switch current through an external sense resistor. Peak primary side current is used in the
converter control loop. Make Kelvin connections to the
if you are not using this function.
CC
must be great enough to start
CC
to this pin sets
IN
level (not VCC).
IN
sense resistor to reduce noise problems. SENSE– connects to the ground side. At maximum current (V
maximum voltage) it has a 98mV threshold. The signal is
blanked (ignored) during the minimum turn-on time.
C
(Pin 13): Pin for external filter capacitor for the op-
CMP
tional load compensation function. Load compensation
reduces the effects of parasitic resistances in the feedback
sensing path. A 0.1µF ceramic capacitor suffices for most
applications. Short this pin to GND in less demanding
applications that don’t require load compensation.
R
(Pin 14): Pin for optional external load compensa-
CMP
tion resistor. Use of this pin allows for nominal compensation of parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See Applications
Information for details.
PGDLY (Pin 15): Pin for external programming resistor to
set delay from synchronous gate turn-off to primary gate
turn-on. See Applications Information for details.
PG (Pin 16): Gate Drive Pin for the Primary Side MOSFET
Switch. Large dynamic currents flow during voltage transitions. See the Applications Information for details.
GND (Exposed Pad, Pin 17): This is the ground connection for both signal ground and gate driver grounds. This
GND should be connected to the PCB ground plane.
Careful attention must be paid to ground layout. See
Applications Information for details.
at its
C
3825f
7
LT3825
BLOCK DIAGRA
W
2
10
V
15.3V
UVLO
CC
V
UVLO
CC
+
–
REFERENCE
1.235V
(V
FB
19.5V
+
–
)
INTERNAL
REGULATOR
+
UVLO
–
I
UVLO
TSD
CURRENT TRIP
CLAMPS
0.7
1.3
3V
–
+
SRQ
CURRENT
COMPARATOR
ERROR AMP
Q
COLLAPSE DETECT
–
+
1V
OVERCURRENT
–
FAULT
–
–
+
CURRENT
SENSE AMP
+
+
SFST
SENSE
FB
8
V
C
9
6
–
11
+
SLOPE COMPENSATION
OSC
7
SYNC
5
t
ON
3
PGDLY
15
ENDLY
4
OSCILLATOR
SET
ENABLE
LOGIC
BLOCK
TO FB
PGATE
SGATE
R
CMPF
50k
+
GATE DRIVE
–
V
CC
SENSE
C
CMP
LOAD
COMPENSATION
R
CMP
PG
12
13
14
16
+
3V
–
V
CC
GATE DRIVE
SG
GND
1
17
8
3825f
W
FLYBACK FEEDBACK A PLIFIER
LT3825
R1
FB
8
R2
–
UWW
TI I G DIAGRA
LT3825 FEEDBACK AMP
1V
V
FB
1.25V
+
COLLAPSE
DETECT
ENABLE
–
+
SRQ
V
FLBK
V
T1
FLYBACK
•
C
9
3825 FFA
V
IN
C
VC
V
PRIMARY
MP
IN
•
SECONDARY
•
MS
ISOLATED
C
OUT
OUTPUT
PRIMARY SIDE
MOSFET DRAIN
VOLTAGE
PG VOLTAGE
SG VOLTAGE
V
IN
t
ON(MIN)
ENABLE
DELAY
V
FLBK
MIN ENABLE
FEEDBACK
AMPLIFIER
ENABLED
0.8 • V
FLBK
PG DELAY
3825 TD
3825f
9
LT3825
OPERATIO
U
The LT3825 is a current mode switcher controller IC
designed specifically for use in an isolated flyback topology employing synchronous rectification. The LT3825
operation is similar to traditional current mode switchers.
The major difference is that output voltage feedback is
derived via sensing the output voltage through the transformer. This precludes the need of an optoisolator in
isolated designs greatly improving dynamic response and
reliability. The LT3825 has a unique feedback amplifier
that samples a transformer winding voltage during the
flyback period and uses that voltage to control output
voltage.
The internal blocks are similar to many current mode
controllers. The differences lie in the flyback feedback
amplifier and load compensation circuitry. The logic block
also contains circuitry to control the special dynamic
requirements of flyback control.
For more information on the basics of current mode
switcher/controllers and isolated flyback converters see
Application Note 19.
Feedback Amplifier—Pseudo DC Theory
For the following discussion refer to the simplified Flyback
Feedback Amplifier diagram. When the primary side MOSFET switch MP turns off, its drain voltage rises above the
V
rail. Flyback occurs when the primary MOSFET is off
IN
and the synchronous secondary MOSFET is on. During
flyback the voltage on nondriven transformer pins is
determined by the secondary voltage. The amplitude of
this flyback pulse as seen on the third winding is given as:
VI ESRR
++
•
V
FLBK
R
DS(ON)
I
= transformer secondary current
SEC
ESR = impedance of secondary circuit capacitor, winding
and traces
= transformer effective secondary-to-feedback wind-
N
SF
ing turns ratio (i.e., N
The flyback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
OUT SEC DS ON
=
= on resistance of the synchronous MOSFET M
()
N
SF
S/NFLBK
)
()
S
amplifier compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
amplifier whose output is connected to V
period in the flyback time. An external capacitor on the V
pin integrates the net feedback amp current to provide the
control voltage to set the current mode trip point.
The regulation voltage at the FB pin is nearly equal to the
bandgap reference VFB because of the high gain in the
overall loop. The relationship between V
expressed as:
RR
V
FLBK FB
Combining this with the previous V
an expression for V
programming resistors and secondary resistances:
V
=
OUT FB SF SEC DS ON
The effect of nonzero secondary output impedance is
discussed in further detail; see Load Compensation Theory.
The practical aspects of applying this equation for V
found in the Applications Information.
Feedback Amplifier Dynamic Theory
So far, this has been a pseudo-DC treatment of flyback
feedback amplifier operation. But the flyback signal is a
pulse, not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the “Enable” line in the diagram.
Timing signals are then required to enable and disable the
flyback amplifier. There are several timing signals which
are required for proper LT3825 operation. Please refer to
the Timing Diagram.
Minimum Output Switch On Time (t
The LT3825 affects output voltage regulation via flyback
pulse action. If the output switch is not turned on, there
is no flyback pulse and output voltage information is not
available. This causes irregular loop response and startup/latch-up problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. If the output load is less than that
=
R
RR
+
12
⎛
⎜
⎝
R
2
+12
V
•
2
FLBK
in terms of the internal reference,
OUT
VN I ESRR
•• – •
⎞
⎟
⎠
only during a
C
C
and VFB is
FLBK
expression yields
+
(()
ON(MIN)
)
()
OUT
are
3825f
10
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