LINEAR TECHNOLOGY LT3581 Technical data

V

IN

5V

V

IN

6.04k

100k

130k

43.2k

4.7µF

1.5µH

1nF

3581 TA01

0.1µF

4.7µF

10.5k

4.7µF

V

OUT

12V 830mA

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

56pF

18.7k

10k

LOAD CURRENT (mA)

0

50

EFFICIENCY (%)

POWER LOSS (mW)

55

65

70

75

400

100

95

3581 TA01b

60

200 1000800600

80

85

90

0

200

600

2000

1200

1400

1600

1800

400

800

1000

查询LT3581供应商

LT3581

3.3A Boost/Inverting DC/DC

Converter with Fault Protection

FeaTures

n

3.3A, 42V Combined Power Switch

n

Master/Slave (1.9A/1.4A) Switch Design

n

Output Short Circuit Protection

n

Wide Input Range: 2.5V to 22V Operating,

40V Maximum Transient

n

Switching Frequency Up to 2.5MHz

n

Easily Configurable as a Boost, SEPIC, Inverting or

Flyback Converter

n

User Configurable Undervoltage Lockout

n

Low V

n

Can be Synchronized to External Clock

n

Can Be Synchronized to other Switching Regulators

n

High Gain SHDN Pin Accepts Slowly Varying Input

Switch: 250mV at 2.75A (Typical)

CESAT

Signals

n

14-Pin 4mm × 3mm DFN and 16-Lead MSE Packages

applicaTions

n

Local Power Supply

n

Vacuum Fluorescent Display (VFD) Bias Supplies

n

TFT-LCD Bias Supplies

n

Automotive Engine Control Unit (ECU) Power

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7579816.

DescripTion

The LT®3581 is a PWM DC/DC converter with built-in fault protection features to aid in protecting against output shorts, input/output overvoltages, and overtemperature conditions. The part consists of a 42V master switch, and a 42V slave switch that can be tied together for a total current limit of 3.3A.

The LT3581 is ideal for many local power supply designs. It can be easily configured in Boost, SEPIC, Inverting or Flyback configurations, and is capable of generating 12V at 830mA, or –12V at 625mA from a 5V input. In addition, the LT3581’s slave switch allows the part to be configured in high voltage, high power charge pump topologies that are very efficient and require fewer components than traditional circuits.

he LT3581’s switching frequency range can be set between

T 200kHz and 2.5MHz. The part may be clocked internally at a frequency set by the resistor from the RT pin to ground, or it may be synchronized to an external clock. A buffered version of the clock signal is driven out of the CLKOUT pin, and may be used to synchronize other compatible switching regulator ICs to the LT3581.

The LT3581 also features innovative SHDN pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. Additional features such as frequency foldback and soft-start are integrated. The LT3581 is available in 14-Pin 4mm × 3mm DFN and 16-Lead MSE packages.

Typical applicaTion

Output Short Protected, 5V to 12V Boost Converter Operating at 2MHz

Efficiency and Power Loss vs

Load Current

3581f

1

LT3581

1

2

3

4

5

6

7

14

13

12

11

10

9

8

SYNC

SS

RT

SHDN

CLKOUT

SW2

FB

V

C

GATE

FAULT

V

IN

SW1

TOP VIEW

DE14 PACKAGE

14-PIN (4mm s 3mm) PLASTIC DFN

15

GND

1 2 3 4 5 6 7 8

FB V

C

GATE

FAULT

V

IN

SW1 SW1 SW1

16 15 14 13 12 11 10 9

SYNC SS RT

SHDN

CLKOUT SW2 SW2 SW2

TOP VIEW

MSE PACKAGE

16-LEAD PLASTIC MSOP

17

GND

查询LT3581供应商

absoluTe MaxiMuM raTings

(Note 1)

VIN Voltage .................................................–0.3V to 40V

SW1/SW2 Voltage ..................................... –0.4V to 42V

RT Voltage ...................................................–0.3V to 5V

SS, FB Voltage .......................................... –0.3V to 2.5V

Voltage .................................................... –0.3V to 2V

V

C

SHDN Voltage ............................................ –0.3V to 40V

SYNC Voltage ............................................ –0.3V to 5.5V

GATE Voltage ............................................. –0.3V to 80V

pin conFiguraTion

= 125°C, θJA = 43°C/W, θJC = 4.3°C/W

T

JMAX

EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB

FAULT Voltage ............................................ –0.3V to 40V

FAULT Current .....................................................±500µA

CLKOUT Voltage .......................................... –0.3V to 3V

CLKOUT Current ......................................................1mA

Operating Junction Temperature Range

LT3581E (Notes 2, 4) ......................... –40°C to 125°C

LT3581I (Notes 2, 4) ..........................– 40°C to 125°C

Storage Temperature Range .................. – 65°C to 150°C

T

= 125°C, θJA = 45°C/W, θJC = 10°C/W

JMAX

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3581EDE#PBF LT3581EDE#TRPBF 3581

LT3581IDE#PBF LT3581IDE#TRPBF 3581

LT3581EMSE#PBF LT3581EMSE#TRPBF 3581 16-Lead Plastic MSOP –40°C to 125°C

LT3581IMSE#PBF LT3581IMSE#TRPBF 3581 16-Lead Plastic MSOP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

2

14-Lead (4mm × 3mm) Plastic DFN 14-Lead (4mm × 3mm) Plastic DFN

–40°C to 125°C

3581f

查询LT3581供应商

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Minimum Input Voltage

Overvoltage Lockout 22.1 23.5 25 V

V

IN

Positive Feedback Voltage

Negative Feedback Voltage

Positive FB Pin Bias Current V

Negative FB Pin Bias Current V

Error Amp Transconductance ΔI = 10μA 270 µmhos

Error Amp Voltage Gain 70 V/V

Quiescent Current Not Switching 1.9 2.3 mA

Quiescent Current in Shutdown V

Reference Line Regulation 2.5V ≤ V

Switching Frequency, f

Switching Frequency in Foldback Compared to Normal f

Switching Frequency Range Free-Running or Synchronizing

SYNC High Level for Synchronization

SYNC Low Level for Synchronization

SYNC Clock Pulse Duty Cycle V

Recommended Minimum SYNC Ratio f

SYNC/fOSC

Minimum Off-Time 45 ns

Minimum On-Time 55 ns

SW1 Current Limit At All Duty Cycles

Current Sharing (SW2/SW1) 78 %

SW1 + SW2 Current Limit At All Duty Cycles, SW2/SW1 = 78% (Note 3)

Switch V

CESAT

SW1 Leakage Current V

SW2 Leakage Current V

OSC

= Positive Feedback Voltage, Current into Pin

FB

= Negative Feedback Voltage, Current out of Pin

FB

= 0V 0 1 µA

SHDN

≤ 20V 0.01 0.05 %/V

IN

RT = 34k

= 432k

R

T

OSC

= 0V to 2V 20 80 %

SYNC

SW1 & SW2 Tied Together, I

= 5V 0.01 1 µA

SW1

= 5V 0.01 1 µA

SW2

SW1

+ I

= VIN, V

SHDN

= 2.75A 250 mV

SW2

= VIN, unless otherwise noted. (Note 2).

FAULT

l

1.195 1.215 1.230 V

l

3 9 16 mV

l

81 83.3 85 µA

l

81 83.3 85.5 µA

l

2.25 2.5 2.75 MHz

l

180 200 220 kHz

l

200 2500 kHz

l

1.3 V

l

1.9 2.4 3 A

l

3.3 4.3 5.4 A

LT3581

2.3 2.5 V

1/6 ratio

0.4 V

3/4

3581f

3

LT3581

查询LT3581供应商

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Soft-Start Charge Current V

Soft-Start Discharge Current Part in FAULT, V

Soft-Start High Detection Voltage Part in FAULT

Soft-Start Low Detection Voltage Part Exiting FAULT

SHDN Minimum Input Voltage High Active Mode, SHDN Rising

SHDN Input Voltage Low Shutdown Mode SHDN Pin Bias Current V

CLKOUT Output Voltage High C

CLKOUT Output Voltage Low C

CLKOUT Duty Cycle T

CLKOUT Rise Time C

CLKOUT Fall Time C

GATE Pull Down Current V

GATE Leakage Current V

FAULT Output Voltage Low 100μA into FAULT Pin FAULT Leakage Current V FAULT Input Voltage Low FAULT Input Voltage High

= 30mV, Current Flows Out of SS pin

SS

= 2.1V, Current Flows into SS Pin

SS

Active Mode, SHDN Falling

= 3V

SHDN

V

= 1.3V

SHDN

V

= 0V

SHDN

= 50pF 1.9 2.1 2.3 V

CLKOUT

= 50pF 5 200 mV

CLKOUT

= 25°C 42 %

J

= 50pF 12 ns

CLKOUT

= 50pF 8 ns

CLKOUT

= 3V

GATE

V

= 80V

GATE

= 50V, GATE Off 0.01 1 µA

GATE

= 40V, FAULT Off 0.01 1 µA

FAULT

SHDN

= VIN, V

= VIN, unless otherwise noted. (Note 2).

FAULT

l

5.7 8.7 11.3 µA

l

5.7 8.7 11.3 µA

l

1.65 1.8 1.95 V

l

30 50 85 mV

l

1.27

l

1.24

l

9.7

l

800

l

800

l

700 750 800 mV

l

950 1000 1050 mV

1.33

1.3

40

11.4 0

933 933

150 300 mV

1.41

1.38

13.4

1100 1100

0.3 V

60

0.1

µA µA µA

µA µA

V V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: The LT3581E is guaranteed to meet performance specifications from 0°C to 125°C. Specifications over the –40°C to 125°C junction temperature range are assured by design, characterization and correlation with statistical process controls.

Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reliability.

3581f

4

DUTY CYCLE (%)

20

0

SW1 + SW2 FAULT CURRENT LIMIT (A)

1

2

3

4

30 50

70

80

3581 G01

5

6

40

60

SW1 + SW2 CURRENT (A)

0

SATURATION VOLTAGE (mV)

200

250

300

54

3581 G02

150

100

0

321

50

450

400

350

SW1 + SW2 CURRENT (A)

0

CURRENT SHARING = SW2/SW1 (%)

50

60

70

54

3581 G03

40

30

0

321

10

20

100

90

80

TEMPERATURE (°C)

–50 –25

0

SW1 + SW2 FAULT CURRENT LIMIT (A)

1

2

3

4

0 50 125 150

3581 G04

5

6

25 75 100

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

1.2100

POSITIVE FB VOLTAGE (V)

1.2125

1.2200

3581 G05

1.2175

1.2150

TEMPERATURE (°C)

–75 –50 –25

10

CLKOUT DC (%)

20

30

40

50

0 50 125 150

3581 G06

60

80

70

25 75 100

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

0

FREQUENCY (kHz)

3200

3581 G07

2800

2400

2000

1600

1200

800

400

RT = 34k

RT = 432k

FB VOLTAGE (V)

0

SWITCHING FREQUENCY RATIO (f

SW

/f

OSC

)

1/4 1/5 1/6

1/2

1/3

1

0.2 0.4 0.6 0.8

3581 G08

1.0 1.2

BOOSTING

CONFIGURATIONS

INVERTING

CONFIGURATIONS

0 60 8020 40

GATE VOLTAGE (V)

0

GATE CURRENT (µA)

1000

3581 G09

900

800

700

600

500

400

200

100

300

125°C

–40°C

25°C

查询LT3581供应商

Typical perForMance characTerisTics

= 25°C, unless otherwise noted.

T

A

LT3581

Switch Fault Current Limit vs Duty Cycle

Switch Fault Current Limit vs Temperature

Switch Saturation Voltage with SW1 and SW2 Tied Together

Positive Feedback Voltage vs Temperature

Current Sharing Between SW1 and SW2 When Tied Together

CLKOUT Duty Cycle vs Temperature

Oscillator Frequency Frequency Foldback Gate Current vs Gate Voltage

3581f

5

LT3581

SS VOLTAGE (V)

0

GATE CURRENT (µA)

100

300

500

700

200

400

600

800

0.25 0.50 0.75 1.00

3581 G10

1.25 1.50

900

1000

SS VOLTAGE (V)

0

SW1 + SW2 CURRENT (A)

1

2

3

0.2 0.4 0.6 0.8

3580 G11

1.0 1.2

4

5

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

1.20

SHDN VOLTAGE (V)

1.22

1.26

1.28

1.30

1.40

1.34

3581 G12

1.24

1.36

1.38

1.32

SHDN RISING

SHDN FALLING

SHDN VOLTAGE (V)

0

SHDN PIN CURRENT (µA)

4

8

12

16

20

24

28

32

0.4 1.0 1.40.2 1.20.6 1.60.8 1.8 2.0

3581 G13

125°C

–40°C

25°C

SHDN VOLTAGE (V)

0

SHDN PIN CURRENT (µA)

200

250

15 25

3581 G14

150

100

5 10 20 403530

50

0

125°C

–40°C

25°C

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

2.20

V

IN

VOLTAGE (V)

2.22

2.26

2.28

2.30

2.40

2.34

3581 G15

2.24

2.36

2.38

2.32

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

16

V

IN

VOLTAGE (V)

18

20

30

24

3581 G17

26

28

22

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

0

FAULT VOLTAGE (V)

1.25

0.50

3581 G18

0.75

1.00

0.25

FAULT RISING

FAULT FALLING

0 50 250200150100

CLKOUT CAPACITIVE LOAD (pF)

0

CLKOUT RISE OR FALL TIME (ns)

5

15

20

25

50

35

3581 G16

10

40

45

30

CLKOUT FALL TIME

CLKOUT RISE TIME

查询LT3581供应商

Typical perForMance characTerisTics

TA = 25°C, unless otherwise noted.

Commanded Current Limit vs

Gate Current vs SS Voltage

SS Voltage

SHDN Pin Current SHDN Pin Current Internal UVLO

SHDN Voltage Threshold with

Hysteresis

CLKOUT Rise Time at 1MHz VIN OVLO

6

FAULT Input Voltage Threshold with Hysteresis

3581f

R

V V

Boost or SEPIC

FB

OUT

=

•

 



 



– .

.

;

–

1 215

83 3 10

6

CConverter

R

V mV

Inv

FB

OUT

=

+

•

 



 



| |

.

;

–

9

83 3 10

6

eertingConverter

查询LT3581供应商

LT3581

pin FuncTions

(DFN/MSOP)

FB (Pin 1/Pin 1): Positive and Negative Feedback Pin. For

a Boost or Inverting Converter, tie a resistor from the FB pin to V

according to the following equations:

OUT

VC (Pin 2/Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin.

GATE (Pin 3/Pin 3): PMOS Gate Drive Pin. The GATE pin is a pull-down current source, used to drive the gate of an external PMOS for output short circuit protection or output disconnect. The GATE pin current increases linearly with the SS pin’s voltage, with a maximum pull-down current of 933µA at SS voltages exceeding 500mV. Note that if the SS voltage is greater than 500mV and the GATE pin voltage is less than 2V, then the GATE pin looks like a 2kΩ impedance to ground. See the Appendix for more information.

FAULT (Pin 4/Pin 4): Fault Indication Pin. This active low, bidirectional pin can either be pulled low (below 750mV) by an external source, or internally by the chip to indicate a fault. When pulled low, this pin causes the power switches to turn off, the GATE pin to become high impedance, the CLKOUT pin to become disabled, and the SS pin to go through a charge/discharge sequence. The end/absence of a fault is indicated when the voltage on this pin exceeds 1V. A pull-up resistor or current source is needed on this pin to pull it above 1V in the absence of a fault.

(Pin 5/Pin 5): Input Supply Pin. Must be locally by-

V

IN

passed.

SW1 (Pins 6, 7/Pins 6,7, 8): Master Switch Pin. This is the collector of the internal master NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI.

CLKOUT (Pin 10/Pin 12): Clock Output Pin. Use this pin to synchronize one or more other compatible switching regulator ICs to the LT3581. The clock that this pin outputs runs at the same frequency as the internal oscillator of the part or as the SYNC pin. CLKOUT may also be used as a temperature monitor since the CLKOUT pin’s duty cycle varies linearly with the part’s junction temperature. Note that the CLKOUT pin is only meant to drive capacitive loads up to 50pF.

SHDN (Pin 11/Pin 13): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below 300mV to disable the chip. Drive above 1.33V (typical) to activate the chip and restart the soft-start sequence. Do not float this pin.

RT (Pin 12/Pin 14): Timing Resistor Pin. Adjusts the LT3581’s switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float this pin.

SS (Pin 13/Pin 15): Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a (nominally) 250k resistor to about 2.1V. During a fault, the SS pin will be slowly charged up and eventually discharged as part of a timeout sequence (see the State Diagram for more information on the SS pin’s role during a fault event).

SYNC (Pin 14/Pin 16): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock must exceed

1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information.

GND (Exposed Pad Pin 15/Exposed Pad Pin 17): Ground. Exposed pad must be soldered directly to local ground plane.

SW2 (Pins 8, 9/Pins 9, 10, 11): Slave Switch Pin. This is the collector of the internal slave NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI.

3581f

7

LT3581

FREQUENCY

FOLDBACK

RAMP

GENERATOR

COMPARATOR

DRIVER DISABLE

SS

LDO

V

C

R

GATE

14.6k

SR1

A3

SYNC CLKOUT

÷N

SS

SHDN

C

OUT1

SW1

SW2

FB

27mΩ

R

S

20mΩ

GND

R

T

RT

R

C

V

C

R

FB

DRIVER

D1

V

IN

SYNC

BLOCK

UVLO

R

S

Q

3581 BD

–

+

A4

Q2

+ –

TD ~ 30ns

VBE • 0.9

1.17V

45mV

L1

FB

∑

ADJUSTABLE OSCILLATOR

–

+

–

+

A1

A3

C

SS

C

IN

1.33V

+ –

– +

+ –

250k

2.1V

1.8V

50mV

SOFT-

START

STARTUP

AND FAULT

LOGIC

C

OUT2

V

OUT

V

IN

M1

GATE

OPTIONAL

SAMPLE MODE BLOCK

R

FAULT

933µA

–

+

–

+

–

+ –

DIE TEMP

22V

MIN

165°C

V

IN

750mV

SW1

**

**SW OVERVOLTAGE PROTECTION IS NOT GUARANTEED TO PROTECT THE LT3581 DURING SW OVERVOLTAGE EVENTS

**

I

SW1

42V MIN

1.9A MIN

SW2

SAMPLE

–

+

A2

1.215V

REFERENCE

Q1

查询LT3581供应商

block DiagraM

3581f

Figure 1. Block Diagram

8

SHDN < 1.33V (TYPICAL)

or

V

IN

< 2.3V (TYPICAL)

SHDN > 1.33V (TYPICAL)

AND

V

IN

> 2.3V (TYPICAL)

FAULT DETECTED

• SS CHARGES UP

• IGATE OFF

• FAULT PIN PULLED LOW INTERNALLY BY LT3581

• SWITCHER DISABLED

• CLKOUT DISABLED

SS < 50mV

IF |V

OUT

| DROPS CAUSING:

FB < 1.17V (BOOST)

OR

FB > 45mV (INVERTING)

FAULT1

SS > 1.8V AND NO FAULT1 CONDITIONS STILL DETECTED

SS < 50mV

FAULT1

FAULT2

FAULT PIN > 1.0V

FAULT1 = OVER VOLTAGE PROTECTION ON V

IN

(VIN > 22V MIN)

OVER TEMPERATURE (T

JUNCTION

> 165°C)

OVER CURRENT ON SW1 (I

SW1

> 1.9A MIN)

OVER VOLTAGE PROTECTION ON SW1 (V

SW1

> 42V MIN)

OVER VOLTAGE PROTECTION ON SW2 (V

SW2

> 42V MIN)

FAULT2 = FAULT PULLED LOW EXTERNALLY (FAULT < 0.75V)

CHIP OFF

• ALL SWITCHES DISABLED

• I

GATE

OFF

• FAULTS CLEARED

INITIALIZE

• SS PULLED LOW

NORMAL MODE

• NORMAL OPERATION

• CLKOUT ENABLED WHEN SS > 1.8V

SAMPLE MODE

• Q1 & Q2 SWITCHES FORCED ON EVERY CYCLE FOR AT LEAST MINIMUM ON TIME

• I

GATE

FULLY ACTIVATED

WHEN SS > 500mV

SOFT START

• I

GATE

ENABLED

• SS CHARGES UP

• SWITCHER ENABLED

POST FAULT DELAY

• SS SLOWLY DISCHARGES

LOCAL FAULT OVER

• INTERNAL FAULT PIN PULLDOWN RELEASED BY LT3581

• SS CONTINUES DISCHARGING TO GND

3581 SD

查询LT3581供应商

sTaTe DiagraM

LT3581

Figure 2. State Diagram

3581f

9

LT3581

R

V V

V

R

µ

UVLO

INUVLO

UVLO12

1 33

11 6

=

 



 



+

– .

.

AA

R

UVLO2

(OPTIONAL)

1.33V

R

UVLO1

3581 F03

V

IN

V

IN

ACTIVE/

LOCKOUT

GND

11.6µA

AT 1.33V

–

+

SHDN

查询LT3581供应商

operaTion

OPERATION – OVERVIEW

The LT3581 uses a constant-frequency, current mode con- trol scheme to provide excellent line and load regulation. The part’s undervoltage lockout (UVLO) function, together with soft-start and frequency foldback, offers a controlled means of starting up. Fault features are incorporated in the LT3581 to aid in the detection of output shorts, over-volt- age, and overtemperature conditions. Refer to the Block Diagram (Figure 1) and the State Diagram (Figure 2) for the following description of the part’s operation.

Figure 3. Configurable UVLO

PERATION – START-UP

O

Several functions are provided to enable a very clean start-up for the LT3581:

Precise Turn-On Voltage

The SHDN pin is compared to an internal voltage reference to give a precise turn on voltage level. Taking the SHDN pin above 1.33V (typical) enables the part. Taking the SHDN pin below 300mV shuts down the chip, resulting in extremely low quiescent current. The SHDN pin has 30mV of hysteresis to protect against glitches and slow ramping.

Undervoltage Lockout (UVLO)

The SHDN pin can also be used to create a configurable UVLO. The UVLO function sets the turn on/off of the LT3581 at a desired input voltage (V resistor divider (or single resistor) from V pin can be used to set V

INUVLO

). Figure 3 shows how a

INUVLO

IN

. R

is optional. It may

UVLO2

to the SHDN

be left out, in which case set it to infinite in the equation below. For increased accuracy, set R

UVLO1

as follows:

R

≤ 10k. Pick

UVLO2

The LT3581 also has internal UVLO circuitry that disables the chip when V

< 2.3V (typical).

IN

Soft-Start of Switch Current

The soft-start circuitry provides for a gradual ramp-up of the switch current (refer to Commanded Current Limit vs SS Voltage in Typical Performance Characteristics). When the part is brought out of shutdown, the external SS capacitor is first discharged which resets the states of the logic circuits in the chip. Then an integrated 250k resistor pulls the SS pin to ~1.8V. The ramp rate of the SS pin voltage is set by this 250k resistor and the external capacitor connected to this pin. Once SS gets to 1.8V, the CLKOUT pin is enabled, and an internal regulator pulls the pin up quickly to ~2.1V. Typical values for the external soft-start capacitor range from 100nF to 1μF.

Soft-Start of External PMOS (if used)

The soft-start circuitry also gradually ramps up the GATE pin pull-down current which allows an external PMOS to slowly turn on (M1 in Block Diagram). The GATE pin current increases linearly with the SS voltage, with a maximum current of 933µA when the SS voltage gets above 500mV. Note that if the GATE pin voltage is less than 2V for SS voltages exceeding 500mV, then the GATE pin impedance to ground is 2kΩ. The soft turn on of the external PMOS helps limit inrush current at start-up, making hot-plugs of LT3581s feasible and safe.

10

3581f

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operaTion

LT3581

Sample Mode

Sample Mode is the mechanism used by the LT3581 to aid in the detection of output shorts. It refers to a state of the LT3581 where the master and slave power switches (Q1 and Q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to “sample” the inductor current. If the sampled current through Q1 exceeds the master switch cur- rent limit of 1.9A (min), the LT3581 triggers an overcurrent fault internally (see Operation-Fault section for details). Sample Mode is active when FB is out of regulation by more than approximately 3.7% (45mV < FB < 1.17V).

Frequency Foldback

The frequency foldback circuit reduces the switching fre- quency when 350mV < FB < 900mV (typical). This feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current dur- ing start-up. When the FB voltage is pulled outside of this range, the switching frequency returns to normal.

Note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target V

every application’s performance at start-up to ensure that the peak inductor current does not exceed the minimum fault current limit.

, VIN, switching frequency, etc. Test each and

OUT

Q1’s emitter current flows through a current sense resistor

) generating a voltage proportional to the total switch

(R

S

current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When the voltage on the positive input of A3 exceeds the voltage on the negative input, the SR latch is reset, turning off the master and slave power switches. The voltage on the negative input of A3

pin) is set by A1 (or A2), which is simply an amplified

(V

C

difference between the FB pin voltage and the reference voltage (1.215V if the LT3581 is configured as a boost converter, or 9mV if configured as an inverting converter). In this manner, the error amplifier sets the correct peak current level to maintain output regulation.

As long as the part is not in fault (see Operation – Fault section) and the SS pin exceeds 1.8V, the LT3581 drives its CLKOUT pin at the frequency set by the RT pin or the SYNC pin. The CLKOUT pin can be used to synchronize other compatible switching regulator ICs (including additional LT3581s) with the LT3581. Additionally, CLKOUT’s duty cycle varies linearly with the part’s junction temperature, and may be used as a temperature monitor.

TION – FAULT

PERA

O

The LT3581’s FAULT pin is an active low, bidirectional pin that is pulled low to indicate a fault. Each of the following events can trigger a fault in the LT3581:

PERATION – REGULATION

O

The following description of the LT3581’s operation as- sumes that the FB voltage is close enough to its regulation target so that the part is not in sample mode. Use the Block Diagram as a reference when stepping through the following description of the LT3581 operating in regulation. At the start of each oscillator cycle, the SR latch (SR1) is set, which turns on the power switches Q1 and Q2. The collector current through the master switch, Q1, is ~1.3 times the collector current through the slave switch, Q2, when the collectors of the two switches are tied together.

AULT1 events:

A. F

1. SW Over a. b. (I

2. V

3. SW1 Voltage and/or SW2 Voltage > 42V (minimum)

4. Die T B. FAULT2 events:

1. Pulling the F

I

IN

current:

> 1.9A (minimum)

SW1

+ I

SW1

Voltage > 22V (minimum)

emperature > 165°C

) > 3.3A (minimum)

SW2

AULT pin low externally

3581f

11

LT3581

V

OUT

10V/DIV

V

CLKOUT

2V/DIV

I

L

2A/DIV

V

FAULT

5V/DIV

3581 F04

5µs/DIV

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operaTion

Refer to the State Diagram (Figure 2) for the following description of the LT3581’s operation during a fault event. When a fault is detected, in addition to the FAULT pin being pulled low internally, the LT3581 also disables its CLKOUT pin, turns off its power switches, and the GATE pin becomes high impedance. The external PMOS, M1, turns off when the gate of M1 is pulled up to its source by the external

resistor (see Block Diagram). With the external

R

GATE

PMOS turned off, the power path from V

IN

to V

OUT

is cut

off, protecting power components downstream.

At the same time, a timeout sequence commences where the SS pin is charged up to 1.8V (the SS pin will continue charging up to 2.1V and be held there in the case of a FAULT1 event that has still not ended), and then discharged to 50mV. This timeout period relieves the part, the PMOS, and other downstream power components from electrical

and thermal stress for a minimum amount of time as set by the voltage ramp rate on the SS pin.

In the absence of faults, the FAULT pin is pulled high by the external R

resistor (typically 100k). Figure 4 shows

FAULT

the events that accompany the detection of an output short on the LT3581.

Figure 4. Output Short Circuit Protection of the LT3581

3581f

12

D1

20V, 2A

V

IN

5V

R

GATE

6.04k

R

FAULT

100k

R

FB

130k

R

T

43.2k

C

IN

4.7µF

L1

1.5µH

C

1nF

C

OUT2

4.7µF

3581 F05

C

SS

0.1µF

R

C

10.5k

C

OUT1

4.7µF

V

OUT

12V I

OUT

< 0.83A

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

C

F

56pF

OPTIONAL

PMOS

DC

V V V

OUT IN

OUT

≅

+

– .

. – .

0 5

0 5 0 3

L

V V DC

f A

L

V V

TYP

IN

OSC

MIN

IN

=

( )

•

=

( )

• •

– .

0 3

1

0 3 2

DDC

A f DC

L

V V DC

f

OSC

MAX

IN

O

–

. –

– .

1

2 2 1

0 3

( )

• •

( )

=

( )

•

SSC

A• 0 35.

I

V V DC

f L

RIPPLE

IN

OSC

=

( )

•

– .0 3

1

I A

I

DC

OUT

RIPPLE

=

 



 



•

( )

3 3

2

1. – –

V V I I

R OUT AVG OUT

> >;

C C

I DC

f V I

OUT OUT

OUT

OSC OUT OUT

1 2

0 01 0 50

= ≥

•

. • – . • •

RR

DSON PMOS_









C C C

A DC

f V

I

IN VIN PWR

OSC IN

RIP

≥ + ≥

•

• • •

+

3 3

45 0 005..

PPLE

OSC IN

f V8 0 005• • . •

R

V V

µA

FB

OUT

=

– ..1 215

83 3

R

f

f in MHz and R in k

T

OSC

OSC T

=

87 61.

– ; Ω

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applicaTions inForMaTion

LT3581

BOOST CONVERTER COMPONENT SELECTION

Figure 5. Boost Converter – The Component Values and Voltages Given Are Typical Values for a 2MHz, 5V to 12V Boost

The LT3581 can be configured as a Boost converter as in Figure 5. This topology allows for positive output volt- ages that are higher than the input voltage. An external PMOS (optional) driven by the GATE pin of the LT3581 can achieve input or output disconnect during a fault event. A single feedback resistor sets the output voltage. For output voltages higher than 40V, see the Charge Pump Aided Regulators section.

Table 1 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a boost converter. Input parameters are input and output voltage, and switching frequency (V

IN

OUT

and f

OSC

re-

, V spectively). Refer to the Appendix for further information on the design equations presented in Table 1.

Table 1. Boost Design Equations

PARAMETERS/EQUATIONS

Step 1: Inputs

Step 2: DC

Step 3: L1

Step 4: I

RIPPLE

Step 5: I

OUT

Step 6: D1

Step 7: C C

Pick V

, V

, and f

IN

OUT

to calculate equations below.

OSC

• Pick L1 out of a range of inductor values where the minimum

value of the range is set by L The maximum value of the range is set by L on how to choose current rating for inductor value chosen.

,

OUT1 OUT2

• If PMOS is not used, then use just one capacitor where

C

= C

+ C

OUT

OUT1

OUT2

.

TYP

or L

, whichever is higher.

MIN

. See appendix

MAX

(1)

(2)

(3)

Variable Definitions:

= Input Voltage

V

IN

= Output Voltage

V

OUT

DC = Power Switch Duty Cycle

= Switching Frequency

f

OSC

= Maximum Average Output Current

I

OUT

I R using PMOS)

= Inductor Ripple Current

RIPPLE

DSON_PMOS

= R

DSON

of External PMOS (set to 0 if not

Step 8: C

IN

• Refer to Input Capacitor Selection in Appendix for definition of

C

VIN

and C

PWR

.

Step 9: R

FB

Step 10: R

T

Step 11: PMOS

Only needed for input or output disconnect. See PMOS Selection in the Appendix for information on sizing the PMOS, R picking appropriae UVLO components.

GATE

and

Note 1: The maximum design target for peak switch current is 3.3A and is used in this table.

, C

Note 2: The final values for C above equations in order to obtain desired load transient performance.

OUT1

and CIN may deviate from the

OUT2

3581f

13

LT3581

DC

V V

V V V V

OUT

IN OUT

≅

+

+ +

0 5

0 5 0 3

.

. – .

L

V V DC

f A

L

V V

TYP

IN

OSC

MIN

IN

=

( )

•

=

( )

• •

– .

0 3

1

0 3 2

DDC

A f DC

L

V V DC

f

OSC

MAX

IN

O

–

. –

– .

1

2 2 1

0 3

( )

• •

( )

=

( )

•

SSC

A• 0 35.

I

V V DC

f L

RIPPLE

IN

OSC

=

( )

•

– .0 3

I A

I

DC

OUT

RIPPLE

=

 



 



•

( )

3 3

2

1. – –

V V V I I

R IN OUT AVG OUT

> + >;

C µF V V

RATING IN

1 1≥ ≥;

C

I DC

f V

OUT

OSC OUT

≥

•

• •0 005.

C C C

A DC

f V

I

IN VIN PWR

OSC IN

RIP

≥ + ≥

•

• • •

+

3 3

45 0 005..

PPLE

OSC IN

f V8 0 005• • . •

R

V V

µA

FB

OUT

=

– ..1 215

83 3

R

f

f in MHz and R in k

T

OSC

OSC T

=

87 61.

– ; Ω

D1

30V, 2A

V

IN

3V TO 16V

R

FAULT

100k

R

T

124k

L1

3.3µH

3581 F06

C

SS

1µF

C

OUT

22µF s2

L2

3.3µH

C

IN

22µF

V

OUT

5V I

OUT

< 0.9A (VIN = 3V)

I

OUT

< 1.5A (VIN = 12V)

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT SHDN

ENABLE

LT3581

C

F

100pF

C1

1µF

R

FB

45.3k

•

C

2.2nF

R

C

7.87k

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applicaTions inForMaTion

SEPIC CONVERTER COMPONENT SELECTION (COUPLED OR UN-COUPLED INDUCTORS)

Figure 6. SEPIC Converter – The Component Values and Voltages Given Are Typical Values for a 700kHz, Wide Input Range (3V to 16V) SEPIC Converter with 5V Out

The LT3581 can also be configured as a SEPIC as shown in Figure 6. This topology allows for positive output voltages that are lower, equal, or higher than the input voltage. Out- put disconnect is inherently built into the SEPIC topology, meaning no DC path exists between the input and output due to capacitor C1. This implies that a PMOS controlled by the GATE pin is not required in the power path.

Table 2 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a SEPIC converter. Input parameters are input and output voltage, and switching frequency (V

IN

OUT

and f

OSC

re-

, V spectively). Refer to the Appendix for further information on the design equations presented in Table 2.

Variable Definitions:

Table 2. SEPIC Design Equations

PARAMETERS/EQUATIONS

Step 1: Inputs

Step 2: DC

Step 3: L

Step 4: I

RIPPLE

Step 5: I

OUT

Step 6: D1

Step 7: C1

Step 8: C

OUT

Pick V

, V

, and f

IN

OUT

to calculate equations below.

OSC

• Pick L out of a range of inductor values where the minimum value of the range is set by L The maximum value of the range is set by L Appendix on how to choose current rating for inductor value chosen.

• Pick L1 = L2 = L for coupled inductors.

• Pick L1L2 = L for un-coupled inductors.

• L = L1 = L2 for coupled inductors.

• L = L1L2 for un-coupled inductors.

TYP

or L

, whichever is higher.

MIN

MAX

(1)

(2)

(3)

. See

= Input Voltage

V

IN

= Output Voltage

V

OUT

DC = Power Switch Duty Cycle

= Switching Frequency

f

OSC

= Maximum Average Output Current

I

OUT

I

14

= Inductor Ripple Current

RIPPLE

Step 9: C

IN

• Refer to Input Capacitor Selection in Appendix for definition

of C

VIN

and C

PWR

.

Step 10: R

FB

Step 11: R

T

Note 1: The maximum design target for peak switch current is 3.3A and is used in this table.

Note 2: The final values for C equations in order to obtain desired load transient performance.

, CIN and C1 may deviate from the above

OUT

3581f

DC

V V

V V V V

OUT

IN OUT

≅

+

+ +

| | .

| | . – .

0 5

0 5 0 3

L

V V DC

f A

L

V V

TYP

IN

OSC

MIN

IN

=

( )

•

=

( )

• •

– .

0 3

1

0 3 2

DDC

A f DC

L

V V DC

f

OSC

MAX

IN

O

–

. –

– .

1

2 2 1

0 3

( )

• •

( )

=

( )

•

SSC

A• 0 35.

I

V V DC

f L

RIPPLE

IN

OSC

=

( )

•

– .0 3

I A

I

DC

OUT

RIPPLE

=

 



 



•

( )

3 3

2

1. – –

V V V I I

R IN OUT AVG OUT

> + >| | ;

C µF V V V

RATING IN OUT

1 1≥ ≥ +; | |

C

I

f V

OUT

RIPPLE

OSC OUT

≥

• •

( )

8 0 005. | |

C C C

A DC

f V

I

IN VIN PWR

OSC IN

RIP

≥ + ≥

•

• • •

+

3 3

45 0 005..

PPLE

OSC IN

f V8 0 005• • . •

R

V mV

µA

FB

OUT

=

+| |.5

83 3

R

f

f in MHz and R in k

T

OSC

OSC T

=

87 61.

– ; Ω

L2

3.3µH

D1 20V 1A

V

IN

5V

R

FAULT

100k

R

T

43.2k

L1

3.3µH

3581 F07

C

SS

100nF

C

OUT

4.7µF

C

IN

3.3µF

V

OUT

–12V I

OUT

< 625mA

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT SHDN

ENABLE

LT3581

C

F

47pF

R

FB

143k

•

C

1nF

R

C

11k

C1

1µF

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applicaTions inForMaTion

LT3581

DUAL INDUCTOR INVERTING CONVERTER COMPONENT SELECTION (COUPLED OR UN-COUPLED INDUCTORS)

Figure 7. Dual Inductor Inverting Converter – The Component Values and Voltages Given Are Typical Values for a 2MHz, 5V to –12V Inverting Topology Using Coupled Inductors

Due to its unique FB pin, the LT3581 can work in a Dual Inductor Inverting configuration as in Figure 7. Changing the connections of L2 and the Schottky diode in the SEPIC topology results in generating negative output voltages. This solution results in very low output voltage ripple due to inductor L2 being in series with the output. Output disconnect is inherently built into this topology due to the capacitor C1.

Table 3. Dual Inductor Inverting Design Equations

PARAMETERS/EQUATIONS

, V

Step 1: Inputs Pick V

Step 2: DC

Step 3: L

• Pick L out of a range of inductor values where the

minimum value of the range is set by L whichever is higher. The maximum value of the range is set by L rating for inductor value chosen.

• Pick L1 = L2 = L for coupled inductors.

• Pick L1L2 = L for un-coupled inductors.

Step 4: I

RIPPLE

• L = L1 = L2 for coupled inductors.

• L = L1L2 for un-coupled inductors.

Step 5: I

OUT

Step 6: D1

, and f

IN

OUT

MAX

to calculate equations below.

OSC

TYP

. See Appendix on how to choose current

or L

MIN

(1)

(2)

(3)

,

Table 3 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a dual inductor inverting converter. Input parameters are input and output voltage, and switching frequency (V

and f

V

OUT

OSC

further information on the design equations presented in Table 3.

Variable Definitions:

= Input Voltage

V

IN

= Output Voltage

V

OUT

DC = Power Switch Duty Cycle

= Switching Frequency

f

OSC

I I

= Maximum Average Output Current

OUT

= Inductor Ripple Current

RIPPLE

respectively). Refer to the Appendix for

IN

Step 7: C1

Step 8: C

,

Step 9: C

Step 10: R

Step 11: R

Note 1: The maximum design target for peak switch current is 3.3A and is used in this table.

Note 2: The final values for C equations in order to obtain desired load transient performance.

OUT

IN

• Refer to Input Capacitor Selection in Appendix for

definition of C

FB

T

and C

VIN

, CIN and C1 may deviate from the above

OUT

PWR

.

3581f

15

LT3581

3581 F08

V

OUT

C

IN

B

A

SYNC

GND

A: RETURN C

IN

GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT

COMBINE C

IN

GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

B: RETURN C

OUT

AND C

OUT1

GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED

TO NOT COMBINE C

OUT

AND C

OUT1

GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

SHDN

CLKOUT

+

–

V

IN

+

–

L1

17

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C

OUT1

R

GATE

C

OUT

D1

M1

D2

3581 F09

V

OUT

C

IN

C1

D1

B

A

SYNC

GND

A: RETURN C

IN

AND L2 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED

TO NOT COMBINE C

IN

AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

B: RETURN C

OUT

GROUNDS DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED

TO NOT COMBINE C

OUT

GROUND WITH GND EXCEPT AT THE EXPOSED PAD. L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.

C

OUT

SHDN

CLKOUT

+

–

V

IN

+

–

•

L2

L1

17

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

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applicaTions inForMaTion

LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL INDUCTOR INVERTING TOPOLOGIES

General Layout Guidelines

• To optimize thermal performance, solder the exposed ground pad of the LT3581 to the ground plane, with multiple vias around the pad connecting to additional ground planes.

• A

ground plane should be used under the switcher circuitry

to prevent interplane coupling and overall noise.

• High

speed switching path (see specific topology for

more information) must be kept as short as possible.

• The

V

, FB, and RT components should be placed as

C

close to the LT3581 as possible, while being as far away as practically possible from the switch node. The ground for these components should be separated from the switch current path.

• Place the bypass capacitor for the V

pin as close as

IN

possible to the LT3581.

• Place the bypass capacitor for the inductor as close as possible to the inductor.

• The

load should connect directly to the positive and negative terminals of the output capacitor for best load regulation.

Boost Topology Specific Layout Guidelines

• Keep length of loop (high speed switching path) governing switch, diode D1, output capacitor C

OUT1

, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching.

SEPIC Topology Specific Layout Guidelines

• Keep

length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, output capacitor C

, and ground return as short as possible

OUT

to minimize parasitic inductive spikes at the switch node during switching.

Inverting Topology Specific Layout Guidelines

• Keep

ground return path from the cathode of D1 (to chip) separated from output capacitor C

OUT

’s ground return path (to chip) in order to minimize switching noise coupling into the output.

• Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching.

Figure 8. Suggested Component Placement for Boost Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance

16

Figure 9. Suggested Component Placement for SEPIC Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance

3581f

DC

V V V

OUT IN D

OUT D CESAT

=

+

+––

DC

V V V

=

+

12 5 0 45

12 0 45 0 21

– .

. – .

I

V I

V

IN

OUT OUT

IN

=

•

• η

I

V A V

IN

=

•

12 0 83

5 0 88..

P DC I R

SWDC IN SW

= • •

2

P A m

SWDC

= • •0 609 2 3 90

2

. ( . ) Ω

P ns I V f

SWAC IN OUT OSC

= • • •13

P ns A V MHz

SWAC

=

( )

• • •

( )

13 2 3 12 2.

P

V I DC

BDC

IN IN

=

• •

45

P

V A

BDC

=

• •5 2 3 0 609

45

. .

P mA V

INP IN

= •9

P mA V

INP

= •9 5

3581 F10

C

IN

B

A

C

SYNC

GND

A: RETURN C

IN

GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED

TO NOT COMBINE C

IN

GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

B: RETURN C

OUT

GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED

TO NOT COMBINE C

OUT

GROUND WITH GND EXCEPT AT THE EXPOSED PAD. C: RETURN D1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.

C

OUT

SHDN

CLKOUT

– V

OUT

GND

V

IN

+

–

•

L2

L1

17

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C1

D1

查询LT3581供应商

applicaTions inForMaTion

LT3581

the heat generated within the package. This can be accomplished by taking advantage of the thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible.

Power and Thermal Calculations

Power dissipation in the LT3581 chip comes from four

2

primary sources: switch I

R losses, switch dynamic losses, NPN base drive DC losses, and miscellaneous input current losses. These formulas assume continuous mode operation, so they should not be used for calculating thermal losses or efficiency in discontinuous mode or at light load currents.

The following example calculates the power dissipa-

Figure 10. Suggested Component Placement for Dual Inductor Inverting Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance

THERMAL CONSIDERATIONS

Overview

For the

LT3581 to deliver its full output power, it is imp-

tion in the LT3581 for a particular boost application (V

IN

V

CESAT

= 5V, V

= 0.21V).

OUT

= 12V, I

OUT

= 0.83A, f

= 2MHz, VD = 0.45V,

OSC

To calculate die junction temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature:

= TA + θJA • P

T

J

TOTAL

erative that a good thermal path be provided to dissipate

Table 4. Power Calculations Example for Boost Converter with VIN = 5V, V

DEFINITION OF VARIABLES EQUATIONS DESIGN EXAMPLE VALUE

DC = SWITCH DUTY CYCLE

OUT

= 12V, I

= 0.83A, f

OUT

= 2MHz, VD = 0.45V, V

OSC

= 0.21V

CESAT

DC = 60.9%

= Average Switch Current

I

IN

η = Power Conversion Efficiency (typically 88% at high currents)

= Switch I2R Loss (DC)

P

SWDC

R

= Switch Resistance (typically

SW

90mΩ combined SW1 and SW2)

= Switch Dynamic Loss (AC)

P

SWAC

= Base Drive Loss (DC)

P

BDC

= Input Power Loss

P

INP

IIN = 2.3A

P

SWDC

P

SWAC

P

BDC

P

INP

P

TOTAL

= 290mW

= 718mW

= 156mW

= 45mW

= 1.209W

3581f

17

LT3581

T

DC

J

CLKOUT

=

– %

. %

35

0 3

f

R

OSC

T

=

+

87 61.

R

f

T

OSC

=

87 61.

–

查询LT3581供应商

applicaTions inForMaTion

where TJ = Die Junction Temperature, TA = Ambient Tem- perature, P shown in Table 4, and θ

is the final result from the calculations

TOTAL

is the thermal resistance from

JA

the silicon junction to the ambient air.

The published (http://www.linear.com/designtools/packag- ing/Linear_Technology_Thermal_Resistance_Table.pdf)

value is 43°C/W for the 4mm × 3mm 14-pin DFN

θ

JA

package and 45°C/W for the 16-lead MSOP package. In practice, lower θ

values are realizable if board layout is

JA

performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the Layout Guidelines section. For instance, a

value of ~24°C/W was consistently achieved for both

θ

JA

MSE and DFN packages of the LT3581 (at V 12V, I

= 0.83A, f

OUT

= 2MHz) when board layout was

OSC

= 5V, V

IN

OUT

=

optimized as per the suggestions in the Board Layout Guidelines section.

Junction Temperature Measurement

The duty cycle of the CLKOUT signal is linearly propor- tional to die junction temperature, T

. To get a temperature

J

reading, measure the duty cycle of the CLKOUT signal and use the following equation to approximate the junction temperature:

Thermal Lockout

A fault condition occurs when the die temperature exceeds 165°C (see Operation Section), and the part goes into thermal lockout. The fault condition ceases when the die temperature drops by ~5°C (nominal).

WITCHING

S

FREQUENCY

There are several considerations in selecting the operating frequency of the converter. The first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. For example, in products incorporating RF communications, the 455kHz IF frequency is sensitive to any noise, therefore switching above 600kHz is desired. Some communications have sensitivity to 1.1MHz and in that case a 1.5MHz switching converter frequency may be employed. The second consideration is the physical size of the converter. As the operating frequency goes up, the inductor and filter capacitors go down in value and size. The tradeoff is efficiency, since the losses due to switching dynamics (see Thermal Considerations), Schottky diode charge, and other capacitive loss terms increase proportionally with frequency.

Oscillator Timing Resistor (R

)

T

where DC

CLKOUT

is the CLKOUT duty cycle in % and TJ is the die junction temperature in °C. Although the actual die temperature can deviate from the above equation by ±15°C, the relationship between change in CLKOUT duty cycle and change in die temperature is well defined. Basi- cally a 1% change in CLKOUT duty cycle corresponds to a

3.33°C change in die temperature. Note that the CLKOUT pin is only meant to drive capacitive loads up to 50pF.

The operating frequency of the LT3581 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from the R

pin to ground. An internally trimmed timing

T

capacitor resides inside the IC. The oscillator frequency is calculated using the following formula:

where f

is in MHz and RT is in k. Conversely, RT (in k)

OSC

can be calculated from the desired frequency (in MHz) using:

3581f

18

ENABLE

1.5µH

6.8µF

4.7µF

2.2µF

100pF

SW1 SW2

GATE FB

V

C

SS

GND

SYNC

CLKOUTV

IN

RT

SHDN FAULT

LT3581

SLAVE

SW1 SW2

GATE CLKOUT

V

C

SS

GND

SYNC

FBV

IN

RT

FAULT SHDN

LT3581

MASTER

143k

V

OUT

–12V 450mA

V

IN

5V

V

OUT

12V 830mA

10k

10.5k

2.2nF

0.1µF

130k

43.2k

56pF

1nF

43.2k

100k

10k

3581 F11

6.8µF

查询LT3581供应商

LT3581

applicaTions inForMaTion

Clock Synchronization

The operating frequency of the LT3581 can be set by an external source by simply providing a digital clock signal into the SYNC pin (R will revert to its internal free-running oscillator clock (set by the R

resistor) when the SYNC pin is driven below

T

0.4V for a few free-running clock periods.

Driving SYNC high for an extended period of time effec- tively stops the operating clock and prevents latch SR1 from becoming set (see Block Diagram). As a result, the switching operation of the LT3581 will stop and the CLKOUT pin will be held at ground.

The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria:

SYNC may not toggle outside the frequency range of

(1)

200kHz to 2.5MHz unless it is stopped low (below

0.4V) to enable the free-running oscillator.

(2) The SYNC frequency can always be higher than the

free-running oscillator frequency (as set by the R resistor), f below f

OSC

CLOCK SYNCHRONIZATION OF ADDITIONAL REGULATORS

The CLKOUT pin of the LT3581 can be used to synchronize one or more other compatible switching regulator ICs as shown in Figure 11.

The frequency of the master LT3581 is set by the external

resistor. The SYNC pin of the slave LT3581 is driven

R

T

by the CLKOUT pin of the master LT3581. Note that the RT pin of the slave LT3581 must have a resistor tied to ground. It takes a few clock cycles for the CLKOUT signal to begin oscillating, and it’s preferable for all LT3581s to have the same internal free-running frequency. Therefore, in general, use the same value R synchronized LT3581s.

resistor still required). The LT3581

T

, but should not be less than 25%

OSC

.

resistor for all of the

T

Figure 11. A Single Inductor Inverting Topology Is Synchronized with a Boost Regulator to Generate –12V and 12V Outputs. The External PMOS Helps Disconnect the Input from the Power Paths During Fault Events

T

Also, the FAULT pins can be tied together so that a fault condition from one LT3581 causes all of the LT3581s to enter fault, until the fault condition disappears.

HARGE

C

PUMP AIDED REGULATORS

Designing charge pumps with the LT3581 can offer efficient solutions with fewer components than traditional circuits because of the master/slave switch configuration on the IC. Although the slave switch, SW2, operates in phase with the master switch, SW1, it is only the current through the master switch (SW1) that is sensed by the current comparator (A4 in Block Diagram) as part of the current feedback loop. This method of operation by the master/slave switches can offer the following benefits to charge pump designs:

3581f

19

LT3581

V

IN

12V

V

OUT2

97V 140mA

V

OUT1

65V 70mA

24k

2.2µF

10µH

2.2µF

0.47µF

43.2k

100pF

1nF

100k

2.2µF

370k

SW1 SW2

FB

V

C

SS

GND

SYNC

GATE

CLKOUT

V

IN

RT

FAULT

SHDN

LT3581

3581 F12

8.06k

2.2µF

ENABLE

C

VC2

V

IN

C

OUT

V

OUT

< 0V

AND |V

OUT

| > |VIN|

SW1 SW2

GATE FB

V

C

SS

GND

SYNC

CLKOUTV

IN

RT

FAULT SHDN

LT3581

100k

L1

D1

D2

D3

C1

R

FB

C

VC1

C

SS

C

IN

R

VC

R

T

3579 F13

查询LT3581供应商

applicaTions inForMaTion

• The slave switch, by not performing a current sense

operation like the master switch, can sustain fairly large current spikes when the flying capacitors charge up. Since this current spike flows through SW2, it does not affect the operation of the current comparator (A4 in Block Diagram).

The

•

• Since the slave switch can sustain large current spikes,

master switch, immune from the capacitor current spike (seen only by the slave switch) can sense the inductor current more accurately.

the diodes that feed current into the flying capacitors do not need current limiting resistors, leading to efficiency and thermal improvements.

High V

Charge Pump Topology

OUT

The LT3581 can be used in a charge-pump topology as shown in Figure 12, multiplying the output of an inductive boost converter. The master switch (SW1) can be used to drive the inductive boost converter (first stage of charge pump), while the slave switch (SW2) can be used to drive one or more other charge pump stages. This topology is useful for high voltage applications including VFD bias supplies.

Single Inductor Inverting Topology

If there is a need to use just one inductor to generate a negative output voltage whose magnitude is greater than

, the single inductor inverting topology (shown in Figure

V

IN

13) can be used. Since the master and slave switches are isolated by a Schottky diode, the current spike through C1 will flow only through the slave switch, thereby preventing the current comparator, (A4 in the Block Diagram), from falsely tripping. Output disconnect is inherently built into the single inductor topology.

Figure 12. High V

Charge Pump Topology Can Be Used to

OUT

Build VFD Bias Supplies

Figure 13. Single Inductor Inverting Topology

20

3581f

V

OUT

10V/DIV

SS

1V/DIV

I

L

5A/DIV

V

IN

5V/DIV

3581 F14

1s/DIV

查询LT3581供应商

applicaTions inForMaTion

LT3581

HOT-PLUG

The high inrush current associated with hot-plugging V

IN

can be largely rejected with the use of an external PMOS. A simple hot-plug controller can be designed by connecting an external PMOS in series with V

, with the gate of the

IN

PMOS being driven by the GATE pin of the LT3581. Since the GATE pin pull-down current is linearly proportional to the SS voltage, and the SS charge up time is relatively slow, the GATE pin pull-down current will increase gradually, thereby turning on the external PMOS slowly. Controlled in this manner, the PMOS acts as an input current limiter when V

hot-plugs or ramps up sharply.

IN

Likewise, when the PMOS is connected in series with the output, inrush currents into the output capacitor can be limited during a hot-plug event. To illustrate this, the circuit in Figure 18 was re-configured by adding a large 1500µF

capacitor to the output. An 18Ω resistive load was used and a 2.2µF capacitor was placed on SS. Figure 14 shows the results of hot-plugging this re-configured circuit. Notice how the inductor current is well behaved.

Figure 14. Inrush Current Is Well Controlled in Spite Of HotPlugging the Re-configured Boost Converter in Figure 18

3581f

21

LT3581

R

V V

µA

FB

OUT FB

=

| – |

.83 3

DC

T MinOffTime

T

MAX

P

=

( )

•–%100

DC

MinOnTime

T

MIN

P

=

( )

•100%

DC

V V V

BOOST

OUT IN D

OUT D CESAT

≅

+

+––

DC

V V

V V V V

SEPIC INVERT

D OUT

IN OUT D CE

_&_

| |

≅

+

+ + −

SSAT

DC

V V V V

V

SI INVERT

OUT IN CESAT D

OUT

_

| |

=

− + + • + •33

VV

D

查询LT3581供应商

appenDix

SETTING THE OUTPUT VOLTAGE

The output voltage is set by connecting a resistor (R from V

to the FB pin. RFB is determined by using the

OUT

FB

)

following equation:

where VFB is 1.215V (typical) for non-inverting topologies (i.e. boost and SEPIC regulators) and 5mV (typical) for inverting topologies.

OWER

P

SWITCH DUTY CYCLE

In order to maintain loop stability and deliver adequate current to the load, the power NPNs (Q1 and Q2 in the Block Diagram) cannot remain “on” for 100% of each clock cycle. The maximum allowable duty cycle is given by:

where TP is the clock period and MinOffTime (found in the Electrical Characteristics) is typically 60ns.

Conversely, the power NPNs (Q1 and Q2 in the Block Dia- gram) cannot remain “off” for 100% of each clock cycle, and will turn on for a minimum on time (MinOnTime) when in regulation. This MinOnTime governs the minimum al- lowable duty cycle given by:

Where TP is the clock period and MinOnTime (found in the Electrical Characteristics) is typically 100ns.

The application should be designed such that the operating duty cycle is between DC

MIN

and DC

MAX

.

Duty cycle equations for several common topologies are given below where V

is the diode forward voltage drop and V

D

CESAT

is the collector to emitter saturation voltage of the switch.

, with SW1 and SW2 tied together, is typically 250mV

V

CESAT

when the combined switch current (I

SW1

+ I

) is 2.75A.

SW2

For the boost topology (see Figure 5):

For the SEPIC or Dual Inductor Inverting topology (see Figures 6 and 7):

For the Single Inductor Inverting topology (see Figure 13):

The LT3581 can be used in configurations where the duty cycle is higher than DC

, but it must be operated in

MAX

the discontinuous conduction mode so that the effective duty cycle is reduced.

NDUCTOR

I

SELECTION

General Guidelines: The high frequency operation of the LT3581 allows for the use of small surface mount inductors. For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. Also to improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low

2

DCR (copper-wire resistance) to reduce I

R losses, and must be able to handle the peak inductor current without saturating. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology where each inductor only carries one half of the total switch current. Molded chokes or chip inductors usually do not have enough core area to support peak inductor currents in the 2A to 6A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 5 for a list of inductor manufacturers.

Table 5. Inductor Manufacturers

Sumida CDR6D28MN and CDR7D28MN

Coilcraft MSD7342 Series www.coilcraft.com

Vishay IHLP-1616BZ-01, IHLP-2020BZ-01

Taiyo Yuden NR Series www.t-yuden.com

Wurth WE-PD Series www.we-online.com

TDK VLF, SLF and RLF Series www.tdk.com

Series

and IHLP-2525CZ-01 Series

www.sumida.com

www.vishay.com

22

3581f

L

DC V V

f I

V I

BOOST

IN CESAT

OSC PK

OUT OU

>

• −

( )

• • −

•

2

| |

TT

IN

DUAL

IN CESAT

OSC

V

or

L

DC V V

f

•

 



 



>

• −

( )

• •

η

2 II

V I

V

I

PK

OUT OUT

IN

OUT

−

•

−

 



 



| |

η

Boost Topology

SEPIC or Inverting Topologies

L

V V DC

A f DC

MIN

IN CESAT

OSC

=

−

( )

• • −

( )

• • −

( )

2 1

2 2 1.

L

V V

mA

DC

f

MAX

IN CESAT

OSC

=

−

•

350

查询LT3581供应商

appenDix

LT3581

Minimum Inductance

Although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are three conditions that limit the minimum inductance: (1) provid- ing adequate load current, (2) avoidance of subharmonic oscillations and (3) supplying a minimum ripple current to avoid false tripping of the current comparator.

Adequate Load Current

Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. In order to provide adequate load current, L should be at least:

Negative values of L put load current, I

OUT

BOOST

or L

indicate that the out-

DUAL

, exceeds the switch current limit

capability of the LT3581.

Avoiding Sub-Harmonic Oscillations

The LT3581’s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a certain minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least:

where:

L L

= L1 for Boost Topologies (see Figure 5)

MIN

= L1 = L2 for Coupled Dual Inductor

MIN

Topologies (see Figures 6 and 7) L

= L1 || L2 for Uncoupled Dual Inductor

MIN

Topologies (see Figures 6 and 7)

where:

L L

= L1 for Boost Topologies (see Figure 5)

BOOST

= L1 = L2 for Coupled Dual Inductor

DUAL

Topologies (see Figures 6 and 7) L

= L1 || L2 for Uncoupled Dual Inductor

DUAL

Topologies (see Figures 6 and 7) DC = Cycle section in Appendix)

Switch Duty Cycle (see Power Switch Duty

IPK = Maximum Peak Switch Current; should not exceed 3.3A for a combined SW1 + SW2

η =

current, or 1.9A of SW1 current if SW1 is being used by itself.

P

ower Conversion Efficiency (typically 88%

for Boost and 75% for Dual Inductor

f

OSC

I

OUT

Topologies at High Currents) = Switching Frequency = Maximum Output Current

Maximum Inductance

Excessive inductance can reduce ripple current to levels that are difficult for the current comparator (A4 in the Block Diagram) to cleanly discriminate, causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by:

where:

L L

= L1 for Boost Topologies (see Figure 5)

MAX

= L1 = L2 for Coupled Dual Inductor

MAX

Topologies (see Figures 6 and 7) L

= L1 || L2 for Uncoupled Dual Inductor

MAX

Topologies (see Figures 6 and 7)

3581f

23

LT3581

I I

V T

L

L PEAK LIM

IN MIN PROP

_

= +

•

查询LT3581供应商

appenDix

Inductor Current Rating

Inductors must have a rating greater than their peak operating current, or else they could saturate and hence contribute to losses in efficiency. The maximum inductor current (considering start-up and steady-state conditions) is given by:

where:

I

= Peak Inductor Current in L1 for a Boost

L_PEAK

Topology, or the Peak of the sum of the

** = 3.3A with SW1 and SW2 Tied Together,

I

LIM

Inductor Currents in L1 and L2 for Dual Inductor Topologies.

or 1.9A with just SW1 (This assumes

T

MIN_PROP

usage of an inductor whose core material soft-saturates such as powdered iron core).

= 100ns (Propagation Delay through the

Current Feedback Loop).

**If using an inductor whose core material saturates

hard (e.g., ferrite), then pick I

to be 5.4A with SW1

LIM

and SW2 tied together, or 3A when just SW1 is used.

Note that these equations offer conservative results for the required inductor current ratings. The current ratings could be lower for applications with light loads, if the SS capacitor is sized appropriately to limit inductor currents at start-up.

Multilayer ceramic capacitors are an excellent choice, as they have extremely low ESR and are available in very small packages. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. A 10μF to 22μF output capacitor is sufficient for most applications, but systems with very low output currents may need only 2.2μF to 10μF. Always use a capacitor with a sufficient voltage rating. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. Tantalum Polymer or OS-CON capacitors can be used, but it is likely that these capacitors will occupy more board area than a ceramic, and will have higher ESR with greater output ripple.

CAPACITOR SELECTION

NPUT

I

Ceramic capacitors make a good choice for the input decoupling capacitor, and should be placed such that it is in close proximity to the V

of the chip as well as to the

IN

inductor connected to the input of the power path. If it is not possible to optimally place a single input capacitor, then use two separate capacitors—use one at the V the chip (see equation for C

in Tables 1, 2 and 3) and

VIN

one at the input to the power path (see equation for C

of

IN

PWR

in Tables 1, 2 and 3) A 4.7μF to 20μF input capacitor is sufficient for most applications.

able

6 shows a list of several ceramic capacitor man-

T ufacturers. Consult the manufacturers for detailed information on their entire selection of ceramic parts.

IODE SELECTION

D

Schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the LT3581. Choose a Schottky diode with low parasitic capaci- tance to reduce reverse current spikes through the power switch of the LT3581. The Central Semiconductor Corp. CMMSH2-40 diode is a very good choice with a 40V reverse voltage rating and an average forward current of 2A.

UTPUT

O

Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage.

24

CAPACITOR SELECTION

Table 6: Ceramic Capacitor Manufacturers

AVX www.avxcorp.com

Murata www.murata.com

Taiyo Yuden www.t-yuden.com

PMOS SELECTION

An external PMOS, controlled by the LT3581’s GATE pin, can be used to facilitate input or output disconnect. The GATE pin turns on the PMOS gradually during start-up (see Soft-Start of External PMOS in the Operation section), and turns the PMOS off when the LT3581 is in shutdown or in fault.

3581f

V

R

R k

if V V

µA R i

SG

IN

GATE

=

+

<

•

2

933

Ω

ff V V

GATE

≥

 







2

查询LT3581供应商

appenDix

LT3581

The use of the external PMOS, controlled by the GATE pin, is particularly beneficial when dealing with unintended output shorts in a boost regulator. In a conventional boost regulator, the inductor, Schottky diode, and power switches are susceptible to damage in the event of an output short to ground. Using an external PMOS in the boost regulator’s power path (path from V

IN

to V

) controlled by the GATE

OUT

pin, will serve to disconnect the input from the output when the output has a short to ground, thereby helping save the IC, and the other components in the power path from damage. Ensure that both, the diode and the inductor can survive low duty cycle current pulses of 3 to 4 times their steady state levels.

The PMOS chosen must be capable of handling the maxi- mum input or output current depending on whether the PMOS is used at the input (see Figure 11) or the output (see Figure 18).

Ensure that the PMOS is biased with enough source to gate voltage (V mode of operation. The higher the V the PMOS into triode, the lower the R

) to enhance the device into the triode

SG

voltage that biases

SG

of the PMOS,

DSON

thereby lowering power dissipation in the device during normal operation, as well as improving the efficiency of the application in which the PMOS is used. The follow- ing equations show the relationship between R Block Diagram) and the desired V

that the PMOS is

SG

GATE

(see

biased with:

event of hard shorts. The resistor divider from V

to the

IN

SHDN pin sets a UVLO of 4V for this application.

Connecting the PMOS in series with the output offers certain advantages over connecting it in series with the input:

Since the load current is always less than the input

• current for a boost converter, the current rating of the PMOS goes down.

• A PMOS in series with the output can be biased with a higher overdrive voltage than a PMOS used in series with the input, since V results in a lower R

> VIN. This higher overdrive

OUT

rating for the PMOS, thereby

DSON

improving the efficiency of the regulator.

In contrast, an input connected PMOS works as a simple hot-plug controller (covered in more detail in the Hot-Plug section). The input connected PMOS also functions as an inexpensive means of protecting against multiple output shorts in boost applications that synchronize the LT3581 with other compatible ICs (see Figure 11).

7 shows a list of several discrete PMOS manufa-

able

T cturers. Consult the manufacturers for detailed information on their entire selection of PMOS devices.

Table 7. Discrete PMOS Manufacturers

Vishay www.vishay.com

Fairchild Semiconductor www.fairchildsemi.com

COMPENSATION – ADJUSTMENT

To compensate the feedback loop of the LT3581, a series resistor-capacitor network in parallel with an optional

When using a PMOS, it is advisable to configure the specific application for undervoltage lockout (see the Operations section). The goal is to have V

get to a certain minimum

IN

voltage where the PMOS has sufficient headroom to attain a high enough V

, which prevents it from entering the

SG

saturation mode of operation during start-up.

single capacitor should be connected from the V GND. For most applications, choose a series capacitor in the range of 1nF to 10nF with 2.2nF being a good starting value. The optional parallel capacitor should range in value from 47pF to 160pF with 100pF being a good starting value. The compensation resistor, R

, is usually in the

C

range of 5k to 50k with 10k being a good starting value.

pin to

C

A good technique to compensate a new application is to

Figure 18 shows the PMOS connected in series with the output to act as an output disconnect during a fault con- dition. The Schottky diode from the V

pin to the GATE

IN

pin is optional and helps turn off the PMOS quicker in the

use a 100k potentiometer in place of the series resistor R With the series and parallel capacitors at 2.2nF and 100pF respectively, adjust the potentiometer while observing the transient response and the optimum value for R

C

25

C

can be

3581f

.

LT3581

V

OUT

AC-COUPLED

500mV/DIV

I

L

1A/DIV

3581 F15a

50µs/DIV

V

OUT

AC-COUPLED

500mV/DIV

I

L

1A/DIV

3581 F15b

50µs/DIV

V

OUT

AC-COUPLED

500mV/DIV

I

L

1A/DIV

3581 F15c

50µs/DIV

1.215V

REFERENCE

I

VIN

H•V

IN

V

OUT

•

I

VIN

V

OUT

C

OUT

C

PL

R

ESRRL

R

O

V

C

R

C

F

R1

FB

R2

–

+

–

+

3581 F16

g

mp

g

ma

CC: COMPENSATION CAPACITOR C

OUT

: OUTPUT CAPACITOR

C

PL

: PHASE LEAD CAPACITOR

C

F

: HIGH FREQUENCY FILTER CAPACITOR

g

ma

: TRANSCONDUCTOR AMPLIFIER INSIDE IC

g

mp

: POWER STAGE TRANSCONDUCTANCE AMPLIFIER

R

C

: COMPENSATION RESISTOR

R

L

: OUTPUT RESISTANCE DEFINED AS V

OUT/ILOAD(MAX)

RO: OUTPUT RESISTANCE OF g

ma

R1, R2; FEEDBACK RESISTOR DIVIDER NETWORK R

ESR

: OUTPUT CAPACITOR ESR

查询LT3581供应商

appenDix

found. Figures 15a to 15c illustrate this process for the circuit of Figure 18 with a load current stepped between 540mA and 800mA. Figure 15a shows the transient re- sponse with R

equal to 1k. The phase margin is poor as

C

evidenced by the excessive ringing in the output voltage and inductor current. In Figure 15b, the value of R

C

is increased to 3k, which results in a more damped response. Figure 15c shows the results when R

is increased further

C

to 10.5k. The transient response is nicely damped and the compensation procedure is complete.

Figure 15a. Transient Response Shows Excessive Ringing

COMPENSATION – THEORY

Like all other current mode switching regulators, the LT3581 needs to be compensated for stable and efficient operation. Two feedback loops are used in the LT3581: a fast current loop which does not require compensation, and a slower voltage loop which does. Standard Bode plot analysis can be used to understand and adjust the voltage feedback loop.

As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 16 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier g current source (which converts I

acts as a current source where the peak input current,

g

mp

, is proportional to the VC voltage. η is the efficiency of

I

VIN

and the current controlled

mp

to ηVIN/V

VIN

OUT

• I

VIN

).

the switching regulator and is typically about 80%.

Note that the maximum output currents of the g

stages are finite. The output of the gmp stage is

g

ma

mp

and

limited by the minimum switch current limit (see Electrical Specifications) and the output of the g

stage is nominally

ma

limited to about ±12μA.

26

Figure 15b. Transient Response is Better

Figure 15c. Transient Response is Well Damped

Figure 16. Boost Converter Equivalent Model

3581f

DC Gain

A A

DC OL

:

( )

(Breaking loop at FB pin)

= =0

∂∂

∂

•

∂

•

∂

•

∂

=

•

V

I

V

I

V

g

C

FB

VIN

C

OUT

VIN

FB

OUT

ma

RR g

V

R R

O mp

IN

OUT

L

( )

• • • •

 



 



• +

η

2

0 5

2

1 2

.

OOutput Pole P

R C

Error AmpPole P

L OUT

::1

2

=

• • •

=

π

11

2

1

2

• • +









•

=

• • •

ππR R C

Error Amp Zero Z

R C

O C C

C

:

CC

ESR OUT

IN

ESR Zero Z

R C

RHP Zero Z

V

::2

1

2

3

2

=

• • •

=

•

π

RR

V L

HighFrequency Pole P

f

Phase

L

OUT

S

2

3

2

• • •

>

π

:

LLead Zero Z

R C

Phase Lead Pole P

PL

::4

1

2 1

4

1

2

=

• • •

=

π

•• •

•

+

•

=

π

R

C

Error AmpFilter Pole

P

PL

1

2

1

2

5

1

:

2210• •

•

+

•

<

π

R R

C

C O

F

C

,

FREQUENCY (Hz)

10

50

GAIN (dB)

PHASE (DEG)

70

90

110

130

100 1k 10k 100k 1M

3851 F17

30

10

–10

–30

150

170

–120

–80

–40

–240

–280

–160

–180

–360

–320

–200

0

PHASE

GAIN

查询LT3581供应商

appenDix

LT3581

From Figure 16, the DC gain, poles and zeros can be calculated as follows:

The current mode zero (Z3) is a right half plane zero which can be an issue in feedback control design, but is manage- able with proper external component selection.

Using the circuit in Figure 18 as an example, Table 8 shows the parameters used to generate the Bode plot shown in Figure 17.

Table 8. Bode Plot Parameters

PARAMETER VALUE UNITS COMMENT

R

L

C

OUT

R

ESR

R

O

C

F

C

PL

R

C

R1 130 kΩ Adjustable

R2 14.6 kΩ Not Adjustable

V

REF

V

OUT

V

IN

g

ma

g

mp

L 1.5 µH Application Specific

f

OSC

14.5 Ω Application Specific

9.4 µF Application Specific

1 mΩ Application Specific

305 kΩ Not Adjustable

1000 pF Adjustable

56 pF Optional/Adjustable

0 pF Optional/Adjustable

10.5 kΩ Adjustable

1.215 V Not Adjustable

12 V Application Specific

5 V Application Specific

270 µmho Not Adjustable

15.1 mho Not Adjustable

2 MHz Adjustable

From Figure 17, the phase is –130° when the gain reaches 0dB giving a phase margin of 50°. The crossover frequency is 17kHz, which is more than three times lower than the frequency of the RHP zero Z3 to achieve adequate phase margin.

Figure 17. Bode Plot for Example Boost Converter

3581f

27

LT3581

V

IN

5V

V

IN

6.04k

100k

130k

D2

D1

M1

43.2k

C1

4.7µF

L1

1.5µH

1nF

3581 F18

0.1µF

10.5k

C2

4.7µF

V

OUT

12V 830mA

C3

4.7µF

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

C1: 4.7µF, 16V, X7R, 1206 C2, C3: 4.7µF, 25V, X7R, 1206 D1: DIODES INC. PD3S230H-7

D2: VISHAY MSS2P3 L1: SUMIDA CDR6D28MN-IR5 M1: VISHAY SILICONIX SI7123DN

FAULT

SHDN

LT3581

56pF

18.7k

10k

V

OUT

AC-COUPLED

1V/DIV

LOAD

0.5A/DIV

I

L

1A/DIV

3581 TA02a

50µs/DIV

V

OUT

AC-COUPLED

200mV/DIV

V

CLKOUT

(BW LIMIT)

2V/DIV

V

SW

0.5A/DIV

I

L

1A/DIV

3581 TA02b

500ns/DIV

D1

V

IN

2.8V TO 4.2V

100k

45.3k

43.2k

C1

3.3µF

L1

0.68µH

1.5nF

3581 TA03a

0.1µF

6.98k

V

OUT

5V

1.1A

C2

22µF

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

68pF

C1: 3.3µF, 16V, X7R, 1206 C2: 22µF, 16V, X7R, 1210 D1: DIODES INC. PD3S230H-7 L1: VISHAY IHLP1616 BZ-01-OR68 (ONLY 4.1mm s 4.5mm s 2mm)

LOAD CURRENT (mA)

0

50

EFFICIENCY (%)

POWER LOSS (mW)

55

65

70

75

400

90

3581 TA03b

60

200 12001000800600

80

85

0

200

600

2000

1200

1400

1600

1800

400

800

1000

查询LT3581供应商

Typical applicaTions

Figure 18. 2MHz, 5V to 12V, 830mA Boost Converter with Output Short Circuit Protection

Transient Response with 430mA to 830mA to 430mA Load Step

28

2MHz, 5V, 1.1A Boost Converter Operates from an Input Range of 2.8V to 4.2V

Switching Waveforms with 830mA Load

Efficiency and Power Loss at VIN = 3.3V

3581f

V

IN

9V TO 16V

V

IN

V

OUT2

97V 90mA (V

IN

= 9V)

140mA (V

IN

= 12V)

180mA (V

IN

= 16V)

V

OUT1

65V 60mA (V

IN

= 9V)

70mA (V

IN

= 12V)

90mA (V

IN

= 16V)

24k

C2

2.2µF

L1

10µH

C5

2.2µF

C4

2.2µF

0.47µF

43.2k

100pF

1nF

100k

C1

2.2µF

365k

D3

D2

D1

D7

D9* 10V

D4

D5

D6

10k

32.6k

SW1 SW2

FB

V

C

SS

GND

SYNC

GATE

CLKOUT

V

IN

RT

FAULT

SHDN

LT3581

3581 TA04a

8.06k

C6

2.2µF

C7

2.2µF

C3

2.2µF

D8*

M1*

C1: 2.2µF, 25V, X7R, 1206 C2 TO C7: 2.2µF, 50V, X7R, 1206 D1 TO D7: CENTRAL SEMI SOD123F

D8: CENTRAL SEMI CMDSH-3TR D9: CENTRAL SEMI CMHZ5240B-LTZ L1: TAIYO YUDEN NR6045T100M M1: VISHAY SILICONIX SI7611DN

*OPTIONAL, FOR OUTPUT SHORT-CIRCUIT PROTECTION

DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

V

OUT

AC-COUPLED

2V/DIV

I

LOAD

0.1A/DIV

I

L

0.5A/DIV

3581 TA04b

100µs/DIV

V

OUT2

50V/DIV

V

OUT1

50V/DIV

V

SS

1V/DIV

I

L

0.5A/DIV

3581 TA04c

100ms/DIV

TOTAL OUTPUT POWER (W)

0

70

EFFICIENCY (%)

POWER LOSS (mW)

75

8

90

3581 TA04d

4 201612

80

85

1.0

3.0

1.5

2.0

2.5

查询LT3581供应商

Typical applicaTions

High Efficiency, VFD (Vacuum Fluorescent Display) Power Supply Switches at 2MHz to Avoid AM Band

LT3581

Transient Response with 60mA to 140mA to 60mA

Load Step on V

(VIN = 12V)

OUT2

Efficiency and Power Loss at VIN = 12V

Start-Up Waveforms

3581f

29

LT3581

V

IN

9V TO 16V

100k

130k

43.2k

C1

3.3µF

2.2nF

3581 TA06a

0.1µF

C3 10µF

10k

V

OUT

12V 1A (V

IN

= 9V)

1.1A (V

IN

= 12V)

1.3A (V

IN

= 16V)

C2

2.2µF

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

100pF

C1: 3.3µF, 25V, X7R, 1206 C2: 2.2µF, 50V, X7R, 1206 C3: 10µF, 25V, X7R, 1210 D1: CENTRAL SEMI CTLSH2-40M832 L1, L2: COILCRAFT MSD7342-332MLB

L2

3.3µH

L1

3.3µH

•

D1

LOAD CURRENT (mA)

0

50

EFFICIENCY (%)

55

65

70

75

1200

100

95

3581 TA06b

60

300 1500900600

80

85

90

VIN = 16V

VIN = 9V

VIN = 12V

VIN (V)

8

11.990

V

OUT

(V)

11.998

11.996

11.994

11.992

12.000

9 12 141310 1511 16 17

3581 TA06c

LINE REGULATION ~0.0044%/V

I

LOAD

(mA)

0

11.96

V

OUT

(V)

12.00

11.99

11.98

11.97

12.01

400 800600 1000200 1200 1400

3581 TA06d

LOAD REGULATION ~0.25%/A

查询LT3581供应商

Typical applicaTions

2MHz, 12V SEPIC Converter Can Accept Input Voltages from 9V to 16V

30

Efficiency Line Regulation with No Load

Load Regulation at V

IN

= 12

3581f

V

BAT

3V TO 36V

(V

BAT

AT START-UP = 6V TO 16V)

100k

10k

24.9k

174k

C1 10µF

2.2nF

3581 TA07a

1µF

C5 47µF s2

10k

V

OUT

3.3V

0.9A (3V < V

BAT

< 9V)

1.5A (V

BAT

= 9V)

C2

10nF

Q1

C3

4.7µF

C4

2.2µF

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

47pF

C1: 10µF, 50V, X7R, 1210 C2: 10nF, 25V, X7R, 0603 C3: 4.7µF, 25V, X7R, 1206 C4: 2.2µF, 50V, X7R, 1206 C5: 47µF, 10V, X7R, 1210 D1: CENTRAL SEMI CMHZ5248B-LTZ

D2: CENTRAL SEMI CMMSH2-40 D3: DIODES INC. PD3S230H-7 L1, L2: COILCRAFT MSD7342-332MLB M1: 2N7002 Q1: MMBT3904

L2

3.3µH

L1

3.3µH

•

D2

M1

D3

D1

18V

470pF

10k

200k

V

BAT

10V/DIV

V

OUT

2V/DIV

I

L

2A/DIV

3581 TA07c

1s/DIV

V

BAT

= 17V

V

BAT

= 31V

V

OUT

= 3.3V

LOAD CURRENT (mA)

0

50

EFFICIENCY (%)

55

65

70

75

400

80

3581 TA07b

60

1600800 1200

V

BAT

= 3V

V

BAT

= 9V

V

BAT

= 12V

查询LT3581供应商

Typical applicaTions

Wide Input Range, 3.3V SEPIC Converter Can Operate from 3V to 36V

LT3581

Efficiency

Wide Input Range SEPIC Can Ride Through V

Voltages that Are Higher than V

IN_OVP

BAT

31

3581f

LT3581

V

IN

5V

100k

130k

86.6k

C1

3.3µF

2.2nF

3581 TA08a

0.1µF

C4 10µF

C5 10µF

16.9k

V

OUT

+

12V

0.27A

V

OUT

–

–12V

0.27A

C2

1µF

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

100pF

C1: 3.3µF, 25V, X7R, 1206 C2, C3: 1µF, 25V, X7R, 1206 C4, C5: 10µF, 50V, X7R, 1210 D1 TO D5: DIODES INC. PD3S230H-7 L1: VISHAY IHLP-2525CZ-01-8R2 R1: 2.4k, 2W

*IF DRIVING ASYMMMETRICAL LOADS, PLACE A 2.4k, 2W RESISTOR FROM THE 12V OUTPUT TO THE –12V OUTPUT FOR IMPROVED LOAD REGULATION OF THE –12V OUTPUT

D2

D1

L1

8.2µH

D3

C3

1µF

D4

D5

R1

*2.4k

V

IN

3V TO 16V

100k

60.4k

124k

C1

22µF

2.2nF

3581 TA09a

0.1µF

C3 22µF

6.19k

V

OUT

–5V

0.9A (V

IN

= 3.3V)

1.5A (V

IN

= 12V)

1.6A (V

IN

= 16V)

C2

1µF

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

56pF

C1: 22µF, 25V, X7R, 1210 C2: 1µF, 50V, X7R, 1206 C3: 22µF, 16V, X7R, 1210 D1: VISHAY SSB44 L1, L2: COILCRAFT MSD7342-332MLB

L2

3.3µH

D1

L1

3.3µH

•

LOAD CURRENT (mA)

0

50

EFFICIENCY (%)

POWER LOSS (mW)

55

65

70

75

15050

90

3581 TA08b

60

100 300250200

80

85

0

200

600

1800

1200

1400

1600

400

800

1000

LOAD CURRENT (mA)

0

50

EFFICIENCY (%)

55

65

70

75

300

90

3581 TA09b

60

1800900 1500600 1200

80

85

VIN = 3.3V

VIN = 12V

VIN = 16V

查询LT3581供应商

Typical applicaTions

1MHz, ±12V Charge Pump Topology Uses Only Single Inductor

Efficiency and Power Loss with

Symmetric Load

700kHz, –5V Inverting Converter Can Accept Input Voltages from 3V to 16V

32

Efficiency

3581f

V

IN

3V TO 16V

100k

45.3k

124k

C1

22µF

2.2nF

3581 TA10a

1µF

C3 22µF s2

7.87k

V

OUT

5V

0.9A (V

IN

= 3V)

1.5A (12V ≤ V

IN

≤ 16V)

C2

1µF

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

100pF

C1: 22µF, 25V, X7R, 1210 C2: 1µF, 50V, X7R, 1206 C3: 22µF, 16V, X7R, 1210 D1: DIODES INC. B230LA L1, L2: COILCRAFT MSD7342-332MLB

L2

3.3µH

L1

3.3µH

•

D1

LOAD CURRENT (mA)

0

50

EFFICIENCY (%)

55

65

70

75

400

90

3581 TA10b

60

1600800 1200

80

85

VIN = 3.3V

VIN = 12V

VIN = 16V

查询LT3581供应商

Typical applicaTions

700kHz, 5V SEPIC Can Accept Input Voltages from 3V to 16V

LT3581

Efficiency

3581f

33

LT3581

MSOP (MSE16) 0608 REV A

0.53 p 0.152

(.021 p .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

16

16151413121110

1 2 3 4 5 6 7 8

9

1

8

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010)

0o – 6o TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 p 0.127 (.035 p .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 p 0.038

(.0120 p .0015)

TYP

0.50

(.0197)

BSC

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 p 0.102 (.112 p .004)

4.039 p 0.102 (.159 p .004)

(NOTE 3)

1.651 p 0.102 (.065 p .004)

0.1016 p 0.0508 (.004 p .002)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

0.280 p 0.076 (.011 p .003)

REF

4.90 p 0.152

(.193 p .006)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.12 REF

0.35 REF

查询LT3581供应商

package DescripTion

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev A)

34

3581f

3.00 p0.10 (2 SIDES)

4.00 p0.10 (2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 p 0.10

BOTTOM VIEW—EXPOSED PAD

1.70 p 0.10

0.75 p0.05

R = 0.115

TYP

R = 0.05

TYP

3.00 REF

1.70 p 0.05

17

148

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DE14) DFN 0806 REV B

PIN 1 NOTCH R = 0.20 OR

0.35 s 45o CHAMFER

3.00 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

2.20 p0.05

0.70 p0.05

3.60 p0.05

PACKAGE OUTLINE

0.25 p 0.05

0.50 BSC

3.30 p0.05

3.30 p0.10

0.50 BSC

查询LT3581供应商

package DescripTion

LT3581

DE Package

14-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1708 Rev B)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3581f

35

LT3581

V

IN

5V

100k

143k

43.2k

C1

3.3µF

1nF

3581 TA05a

0.1µF

C3

4.7µF

11k

V

OUT

–12V 625mA

C2

1µF

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

47pF

C1: 3.3µF, 16V, X7R, 1206 C2: 1µF, 25V, X7R, 1206 C3: 4.7µF, 25V, X7R, 1206 D1: DIODES INC. PD3S230H-7 L1, L2: COILCRAFT MSD7342-332MLB

L2

3.3µH

D1

L1

3.3µH

•

50

55

65

70

75

90

60

80

85

LOAD CURRENT (mA)

0

EFFICIENCY (%)

POWER LOSS (mW)

250

3581 TA05b

125 625500375

0

200

600

2000

1200

1400

1600

1800

400

800

1000

查询LT3581供应商

Typical applicaTion

5V to –12V Inverting Converter Switches at 2MHz

Efficiency and Power Loss

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LT3580 2A (I

LT3471 Dual Output 1.3A (I

LT3479 40V, 3A, Full Featured DC/DC Converter with Soft-Start and Inrush

LT3477 40V, 3A, Full Featured DC/DC Converter V

LT1946/LT1946A 1.5A (I

LT1935 2A (I

LT1310 2A (I

LT3436 3A (I

36

), 2.5MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.5V to 32V, V

SW

), 1.2MHz, High Efficiency Step-Up DC/DC

SW

Converter

Current Protection

), 1.2MHz/2.7MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.6V to 16V, V

SW

), 40V, 1.2MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.3V to 16V, V

SW

), 40V, 1.2MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.3V to 16V, V

SW

), 800kHz, 34V Step-Up DC/DC Converter VIN = 3V to 25V, V

SW

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

OUT(MAX)

= 42V, IQ = 1mA, I

SD

< 1µA,

3mm × 3mm DFN-8, MSOP-8E Packages

VIN = 2.4V to 16V, V

= ±40V, IQ = 2.5mA, I

OUT(MAX)

SD

< 1µA,

3mm × 3mm DFN-10 Package

V

= 2.5V to 24V, V

IN

I

< 1µA, DFN, TSSOP Packages

SD

= 2.5V to 25V, V

IN

I

< 1µA, QFN, TSSOP-20E Packages

SD

= 40V, IQ = Analog/PWM,

OUT(MAX)

= 40V, IQ = Analog/PWM,

OUT(MAX)

= 34V, IQ = 3.2mA, I

OUT(MAX)

SD

< 1µA,

MS8E Package

OUT(MAX)

= 40V, IQ = 3mA, I

SD

< 1µA,

ThinSOT Package

OUT(MAX)

= 40V, IQ = 3mA, I

SD

< 1µA,

ThinSOT Package

= 34V, IQ = 0.9mA, I

OUT(MAX)

SD

< 6µA,

TSSOP-16E Package

3581f

LT 0310 • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2010

LINEAR TECHNOLOGY LT3581 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual