LINEAR TECHNOLOGY LT3581 Technical data

V

IN

5V

V

IN

6.04k

100k

130k

43.2k

4.7µF

1.5µH

1nF

3581 TA01

0.1µF

4.7µF

10.5k

4.7µF

V

OUT

12V
830mA

SW1 SW2

FB

CLKOUT

GATE

V

C

SS

V

IN

RT

GND

SYNC

FAULT

SHDN

LT3581

56pF

18.7k

10k

LOAD CURRENT (mA)

0

50

EFFICIENCY (%)

POWER LOSS (mW)

55

65

70

75

400

100

95

3581 TA01b

60

200 1000800600

80

85

90

0

200

600

2000

1200

1400

1600

1800

400

800

1000

查询LT3581供应商

LT3581

3.3A Boost/Inverting DC/DC

Converter with Fault Protection

FeaTures

n

3.3A, 42V Combined Power Switch

n

Master/Slave (1.9A/1.4A) Switch Design

n

Output Short Circuit Protection

n

Wide Input Range: 2.5V to 22V Operating,

40V Maximum Transient

n

Switching Frequency Up to 2.5MHz

n

Easily Configurable as a Boost, SEPIC, Inverting or

Flyback Converter

n

User Configurable Undervoltage Lockout

n

Low V

n

Can be Synchronized to External Clock

n

Can Be Synchronized to other Switching Regulators

n

High Gain SHDN Pin Accepts Slowly Varying Input

Switch: 250mV at 2.75A (Typical)

CESAT

Signals

n

14-Pin 4mm × 3mm DFN and 16-Lead MSE Packages

applicaTions

n

Local Power Supply

n

Vacuum Fluorescent Display (VFD) Bias Supplies

n

TFT-LCD Bias Supplies

n

Automotive Engine Control Unit (ECU) Power

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 7579816.

DescripTion

The LT®3581 is a PWM DC/DC converter with built-in fault
protection features to aid in protecting against output
shorts, input/output overvoltages, and overtemperature
conditions. The part consists of a 42V master switch, and
a 42V slave switch that can be tied together for a total
current limit of 3.3A.

The LT3581 is ideal for many local power supply designs. It
can be easily configured in Boost, SEPIC, Inverting or Flyback
configurations, and is capable of generating 12V at 830mA,
or –12V at 625mA from a 5V input. In addition, the LT3581’s
slave switch allows the part to be configured in high voltage,
high power charge pump topologies that are very efficient
and require fewer components than traditional circuits.

he LT3581’s switching frequency range can be set between

T
200kHz and 2.5MHz. The part may be clocked internally at
a frequency set by the resistor from the RT pin to ground,
or it may be synchronized to an external clock. A buffered
version of the clock signal is driven out of the CLKOUT
pin, and may be used to synchronize other compatible
switching regulator ICs to the LT3581.

The LT3581 also features innovative SHDN pin circuitry
that allows for slowly varying input signals and an adjust­able undervoltage lockout function. Additional features
such as frequency foldback and soft-start are integrated.
The LT3581 is available in 14-Pin 4mm × 3mm DFN and
16-Lead MSE packages.

Typical applicaTion

Output Short Protected, 5V to 12V Boost Converter Operating at 2MHz

Efficiency and Power Loss vs

Load Current

3581f

1

LT3581

1

2

3

4

5

6

7

14

13

12

11

10

9

8

SYNC

SS

RT

SHDN

CLKOUT

SW2

SW2

FB

V

C

GATE

FAULT

V

IN

SW1

SW1

TOP VIEW

DE14 PACKAGE

14-PIN (4mm s 3mm) PLASTIC DFN

15

GND

1
2
3
4
5
6
7
8

FB
V

C

GATE

FAULT

V

IN

SW1
SW1
SW1

16
15
14
13
12
11
10
9

SYNC
SS
RT

SHDN

CLKOUT
SW2
SW2
SW2

TOP VIEW

MSE PACKAGE

16-LEAD PLASTIC MSOP

17

GND

查询LT3581供应商

absoluTe MaxiMuM raTings

(Note 1)

VIN Voltage .................................................–0.3V to 40V

SW1/SW2 Voltage ..................................... –0.4V to 42V

RT Voltage ...................................................–0.3V to 5V

SS, FB Voltage .......................................... –0.3V to 2.5V

Voltage .................................................... –0.3V to 2V

V

C

SHDN Voltage ............................................ –0.3V to 40V

SYNC Voltage ............................................ –0.3V to 5.5V

GATE Voltage ............................................. –0.3V to 80V

pin conFiguraTion

= 125°C, θJA = 43°C/W, θJC = 4.3°C/W

T

JMAX

EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB

FAULT Voltage ............................................ –0.3V to 40V

FAULT Current .....................................................±500µA

CLKOUT Voltage .......................................... –0.3V to 3V

CLKOUT Current ......................................................1mA

Operating Junction Temperature Range

LT3581E (Notes 2, 4) ......................... –40°C to 125°C

LT3581I (Notes 2, 4) ..........................– 40°C to 125°C

Storage Temperature Range .................. – 65°C to 150°C

T

= 125°C, θJA = 45°C/W, θJC = 10°C/W

JMAX

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3581EDE#PBF LT3581EDE#TRPBF 3581

LT3581IDE#PBF LT3581IDE#TRPBF 3581

LT3581EMSE#PBF LT3581EMSE#TRPBF 3581 16-Lead Plastic MSOP –40°C to 125°C

LT3581IMSE#PBF LT3581IMSE#TRPBF 3581 16-Lead Plastic MSOP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

2

14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN

–40°C to 125°C

–40°C to 125°C

3581f

查询LT3581供应商

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Minimum Input Voltage

Overvoltage Lockout 22.1 23.5 25 V

V

IN

Positive Feedback Voltage

Negative Feedback Voltage

Positive FB Pin Bias Current V

Negative FB Pin Bias Current V

Error Amp Transconductance ΔI = 10μA 270 µmhos

Error Amp Voltage Gain 70 V/V

Quiescent Current Not Switching 1.9 2.3 mA

Quiescent Current in Shutdown V

Reference Line Regulation 2.5V ≤ V

Switching Frequency, f

Switching Frequency in Foldback Compared to Normal f

Switching Frequency Range Free-Running or Synchronizing

SYNC High Level for Synchronization

SYNC Low Level for Synchronization

SYNC Clock Pulse Duty Cycle V

Recommended Minimum SYNC Ratio
f

SYNC/fOSC

Minimum Off-Time 45 ns

Minimum On-Time 55 ns

SW1 Current Limit At All Duty Cycles

Current Sharing (SW2/SW1) 78 %

SW1 + SW2 Current Limit At All Duty Cycles, SW2/SW1 = 78% (Note 3)

Switch V

CESAT

SW1 Leakage Current V

SW2 Leakage Current V

OSC

= Positive Feedback Voltage, Current into Pin

FB

= Negative Feedback Voltage, Current out of Pin

FB

= 0V 0 1 µA

SHDN

≤ 20V 0.01 0.05 %/V

IN

RT = 34k

= 432k

R

T

OSC

= 0V to 2V 20 80 %

SYNC

SW1 & SW2 Tied Together, I

= 5V 0.01 1 µA

SW1

= 5V 0.01 1 µA

SW2

SW1

+ I

= VIN, V

SHDN

= 2.75A 250 mV

SW2

= VIN, unless otherwise noted. (Note 2).

FAULT

l

l

1.195 1.215 1.230 V

l

3 9 16 mV

l

81 83.3 85 µA

l

81 83.3 85.5 µA

l

2.25 2.5 2.75 MHz

l

180 200 220 kHz

l

200 2500 kHz

l

1.3 V

l

l

1.9 2.4 3 A

l

3.3 4.3 5.4 A

LT3581

2.3 2.5 V

1/6 ratio

0.4 V

3/4

3581f

3

LT3581

查询LT3581供应商

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Soft-Start Charge Current V

Soft-Start Discharge Current Part in FAULT, V

Soft-Start High Detection Voltage Part in FAULT

Soft-Start Low Detection Voltage Part Exiting FAULT

SHDN Minimum Input Voltage High Active Mode, SHDN Rising

SHDN Input Voltage Low Shutdown Mode
SHDN Pin Bias Current V

CLKOUT Output Voltage High C

CLKOUT Output Voltage Low C

CLKOUT Duty Cycle T

CLKOUT Rise Time C

CLKOUT Fall Time C

GATE Pull Down Current V

GATE Leakage Current V

FAULT Output Voltage Low 100μA into FAULT Pin
FAULT Leakage Current V
FAULT Input Voltage Low
FAULT Input Voltage High

= 30mV, Current Flows Out of SS pin

SS

= 2.1V, Current Flows into SS Pin

SS

Active Mode, SHDN Falling

= 3V

SHDN

V

= 1.3V

SHDN

V

= 0V

SHDN

= 50pF 1.9 2.1 2.3 V

CLKOUT

= 50pF 5 200 mV

CLKOUT

= 25°C 42 %

J

= 50pF 12 ns

CLKOUT

= 50pF 8 ns

CLKOUT

= 3V

GATE

V

= 80V

GATE

= 50V, GATE Off 0.01 1 µA

GATE

= 40V, FAULT Off 0.01 1 µA

FAULT

SHDN

= VIN, V

= VIN, unless otherwise noted. (Note 2).

FAULT

l

5.7 8.7 11.3 µA

l

5.7 8.7 11.3 µA

l

1.65 1.8 1.95 V

l

30 50 85 mV

l

1.27

l

1.24

l

9.7

l

800

l

800

l

l

700 750 800 mV

l

950 1000 1050 mV

1.33

1.3

40

11.4
0

933
933

150 300 mV

1.41

1.38

13.4

1100
1100

0.3 V

60

0.1

µA
µA
µA

µA
µA

V
V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LT3581E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C junction
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: Current limit guaranteed by design and/or correlation to static test.
Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.

3581f

4

DUTY CYCLE (%)

20

0

SW1 + SW2 FAULT CURRENT LIMIT (A)

1

2

3

4

30 50

70

80

3581 G01

5

6

40

60

SW1 + SW2 CURRENT (A)

0

SATURATION VOLTAGE (mV)

200

250

300

54

3581 G02

150

100

0

321

50

450

400

350

SW1 + SW2 CURRENT (A)

0

CURRENT SHARING = SW2/SW1 (%)

50

60

70

54

3581 G03

40

30

0

321

10

20

100

90

80

TEMPERATURE (°C)

–50 –25

0

SW1 + SW2 FAULT CURRENT LIMIT (A)

1

2

3

4

0 50 125 150

3581 G04

5

6

25 75 100

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

1.2100

POSITIVE FB VOLTAGE (V)

1.2125

1.2200

3581 G05

1.2175

1.2150

TEMPERATURE (°C)

–75 –50 –25

10

CLKOUT DC (%)

20

30

40

50

0 50 125 150

3581 G06

60

80

70

25 75 100

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

0

FREQUENCY (kHz)

3200

3581 G07

2800

2400

2000

1600

1200

800

400

RT = 34k

RT = 432k

FB VOLTAGE (V)

0

0

SWITCHING FREQUENCY RATIO (f

SW

/f

OSC

)

1/4
1/5
1/6

1/2

1/3

1

0.2 0.4 0.6 0.8

3581 G08

1.0 1.2

BOOSTING

CONFIGURATIONS

INVERTING

CONFIGURATIONS

0 60 8020 40

GATE VOLTAGE (V)

0

GATE CURRENT (µA)

1000

3581 G09

900

800

700

600

500

400

200

100

300

125°C

–40°C

25°C

查询LT3581供应商

Typical perForMance characTerisTics

= 25°C, unless otherwise noted.

T

A

LT3581

Switch Fault Current Limit vs
Duty Cycle

Switch Fault Current Limit vs
Temperature

Switch Saturation Voltage with
SW1 and SW2 Tied Together

Positive Feedback Voltage
vs Temperature

Current Sharing Between SW1 and
SW2 When Tied Together

CLKOUT Duty Cycle
vs Temperature

Oscillator Frequency Frequency Foldback Gate Current vs Gate Voltage

3581f

5

LT3581

SS VOLTAGE (V)

0

0

GATE CURRENT (µA)

100

300

500

700

200

400

600

800

0.25 0.50 0.75 1.00

3581 G10

1.25 1.50

900

1000

SS VOLTAGE (V)

0

0

SW1 + SW2 CURRENT (A)

1

2

3

0.2 0.4 0.6 0.8

3580 G11

1.0 1.2

4

5

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

1.20

SHDN VOLTAGE (V)

1.22

1.26

1.28

1.30

1.40

1.34

3581 G12

1.24

1.36

1.38

1.32

SHDN RISING

SHDN FALLING

SHDN VOLTAGE (V)

0

0

SHDN PIN CURRENT (µA)

4

8

12

16

20

24

28

32

0.4 1.0 1.40.2 1.20.6 1.60.8 1.8 2.0

3581 G13

125°C

–40°C

25°C

SHDN VOLTAGE (V)

0

SHDN PIN CURRENT (µA)

200

250

15 25

3581 G14

150

100

5 10 20 403530

50

0

125°C

–40°C

25°C

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

2.20

V

IN

VOLTAGE (V)

2.22

2.26

2.28

2.30

2.40

2.34

3581 G15

2.24

2.36

2.38

2.32

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

16

V

IN

VOLTAGE (V)

18

20

30

24

3581 G17

26

28

22

–50 –25 0 50 125 15025 75 100

TEMPERATURE (°C)

0

FAULT VOLTAGE (V)

1.25

0.50

3581 G18

0.75

1.00

0.25

FAULT RISING

FAULT FALLING

0 50 250200150100

CLKOUT CAPACITIVE LOAD (pF)

0

CLKOUT RISE OR FALL TIME (ns)

5

15

20

25

50

35

3581 G16

10

40

45

30

CLKOUT FALL TIME

CLKOUT RISE TIME

查询LT3581供应商

Typical perForMance characTerisTics

TA = 25°C, unless otherwise noted.

Commanded Current Limit vs

Gate Current vs SS Voltage

SS Voltage

SHDN Pin Current SHDN Pin Current Internal UVLO

SHDN Voltage Threshold with

Hysteresis

CLKOUT Rise Time at 1MHz VIN OVLO

6

FAULT Input Voltage Threshold
with Hysteresis

3581f

R

V V

Boost or SEPIC

FB

OUT

=

•











– .

.

;

–

1 215

83 3 10

6

CConverter

R

V mV

Inv

FB

OUT

=

+

•











| |

.

;

–

9

83 3 10

6

eertingConverter

查询LT3581供应商

LT3581

pin FuncTions

(DFN/MSOP)

FB (Pin 1/Pin 1): Positive and Negative Feedback Pin. For

a Boost or Inverting Converter, tie a resistor from the FB
pin to V

according to the following equations:

OUT

VC (Pin 2/Pin 2): Error Amplifier Output Pin. Tie external
compensation network to this pin.

GATE (Pin 3/Pin 3): PMOS Gate Drive Pin. The GATE pin
is a pull-down current source, used to drive the gate of
an external PMOS for output short circuit protection or
output disconnect. The GATE pin current increases linearly
with the SS pin’s voltage, with a maximum pull-down
current of 933µA at SS voltages exceeding 500mV. Note
that if the SS voltage is greater than 500mV and the GATE
pin voltage is less than 2V, then the GATE pin looks like
a 2kΩ impedance to ground. See the Appendix for more
information.

FAULT (Pin 4/Pin 4): Fault Indication Pin. This active low,
bidirectional pin can either be pulled low (below 750mV)
by an external source, or internally by the chip to indicate a
fault. When pulled low, this pin causes the power switches
to turn off, the GATE pin to become high impedance, the
CLKOUT pin to become disabled, and the SS pin to go
through a charge/discharge sequence. The end/absence
of a fault is indicated when the voltage on this pin exceeds
1V. A pull-up resistor or current source is needed on this
pin to pull it above 1V in the absence of a fault.

(Pin 5/Pin 5): Input Supply Pin. Must be locally by-

V

IN

passed.

SW1 (Pins 6, 7/Pins 6,7, 8): Master Switch Pin. This is the
collector of the internal master NPN power switch.
Minimize the metal trace area connected to this pin to
minimize EMI.

CLKOUT (Pin 10/Pin 12): Clock Output Pin. Use this pin
to synchronize one or more other compatible switching
regulator ICs to the LT3581. The clock that this pin outputs
runs at the same frequency as the internal oscillator of the
part or as the SYNC pin. CLKOUT may also be used as a
temperature monitor since the CLKOUT pin’s duty cycle
varies linearly with the part’s junction temperature. Note
that the CLKOUT pin is only meant to drive capacitive
loads up to 50pF.

SHDN (Pin 11/Pin 13): Shutdown Pin. In conjunction
with the UVLO (undervoltage lockout) circuit, this pin is
used to enable/disable the chip and restart the soft-start
sequence. Drive below 300mV to disable the chip. Drive
above 1.33V (typical) to activate the chip and restart the
soft-start sequence. Do not float this pin.

RT (Pin 12/Pin 14): Timing Resistor Pin. Adjusts the
LT3581’s switching frequency. Place a resistor from this
pin to ground to set the frequency to a fixed free running
level. Do not float this pin.

SS (Pin 13/Pin 15): Soft-Start Pin. Place a soft-start
capacitor here. Upon start-up, the SS pin will be charged
by a (nominally) 250k resistor to about 2.1V. During a
fault, the SS pin will be slowly charged up and eventually
discharged as part of a timeout sequence (see the State
Diagram for more information on the SS pin’s role during
a fault event).

SYNC (Pin 14/Pin 16): To synchronize the switching
frequency to an outside clock, simply drive this pin with
a clock. The high voltage level of the clock must exceed

1.3V, and the low level must be less than 0.4V. Drive this
pin to less than 0.4V to revert to the internal free running
clock. See the Applications Information section for more
information.

GND (Exposed Pad Pin 15/Exposed Pad Pin 17): Ground.
Exposed pad must be soldered directly to local ground
plane.

SW2 (Pins 8, 9/Pins 9, 10, 11): Slave Switch Pin. This
is the collector of the internal slave NPN power switch.
Minimize the metal trace area connected to this pin to
minimize EMI.

3581f

7

LT3581

FREQUENCY

FOLDBACK

RAMP

GENERATOR

COMPARATOR

DRIVER
DISABLE

SS

LDO

V

C

R

GATE

14.6k

14.6k

SR1

A3

SYNC CLKOUT

÷N

SS

SHDN

C

OUT1

SW1

SW2

FB

27mΩ

R

S

20mΩ

GND

R

T

RT

R

C

C

C

V

C

R

FB

DRIVER

D1

V

IN

SYNC

BLOCK

UVLO

R

S

Q

3581 BD

–

+

A4

Q2

+
–

TD ~ 30ns

VBE • 0.9

1.17V

45mV

L1

FB

∑

ADJUSTABLE
OSCILLATOR

–

+

–

+

A1

A3

C

SS

C

IN

1.33V

+
–

–
+

+
–

250k

2.1V

1.8V

50mV

SOFT-

START

STARTUP

AND FAULT

LOGIC

C

OUT2

V

OUT

V

IN

M1

GATE

OPTIONAL

SAMPLE MODE BLOCK

R

FAULT

FAULT

933µA

–

+

+

–

+

–

+
–

+
–

+
–

+
–

+
–

DIE TEMP

22V

MIN

165°C

V

IN

750mV

SW1

**

**SW OVERVOLTAGE PROTECTION IS NOT GUARANTEED TO PROTECT THE LT3581 DURING SW OVERVOLTAGE EVENTS

**

I

SW1

42V
MIN

42V
MIN

1.9A
MIN

SW2

SAMPLE

–

+

A2

1.215V

REFERENCE

Q1

查询LT3581供应商

block DiagraM

3581f

Figure 1. Block Diagram

8

SHDN < 1.33V (TYPICAL)

or

V

IN

< 2.3V (TYPICAL)

SHDN > 1.33V (TYPICAL)

AND

V

IN

> 2.3V (TYPICAL)

FAULT DETECTED

• SS CHARGES UP

• IGATE OFF

• FAULT PIN PULLED LOW
INTERNALLY BY LT3581

• SWITCHER DISABLED

• CLKOUT DISABLED

SS < 50mV

IF |V

OUT

| DROPS CAUSING:

FB < 1.17V (BOOST)

OR

FB > 45mV (INVERTING)

FAULT1

FAULT1

SS > 1.8V AND
NO FAULT1 CONDITIONS
STILL DETECTED

SS < 50mV

FAULT1

FAULT1

FAULT1

FAULT1

FAULT2

FAULT PIN > 1.0V

FAULT1 = OVER VOLTAGE PROTECTION ON V

IN

(VIN > 22V MIN)

OVER TEMPERATURE (T

JUNCTION

> 165°C)

OVER CURRENT ON SW1 (I

SW1

> 1.9A MIN)

OVER VOLTAGE PROTECTION ON SW1 (V

SW1

> 42V MIN)

OVER VOLTAGE PROTECTION ON SW2 (V

SW2

> 42V MIN)

FAULT2 = FAULT PULLED LOW EXTERNALLY (FAULT < 0.75V)

CHIP OFF

• ALL SWITCHES DISABLED

• I

GATE

OFF

• FAULTS CLEARED

INITIALIZE

• SS PULLED LOW

NORMAL MODE

• NORMAL OPERATION

• CLKOUT ENABLED WHEN
SS > 1.8V

SAMPLE MODE

• Q1 & Q2 SWITCHES
FORCED ON EVERY CYCLE
FOR AT LEAST MINIMUM
ON TIME

• I

GATE

FULLY ACTIVATED

WHEN SS > 500mV

SOFT START

• I

GATE

ENABLED

• SS CHARGES UP

• SWITCHER ENABLED

POST FAULT DELAY

• SS SLOWLY DISCHARGES

LOCAL FAULT OVER

• INTERNAL FAULT PIN PULLDOWN
RELEASED BY LT3581

• SS CONTINUES DISCHARGING
TO GND

3581 SD

查询LT3581供应商

sTaTe DiagraM

LT3581

Figure 2. State Diagram

3581f

9

LT3581

R

V V

V

R

µ

UVLO

INUVLO

UVLO12

1 33

1 33

11 6

=











+

– .

.

.

AA

R

UVLO2

(OPTIONAL)

1.33V

R

UVLO1

3581 F03

V

IN

V

IN

ACTIVE/

LOCKOUT

GND

11.6µA

AT 1.33V

–

+

SHDN

查询LT3581供应商

operaTion

OPERATION – OVERVIEW

The LT3581 uses a constant-frequency, current mode con-
trol scheme to provide excellent line and load regulation.
The part’s undervoltage lockout (UVLO) function, together
with soft-start and frequency foldback, offers a controlled
means of starting up. Fault features are incorporated in the
LT3581 to aid in the detection of output shorts, over-volt-
age, and overtemperature conditions. Refer to the Block
Diagram (Figure 1) and the State Diagram (Figure 2) for
the following description of the part’s operation.

Figure 3. Configurable UVLO

PERATION – START-UP

O

Several functions are provided to enable a very clean
start-up for the LT3581:

Precise Turn-On Voltage

The SHDN pin is compared to an internal voltage reference
to give a precise turn on voltage level. Taking the SHDN pin
above 1.33V (typical) enables the part. Taking the SHDN pin
below 300mV shuts down the chip, resulting in extremely
low quiescent current. The SHDN pin has 30mV of hysteresis
to protect against glitches and slow ramping.

Undervoltage Lockout (UVLO)

The SHDN pin can also be used to create a configurable
UVLO. The UVLO function sets the turn on/off of the LT3581
at a desired input voltage (V
resistor divider (or single resistor) from V
pin can be used to set V

INUVLO

). Figure 3 shows how a

INUVLO

IN

. R

is optional. It may

UVLO2

to the SHDN

be left out, in which case set it to infinite in the equation
below. For increased accuracy, set R

UVLO1

as follows:

R

≤ 10k. Pick

UVLO2

The LT3581 also has internal UVLO circuitry that disables
the chip when V

< 2.3V (typical).

IN

Soft-Start of Switch Current

The soft-start circuitry provides for a gradual ramp-up
of the switch current (refer to Commanded Current Limit
vs SS Voltage in Typical Performance Characteristics).
When the part is brought out of shutdown, the external
SS capacitor is first discharged which resets the states
of the logic circuits in the chip. Then an integrated 250k
resistor pulls the SS pin to ~1.8V. The ramp rate of the SS
pin voltage is set by this 250k resistor and the external
capacitor connected to this pin. Once SS gets to 1.8V, the
CLKOUT pin is enabled, and an internal regulator pulls
the pin up quickly to ~2.1V. Typical values for the external
soft-start capacitor range from 100nF to 1μF.

Soft-Start of External PMOS (if used)

The soft-start circuitry also gradually ramps up the GATE
pin pull-down current which allows an external PMOS to
slowly turn on (M1 in Block Diagram). The GATE pin current
increases linearly with the SS voltage, with a maximum
current of 933µA when the SS voltage gets above 500mV.
Note that if the GATE pin voltage is less than 2V for SS
voltages exceeding 500mV, then the GATE pin impedance
to ground is 2kΩ. The soft turn on of the external PMOS
helps limit inrush current at start-up, making hot-plugs
of LT3581s feasible and safe.

10

3581f

查询LT3581供应商

operaTion

LT3581

Sample Mode

Sample Mode is the mechanism used by the LT3581 to
aid in the detection of output shorts. It refers to a state of
the LT3581 where the master and slave power switches
(Q1 and Q2) are turned on for a minimum period of time
every clock cycle (or every few clock cycles in frequency
foldback) in order to “sample” the inductor current. If the
sampled current through Q1 exceeds the master switch cur-
rent limit of 1.9A (min), the LT3581 triggers an overcurrent
fault internally (see Operation-Fault section for details).
Sample Mode is active when FB is out of regulation by
more than approximately 3.7% (45mV < FB < 1.17V).

Frequency Foldback

The frequency foldback circuit reduces the switching fre-
quency when 350mV < FB < 900mV (typical). This feature
lowers the minimum duty cycle that the part can achieve,
thus allowing better control of the inductor current dur-
ing start-up. When the FB voltage is pulled outside of this
range, the switching frequency returns to normal.

Note that the peak inductor current at start-up is a function
of many variables including load profile, output capacitance,
target V

every application’s performance at start-up to ensure that
the peak inductor current does not exceed the minimum
fault current limit.

, VIN, switching frequency, etc. Test each and

OUT

Q1’s emitter current flows through a current sense resistor

) generating a voltage proportional to the total switch

(R

S

current. This voltage (amplified by A4) is added to a sta­bilizing ramp and the resulting sum is fed into the positive
terminal of the PWM comparator A3. When the voltage on
the positive input of A3 exceeds the voltage on the negative
input, the SR latch is reset, turning off the master and slave
power switches. The voltage on the negative input of A3

pin) is set by A1 (or A2), which is simply an amplified

(V

C

difference between the FB pin voltage and the reference
voltage (1.215V if the LT3581 is configured as a boost
converter, or 9mV if configured as an inverting converter).
In this manner, the error amplifier sets the correct peak
current level to maintain output regulation.

As long as the part is not in fault (see Operation – Fault
section) and the SS pin exceeds 1.8V, the LT3581 drives its
CLKOUT pin at the frequency set by the RT pin or the SYNC
pin. The CLKOUT pin can be used to synchronize other
compatible switching regulator ICs (including additional
LT3581s) with the LT3581. Additionally, CLKOUT’s duty
cycle varies linearly with the part’s junction temperature,
and may be used as a temperature monitor.

TION – FAULT

PERA

O

The LT3581’s FAULT pin is an active low, bidirectional pin
that is pulled low to indicate a fault. Each of the following
events can trigger a fault in the LT3581:

PERATION – REGULATION

O

The following description of the LT3581’s operation as-
sumes that the FB voltage is close enough to its regulation
target so that the part is not in sample mode. Use the
Block Diagram as a reference when stepping through the
following description of the LT3581 operating in regulation.
At the start of each oscillator cycle, the SR latch (SR1) is
set, which turns on the power switches Q1 and Q2. The
collector current through the master switch, Q1, is ~1.3
times the collector current through the slave switch, Q2,
when the collectors of the two switches are tied together.

AULT1 events:

A. F

1. SW Over
a.
b. (I

2. V

3. SW1 Voltage and/or SW2 Voltage > 42V
(minimum)

4. Die T
B. FAULT2 events:

1. Pulling the F

I

IN

current:

> 1.9A (minimum)

SW1

+ I

SW1

Voltage > 22V (minimum)

emperature > 165°C

) > 3.3A (minimum)

SW2

AULT pin low externally

3581f

11