LINEAR TECHNOLOGY LT1813 Technical data

Application Note 79

INPUT

OUTPUT

AN79 F01

SETTLING TIME

SLEW

TIME

RING TIME

ALLOWABLE

OUTPUT

ERROR

BAND

DELAY TIME

September 1999

30 Nanosecond Settling Time Measurement for a
Precision Wideband Amplifier

Quantifying Prompt Certainty

Jim Williams

Introduction

Instrumentation, waveform generation, data acquisition,
feedback control systems and other application areas
utilize wideband amplifiers. New components (see page 2
“A Precision Wideband Dual Amplifier with 30ns Settling
Time”) have introduced precision while maintaining high
speed operation. The amplifier’s DC and AC specifications
approach or equal previous devices at significantly lower
cost while saving power.

Settling Time Defined

Amplifier DC specifications are relatively easy to verify.
Measurement techniques are well understood, albeit often
tedious. AC specifications require more sophisticated
approaches to produce reliable information. In particular,
amplifier settling time is extraordinarily difficult to deter­mine. Settling time is the elapsed time from input applica­tion until the output arrives at and remains within a
specified error band around the final value. It is usually
specified for a full-scale transition. Figure 1 shows that
settling time has three distinct components. The

time

is small and is almost entirely due to amplifier

delay

propagation delay. During this interval there is no output
movement. During
highest possible speed towards the final value.

slew time

the amplifier moves at its

Ring time

defines the region where the amplifier recovers from
slewing and ceases movement within some defined error
band. There is normally a trade-off between slew and ring
time. Fast slewing amplifiers generally have extended ring
times, complicating amplifier choice and frequency com-

Figure 1. Settling Time Components Include Delay, Slew and
Ring Times. Fast Amplifiers Reduce Slew Time, Although
Longer Ring Time Usually Results. Delay Time is Normally a
Small Term

pensation. Additionally, the architecture of very fast ampli­fiers usually dictates trade-offs which degrade DC error

1

terms.
Measuring anything at any speed requires care. Dynamic

measurement is particularly challenging. Reliable nano­second region settling time measurement constitutes a
high order difficulty problem requiring exceptional care
in approach and experimental technique.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Note 1: This issue is treated in detail in latter portions of the text.
Also see Appendix D “Practical Considerations for Amplifier
Compensation.

Note 2: The approach used for settling time measurement and its
description borrows heavily from a previous publication. See
Reference 1.

2

AN79-1

Application Note 79

A PRECISION WIDEBAND DUAL AMPLIFIER WITH
30ns SETTLING TIME

Until recently, wideband amplifiers provided speed,
but sacrificed precision, power consumption and,
often, settling time. The LT®1813 dual op amp does not
require this compromise. It features low offset voltage
and bias current and high DC gain while operating at
low supply current. Settling time is 30ns to 0.1% for a
5V step. The output will drive a 100Ω load to ±3.5V
with ±5V supplies, and up to 100pF capacitive loading
is permissible. The table below provides short form
specifications.

LT1813 Short Form Specifications

CHARACTERISTIC SPECIFICATION

Offset Voltage 0.5mV
Offset Voltage vs Temperature 10µV/°C
Bias Current 1.5µA
DC Gain 3000
Noise Voltage 8nV/√Hz
Output Current 60mA
Slew Rate 750V/µs
Gain-Bandwidth 100MHz
Delay 2.5ns
Settling Time 30ns/0.1%
Supply Current 3mA per Amplifier

Considerations for Measuring Nanosecond Region
Settling Time

Historically, settling time has been measured with circuits
similar to that in Figure 2. The circuit uses the “false sum
node” technique. The resistors and amplifier form a bridge
type network. Assuming ideal resistors, the amplifier
output will step to –VIN when the input is driven. During
slew, the settle node is bounded by the diodes, limiting
voltage excursion. When settling occurs, the oscilloscope
probe voltage should be zero. Note that the resistor
divider’s attenuation means the probe’s output will be one­half of the actual settled voltage.

In theory, this circuit allows settling to be observed to
small amplitudes. In practice, it cannot be relied upon to
produce useful measurements. Several flaws exist. The
circuit requires the input pulse to have a flat top within the
required measurement limits. Typically, settling within
5mV or less for a 5V step is of interest. No general purpose
pulse generator is meant to hold output amplitude and
noise within these limits. Generator output-caused aber­rations appearing at the oscilloscope probe will be indis­tinguishable from amplifier output movement, producing
unreliable results. The oscilloscope connection also pre­sents problems. As probe capacitance rises, AC loading of
the resistor junction influences observed settling wave­forms. A 10pF probe alleviates this problem but its 10×
attenuation sacrifices oscilloscope gain. 1× probes are not
suitable because of their excessive input capacitance. An

AN79-2

INPUT STEP TO
OSCILLOSCOPE

POSITIVE INPUT

FROM PULSE

GENERATOR

Figure 2. Popular Summing Scheme for Settling Time Measurement Provides Misleading
Results. Pulse Generator Posttransition Aberrations Appear at Output. 10× Oscilloscope
Overdrive Occurs. Displayed Information Is Meaningless

–

AMPLIFIER

+

+V

REF

OUTPUT TO
OSCILLOSCOPE

AN79 F02

Application Note 79

active 1× FET probe will work, but another issue remains.
The clamp diodes at the settle node are intended to reduce

swing during amplifier slewing, preventing excessive os­cilloscope overdrive. Unfortunately, oscilloscope overdrive
recovery characteristics vary widely among different types
and are not usually specified. The Schottky diodes’ 400mV
drop means the oscilloscope will undergo an unaccept­able overload, bringing displayed results into question.

3

At 0.1% resolution (5mV at the output—2.5mV at the
oscilloscope), the oscilloscope typically undergoes a 10×
overdrive at 10mV/DIV, and the desired 2.5mV baseline is
unattainable. At nanosecond speeds, the measurement
becomes hopeless with this arrangement. There is clearly
no chance of measurement integrity.

The preceding discussion indicates that measuring ampli­fier settling time requires an oscilloscope that is somehow
immune to overdrive and a “flat-top” pulse generator.
These become the central issues in wideband amplifier
settling time measurement.

The only oscilloscope technology that offers inherent
overdrive immunity is the classical sampling ‘scope.

4

Unfortunately, these instruments are no longer manufac­tured (although still available on the secondary market).
It is possible, however, to construct a circuit that borrows
the overload advantages of classical sampling ‘scope
technology. Additionally, the circuit can be endowed with

features particularly suited for measuring nanosecond
range settling time.

The “flat-top” pulse generator requirement can be avoided
by switching current, rather than voltage. It is much easier
to gate a quickly settling current into the amplifier’s
summing node than to control a voltage. This makes the
input pulse generator’s job easier, although it still must
have a rise time of 1 nanosecond or less to avoid measure­ment errors.

5

Practical Nanosecond Settling Time Measurement

Figure 3 is a conceptual diagram of a settling time mea­surement circuit. This figure shares attributes with
Figure␣ 2, although some new features appear. In this case,
the oscilloscope is connected to the settle point by a

Note 3: For a discussion of oscilloscope overdrive considerations, see
Appendix A, “Evaluating Oscilloscope Overdrive Performance.”

Note 4: Classical sampling oscilloscopes should not be confused with
modern era digital sampling ‘scopes that have overdrive restrictions.
See Appendix A, “Evaluating Oscilloscope Overload Performance” for
comparisons of various type ‘scopes with respect to overdrive. For
detailed discussion of classical sampling ‘scope operation see
References 16 through 19 and 22 through 24. Reference 17 is
noteworthy; it is the most clearly written, concise explanation of
classical sampling instruments the author is aware of—a 12-page
jewel.

Note 5: Subnanosecond rise time pulse generators are considered in
Appendix B, “Subnanosecond Rise Time Pulse Generators for the Rich
and Poor.”

+V

CURRENT

SWITCH

INPUT FROM

PULSE

GENERATOR

Figure 3. Conceptual Arrangement is Insensitive to Pulse Generator Aberrations and Eliminates Oscilloscope
Overdrive. Switch at Input Gates Current Step to Amplifer. Second Switch is Controlled by Delayed Pulse
Generator, Preventing Oscilloscope from Monitoring Settle Node Until Settling is Nearly Complete

–

AMPLIFIER

+

SETTLE
NODE

–V

REF

DELAYED

PULSE

GENERATOR

SWITCH

AN79 F03

OUTPUT TO
OSCILLOSCOPE

AN79-3

Application Note 79

switch. The switch state is determined by a delayed pulse
generator, which is triggered from the input pulse. The
delayed pulse generator’s timing is arranged so that the
switch does not close until settling is very nearly complete.
In this way the incoming waveform is sampled in time, as
well as amplitude. The oscilloscope is never subjected to
overdrive—no off-screen activity ever occurs.

A switch at the amplifier’s summing junction is controlled
by the input pulse. This switch gates current to the
amplifier via a voltage-driven resistor. This eliminates the
“flat-top” pulse generator requirement, although the switch
must be fast and devoid of drive artifacts.

Figure 4 is a more complete representation of the settling
time scheme. Figure 3’s blocks appear in greater detail
and some new refinements show up. The amplifier sum­ming area is unchanged. Figure 3’s delayed pulse genera­tor has been split into two blocks; a delay and a pulse
generator, both independently variable. The input step to
the oscilloscope runs through a section that compensates
for the propagation delay of the settling time measure-

ment path. The most striking new aspect of the diagram
are the diode bridge switches. Borrowed from classical
sampling oscilloscope circuitry, they are the key to the
measurement. The diode bridge’s inherent balance elimi­nates charge injection based errors. It is far superior to
other electronic switches in this character

istic. Any other
high speed switch technology contributes excessive out­put spikes due to charge-based feedthrough. FET switches
are not suitable because their gate-channel capacitance
permits such feedthrough. This capacitance allows gate­drive artifacts to corrupt switching, defeating the switches
purpose.

The diode bridge’s balance, combined with matched, low
capacitance monolithic diodes and high speed switching,
yields clean switching. The input-driven bridge switches
current into the amplifier’s summing point very quickly,
with settling inside a few nanoseconds. The diode clamp
to ground prevents excessive bridge drive swings and
ensures that input pulse characteristics are irrelevant.

TIME-CORRECTED
INPUT STEP TO
OSCILLOSCOPE

OUTPUT TO
OSCILLOSCOPE
SETTLE NODE

()

2

INPUT FROM

PULSE

GENERATOR

VARIABLE

DELAY

+V

–V

+V

REF

–

OUTPUT

AMPLIFIER

+

DELAYED

PULSE GENERATOR

0V TO 10V
TRANSITION

SETTLE

R

NODE

R

VARIABLE WIDTH

PULSE GENERATOR

DELAY COMPENSATION

SAMPLING

BRIDGE
DRIVER

×1

BRIDGE SWITCHING

CONTROL

SAMPLING

BRIDGE
SWITCH

AN79 F04

Figure 4. Block Diagram of Settling Time Measurement Scheme. Diode Bridge Switches Input Current to Amplifier.
Second Diode Bridge Switch Minimizes Switching Feedthrough, Preventing Oscilloscope Overdrive. Input Step
Time Reference is Compensated for Test Circuit Delays

AN79-4

Application Note 79

Figure 5 details considerations for the output diode bridge
switch. This bridge requires considerable attention to
achieve desired performance. The monolithic bridge
diodes tend to cancel each other’s temperature coeffi­cient—drift is only about 100µV/°C—but a DC balance is
required to minimize offset.

DC balance is achieved by trimming the bridge on-current
for zero input-output offset voltage. Two AC trims are
required. The “AC balance” corrects for diode and layout
capacitive imbalances and the “skew compensation” cor­rects for any timing asymmetry in the nominally comple­mentary bridge drive. These AC trims compensate small
dynamic imbalances, minimizing parasitic bridge outputs.

ON

OFF

+

–

V

V

AC BALANCE

ALL DIODES = CA3039

MONOLITHIC ARRAY

INPUT

DC BALANCE

SKEW
COMPENSATION

OUTPUT

AN79 F05

The input pulse triggers the C2-C3 based delayed pulse
generator. This circuitry is arranged to produce a delayed
(controllable by the 10k potentiometer) pulse whose width
(controllable by the 2k potentiometer) sets diode bridge
on-time. If the delay is set appropriately, the oscilloscope
will not see any input until settling is nearly complete,
eliminating overdrive. The sample window width is ad­justed so that all remaining settling activity is observable.
In this way the oscilloscope’s output is reliable and mean­ingful data may be taken. The delayed generator’s output
is level shifted by the Q1-Q4 transistors, providing comple­mentary switching drive to the bridge. The actual switch­ing transistors, Q1-Q2, are UHF types, permitting true
differential bridge switching with less than 1ns of time

7

skew.
Figure 7 shows circuit waveforms. Trace A is the time-

corrected input pulse, trace B the amplifier output, trace C
the sample gate and trace D the settling time output. When
the sample gate goes low, the bridge switches cleanly, and
the last 10mV of slew are easily observed. Ring time is also
clearly visible, and the amplifier settles nicely to final value.
When the sample gate goes high, the bridge switches off,
with only millivolts of feedthrough. Note that there is no
off-screen activity at any time—the oscilloscope is never
subjected to overdrive.

–

+

V

V
ON

OFF

Figure 5. Diode Sampling Bridge Switch Trims Include
AC and DC Balance and Switch Drive Timing Skew

Detailed Settling Time Circuitry

Figure 6 is a detailed schematic of the settling time
measurement circuitry. The input pulse switches the input
bridge and is also routed to the oscilloscope via a delay­compensation network. The delay network, composed of
a fast comparator and an adjustable RC network, compen­sates the oscilloscope’s input step signal for the 6ns delay
through the circuit’s measurement path.6 The amplifier’s
output is compared against the 5V reference via the
summing resistors. The 5V reference also furnishes the
bridge input current, making the measurement ratiometric.
The –5V reference supply pulls a current from the sum­ming point, allowing the amplifier a 5V step from 2.5V to
–2.5V. The clamped settle node is unloaded by A1, which
drives the sampling bridge.

Figure 8 expands vertical and horizontal scales so that
settling detail is more visible.8 Trace A is the time-cor­rected input pulse and trace B the settling output. The last
15mV of slew (beginning at the center-screen vertical
marker) are easily observed, and the amplifier settles
inside 5mV (0.1%) in 30 nanoseconds.

The circuit requires trimming to achieve this level of
performance. DC and AC trims are required. Making these
adjustments requires disabling the amplifier (disconnect
the input current switch and the 1k resistor at the ampli­fier), and shorting the settle node directly to the ground
plane. Figure 9 shows typical results before trimming.

Note 6: See Appendix C, “Measuring and Compensating Settling
Circuit Delay.”

Note 7: The bridge switching scheme was developed at LTC by
George Feliz.

Note 8: In this and all following photos, settling time is measured from
the onset of the time-corrected input pulse. Additionally, settling signal
amplitude is calibrated with respect to the amplifier, not the sampling
bridge output. This eliminates ambiguity introduced by the summing
resistor’s ÷ 2 ratio.

AN79-5

Application Note 79

+

AC

BALANCE

2.5k

TIME-CORRECTED

INPUT STEP TO

OSCILLOSCOPE

VIA HP-1120A

FET PROBE

SAMPLING BRIDGE

1k

SAMPLING

BRIDGE

DRIVER

8

1.1k

Q1

Q4

11

10

13

8

7

96

Q3

5pF

3pF

0.1µF

10pF

10µF

510Ω

100Ω

100Ω

2k

SAMPLE

WINDOW

WIDTH

10pF

Q2

CA3039

ARRAY

13

–5V

–5V

–5V

SKEW COMP

2.5k

2

7

11

10

4

3

5

2.2k

1.1k

5V

2.2k

10µF

1µF

0.1µF

470Ω

560Ω

51Ω

820Ω 51Ω

680Ω

500Ω

BASELINE

ZERO

5V

OUTPUT TO

OSCILLOSCOPE

VIA HP-1120A

FET PROBE

–

+

–

+

A1

LT1813

–

+

C1

1/2 LT1720

LT1813

0.1µF10µF

+

: 1N4148

: 1N5711

DIODE BRIDGES: HARRIS CA3039M

* = 1% FILM RESISTOR

Q1, Q2: MRF-501

Q3, Q4: LM3045 ARRAY

USE IN-LINE COAXIAL TERMINATOR FOR

PULSE GENERATOR INPUT. DO NOT MOUNT

50Ω RESISTOR ON BOARD

DERIVE 5V AND –5V SUPPLIES FROM

±15V.

USE LT317A FOR 5V, LT1175-5 FOR –5V

CONSTRUCTION IS CRITICAL—SEE TEXT

+

1µF

+

5V

DELAY COMPENSATION = 6ns

2k

2k

SAMPLE DELAY/WINDOW GENERATOR

SAMPLE GATE LINE

5V

3.9pF

DELAY

COMP

2k

2k

1k

10k

SAMPLE

DELAY

AN79 F06

909Ω*

499Ω*

2pF TO 8pF (SEE TEXT)

200Ω

SETTLE

NODE

SETTLE

NODE

ZERO

1k*

7

8

2pF

11

5V

CURRENT

SWITCH

–5V

AMPLIFIER

UNDER TEST

–5V

430Ω*

1k*

270Ω

50Ω

2

10

4

CA3039

ARRAY

PULSE

GENERATOR

INPUT

3

5

–

+

C3

1/2 LT1720

–

+

C2

+

13

–5V

INLINE

TERMINATION

(SEE TEXT

AND NOTES)

1/2 LT1720

430Ω*

ttention to Layout

AN79-6

Figure 6. Detailed Schematic of Settling Time Measurement Circuit Closely Follows Block Diagram. Optimum Performance Requires A

Application Note 79

A = 2V/DIV
B = 2V/DIV

C = 5V/DIV

D = 20mV/DIV

20ns/DIV

Figure 7. Settling Time Circuit Waveforms Include Time­Corrected Input Pulse (Trace A), Amplifier-Under-Test Output
(Trace B), Sample Gate (Trace C) and Settling Time Output
(Trace D). Sample Gate Window’s Delay and Width are Variable

A = 2V/DIV

B = 5mV/DIV

AN79 F07

A = 2V/DIV

B = 5mV/DIV

10ns/DIV

Figure 9. Settling Time Circuit’s Output (Trace B) with
Unadjusted Sampling Bridge AC and DC Trims. Settle Node is
Grounded for This Test. Excessive Switch Drive Feedthrough and
Baseline Offset are Present. Trace A is the Sample Gate

A = 2V/DIV

B = 5mV/DIV

10ns/DIV

AN79 F09

AN79 F10

5ns/DIV AN79 F08

Figure 8. Expanded Vertical and Horizontal Scales Show
30ns Amplifier Settling Within 5mV (Trace B). Trace A is
Time-Corrected Input Step

Trace A is the input pulse and trace B the settle signal
output. With the amplifier disabled and the settle node
grounded, the output should (theoretically) always be
zero. The photo shows this is not the case for an un­trimmed bridge. AC and DC errors are present. The sample
gate’s transitions cause large swings. Additionally, the
output shows significant DC offset error during the sam­pling interval. Adjusting the AC balance and skew compen­sation minimizes the switching induced transients. The
DC offset is adjusted out with the baseline zero trim. Figure
10 shows the results after making these adjustments. All
switching related activity is minimized and offset error
reduced to unreadable levels. Once this level of perfor­mance has been achieved, the circuit is nearly ready for
use.9 Unground the settle node and restore the current
switch and resistor connections to the amplifier. Any

Figure 10. Settling Time Circuit’s Output (Trace B) with
Sampling Bridge Trimmed. As in Figure 9, Settle Node is
Grounded for This Test. Switch Drive Feedthrough and
Baseline Offset are Minimized. Trace A is the Sample Gate

further differences between pre- and postsettling baseline
are corrected with the “settle node zero” trim.

Using the Sampling-Based Settling Time Circuit

Figures 11 and 12 underscore the importance of position­ing the sampling window properly in time. In Figure 10 the
sample gate delay initiates the sample window (trace A)
too early and the residue amplifier’s output (trace B)
overdrives the oscilloscope when sampling commences.
Figure 12 is better, with no off-screen activity. All amplifier
settling residue is well inside the screen boundaries.

Note 9: Achieving this level of performance also depends on layout.
The circuit’s construction involves a number of subtleties and is
absolutely crucial. Please see Appendix E, “Breadboarding, Layout and
Connection Techniques.”

AN79-7

Application Note 79

A = 5V/DIV

B = 5mV/DIV

very light compensation. Trace A is the time-corrected
input pulse and trace B the settling residue output. The
light compensation permits very fast slewing but exces­sive ringing amplitude over a protracted time results.
When sampling is initiated (just prior to the fourth vertical
division) the ringing is seen to be in its final stages,
although still offensive. Total settling time is about 43ns.
Figure 14 presents the opposite extreme. Here a large
value compensation capacitor eliminates all ringing but
slows down the amplifier so much that settling stretches

10ns/DIV

Figure 11. Oscilloscope Display with Inadequate Sample Gate
Delay. Sample Window (Trace A) Occurs Too Early, Resulting in
Off-Screen Activity in Settle Output (Trace B). Oscilloscope is
Overdriven, Making Displayed Information Questionable

A = 5V/DIV

B = 5mV/DIV

10ns/DIV AN79 F12

Figure 12. Optimal Sample Gate Delay Positions Sampling
Window (Trace A) So All Settle Output (Trace B) Information
is Well Inside Screen Boundaries

AN79 F11

A = 5V/DIV

B = 10mV/DIV

10ns/DIV AN79 F13

Figure 13. Settling Profile with Inadequate Feedback
Capacitance Shows Underdamped Response. Trace A is Time­Corrected Input Pulse. Trace B is Settling Residue Output.
t

= 43ns

SETTLE

A = 5V/DIV

In general, it is good practice to “walk” the sampling
window up to the last ten millivolts or so of amplifier
slewing so that the onset of ring time is observable. The
sampling based approach provides this capability and it is
a very powerful measurement tool. Additionally, remem­ber that slower amplifiers may require extended delay and/
or sampling window times. This may necessitate larger
capacitor values in the delayed pulse generator timing
networks.

Compensation Capacitor Effects

The amplifier requires frequency compensation to get the
best possible settling time.10 Figure 13 shows effects of

AN79-8

B = 10mV/DIV

10ns/DIV

Figure 14. Excessive Feedback Capacitance Overdamps
Response. t

Note 10: This section discusses frequency compensation of the

amplifier within the context of sampling-based settling time measure­ment. As such, it is necessarily brief. Considerably more detail is
available in Appendix D, “Practical Considerations for Amplifier
Compensation.”

SETTLE

= 50ns

AN79 F14

Application Note 79

out to 50ns. The best case appears in Figure 15. This photo
was taken with the compensation capacitor carefully cho­sen for the best possible settling time. Damping is tightly
controlled and settling time goes down to 30ns.

A = 5V/DIV

B = 5mV/DIV

5ns/DIV AN79 F15

Figure 15. Optimal Feedback Capacitance Yields Tightly Damped
Signature and Best Settling Time. Optimum Response Allows
Expanded Horizontal and Vertical Scales. t

SETTLE

≤ 30ns

Verifying Results—Alternate Method

The sampling-based settling time circuit appears to be a
useful measurement solution. How can its results be
tested to ensure confidence? A good way is to make the
same measurement with an alternate method and see if
results agree. It was stated earlier that classical sampling
oscilloscopes were inherently immune to overdrive.11 If
this is so, why not utilize this feature and attempt settling
time measurement directly at the clamped settle node?
Figure 16 does this. Under these conditions, the sampling
‘scope12 is heavily overdriven, but is ostensibly immune to
the insult. Figure 17 puts the sampling oscilloscope to the
test. Trace A is the time corrected input pulse and trace B
the settle signal. Despite a brutal overdrive, the ‘scope
appears to respond cleanly, giving a very plausible settle
signal presentation.

Note 11: See Appendix A, “Evaluating Oscilloscope Overdrive
Performance,” for in-depth discussion.
Note 12: Tektronix type 661 with 4S1 vertical and 5T3 timing plug-ins.

PULSE

GENERATOR

INPUT

* = 1% FILM RESISTOR

5V

100Ω

50Ω

: 1N5711

2pF

510Ω

2k

DELAY

COMP

1k

2

8

2k

+

1µF

3.9pF

13

7

3

–5V–5V

5V

11

430 Ω*

4
CA3039

ARRAY

430Ω*

–

1/2 LT1720

+

–5V

10

5

1k*

TYP 2.2pF (SEE TEXT)

C

COMP

510Ω*

–

LT1813

+

909Ω*

200Ω

SETTLE

NODE

ZERO

TIME-CORRECTED INPUT
STEP TO TEKTRONIX 661
OSCILLOSCOPE VIA
×10 HP-1120A FET PROBE

1k*

OUTPUT TO
TEKTRONIX 661 OSCILLOSCOPE
VIA ×1 HP-1120A FET PROBE

5V

AN79 F16

Figure 16. Settling Time Test Circuit Using Classical Sampling Oscilloscope.
Sampling ‘Scope’s Inherent Overload Immunity Permits Large Off-Screen Excursions

AN79-9

Application Note 79

A = 2V/DIV

B = 5mV/DIV

5ns/DIV AN79 F17

Figure 17. Settling Time Measurement with the Classical
Sampling ‘Scope. Oscilloscope’s Overload Immunity Allows
Accurate Measurement Despite Extreme Overdrive

Summary of Results

The simplest way to summarize the different method’s
results is by visual comparison. Figures 18 and 19 repeat
previous photos of the two different settling-time meth­ods. If both approaches represent good measurement
technique and are properly constructed, results should be
indentical.13 If this is the case, the identical data produced
by the two methods has a high probability of being valid.

A = 2V/DIV

B = 5mV/DIV

5ns/DIV AN79 F18

Figure 18. Settling Time Measurement Using the Sampling
Bridge Circuit. t

A = 2V/DIV

B = 5mV/DIV

SETTLE

= 30ns

Examination of the photographs shows nearly identical
settling times and settling waveform signatures. The shape
of the settling waveform is essentially identical in both
photos.14 This kind of agreement provides a high degree
of credibility to the measured results.

Note 13: Construction details of the settling time fixtures discussed
here appear (literally) in Appendix E, “Breadboarding, Layout and
Connection Techniques.”

Note 14: The slightly rougher appearance of figure 19’s final settling
movement (7th through 9th vertical divisions) may be due to the
sampling ‘scope’s substantially higher bandwidth. Figure 18 was taken
with a150MHz instrument; sampling oscilloscope bandwidth is 1GHz.

5ns/DIV

AN79 F19

Figure 19. Settling Time Measurement using the Classical
Sampling ‘Scope. t

SETTLE

= 30ns

AN79-10