LINEAR TECHNOLOGY LT1768 Technical data

LT1768

High Power CCFL Controller

for Wide Dimming Range and

FEATURES

■

Ultrawide Multimode DimmingTM Range

■

Multiple Lamp Capability

■

Programmable PWM Dimming Range and
Frequency

■

Precision Maximum and Minimum Lamp
Currents Maximize Lamp Lifetime

■

No Lamp Flicker Under All Supply and Load
Conditions

■

Open Lamp Detection and Protection

■

350kHz Switching Frequency

■

1.5A MOSFET Gate Driver

■

100mV Current Sense Threshold

■

5V Reference Voltage Output

■

The 16-Lead SSOP Package

U

APPLICATIO S

■

Desktop Flat Panel Displays

■

Multiple Lamp Displays

■

Notebook LCD Displays

■

Point of Sale Terminal Displays

Maximum Lamp Lifetime

U

DESCRIPTIO

The LT®1768 is designed to control single or multiple cold
cathode fluorescent lamp (CCFL) displays. A unique Mul­timode Dimming scheme* combines both linear and PWM
control functions to maximize lamp life, efficiency, and
dimming range. Accurate maximum and minimum lamp
currents can be easily set. The LT1768 can detect and
protect against lamp failures and overvoltage start-up
conditions. It is designed to provide maximum flexibility
with a minimum number of external components.

The LT1768 is a current mode PWM controller with a 1.5A
MOSFET driver for high power applications. It contains a
350kHz oscillator, 5V reference, and a current sense
comparator with a 100mV threshold. It operates from an
8V to 24V input voltage. The LT1768 also has undervoltage
lockout, thermal limit, and a shutdown pin that reduces
supply current to 65µA. It is available in a small 16-lead
SSOP package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Multimode Dimming is a trademark of Linear Technology Corporation.
*Patent Pending

TYPICAL APPLICATIO

C4-WIMA MKP2
L1-COILTRONICS UP4-680
T1-2 CTX110607 IN PARALLEL
Q1-ZDT1048
*R5 CAN BE METAL PCB TRACE

PGND GATE

DI02

DI01

SENSE

C4
10µF

V

AGND

C

PROG

PROG

0V TO 5V OR

1kHz PWM

C2

0.033µF

C3

0.1µF

R1

49.9k

Figure 1. 14W CCFL Supply Produces a 100:1 Dimming Ratio While
Maintaining Minimum and Maximum Lamp Current Specifications

C

T

LT1768

V

FAULT

SHDN

R

MIN

R

MAX

PWM

V

IN

REF

LAMP

16.2k

U

33pF

LAMP

V

IN

8V – 24V

C1
33µF

5V

0.1µF

R4

R2

40.2k

R3

60.4k

33pF

250Ω
1/4W

T1

4

MBRS130T3

2200pF

610

53 2

100

C4

0.33µF

Q1

L1
68µH

Si3456DY

R5*

0.025

1

Lamp Output and Dimming

Ratio vs Lamp Current

10000

1000

Q1

1768 TA01

DIMMING RATIO (NITS/NITS)

100

10

1

0.1

LAMP MANUFACTURERS

SPECIFIED CURRENT RANGE

2

0

LAMP CURRENT (mA)

LAMP OUTPUT (NITS)

6

4

8

10

1768 TA01b

1

LT1768

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

Input Voltage (VIN Pin) ............................................ 28V

SHDN Pin Voltage.................................................... 28V

FAULT Pin Voltage ................................................... 28V

PROG Pin Voltage................................................... 5.5V

PWM Pin Voltage.................................................... 4.5V

CT Pin Voltage ........................................................ 4.5V

SENSE Pin Voltage .................................................... 1V

DIO1, DIO2 Input Current ................................... ±50mA

R

Pin Source Current..................................... 750µA

MAX

R

Pin Source Current ..................................... 750µA

MIN

V

Pin Source Current ....................................... 10mA

REF

Operating Junction Temperature Range

LT1768C................................................ 0°C to 125°C

LT1768I ............................................ –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering 10 sec)...................300°C

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

PGND

1

DI01

2

DI02

3

SENSE

4

VC

5

AGND

6

C

7

T

PROG

8

GN PACKAGE

16-LEAD PLASTIC SSOP

T

= 125°C, θJA = 100°C/W

JMAX

Consult LTC Marketing for parts specified with wider operating temperature ranges.

GATE

16

V

15

IN

V

14

REF

FAULT

13

SHDN

12

R

11

MIN

R

10

MAX

PWM

9

ORDER PART

NUMBER

LT1768CGN
LT1768IGN

GN PART

MARKING

1768
1768I

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T
I

= –100µA, unless otherwise specified.

RMIN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

Q

I

SHDN

V

REF

V

RMAX

V

RMIN

FSW Switching Frequency V

I

PROG

V

PROG

Supply Current 9V< V
Supply Current in Shutdown V
SHDN Pin Pull-Up Current V
SHDN Threshold Voltage V
SHDN Threshold Hysteresis ● 100 200 300 mV
VIN Undervoltage Lockout V
VIN Undervoltage Lockout V
REF Voltage I
REF Line Regulation ∆V
REF Load Regulation ∆I
R

Pin Voltage ● 1.225 1.25 1.275 V

MAX

R

Pin Voltage ● 1.22 1.26 1.30 V

MIN

Maximum Duty Cycle V
Minimum ON Time V
PROG Pin Input Bias Current V
PROG Pin Voltage for Zero Lamp Current (Note 2) ● 0.45 0.5 0.55 V

PROG Pin Voltage for Minimum Lamp Current (Note 3)
PROG Pin Voltage for Maximum Lamp Current (Note 4) ● 3.8 4 4.2 V

The ● denotes the specifications which apply over the full operating

= 25°C, V

A

= 12V, I

VIN

< 24V ● 78 mA

VIN

= 0V ● 65 100 µA

SHDN

= 0V ● 4712 µA

SHDN

Off to On ● 0.6 1.26 1.8 V

SHDN

Off to On ● 7.2 7.9 8.2 V

IN

On to Off ● 7.1 7.4 7.6 V

IN

= –1mA ● 4.9 5 5.1 V

REF

8V to 24V I

VIN

–1mA to –10mA ● 10 20 mV

REF

= 0.75V, V

PROG

= 0.75V, V

PROG

= 0.75V, V

PROG

= 5V ● 100 500 nA

PROG

DIO1/2

= 250µA, V

= –1mA ● 720 mV

REF

= 0V ● 300 350 410 kHz

SENSE

= 0V 93 %

SENSE

= 150mV 125 ns

SENSE

= 0V, V

PROG

● 0.9 1 1.1 V

PWM

= 2.5V, I

RMAX

= –100µA,

2

LT1768

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T
I

= –100µA, unless otherwise specified.

RMIN

The ● denotes the specifications which apply over the full operating

= 25°C, V

A

= 12V, I

VIN

DIO1/2

= 250µA, V

PROG

= 0V, V

PWM

= 2.5V, I

RMAX

= –100µA,

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

PWM

PWM Input Bias Current ● 0.6 4 µA
PWM Duty Cycle V

= 1.75 45 50 55 %

PROG

PWM Frequency CT = 0.22µF (Note 7) 90 110 130 Hz

V

DIO1/2

V

VCCLAMP

I

SENSE

V

SENSE

DIO1/2 Positive Voltage I
DIO1/2 Negative Voltage I

VC High Clamp Voltage V
VC Switching Threshold V

SENSE Input Bias Current V

= 14mA 1.7 1.9 V

DIO

= –14mA –1.1 –1.3 V

DIO

PROG
PROG

SENSE

SENSE Threshold for Current Limit VVC = V

VVC = V

I

DIO1/2

to I

Ratio V

RMAX

V

PROG

PROG

= 4.5V (Note 8) 3.6 3.7 3.9 V
= 4.5V (Note 8) 0.5 0.7 0.95 V

= 0V –25 –30 µA

, Duty Cycle <50%, V

VCCLAMP

, Duty Cycle 80%, V

VCCLAMP

= 1V 85 100 115 mV

PROG

= 1V 90 mV

PROG

= 4.5V (Note 5) ● 94 98 104 A/A
= 4.5V, I

DIO1

or I

DIO2

= 0, VVC = 2.5V,

(Note 5) 45 49 55 A/A

I

to I

DIO1/2

Ratio V

RMIN

< 0.75V (Note 6) ● 9 10 11 A/A

PROG

V

PROG

< 0.75V, I

DIO1

or I

DIO2

= 0, VVC = 2.5V,

(Note 6) 9 10 11 A/A

I

GATE

GATE Drive Peak Source Current 1.5 A
GATE Drive Peak Sink Current 1.5 A

GATE Drive Saturation Voltage V
GATE Drive Clamp Voltage V
GATE Drive Low Saturation Voltage I

= 12V, I

VIN

= 24V, I

VIN

= 100mA ● 0.4 0.6 V

GATE

= –100mA, V

GATE

= –10mA, V

GATE

= 4.5V ● 9.8 10.2 V

PROG

= 4.5V ● 12.5 14 V

PROG

Open LAMP Threshold (Note 9) 100 125 150 µA
FAULT Pin Saturation Voltage I
FAULT Pin Leakage Current V

= 1mA, I

FAULT

= 5V 20 100 nA

FAULT

DI01

, I

DI02

= 0µA, V

= 4.5V 0.2 0.3 V

PROG

Thermal ShutdownTemperature 160 °C

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: This is the threshold voltage where the lamp current switches
from zero current to minimum lamp current. For V
threshold voltage, lamp current will be at zero. For V

less than the

PROG

PROG

greater than the
threshold voltage, lamp current will be equal to the minimum lamp
current. Minimum lamp current is set by the value of the resistor from the

pin to ground. See Applications Information for more details.

R

MIN

Note 3: This is the threshold voltage where the device starts to pulse width
modulate the lamp current. For V
lamp current will be equal to the minimum lamp current. For V

less than the threshold voltage,

PROG

PROG

greater than the threshold voltage, lamp current will be pulse width
modulated between the minimum lamp current and some higher value.

MAX

pin

MIN

resistor

Minimum lamp current is set by the value of the resistor from the R
to ground. The higher value lamp current is a function of the R
to ground value, and the voltages on the PWM and PROG pins. See
Applications Information for more details.

Note 4: This is the threshold voltage where the lamp current reaches its
maximum value. For V
be no increase in lamp current. For V

greater than the threshold voltage, there will

PROG

less than the threshold voltage,

PROG

lamp current will be at some lower value. Maximum lamp current is set by

the value of the resistor from the R
lamp current is a function of the R
voltages on the PWM and PROG pins. See Applications Information for
more details.

Note 5: I
V

PROG

to I

DIO1/2

to 4.5V, VVC to 2.5V, and then ramping a DC current out of the

ratio is determined by setting I

RMAX

DIO1/2 pins from zero until the DC current in the VC voltage source
current equals zero. The I

)/I

I

DIO2

Note 6: I
V

PROG

. See Applications Information for more details.

RMAX

to I

DIO1/2

to 0.75V, VVC to 2.5V, and then ramping a DC current out of the

DIO1/2

ratio is determined by setting I

RMIN

DIO1/2 pins from zero until the DC current in the VC voltage source
current equals zero. The I

)/I

I

DIO2

. See Applications Information for more details.

RMIN

DIO1/2

Note 7: The PWM frequency is set by the equation PWMFREQ = 22Hz/

(µF).

C

T

Note 8: For VC voltages less than the switching threshold, GATE switching
is disabled.

Note 9: An open lamp will be detected if either I
the threshold current for at least 1 full PWM cycle.

pin to ground. The lower value

MAX

to I

to I

MIN

RMAX

RMIN

and R

resistors, and the

MAX

ratio is then defined as (I

ratio is then defined as (I

or I

DIO1

RMAX

to –100µA,

RMIN

DIO2

to –100µA,

DIO1

DIO1

is less than

+

+

3

LT1768

UW

TYPICAL PERFOR A CE CHARACTERISTICS

V

, V

V

vs Temperature

REF

5.10
I

= –1mA

REF

5.08

5.06

5.04

5.02

5.00

VOLTAGE (V)

4.98

REF

V

4.96

4.94

4.92

4.90

–50 –25 0 25

TEMPERATURE (°C)

50

Supply Current vs Input Voltage

10

8

6

4

SUPPLY CURRENT (mA)

2

0

05

10

15 20 25

INPUT VOLTAGE (V)

75

100 125

1768 G01

1768 G04

RMIN

1.30

I

= –100µA

RMIN

= –100µA

I

1.29

RMAX

1.28

1.27

1.26

1.25

1.24

VOLTAGE (V)

1.23

1.22

1.21

1.20

–50 –25 0 25

Supply Current vs Temperature

7.40

7.30

7.20

7.10

7.00

6.90

6.80

6.70

SUPPLY CURRENT (mA)

6.60

6.50

6.40

–50 –25 0 25

vs Temperature

RMAX

V

RMIN(V)

V

RMAX(V)

TEMPERATURE (°C)

TEMPERATURE (°C)

50

75

50

75

100 125

1768 G02

100 125

1768 G05

Supply Current in Shutdown vs
Temperature

80

V

= 0V

SHDN

76
72
68
64
60
56
52

SHUTDOWN CURRENT (µA)

48
44
40

–50 –25 0 25

TEMPERATURE (°C)

50

Supply Current in Shutdown vs
Input Voltage

100

V

= 0V

SHDN

80

60

40

SHUTDOWN CURRENT (µA)

20

0

05

10

INPUT VOLTAGE (V)

100 125

75

1768 G03

15 20 25

1768 G06

SHDN Pull-Up Current
vs Input Voltage

10

V

= 0V

SHDN

8

6

4

2

SHDN PULL-UP CURRENT (µA)

0

5

0

4

15

10

INPUT VOLTAGE (V)

Shutdown Threshold Voltage vs
Temperature

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

SHUTDOWN VOLTAGE (V)

0.40

0.20

20

25

1768 G07

0

–50 –25 0 25

V

OFF TO ON

SHDN

V

SHDN

TEMPERATURE (

ON TO OFF

50

°C)

75

100 125

1768 G08

Undervoltage Lockout Threshold
vs Temperature

8.20

8.10

8.00

7.90

7.80

7.70

7.60

7.50

7.40

UNDERVOLTAGE LOCKOUT (V)

7.30

7.20
–50 –25 0 25

V

OFF TO ON

UVL

V

ON TO OFF

UVL

50

TEMPERATURE (°C)

75

100 125

1768 G09

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Switching Frequency vs Temperature

400
390
380
370
360
350
340
330
320

SWITCHING FREQUENCY (kHz)

310
300

–50 –25 0 25

TEMPERATURE (°C)

50

75

100 125

1768 G10

PWM Frequency vs Temperature

124
120
116
112
108
104
100

96

PWM FREQUENCY (Hz)

92
88
84

–50 –25 0 25

TEMPERATURE (°C)

50

CT = 0.22µF
V

PWM

75

= 2.5V

100 125

1768 G11

FAULT Pin Saturation Voltage vs
Temperature

0.250

0.225

0.200

0.175

0.150

0.125

0.100

FAULT VOLTAGE (V)

0.75

0.50

0.25
0

–50 –25 0 25

TEMPERATURE (°C)

50

LT1768

I

= 0µA

DIO1

I

= 0µA

DIO2

= 1mA

I

FAULT

100 125

75

1768 G12

FAULT Pin Saturation Voltage vs
Current

450

I

= 0µA

DIO1

= 0µA

I

DIO2

400

350

300

250

200

FAULT VOLTAGE (mV)

150

100

0

0.5 1.0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

DIO VOLTAGE (V)

0.6

0.4

0.2
0

2468

DIO CURRENT (mA)

2.0 3.0 3.5

1.5 2.5

I

(mA)

FAULT

10

12

Sense Pin Bias Current vs
Temperature

50

V

= 0V

SENSE

45
40
35
30
25
20
15

SENSE CURRENT (µA)

10

5

1768 G13

0

–50 –25 0 25

TEMPERATURE (°C)

50

75

100 125

1768 G14

DIO Pin Voltage vs Current

–2.0

–1.8
–1.6
–1.4
–1.2
–1.0

–0.8

DIO VOLTAGE (V)

–0.6
–0.4
–0.2

0

14 16 18 200

1768 G24

–2 –4 –6 –8

–10

–12

DIO CURRENT (mA)

–14 –16 –18 –200

1768 G20

Maximum Gate Voltage vs
Temperature

15.00

I

= –10mA

GATE

14.50

14.00

13.50

13.00

12.50

12.00

11.50

GATE CLAMP VOLTAGE (V)

11.00

10.50

10.00

–50 –25 0 25

TEMPERATURE (°C)

VC Clamp Voltage vs CurrentDIO Pin Voltage vs Current

3.75

3.74

3.73

3.72

3.71

3.70

3.69

CLAMP VOLTAGE (V)

3.68

C

V

3.67

3.66

3.65
0 50 100 150

200

VC CURRENT (µA)

V

= 24V

IN

V

= 12V

IN

50

75

300 350 400 450 500

250

100 125

1768 G15

1768 G25

5

LT1768

UW

TYPICAL PERFOR A CE CHARACTERISTICS

VC Clamp Voltage vs Temperature

3.90
IVC = 500µA

3.85

3.80

3.75

3.70

(V)

3.65

C CLAMP

3.60

V

3.55

3.50

3.45

3.40

–50 –25 0 25

TEMPERATURE (°C)

50

75

PWM Pin Input Current vs
Temperature

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

PWM INPUT CURRENT (µA)

0.60

0.50

0.40
–50 –25 0 25

TEMPERATURE (°C)

50

V

75

PWM

100 125

1768 G26

= 2.5V

100 125

1768 G29

VC Switching Threshold
vs Temperature

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

SWITCH THRESHOLD VOLTAGE (V)

C

V

0.55

0.50
–50 –25 0 25

TEMPERATURE (°C)

50

Lamp Fault Current Threshold
vs Temperature

200
180
160
140
120
100

80
60
40
20

BULB FAULT CURRENT THRESHOLD (µA)

0

–50 –25 0 25

TEMPERATURE (°C)

50

75

75

100 125

1768 G27

100 125

1768 G31

PWM Pin Input Current
vs Voltage

25

20

15

10

PWM INPUT CURRENT (µA)

5

0

1

0

2

PWM VOLTAGE (V)

Maximum Sense Threshold
vs Gate Drive Duty Cycle

120
110
100

90
80
70
60
50

SENSE THRESHOLD (mV)

40
30
20

0 102030

40

50

GATE DUTY CYCLE (%)

3

4

1768 G28

60 70 80 90 100

1768 G32

5

110
108
106
104
102

RATIO (A/A)

100

RMAX

98

TO I

96

DI01/2

I

94
92
90

6

I

to I

DIO1/2

Current

V

= 4.5V

PROG

= 2.5V

V

VC

0 –60

RMAX

–120

I

RMAX

Ratio vs R

(µA)

MAX

–180 –240 –300

1768 G33

I

DIO1/2

to I

RMAX

Ratio vs R

Current with a Lamp Fault

60

V

= 4.5V

PROG

58

= 2.5V

V

VC

OR I

DI02

= 0µA

–120

I

RMAX

I

DI01

56
54
52

RATIO (A/A)

50

RMAX

48

TO I

46

DI01/2

I

44
42
40

0 –60

MAX

–180 –240 –300

(µA)

1768 G34

I

DIO1/2

Current

11.0

V

10.8

V

10.6

10.4

10.2

RATIO (A/A)

10.0

RMIN

9.8

TO I

9.6

DI01/2

I

9.4

9.2

9.0
0 –60

PROG
VC

to I

= 0.75V

= 2.5V

Ratio vs R

RMIN

–120

I

RMIN

MIN

–180 –240 –300

(µA)

1768 G35

UUU

PIN FUNCTIONS

LT1768

PGND (Pin 1): The PGND pin is the high current ground
path. High switching current transients and lamp current
flow through the PGND pin.

DIO1/DIO2 (Pins 3/2): Each DIO pin is the common
connection between the cathode and anode of two internal
diodes. The remaining terminals of the diodes are con­nected to PGND. In a typical application, the DIO1/2 pins
are connected to the low voltage side of the lamps.
Bidirectional lamp current flows into the DIO1/2 pins and
their diodes conduct alternately on the half cycles. The
diode that conducts on the negative cycle has a percentage
of its current diverted into the VC pin. This current nulls
against the programming current specified by the PROG
and PWM pins. A single capacitor on the VC pin provides
both stable loop compensation and an averaging function
to the half wave-rectified lamp current. The diode that
conducts on the positive cycle is used to detect open lamp
conditions. If the current in either of the DIO pins on the
positive cycle is less than 125µ A for a minimum of 1 PWM
cycle, then the FAULT pin will be activated and the maxi­mum source current into the VC pin will be reduced by
approximately 50%. If the current in both of the DIO pins
on the positive cycle is less than 125µ A, and the VC pin hits
its clamp value (indicating either an open lamp or lamp
lowside short to ground fault condition) for a minimum of
1 PWM cycle, the gate drive will be latched off. The latch
can be cleared by setting the PROG voltage to zero or
placing the LT1768 in shutdown mode.

SENSE (Pin 4): The SENSE pin is the input to the current
sense comparator. The threshold of the comparator is a
function of the voltage on the VC pin and the switch duty
cycle. The maximum threshold is set at 100mV for duty
cycle less than 50% which corresponds to approximately

3.7V on the VC pin. The SENSE pin has a bias current of
25µA, which flows out of the pin.

provides lamp current averaging and single pole loop
compensation.

AGND (Pin 6): The AGND pin is the low current analog
ground. It is the negative sense terminal for the internal
reference and current sense amplifier. Connect critical
external components that terminate to ground directly to
this pin for best performance.

CT (Pin 7): The value of capacitance on the CT pin deter-
mines the PWM modulation frequency. The transfer func­tion of capacitance to frequency equals 22Hz/CT(µ F). The
frequency present on the CT pin also determines the
maximum time allowed for lamp fault conditions. If the

current in either DIO1 or DIO2 is less than 125µA for a
minimum of 1 PWM period, the FAULT pin is activated and
the maximum allowable lamp current is reduced by ap­proximately 50%. If the current in both DIO1 and DIO2 is
absent for a minimum of 1 PWM period, and the VC pin is
clamped at 3.7V, the FAULT pin is activated and the gate
drive of the part is internally latched off. The latch can be
cleared by setting the PROG voltage to zero or placing the
LT1768 in shutdown mode.

PROG (Pin 8): The PROG pin controls the lamp current by
converting a DC input voltage range of 0V to 5V to source
current into the VC pin. The transfer function from pro­gramming voltage to VC current is illustrated in the follow­ing table.

PROG (V) VC SOURCE CURRENT (µA)
V

< 0.5 0

PROG

0.5 < V

1.0 < V

V

PROG

*PWM Duty Cycle = [1 – (V

< 1.0 I

PROG

< V

PROG

PWM

V

> V

CT

PROG

V

< V

CT

PROG

> 4.0 5 • I

RMIN

PWM Mode*

– V

PWM

RMAX

PROG

)/(V

I

RMIN

5 • I

• ( V

RMAX

– 1V)] • 100%

PWM

PWM

– 1V)/ 3V

VC (Pin 5): The VC pin is the summing junction for the
programming current and the half wave rectified lamp
current and is also an input to the current sense compara­tor . A fraction of the voltage on the VC pin is compared to
the voltage on the SENSE pin (switch current) for switch
turnoff. During normal operation the VC pin sits between

0.7V (zero switch current) and 3.7V (maximum switch
current). A single capacitor between VC and AGND

PWM (Pin 9): The PWM pin controls the percentage of the
PROG range between 1V and 4V that is to be pulse width
modulated. The percentage is defined by [(V

PWM

-1)/ 3] •
100%. The minimum and maximum percentages are 25%
(1.75V) and 100% (4V) respectively. Taking the PWM pin
above the 4V maximum will cause significant PWM input
current to flow. (See PWM Input Current vs Voltage curve
in Typical Performance Characteristics).

7

LT1768

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PIN FUNCTIONS

R

(Pin 10): The R

MAX

of 1.25V that is to be loaded with an external resistor. The
current through the external resistor sets the maximum
lamp current. Maximum lamp current in a dual lamp
application will be approximately equal to 100 times I
when the voltage on the PROG pin is greater than 4V. The
value of R
[R

R

• 2.5 • (V

RMIN

(Pin 11): The R

MIN

must be greater than 5K and less than

RMAX

PWM–1

1.26V that is to be loaded with an external resistor. The
current through the external resistor sets the minimum
lamp current. Minimum lamp current in a dual lamp
application will be approximately 10 times the value of
I

when the voltage on the PROG pin is between 0.5V

RMIN

and 1V. To set the minimum current to zero (I
for maximum dimming range, connect the R
V

pin. The value of R

REG

connected to V
R

/[0.4 • (V

RMAX

REG
PWM–1

SHDN (Pin 12): The SHDN pin controls the operation of
the LT1768. Pulling the SHDN pin above 1.26V or leaving
the pin open will result in normal operation of the LT1768.
Pulling the SHDN pin below 1V causes a complete shut­down of the LT1768 which results in a typical quiescent
current of 65µ A. The SHDN pin has an internal 7µ A pull-up
source to VIN and 200mV of voltage hysteresis.

pin outputs a regulated voltage

MAX

RMAX

/3)] for proper PWM operation.

pin outputs a regulated voltage of

MIN

= 0µ A)

RMIN

pin to the

MIN

RMIN

(R

= ∞ when R

RMIN

MIN

is

) must be greater than the value of

)/3] for proper PWM operation.

FAULT (Pin 13): The FAULT pin is an open collector output
with a sink capability of 1mA that is activated when lamp
current falls below 125µ A in either DIO1 or DIO2 for at least
1 full PWM cycle.

V

(Pin 14): The V

REF

pin is a regulated 5V output that is

REF

derived from the VIN pin. The regulated voltage provides up
to 10mA of current to power external circuitry. During
undervoltage lockout, shutdown mode or thermal
shutdown, drive to the V

pin will be disabled.

REF

VIN (Pin 15): The VIN pin is the voltage supply pin for the
LT1768. For normal operation, the VIN pin must be above an
undervoltage lockout of 7.9V and below a maximum of 24V.

GATE (Pin 16): The GATE pin is the output of a NPN high
current output stage used to drive the gate of an external
MOSFET. It has a dynamic source and sink capability of

1.5A. During normal operation, the GATE pin is driven high
at the beginning of each oscillator period and then low
when the appropriate current in the switch is reached. The
GATE pin has a minimum on time of 125ns and a maximum
duty cycle of 93% at a frequency of 350kHz. For input
voltages less than 13V the gate will be driven to within 2V
of VIN. For input voltages greater than 13V the gate pin high
level will be clamped at a typical voltage of 12.5V.

8

BLOCK DIAGRA

LT1768

W

SHDN

V

R

R

MAX

PROG

PWM

V

15

IN

12

14

REF

11

MIN

10

8

9

C

7

T

V

UNDERVOLTAGE

LOCKOUT

THERMAL

SHUTDOWN

1.26V

I

RMAX

1.25V
0

PWM PERIOD

REF

1V 4V

I

RMIN

V

1V

PWM

OSC

CONTROLMODE

I

VC

V

CCLAMP

FAULT

MULTI-MODE

DIMMING BLOCK

16

1768 BD

GATE

SENSE

4

PGND

1

13

FAULT

V

GATE

IN

SW

BLANK

S

Q

R

SLOPE

(I

+ I

)

DIO1

DIO2

GAIN

I

VC

5

VC

6

AGND

3

DI01 DIO2

I

< 125µA

DIO1

I

< 125µA

DIO2

2

Figure 2. LT1768 Block Diagram

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APPLICATIONS INFORMATION

INTRODUCTION

The current trend in desktop monitor design is to migrate
the LCD (liquid crystal display) technology used in laptops
and instruments to the popular desktop display sizes. As
LCD size increases uniform backlighting requires mul­tiple high power lamps. In addition, the lamps must have
a dimming range and lifetime expectancy comparable to
previous generations of desktop displays. Cold cathode
fluorescent lamps (CCFLs) provide the highest available
efficiency for backlighting LCD displays. The CCFL re­quires a high voltage supply for operation. Typically, over
1000 volts is required to initiate CCFL operation, with
sustaining voltages from 200V to 800V. A CCFL can
operate from DC, but migration effects damage the CCFL
and shorten its lifetime. To achieve maximum life CCFL
drive should be sinusoidal, contain zero DC component,
and not exceed the CCFL manufacturers minimum and
maximum operating current ratings. Low crest factor

sinusoidal CCFL drive also maximizes current to light
conversion, reduces display flicker, and minimizes EMI
and RF emissions. The LT1768 high power CCFL control­ler, with its Multimode Dimming, provides the necessary
lamp drive to enable a wide dimming range while main­taining lamp lifetime in multiple lamp CCFL applications.

BASIC OPERATION

Referring to the circuit in Figure 1, CCFL current is con­trolled by a DC voltage on the PROG pin of the LT1768. The
DC voltage on the PROG pin feeds the LT1768’s Multimode
Dimming block and is converted to source current into the
VC pin. As the VC pin voltage rises, the LT1768’s GATE pin
is pulse width modulated at 350kHz. The GATE pulse width
is determined on a cycle by cycle basis by the voltage on
the SENSE pin (L1’s current multiplied by SENSE resistor
R5) exceeding a predetermined voltage set by the VC pin.

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APPLICATIONS INFORMATION

The current mode pulse width modulation produces an
average current in inductor L1 proportional to the VC
voltage. Inductor L1 then acts as a switched mode current
source for a current driven Royer class converter with
efficiencies as high as 90%. T1, C4 and Q1 comprise the
Royer class converter which provides the CCFLs with a
zero DC, 60kHz sinusoidal waveform whose amplitude is
based on the average current in L1. Sinusoidal current
from both CCFLs is then returned to the LT1768 through
the DIO1/2 pins. A fraction of the CCFL current from the
negative half of its sine wave pulls against the internal
current source at the VC pin closing the loop. A single
capacitor on the VC pin provides loop compensation and
CCFL current averaging, which results in constant CCFL
current. Varying the value of the internal current source via
the Multimode Dimming block varies the CCFL current and
resultant CCFL light intensity.

Multimode Dimming

Previous backlighting solutions have used a traditional
error amplifier in the control loop to regulate lamp current.
The approach converted AC current into a DC voltage for
the input of the error amplifier. This approach used several
time constants in order to provide stable loop compensa­tion. This compensation scheme meant that the loop had
to be fairly slow and that the output overshoot with start­up or load conditions had to be carefully evaluated in terms
of transformer stress and breakdown voltage require­ments. In addition, intensity control schemes were limited
to linear or PWM control. Linear intensity control schemes
provide the highest efficiency backlight circuits but either
limit dimming range, or violate lamp minimum or maxi­mum CCFL current specifications to achieve wide dim­ming ratios. PWM control schemes offer wide dimming
range but produce waveforms that may degrade CCFL life,
and waste power at higher CCFL currents. The LT1768’s
Multimode Dimming eliminates the error amplifier con­cept entirely and combines the best of both control schemes
to extend CCFL life while providing the widest possible
dimming range.

The error amplifier is eliminated by summing the current
out of the Multimode Dimming block with a fraction of
feedback lamp current to form the control loop. This
topology reduces the number of time constants in the

control loop by combining the error signal conversion
scheme and frequency compensation into a single capaci­tor (VC pin). The control loop thus exhibits the response
of a single pole system, allows for faster loop transient
response and minimizes overshoot under start-up or
overload conditions.

Referring to Figure 2, the source current into the VC pin
from the Multimode Dimming block (and resultant CCFL
current) has five distinct modes of operation. Which mode
is in use is determined by the voltages on the PROG and
PWM pins, and the currents that flow out of the R
R

pins.

MIN

Off Mode (V
zero, actively pulls VC to ground, and inhibits the GATE pin
from switching which results in zero lamp current.

Minimum current mode (0.5V < V
source current equal to the current out of the 1.26V
referenced R
determines the dimming range of the display. Setting
R

to produce the manufacturer’s minimum specified

RMIN

CCFL current guarantees the maximum CCFL lifetime for
all PROG voltages, but limits the dimming range. Setting
R

to produce currents less than the manufacturer’s

RMIN

minimum specified CCFL current increases dimming range,
but places restrictions on the PROG voltage for normal
operation in order to maximize lifetime. To achieve the
maximum dimming ratio possible, I
zero by connecting the R

For example, the circuit in Figure 1 produces a dimming
ratio of 100:1 at 1mA of lamp current, but sets the
minimum CCFL current to zero (R
V

). In this case, the PROG voltage must be kept above

REF

1.12V to limit the CCFL current to 1mA (1mA is only a
typical minimum lamp current used for illustration, con­sult lamp specifications for actual minimum allowable
value) during normal operation in order to meet CCFL
specifications to maximize lifetime. It should be noted that
taking the PROG voltage in Figure 1 down to 1V (0mA
CCFL current) enables dimming ratios greater than 500:1,
but violates minimum CCFL current specifications in most
lamps and is not recommended. Alternatively, discon­necting R
R

MIN

MIN

to AGND in Figure 1 sets the minimum CCFL current

< 0.5V), sets the VC source current to

PROG

< 1V) sets the VC

PROG

pin. The minimum VC source current

MIN

should be set to

RMIN

from V

pin to the V

MIN

MIN

and adding a 10kΩ resistor from

REF

pin.

REF

is connected to

MAX

and

10

LT1768

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APPLICATIONS INFORMATION

per lamp to 1mA for all PROG voltages but limits the
dimming ratio to 6:1.

Trace B in Figures 3a and 3b shows Figure 1’s CCFL
current waveform operating at 1mA in PWM mode.

Maximum current mode (V
current to five times the current out of the 1.25V refer­enced R

pin. Setting R

MAX

equal to the manufacturer’s maximum rating in this mode
insures no degradation in the specified lamp lifetime. For
example, setting R4 in the circuit in Figure 1 to 16.2k sets
the maximum CCFL current to 9mA (9mA is only a typical
maximum lamp current used for illustration, consult lamp
specifications for the actual value). Trace A in Figure 3a
and 3b shows Figure 1’s CCFL current waveform operating
at 9mA in maximum current mode.

TRACE A

= 4.5V

V

PROG

I

= 9mA

LAMP

V

I

LAMP

I

LAMP

V

I

LAMP

In linear mode (V

RMS

TRACE B

= 1.125V

PROG

= 1mA

RMS

Figure 3a. CCFL Current for Circuit in Figure 1

TRACE A

= 4.5V

V

PROG

= 9mA

RMS

TRACE B

= 1.125V

PROG

= 1mA

RMS

Figure 3b. CCFL Current for Circuit in Figure 1

< V

PWM

PROG

controlled linearly with the voltage on the PROG pin. The
equation for the VC source current in linear mode is
IVC = (V

– 1V)/3V (I

PROG

RMAX

light conversion and highest efficiency, V
set to make the LT1768 normally operate in the linear

> 4V) sets the VC source

PROG

to produce CCFL current

RMAX

1ms/DIV

100µs/DIV

< 4V), VC source current is

• 5). For the best current to
should be

PWM

mode. For example, in the circuit in Figure 1, linear mode
runs from V
equal to (3mA)(V

In PWM Mode (1V < V

PROG

= 3V to V

–1V)/1V.

PROG

< V

PROG

= 4V with lamp current

PROG

), the VC source current

PWM

is modulated between the value set by minimum current
mode and the value for IVC in linear mode with V
V

. The PWM frequency is equal to 22Hz/CT(µF) with

PWM

PROG

=

its duty cycle set by the voltages on the PROG and PWM
pins and follows the equation:

DC = [1 – (V

PWM

– V

PROG

)/(V

– 1V)] • 100%

PWM

The LT1768’s PWM mode enables wide dimming ratios
while reducing the high crest factor found in PWM only
dimming solutions. In the example of Figure 1, PWM
mode runs from V

PROG

= 1V to V

= 3V with CCFL

PROG

current modulated between 0mA and 6mA. The PWM
modulation frequency is set to 220Hz by capacitor C3.

When combined, these five modes of operation allow
creation of a DC controlled CCFL current profile that can be
tailored to each particular display. With linear mode CCFL
current control over the most widely used current range,
and PWM mode at the low end, the LT1768 enables wide
dimming ratios while maximizing CCFL lifetimes.

Lamp Feedback Current

In a typical application, the DIO1/2 pins are connected to
the low voltage side of the lamps. Each DIO pin is the
common connection between the cathode and anode of
two internal diodes (see Block Diagram). The remaining
terminals of the diodes are connected to PGND. Bidirec­tional lamp current flows into the DIO1/2 pins and their
diodes conduct alternately on the half cycles. The diode
that conducts on the negative cycle has a percentage of its
current diverted into the VC pin. This current nulls against
the VC source current specified by the Multimode Dim­ming section. A single capacitor on the VC pin provides
both stable loop compensation and an averaging function
to the halfwave-rectified lamp current. Therefore, current
into the VC pin from the lamp current programming
section relates to

average

lamp current.

The overall gain from the resistor current to average lamp
current is equal to the gain from the Multimode Dimming
block divided by the gain from the DIO pin to the VC pin,

11

LT1768

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APPLICATIONS INFORMATION

and is dependant on the operating mode. For dual lamp
displays, the transfer function for minimum current mode
(I

DIO/IRMIN

mode (I
The transfer functions discussed above are between R

and R
current. Due to the differences between the average and
RMS functions, the actual overall transfer function be­tween actual lamp current and R
empirically determined, and is dependant on the particular
lamp/display housing combination used. For example, in
the circuit of Figure 1 setting R

16.8Ω, sets the minimum and maximum RMS lamp
currents for the example display to 1mA and 9mA per lamp
respectively. Figure 4 shows the lamp current vs program­ming voltage for the circuit in Figure 1.

I

CCFL

Choosing R

The value for R
V

PROG

maximum allowable current specified by the lamp manu­facturer.

The voltage for the PWM pin should then be set so that the
LT1768 normally operates in linear mode. A typical value
for V
region to 50% of the V

The value for R
the minimum manufacturer specified lamp current or
enable a wide dimming range. If a minimum specified
current is desired, the V

) is equal to 10A/A, and for maximum current

DIO/IRMAX

current and average lamp current

MIN

9mA

6mA

(mA)

0mA

Figure 4. Lamp Current vs PROG Voltage for
the Circuit in Figure 1

to 4.5V then adjusting R

is approximately 2.5V, which limits the PWM

PWM

) is equal to 100A/A.

MIN

CURRENT

PWM

(FREQ = 220Hz)

0%

OFF

1.00.5

V

PROG

and R

RMAX

RMAX

RMIN

RMIN

should be determined by setting

PROG

should be chosen to either produce

PROG

not

RMS lamp

current must be

to 10kΩ and R

MAX

CURRENTLINEAR

5.04.03V (V

1768 F04

PWM

to produce the

RMAX

RMIN

100%

(V)

and V

MIN/RMAX

PWM)

input voltage range.

should be set to 0.75V and

MAX

RMAX

to

R

adjusted to produce the specified current. If a wide

RMIN

dimming range is desired, V
and R

adjusted to produce the required dimming

RMIN

ratio. Care must be taken when adjusting R

should be set to 0.75V

PROG

RMIN

to pro­duce extreme dimming ratios. The minimum lamp current
set by R

must be able to fully illuminate the lamp or

RMIN

thermometering (uneven illumination) will occur. If the
desired dimming ratio can’t be achieved by adjusting
R

, the minimum lamp current can be set to zero by

RMIN

connecting the R

pin to the V

MIN

pin. If the minimum

REF

current is set to less than the open lamp threshold current
(approximately 125µ A), the FAULT pin will be activated for
PROG voltages between 0.5V and 1V.

The values chosen for R

RMAX

and R

are extremely

RMIN

critical in determining the lifetime of the display. It is
imperative that proper measurement techniques, such as
those cited in the references, be used when determining
R

RMAX

and R

RMIN

values.

Lamp Fault Modes and Single Lamp Operation

The DIO pin diodes that conduct on the positive cycle are
used to detect open lamp fault conditions. If the current
in either of the DIO pins on the positive half cycle is less
than 125µA due to either an open lamp or lamp lowside
short to ground, for a minimum of 1 PWM cycle, then the
FAULT pin will be activated and the lamp programming
current into the VC pin in high level PWM mode, linear
mode, and maximum current mode, will be reduced by
approximately 50%. Halving the VC source current will cut
the total lamp current to approximately one half of its
programmed value. This function insures that the maxi­mum lamp current level set by R

will not be exceeded

RMAX

even under fault conditions. If the current in both of the
DIO pins on the positive cycle is less than 125µ A, and the
VC pin hits its clamp value (indicating an open lamp or
lamp lowside short to ground fault condition) for a mini­mum of 1 PWM cycle, the gate drive will be latched off. The
latch can be cleared by setting the PROG voltage to zero or
placing the LT1768 in shutdown mode.

Since open lamp fault conditions produce high voltage AC
waveforms, it is imperative that proper layout spacings
between the high voltage and DIO lines be observed.
Coupling capacitance as low as 0.5pF between the high

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LT1768

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APPLICATIONS INFORMATION

voltage and DIO lines can cause enough current flow to
fool the open lamp detection. In situations where coupling
can’t be avoided, resistors can be added from the DIO pins
to ground to increase the open lamp threshold. When
resistors from the DIO pins to ground are added, the
values for R
from their nominal values to compensate for the additional
current.

For single lamp operation, the lowside of the lamp should
be connected to both DIO pins, and the values of R
and R

increased to two times the values that would be

RMIN

used in a dual lamp configuration. In single lamp mode all
fault detection will operate as in the dual lamp configura­tion, but the open lamp threshold will double. If the
increase in the open lamp threshold is not acceptable, a
positive offset current can be added to reduce the open
lamp threshold by placing a resistor between the REF and
DIO pins (a 33k resistor will reduce the open lamp thresh­old by approximately 100µA ((V
an offset current is added, the values for R
may need to be increased from their nominal values to
compensate for the offset current.

VC Compensation

As previously mentioned a single capacitor on the VC pin
combines the error signal conversion, lamp current aver­aging and frequency compensation. Careful consideration
should be given to the value of capacitance used. A large
value (1µF) will give excellent stability at high lamp cur-
rents but will result in degraded line regulation in PWM
mode. On the other hand , a small value (10nF) will give
excellent PWM response but might result in overshoot and
poor load regulation. The value chosen will depend on the
maximum load current and dimming range. After these
parameters are decided upon, the value of the VC capacitor
should be increased until the line regulation becomes
unacceptable. A typical value for the VC capacitor is

0.033µF. For further information on compensation please
refer to the references or consult the factory.

Current Sense Comparator

RMAX

and R

may need to be increased

RMIN

–

+

V

REF

)/33k). When

DIO

RMAX

and R

RMAX

RMIN

start of every oscillator cycle. The GATE is driven back low
when the current reaches a threshold level proportional to
the voltage on the VC pin. The GATE then remains low until
the start of the next oscillator cycle. The peak current is
thus proportional to the VC voltage and controlled on a
cycle by cycle basis. The peak switch current is normally
sensed by placing a sense resistor in the source lead of the
output MOSFET. This resistor converts the switch current
to a voltage that can be compared to a fraction of the VC
voltage [(V

VC

– V

)/30] . For normal conditions and a

DIODE

GATE duty cycle below 50%, the switch current limit will
correspond to IPK = 0.1/R

. For GATE duty cycles

SENSE

above 50% the switch current limit will be reduced
to approximately 90mV at 80% duty cycle to avoid
subharmonic oscillations associated with current mode
controllers.

When the lamp current is programmed to PWM mode, the
VC pin will slew between voltages that represent the
minimum and maximum PWM lamp currents. The slew
time affects the line regulation at low duty cycle, and
should be kept low by making the sense resistor as small
as possible. The lowest value of sense resistor is deter­mined by switching transients and other noise due to
layout configurations. A good rule of thumb is to set the
sense resistor so that the voltage on the VC pin equals

2.5V when the PWM current is in maximum mode (V
= V

). Typical values of the sense resistor run in the

PWM

PROG

25mΩ to 50mΩ range for large displays, and can be
implemented with a copper trace on the PCB.

Since the maximum threshold at the SENSE pin is only
100mV, switching transients and other noise can prema­turely trip the comparator. The LT1768 has a blanking
period of 100ns which prohibits premature switch turn
off, but further filtering the sense resistor voltage is
recommended. A simple RC filter is adequate for most
applications. (Figure 5.)

GATE

LT1768

SENSE

2.2nF

100Ω

0.025mΩ

The LT1768 is a current mode PWM controller. Under
normal operating conditions the GATE is driven high at the

1768 •F05

Figure 5. Sense Pin Filter

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APPLICATIONS INFORMATION

GATE

The LT1768 has a single high current totem pole output
stage. This output stage is capable of driving up to ±1.5A
of output current. Cross-conduction current spikes in the
totem pole output have been eliminated. The GATE pin is
intended to drive an N-channel MOSFET switch. Rise and
fall times are typically 50ns with a 3000pF load. A clamp
is built into the device to prevent the GATE pin from rising
above 13V in order to protect the gate of the MOSFET
switch.

The GATE pin connects directly to the emitter of the upper
NPN drive transistor and the collector of the lower NPN
drive transistor in the totem pole. The collector of the lower
transistor, which is N-type silicon, forms a P-N junction
with the substrate of the device. This junction is reversed
biased during normal operation.

In some applications the parasitic LC of the external
MOSFET gate can ring and pull the GATE pin below
ground. If the GATE pin is pulled negative by more than a
diode drop the parasitic diode formed by the collector of
the GATE NPN and the substrate will turn on. This can
cause erratic operation of the device. In these cases a
Schottky clamp diode is recommended from the GATE pin
to ground. (Figure 6.)

BAT 85

LT1768

PGND

Figure 6. Schottky Gate Clamp

GATE

1768 • G06

up current source. The LT1768 thermal shutdown tem­perature is set at 160°C. A buffered version of the internal
5V is present at the V

pin and is capable of supplying up

REF

to 10mA of current. Note that using any substantial
amount of current from the V

pin will increase power

REF

dissipation in the device, which will reduce the useful
operating ambient temperature range.

Supply and Input Voltage Sequencing

For most applications, where the SHDN pin is left floating,
and the voltages on the PWM and PROG pins are derived
from the V

pin, the LT1768 will power-up and power-

REF

down correctly when the voltage to the VIN pin is applied
and removed. In applications where the voltage inputs for
the VIN pin, SHDN pin, PWM pin, and the PROG pin
originate from different sources (power supply, micropro­cessors etc.), care must be taken during power up/down
sequences. For proper operation during the power-up
sequence, the voltage on the following pins must be taken
from zero to their appropriate values in the following
order; VIN pin, SHDN pin, PWM pin and PROG pin. For
proper operation during the power-down sequence, the
order must be reversed. For example, in the circuit of
Figure 1 where the SHDN pin is left floating, and the PWM
pin voltage is derived from a resistor divider to the V

REF

pin, the proper power-up sequence would be to take the
VIN pin from zero to its value then apply either a voltage or
PWM signal to the PROG pin. The power-down sequence
for the circuit in Figure 1 would be to take the PROG pin
voltage to zero, then take the VIN pin voltage to zero.If the
PROG voltage in the circuit of Figure 1 is present before the
VIN supply voltage, proper power supply sequecing can be
achieved by implementing the circuit shown in Figure 7.

Reference

The internal reference of the LT1768 is a trimmed bandgap
reference. The reference is used to power the majority of
the LT1768 internal circuitry. The reference is inactive if
the LT1768 is in undervoltage lockout, shutdown mode, or
thermal shutdown. The undervoltage lockout is active
when VIN is below 7.9V and the LT1768 is in shutdown
mode when the voltage on the SHDN pin is pulled below
1V. The SHDN pin has 200mV of hysteresis and a 7µ A pull-

14

V

IN

LT1768

0 TO 5V

OR

1kHz PWM

Figure 7. Circuit Insures Proper Supply Sequencing When
Dimming Voltage Exists Before Main Power Supply

VN2222LL

10k

49.9k
PROG

10µF

1768 F07

LT1768

U

WUU

APPLICATIONS INFORMATION

Supply Bypass and Layout Considerations

Proper supply bypassing and layout techniques must be
used to insure proper regulation, avoid display flicker, and
insure long term reliability.

Figure 8 shows the application’s critical high current paths
in thick lines. Ideally, all components in the high current
path should be placed as close as possible and connected
with short thick traces. The most critical consideration is
that T1’s center tap, the Schottky diode D1, LT1768’s V
pin, and a low ESR capacitor (C1) be connected directly

T1

V

IN

C2

*OPTIONAL

L1

D1

LT1768

GATE

V

IN

C1

BOLD LINES INDICATE
HIGH CURRENT PATHS

SENSE

PGND

Figure 8

IN

1768 F08

together with minimum trace between them. If space
constraints prohibit the transformer T1 placement next to
C1, local bypassing (C2) for the center tap of transformer
T1 should be used.

Special attention is also required for the layout of the high
voltage section to avoid any unpleasant surprises. Please
refer to the references for an extensive discussion on high
voltage layout techniques.

Applications Support

Linear Technology invests an enormous amount of time,
resources, and technical expertise in understanding, de­signing and evaluating backlight solutions for systems
designers. The design of an efficient and compact back­light system is a study of compromise in a transduced
electronic system. Every aspect of the design is interre­lated and any design change requires complete re-evalu­ation for all other critical design parameters. Linear
Technology has engineered one of the most complete test
and evaluation setups for backlight designs and under­stands the issues and trade-offs in achieving a compact,
efficient and economical customer solution. Linear Tech­nology welcomes the opportunity to discuss, design,
evaluate, and optimize any backlight system with a cus­tomer. For further information on backlight designs, con­sult the references below.

References

1. Williams, Jim. November 1995. A Fourth Generation of
LCD Backlight Technology. Linear Technology Corpora­tion, Application Note 65.

15

LT1768

TYPICAL APPLICATIONS

U

DC Intensity Control

V

R1

100k

POT

REF

PROG

LT1768

AGND

PWM Intensity Control

1768 TA04

V

REF

PROG

LT1768

AGND

1768 TA05

0 – >5V

1kHz PWM

R1

49.9k

C1
10µF

PWM Intensity Control From 3.3V or 5V Logic

V

REF

0 – >3.3V

OR 0 – >5V

1kHz PWM

R1
10k

Q1
VN2222LL

R1

49.9k
R

ID

C1
10µF

PROG

LT1768

AGND

1768 TA06

16

U

TYPICAL APPLICATIONS

LT1768

2-Wire Serial interface Intensity Control

LTC1663

V

CC

V

OUT

V

REF

PROG

AGND

LT1768

1768 TA08

SCL

SDA

GND

Pushbutton Intensity Control

R1

50k

S1

C1
10µF

V

REF

PROG

AGND

LT1768

CLK1 SHDN

LTC1426

V

CC

V

REF

R1

49.9k

S2

CLK2

AGND

PWM2 PWM1

1768 TA07

17

LT1768

1768 TA10

C8, 0.22µF

CTX110607

R6

499Ω

R9

0.0125Ω

Q1A

ZDT1048

Q1B

ZDT1048

L2

22µH

L1

22µH

T1

C12, 22pF

X1

R7

499Ω

C5

0.1µF

C1

33µF

Q2

Si3456DV

D2

MBRS130LT3

LAMP

D4

BAT54

R3

69.8k

R1

49.9k

R2

30.1k

R5

125k

R11

1k

R4

11.3k

C3

0.1µF

C4

10µF

C2

0.047µF

V

IN

= 12V

PROG

0V TO 5V OR

1kHz PWM

C6

1µF

LT1768

DI02

PGND GATE

VCAGND

CTPROG

DI01

SENSE

SHDN

R

MIN

R

MAX

PWM

FAULT

SHUTDOWN

FAULT

V

REF

V

IN

5V

15

161

12

11

10

9

14

13

5

6

7

8

4

3

2

C13, 22pF

X2

LAMP

C14, 22pF

X3

LAMP

C15, 22pF

X4

LAMP

C7

2200pF

R8

100Ω

C9, 0.22µF

CTX110607

T2

C10, 0.22µF

CTX110607

T3

C11, 0.22µF

CTX110607

T4

D3

BAT54

R10

1k

TYPICAL APPLICATIONS

U

24 Watt Four Lamp CCFL Supply

18

PACKAGE DESCRIPTIO

U

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

16

15

0.189 – 0.196*
(4.801 – 4.978)

12 11 10

14

13

LT1768

0.009

(0.229)

9

REF

0.015

± 0.004

(0.38 ± 0.10)

0.007 – 0.0098
(0.178 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0° – 8° TYP

× 45°

0.229 – 0.244

(5.817 – 6.198)

0.053 – 0.068

(1.351 – 1.727)

0.008 – 0.012

(0.203 – 0.305)

12

3

4

5

678

0.0250

(0.635)

0.150 – 0.157**
(3.810 – 3.988)

0.004 – 0.0098

(0.102 – 0.249)

BSC

GN16 (SSOP) 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LT1768

TYPICAL APPLICATION

VIN = 9V TO 24V

0V TO 5V OR

1kHz PWM

PROG

C1
33µF

C2

0.047µF

C3

0.22µF

R1

49.9k

PGND GATE

2

DI02

3

DI01

4

SENSE

5

V

6

AGND

7

C

8

PROG

C4
10µF

C

T

U

LT1768

4 Watt Single Lamp CCFL Supply

161

15

V

IN

V

REF

FAULT

SHDN

R

MIN

R

MAX

PWM

14

13

12

11

10

31.6k

9

FAULT

SHUTDOWN

R4

C6
1µF

5V

C5

0.1µF

R5

124k

R2

39.2k

R3

61.9k

R7

499Ω

X1

LAMP

T1

CTX110607

D2

MBRS130LT3

C8
1000pF

C9

33pF

Q1A
ZDT1048

R2

100Ω

C7

0.33µF

Q1B

ZDT1048

L1
33µH

Q2
Si3456DV

R6

0.05Ω

1768 TA09

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1170 Current Mode Switching Regulator 5.0A, 100kHz
LT1182/LT1183 CCFL/LCD Contrast Switching Regulators 3V ≤ VIN ≤ 30V, CCFL Switch: 1.25A, LCD Switch: 625mA,

Open Lamp Protection, Positive or Negative Contrast
LT1184 CCFL Current Mode Switching Regulator 1.25A, 200kHz
LT1186 CCFL Current Mode Switching Regulator 1.25A, 100kHz, SMBus Interface
LT1372 500kHz, 1.5A Switching Regulator Small 4.7µH Inductor, Only 0.5 Square Inch of PCB
LT1373 250kHz, 1.5A Switching Regulator 1mA IQ at 250kHz, Regulates Positive or Negative Outputs
LT1786F SMBus Controlled CCFL Switching Regulator Precision 100µA Full Scale Current DAC

sn1768 1768fs LT/TP 0901 2K • PRINTED IN USA

 LINEAR TE CHNOLOGY CORPORATION 2000

20

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

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