Peak Switch Current Rating Maintained Over
Full Duty Cycle Range
■
Low Effective Supply Current: 2.5mA
■
Low Shutdown Current: 25µA
■
1.2V Feedback Reference Voltage (LT1766)
■
5V Fixed Output (LT1766-5)
■
Easily Synchronizable
■
Cycle-by-Cycle Current Limiting
■
Small 16-Pin SSOP and Thermally Enhanced
TSSOP Packages
U
APPLICATIO S
■
High Voltage, Industrial and Automotive
■
Portable Computers
■
Battery-Powered Systems
■
Battery Chargers
■
Distributed Power Systems
®
The LT
1766/LT1766-5 are 200kHz monolithic buck
switching regulators that accept input voltages up to 60V.
A high efficiency 1.5A, 0.2Ω switch is included on the die
along with all the necessary oscillator, control and logic circuitry. A current mode control architecture delivers fast
transient response and excellent loop stability.
Special design techniques and a new high voltage process
achieve high efficiency over a wide input range. Efficiency
is maintained over a wide output current range by using the
output to bias the circuitry and by utilizing a supply boost
capacitor to saturate the power switch. Patented circuitry*
maintains peak switch current over the full duty cycle range.
A shutdown pin reduces supply current to 25µA and the
device can be externally synchronized from 228kHz to
700kHz with logic level inputs.
The LT1766/LT1766-5 are available in a 16-pin fused-lead
SSOP package or a TSSOP package with exposed backside
for improved thermal performance.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. *Protected by U.S. Patents
including 6498466, 6531909
TYPICAL APPLICATIO
5V Buck Converter
6
V
IN
5.5V*
TO 60V
*
2.2µF†
100V
CERAMIC
ONOFF
FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY
†
TDK C4532X7R2A225K
1, 8, 9, 16
4
15
14
V
IN
SHDN
SYNC
GND
0.022µF
BOOST
LT1766
BIAS
2.2k
U
1N4148W
0.33µF
2
SW
10
12
FB
V
C
11
220pF
1766 TA01
47µH
10MQ060N
15.4k
4.99k
+
V
OUT
5V
1A
100µF 10V
SOLID
TANTALUM
Efficiency vs Load Current
1766fb
1
LT1766/LT1766-5
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
Input Voltage (VIN) ................................................. 60V
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
(LT1766E/LT1766I GRADE)
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
= 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.
V
IN
PARAMETERCONDITIONSMINTYPMAXUNITS
Reference Voltage (V
SENSE Voltage (LT1766-5)5.5V ≤ VIN ≤ 60V4.9455.06V
SENSE Pin Resistance (LT1766-5)9.513.819kΩ
FB Input Bias Current (LT1766)
) (LT1766)5.5V ≤ VIN ≤ 60V1.2041.2191.234V
REF
VOL + 0.2 ≤ VC ≤ VOH – 0.2
VOL + 0.2V ≤ VC ≤ VOH – 0.2V
●
1.1951.243V
●
4.905.10V
●
–0.5–1.5µA
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2
LT1766/LT1766-5
ELECTRICAL CHARACTERISTICS
(LT1766E/LT1766I GRADE)
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
= 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.
V
IN
PARAMETERCONDITIONSMINTYPMAXUNITS
Error Amp Voltage Gain(Notes 2, 9)200400V/V
Error Amp g
VC to Switch g
m
m
EA Source CurrentFB = 1V or V
EA Sink CurrentFB = 1.4V or V
VC Switching ThresholdDuty Cycle = 00.9V
VC High ClampSHDN = 1V2.1V
Switch Current LimitVC Open, Boost = VIN + 5V, FB = 1V or V
Switch On ResistanceISW = 1.5A, Boost = VIN + 5V (Note 7)0.20.3Ω
Maximum Switch Duty CycleFB = 1V or V
Switch FrequencyVC Set to Give DC = 50%184200216kHz
SYNC Frequency Range228700kHz
SYNC Input Resistance20kΩ
SENSE
= 4.1V
●
0.7523A
●
●
90%
●
135200228kHz
●
●
●
●
●
●
●
●
●
●
0.050.15%/V
2.32.422.68V
0.150.370.9V
0.250.450.9V
0.8Ω
4.65.5V
1.83V
1240mA
45100mA
500µA
1.52.2V
Note 1: Absolute Maximum Ratings are those values beyond which the life of a
device may be impaired.
Note 2: Gain is measured with a V
swing equal to 200mV above the low clamp
C
level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed by
other tests. It is defined as the voltage where internal bias lines are still regulated
so that the reference voltage and oscillator remain constant. Actual minimum
input voltage to maintain a regulated output will depend upon output voltage and
load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 5: Boost current is the current flowing into the BOOST pin with the pin held
5V above input voltage. It flows only during switch on time.
Note 6: Input supply current is the quiescent current drawn by the input pin when
the BIAS pin is held at 5V with switching disabled. Bias supply current is the
current drawn by the BIAS pin when the BIAS pin is held at 5V. Total input
referred supply current is calculated by summing input supply current (I
a fraction of bias supply current (I
I
= I
+ (I
With V
TOTAL
IN
VIN
= 15V, V
OUT
)(V
BIAS
= 5V, I
OUT/VIN
Note 7: Switch on resistance is calculated by dividing V
BIAS
= 1.4mA, I
VIN
):
)
= 2.9mA, I
BIAS
= 2.4mA.
TOTAL
to SW voltage by the
IN
VIN
) with
4
forced current. See Typical Performance Characteristics for the graph of switch
voltage at other currents.
Note 8: The LT1766EGN, LT1766EGN-5, LT1766EFE and LT1766EFE-5 are
guaranteed to meet performance specifications from 0°C to 125°C junction
temperature. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation with
statistical process controls. The LT1766IGN, LT1766IGN-5, LT1766IFE and
LT1766IFE-5 are guaranteed over the full
–40°C to 125°C operating junction temperature range. The LT1766HGN and
LT1766HFE are guaranteed over the full –40°C to 140°C operating junction
temperature range.
Note 9: Transconductance and voltage gain refer to the internal amplifier exclusive
of the voltage divider. To calculate gain and transconductance, refer to the SENSE
pin on fixed voltage parts. Divide the values shown by the ratio V
OUT
/1.219.
Note 10: This IC includes overtemperature protection that is intended to protect
the device during momentary overload conditions. Junction temperature will
exceed 140°C when overtemperature protection is active. Continuous operation
above the specified maximum operating junction temperature may impair device
reliability.
Note 11: High junction temperatures degrade operating lifetimes. Operating
lifetime at junction temperatures between 125°C and 140°C is derated to 1000
hours.
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JUNCTION TEMPERATURE (°C)
–50
250
200
150
100
12
6
0
2575
1766 G03
–25 0
50100150125
CURRENT (µA)
CURRENT REQUIRED TO FORCE SHUTDOWN
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW µA
AT 2.38V STANDBY THRESHOLD
(CURRENT FLOWS OUT OF PIN)
SHUTDOWN VOLTAGE (V)
0
0
INPUT SUPPLY CURRENT (µA)
50
100
150
200
250
300
0.10.20.30.4
1766 G06
0.5
VIN = 60V
V
IN
= 15V
TA = 25°C
TYPICAL PERFOR A CE CHARACTERISTICS
LT1766/LT1766-5
Switch Peak Current LimitSHDN Pin Bias Current
2.5
TA = 25°C
2.0
1.5
SWITCH PEAK CURRENT (A)
1.0
2040
TYPICAL
GUARANTEED MINIMUM
6080
DUTY CYCLE (%)
1000
1766 G01
FB Pin Voltage and Current
1.234
1.229
1.224
1.219
1.214
FEEDBACK VOLTAGE (V)
1.209
1.204
–50
–25 0
2575
JUNCTION TEMPERATURE (°C)
VOLTAGE
CURRENT
50100 125 150
1766 G02
2.0
1.5
CURRENT (µA)
1.0
0.5
0
Lockout and Shutdown
ThresholdsShutdown Supply Current
GND (Pins 1, 8, 9, 16, 17): The GND pin connections act
as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the
same voltage as the GND pins of the IC. This condition will
occur when load current or other currents flow through
metal paths between the GND pins and the load ground.
Keep the paths between the GND pins and the load ground
short and use a ground plane when possible. The GND pin
also acts as a heat sink and should be soldered to a large
copper plane to reduce thermal resistance. For the FE
package, the exposed pad should be soldered to the
6
UU
copper ground plane underneath the device. (See Applications Information—Layout Considerations.)
SW (Pin 2): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
switch pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum
negative switch voltage allowed is –0.8V.
NC (Pins 3, 5, 7, 13): No Connection.
1766fb
LT1766/LT1766-5
U
UU
PI FU CTIO S
VIN (Pin 4): This is the collector of the on-chip power NPN
switch. V
voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the VCE voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and voltage loss approximates that of a 0.2Ω FET structure, but with much smaller die area.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its
operating current from the output voltage rather than the
input supply. This architecture increases efficiency especially when the input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is 3V.
V
(Pin 11) The VC pin is the output of the error amplifier
C
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 0.9V for light loads and 2.1V at maximum load. It
can be driven to ground to shut off the regulator, but if
driven high, current must be limited to 4mA.
powers the internal control circuitry when a
IN
FB/SENSE (Pin 12): The feedback pin is used to set the
output voltage using an external voltage divider that generates 1.22V at the pin for the desired output voltage. The
5V fixed output voltage parts have the divider included on
the chip and the FB pin is used as a SENSE pin, connected
directly to the 5V output. Three additional functions are
performed by the FB pin. When the pin voltage drops
below 0.6V, switch current limit is reduced and the external SYNC function is disabled. Below 0.8V, switching
frequency is also reduced. See Feedback Pin Functions in
Applications Information for details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
10% and 90% duty cycle. The synchronizing range is
equal to initial operating frequency up to 700kHz. See
Synchronizing in Applications Information for details.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input drain current to a few
microamperes. This pin has two thresholds: one at 2.38V
to disable switching and a second at 0.4V to force complete micropower shutdown. The 2.38V threshold functions as an accurate undervoltage lockout (UVLO);
sometimes used to prevent the regulator from delivering
power until the input voltage has reached a predetermined
level.
If the SHDN pin functions are not required, the pin can
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.
W
BLOCK DIAGRA
The LT1766 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the R
When switch current reaches a level set by the inverting
flip-flop to turn the switch on.
S
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
1766fb
7
LT1766/LT1766-5
BLOCK DIAGRA
W
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
Most of the circuitry of the LT1766 operates from an
internal 2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage higher than 3V, bias
power will be drawn from the external source (typically the
V
4
IN
BIAS
SYNC
COMPARATOR
10
14
SHUTDOWN
2.9V BIAS
REGULATOR
+
0.4V
–
INTERNAL
V
CC
SLOPE COMP
ANTISLOPE COMP
200kHz
OSCILLATOR
Σ
regulated output voltage). This will improve efficiency if
the BIAS pin voltage is lower than regulator input voltage.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external
capacitor and diode. Two comparators are connected to
the shutdown pin. One has a 2.38V threshold for undervoltage lockout and the second has a 0.4V threshold for
complete shutdown.
R
LIMIT
–
+
CURRENT
COMPARATOR
BOOST
6
S
FLIP-FLOP
R
R
S
DRIVER
CIRCUITRY
R
SENSE
Q1
POWER
SWITCH
SHDN
5.5µA
2.38V
+
–
LOCKOUT
COMPARATOR
V
C(MAX)
CLAMP
FREQUENCY
FOLDBACK
×1
Q2
FOLDBACK
Q3
CURRENT
LIMIT
CLAMP
11
V
C
AMPLIFIER
= 2000µMho
g
m
ERROR
–
+
1.22V
15
2
12
1766 F01
SW
FB
GND
1, 8, 9, 16, 17
Figure 1. LT1766 Block Diagram
1766fb
8
WUUU
APPLICATIO S I FOR ATIO
LT1766/LT1766-5
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1766 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The 5V fixed output voltage part (LT1766-5) has
internal divider resistors and the FB pin is renamed SENSE,
connected directly to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
RV
2122
()
R
1
=
Table 1
OUTPUTR1% ERROR AT OUTPUT
VOLTAGER2(NEAREST 1%)DUE TO DISCREET 1%
(V)(k
34.997.32+ 0.32
3.34.998.45– 0.43
54.9915.4– 0.30
64.7518.7+ 0.38
84.4724.9+ 0.20
104.3230.9– 0.54
124.1236.5+ 0.24
154.1246.4– 0.27
OUT
.
−
.
122
Ω
)(k
Ω
)RESISTOR STEPS
More Than Just Voltage Feedback
The feedback pin is used for more than just output
voltage sensing. It also reduces switching frequency and
current limit when output voltage is very low (see the
Frequency Foldback graph in Typical Performance Characteristics). This is done to control power dissipation in
both the IC and in the external diode and inductor during
short-circuit conditions. A shorted output requires the
switching regulator to operate at very low duty cycles,
and the average current through the diode and inductor
is equal to the short-circuit current limit of the switch
(typically 2A for the LT1766, folding back to less than
1A). Minimum switch on time limitations would prevent
the switcher from attaining a sufficiently low duty cycle
if switching frequency were maintained at 200kHz, so
frequency is reduced by about 5:1 when the feedback pin
voltage drops below 0.8V (see Frequency Foldback graph).
This does not affect operation with normal load conditions; one simply sees a gear shift in switching frequency
during start-up as the output voltage rises.
In addition to lower switching frequency, the LT1766 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs this
function by clamping the VC pin to a voltage less than its
normal 2.1V upper clamp level. This
foldback current limit
greatly reduces power dissipation in the IC, diode and inductor during short-circuit conditions. External synchronization is also disabled to prevent interference with foldback operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
affected are current source loads which maintain full load
current with output voltage less than 50% of final value. In
these rare situations the feedback pin can be clamped above
0.6V with an external diode to defeat foldback current limit.
Caution:
clamping the feedback pin means that frequency
shifting will also be defeated, so a combination of high input voltage and dead shorted output may cause the LT1766
to lose control of current limit.
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 1.4kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 115µA out of the FB pin with 0.44V on the pin (R≤ 3.8k).
The net result is that reductions in frequency and
DIV
current limit are affected by output voltage divider impedance. Although divider impedance is not critical, caution
1766fb
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