查询LT1765EFE供应商
FEATURES
■
3A Switch in a Thermally Enhanced 16-Lead
TSSOP or 8-Lead SO Package
■
Constant 1.25MHz Switching Frequency
■
Wide Operating Voltage Range: 3V to 25V
■
High Efficiency 0.09Ω Switch
■
1.2V Feedback Reference Voltage
■
Uses Low Profile Surface Mount Components
■
Low Shutdown Current: 15µA
■
Synchronizable to 2MHz
■
Current Mode Loop Control
■
Constant Maximum Switch Current Rating at
All Duty Cycles*
■
Available in 8-Lead SO and 16-Lead Thermally
Enhanced TSSOP Packages
U
APPLICATIO S
■
DSL Modems
■
Portable Computers
■
Regulated Wall Adapters
■
Battery-Powered Systems
■
Distributed Power
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
Monolithic 3A, 1.25MHz
Step-Down Switching Regulator
U
DESCRIPTIO
The LT®1765 is a 1.25MHz monolithic buck switching
regulator. A high efficiency 3A, 0.09Ω switch is included
on the die together with all the control circuitry required
to construct a high frequency, current mode switching
regulator. Current mode control provides fast transient
response and excellent loop stability.
New design techniques achieve high efficiency at high
switching frequencies over a wide operating voltage range.
A low dropout internal regulator maintains consistent
performance over a wide range of inputs from 24V
systems to Li-Ion batteries. An operating supply current
of 1mA improves efficiency, especially at lower output
currents. Shutdown reduces quiescent current to 15µA.
Maximum switch current remains constant at all duty
cycles. Synchronization allows an external logic level
signal to increase the internal oscillator into the range of
1.6MHz to 2MHz.
Full cycle-by-cycle current control and thermal shutdown
are provided. High frequency operation allows the reduction of input and output filtering components and permits
the use of chip inductors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
* Patent Pending
TYPICAL APPLICATIO
INPUT
5V
2.2µF
CERAMIC
ONOFF
V
IN
SYNC
BOOST
LT1765-3.3
GND
U
Efficiency vs Load Current5V to 3.3V Step-Down Converter
CMDSH-3
0.18µF
V
SW
FBSHDN
V
C
2.2nF
1.5µH
UPS120
OUTPUT
3.3V
2.5A
4.7µF
CERAMIC
1765 TA01
90
85
80
EFFICIENCY (%)
75
70
0
0.5
1.0
SWITCH CURRENT (A)
VIN = 10V
V
OUT
1.5
= 5V
2.0
1765 • TAO1a
1765fb
1
LT1765/LT1765-1.8/LT1765-2.5/
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
BOOST
V
IN
V
IN
SW
SW
NC
GND
GND
NC
SYNC
V
C
FB
SHDN
NC
GND
17
LT1765-3.3/LT1765-5
WW
W
ABSOLUTE AXI U RATI GS
U
(Note 1)
Input Voltage .......................................................... 25V
BOOST Pin Above SW ............................................ 20V
Max BOOST Pin Voltage .......................................... 35V
SHDN Pin ............................................................... 25V
FB Pin Current ....................................................... 1mA
UUW
PACKAGE/ORDER I FOR ATIO
ORDER PART
TOP VIEW
BOOST
1
V
2
IN
SW
3
GND
4
S8 PACKAGE
8-LEAD PLASTIC SO
T
= 125°C, θJA = 90°C/W,
JMAX
θ
JC(PIN 4)
GROUND PIN CONNECTED TO
LARGE COPPER AREA
= 30°C/W
8
SYNC
V
7
C
FB
6
SHDN
5
NUMBER
LT1765ES8
S8 PART
MARKING
1765
SYNC Pin Current .................................................. 1mA
Operating Junction Temperature Range
(Note 2) ........................................... – 40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
LT1765EFE
LT1765EFE-1.8
LT1765EFE-2.5
LT1765EFE-3.3
LT1765EFE-5
FE PART MARKING
1765EFE
θJA = 45°C/W, θ
EXPOSED PAD (PIN 17) SOLDERED TO LARGE
COPPER PLANE
JC(PAD)
= 10°C/W
1765EFE18
1765EFE25
1765EFE33
1765EFE-5
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Maximum Switch Current Limit 346 A
Oscillator Frequency 3.3V < VIN < 25V ● 1.1 1.25 1.6 MHz
Switch On Voltage Drop I = 3A ● 270 430 mV
VIN Undervoltage Lockout (Note 3) ● 2.47 2.6 2.73 V
VIN Supply Current ● 1 1.3 mA
Shutdown Supply Current V
Feedback Voltage 3V < VIN < 25V, 0.4V < VC < 0.9V LT1765 (Adj) 1.182 1.2 1.218 V
2
= 0V, VIN = 25V, VSW = 0V 15 35 µA
SHDN
(Note 3)
LT1765-1.8 ● 1.764 1.8 1.836 V
LT1765-2.5 ● 2.45 2.5 2.55 V
LT1765-3.3 ● 3.234 3.3 3.366 V
LT1765-5 ● 4.9 5 5.1 V
● 55 µA
● 1.176 1.224 V
1765fb
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
= 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
V
IN
PARAMETER CONDITIONS MIN TYP MAX UNITS
FB Input Current LT1765 (Adj) ● – 0.25 – 0.5 µA
FB Input Resistance LT1765 ● 10.5 15 21 kΩ
LT1765-1.8
LT1765-3.3
LT1765-5
FB Error Amp Voltage Gain 0.4V < VC < 0.9V 150 350
FB Error Amp Transconductance ∆IVC = ±10µA ● 500 850 1300 µMho
VC Pin Source Current VFB = V
VC Pin Sink Current VFB = V
VC Pin to Switch Current Transconductance 5 A/V
VC Pin Minimum Switching Threshold Duty Cycle = 0% 0.4 V
VC Pin 3A ISW Threshold 0.9 V
Maximum Switch Duty Cycle VC = 1.2V, ISW = 800mA, VIN = 6V 85 90 %
Minimum Boost Voltage Above Switch ISW = 3A ● 1.8 2.7 V
Boost Current ISW = 1A (Note 4) ● 20 30 mA
I
SW
SHDN Threshold Voltage ● 1.27 1.33 1.40 V
SHDN Threshold Current Hysteresis ● 4710 µA
SHDN Input Current (Shutting Down) SHDN = 60mV Above Threshold ● –7 –10 –13 µA
SYNC Threshold Voltage 1.5 2.2 V
SYNC Input Frequency 1.6 2 MHz
SYNC Pin Resistance I
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1765E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls.
SYNC
– 17% ● 80 120 160 µA
NOM
+ 17% ● 70 110 180 µA
NOM
= 3A (Note 4) ● 70 140 mA
= 1mA 20 kΩ
Note 3: Minimum input voltage is defined as the voltage where the internal
regulator enters lockout. Actual minimum input voltage to maintain a
regulated output will depend on output voltage and load current. See
Applications Information.
Note 4: Current flows into the BOOST pin only during the on period of the
switch cycle.
● 14.7 21 30 kΩ
● 19 27.5 39 kΩ
● 29 42 60 kΩ
● 80 %
1765fb
3
LT1765/LT1765-1.8/LT1765-2.5/
VIN (V)
0 5 10 15 20 25 30
V
IN
CURRENT (µA)
1765 G05
7
6
5
4
3
2
1
0
SHDN = 0V
LT1765-3.3/LT1765-5
UW
TYPICAL PERFOR A CE CHARACTERISTICS
FB vs Temperature (Adj)
1.220
1.215
1.210
1.205
1.200
1.195
FB VOLTAGE (V)
1.190
1.185
1.180
–50
050
–25 25 75 125
TEMPERATURE (°C)
SHDN Threshold vs Temperature
1.40
1.38
1.36
1.34
SHDN THRESHOLD (V)
1.32
100
1765 G01
350
300
250
200
150
100
SWITCH VOLTAGE (mV)
50
0
0
SWITCH CURRENT (A)
Oscillator FrequencySwitch On Voltage Drop
1.50
TA = 125°C
TA = –40°C
TA = 25°C
1
23
1765 G02
1.45
1.40
1.35
1.30
1.25
FREQUENCY (MHz)
1.20
1.15
1.10
–25 0 25 50 75 100 125
–50
TEMPERATURE (°C)
SHDN Supply Current vs V
1765 G03
IN
1.30
–50
–25 0 25 50 75 100 125
TEMPERATURE (°C)
1765 G04
SHDN IP Current vs Temperature
–12
–10
–8
–6
–4
SHDN INPUT (µA)
–2
0
–50
SHUTTING DOWN
STARTING UP
–25 0 25 50 75 100 125
TEMPERATURE (°C)
1765 G06
1765fb
4
LT1765/LT1765-1.8/LT1765-2.5/
1765 G11
INPUT VOLTAGE (V)
0 5 10 15 20 25
OUTPUT CURRENT (A)
3.0
2.8
2.6
2.4
2.2
2.0
L = 4.7µH
L = 2.2µH
L = 1.5µH
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Input Voltage for
2.5V Out
3.5
3.3
3.1
2.9
INPUT VOLTAGE (V)
2.7
SHDN Supply Current
300
VIN = 15V
250
200
150
CURRENT (µA)
IN
100
V
50
LT1765-3.3/LT1765-5
Input Supply Current
1200
1000
800
600
CURRENT (µA)
IN
400
V
200
UNDERVOLTAGE
LOCKOUT
2.5
0.001 0.01
SWITCH PEAK CURRENT (A)
LOAD CURRENT (A)
0.1 1
Current Limit Foldback
4
3
SWITCH CURRENT
2
1
FB CURRENT
0
0 0.2
0.4 0.6 0.8 1 1.2
FEEDBACK VOLTAGE (V)
1765 G07
0
0
0.2 0.4 0.6 0.8 1 1.2 1.4
SHUTDOWN VOLTAGE (V)
40
FB INPUT CURRENT (µA)
30
20
10
0
1765 G10
Maximum Load Current,
V
= 2.5V
OUT
3.0
0
0 5 10 15 20 25 30
1765 G08
Maximum Load Current,
V
= 5V
OUT
INPUT VOLTAGE (V)
1765 G09
2.8
2.6
OUTPUT CURRENT (A)
2.4
2.2
05
INPUT VOLTAGE (V)
L = 4.7µH
L = 2.2µH
L = 1.5µH
10 15 20 25
1765 G12
1765fb
5
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
U
UU
PI FU CTIO S
FB: The feedback pin is used to set output voltage using
an external voltage divider (adjustable version) that generates 1.2V at the pin when connected to the desired
output voltage. The fixed voltage 1.8V, 2.5V, 3.3V and 5V
versions have the divider network included internally and
the FB pin is connected directly to the output. If required,
the current limit can be reduced during start up or shortcircuit when the FB pin is below 0.5V (see the Current Limit
Foldback graph in the Typical Performance Characteristics section). An impedance of less than 5kΩ on the
adjustable version at the FB pin is needed for this feature
to operate.
BOOST: The BOOST pin is used to provide a drive voltage,
higher than the input voltage, to the internal bipolar NPN
power switch.
VIN: This is the collector of the on-chip power NPN switch.
This pin powers the internal circuitry and internal regulator. At NPN switch on and off, high di/dt edges occur on
this pin. Keep the external bypass capacitor and catch
diode close to this pin. All trace inductance on this path will
create a voltage spike at switch off, adding to the V
voltage across the internal NPN. Both VIN pins of the
TSSOP package must be shorted together on the PC
board.
GND: The GND pin acts as the reference for the regulated
output, so load regulation will suffer if the “ground” end of
the load is not at the same voltage as the GND pin of the
IC. This condition will occur when load current or other
currents flow through metal paths between the GND pin
and the load ground point. Keep the ground path short
between the GND pin and the load and use a ground plane
when possible. Keep the path between the input bypass
and the GND pin short. The exposed GND pad and/or GND
pins of the package are directly attached to the internal tab.
These pins/pad should be attached to a large copper area
to reduce thermal resistance.
CE
VSW: The switch pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the switch
pin negative during switch off time. Negative voltage must
be clamped with an external catch diode with a V
Both V
together on the PC board.
SYNC: The sync pin is used to synchronize the internal
oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 20% and
80% duty cycle. The synchronizing range is from 1.6MHz
to 2MHz. See Synchronization section in Applications
Information for details. When not in use, this pin should be
grounded.
SHDN: The shutdown pin is used to turn off the regulator
and to reduce input drain current to a few microamperes.
The 1.33V threshold can function as an accurate undervoltage lockout (UVLO), preventing the regulator from
operating until the input voltage has reached a predetermined level. Float or pull high to put the regulator in the
operating mode.
VC: The VC pin is the output of the error amplifier and the
input of the peak switch current comparator. It is normally
used for frequency compensation, but can do double duty
as a current clamp or control loop override. This pin sits
at about 0.4V for very light loads and 0.9V at maximum
load. It can be driven to ground to shut off the output.
pins of the TSSOP package must be shorted
SW
<0.8V.
BR
6
1765fb
BLOCK DIAGRA
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
W
The LT1765 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
INPUT
2.5V BIAS
REGULATOR
INTERNAL
V
CC
0.005Ω
+
–
CURRENT
SENSE
AMPLIFIER
VOLTAGE GAIN = 40
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing the switch to be saturated.
This boosted voltage is generated with an external capacitor and diode. A comparator connected to the shutdown
pin disables the internal regulator, reducing supply
current.
SYNC
SHDN
SHUTDOWN
COMPARATOR
SLOPE COMP
1.25MHz
OSCILLATOR
7µA
–
+
Σ
0.4V
+
–
CURRENT
COMPARATOR
S
FLIP-FLOP
R
R
S
DRIVER
CIRCUITRY
PARASITIC DIODES
DO NOT FORWARD BIAS
–
1.33V
+
3µA
INTERNAL
V
CC
V
C
AMPLIFIER
= 850µMho
g
m
ERROR
1.2V
BOOST
Q1
POWER
SWITCH
V
SW
FB
GND
1765 F01
Figure 1. Block Diagram
1765fb
7
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
WUUU
APPLICATIO S I FOR ATIO
FB RESISTOR NETWORK
If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required,
the respective fixed option part, -1.8, -2.5, -3.3 or -5,
should be used. The FB pin is tied directly to the output; the
necessary resistive divider is already included on the part.
For other voltage outputs, the adjustable part should be
used and an external resistor divider added. The suggested resistor (R2) from FB to ground is 10k. This
reduces the contribution of FB input bias current to output
voltage to less than 0.25%. The formula for the resistor
(R1) from V
R
1
12 2025=µ
LT1765 (ADJ)
VCGND
to FB is:
OUT
RV
212
(–.)
OUT
RA
.– (. )
ERROR
AMPLIFIER
Figure 2. Feedback Network
1.2V
+
–
V
SW
OUTPUT
FB
R1
+
R2
10k
1765 F02
INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple at the input of LT1765 and to force the switching
current into a tight local loop, thereby minimizing EMI. The
RMS ripple current can be calculated from:
IIVVVV
RIPPLE RMS
= −
()
OUT OUT IN OUT IN
()
2
/
Ceramic capacitors are ideal for input bypassing. At higher
switching frequency, the energy storage requirement of
the input capacitor is reduced so values in the range of 1µF
to 4.7µF are suitable for most applications. Their high
frequency capacitive nature removes most ripple current
rating and turn-on surge problems. Y5V or similar type
ceramics can be used since the absolute value of capacitance is less important and has no significant effect on
loop stability. If operation is required close to the minimum input required by the output or the LT1765, a larger
value may be required. This is to prevent excessive ripple
causing dips below the minimum operating voltage resulting in erratic operation.
If tantalum capacitors are used, values in the 22µF to 470µF
range are generally needed to minimize ESR and meet
ripple current and surge ratings. Care should be taken to
ensure the ripple and surge ratings are not exceeded. The
AVX TPS and Kemet T495 series tantalum capacitors are
surge rated. AVX recommends derating capacitor operating voltage by 2:1 for high surge applications.
OUTPUT CAPACITOR
Unlike the input capacitor, RMS ripple current in the
output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is
triangular, with an RMS value given by:
I
RIPPLE RMS
()
029.
VVV
()
=
OUT IN OUT
LfV
()()( )
−
()
IN
The LT1765 will operate with both ceramic and tantalum
output capacitors. Ceramic capacitors are generally chosen for their small size, very low ESR (effective series
resistance), and good high frequency operation. Ceramic
output capacitors in the 1µF to 10µF range, X7R or X5R
type are recommended.
Tantalum capacitors are usually chosen for their bulk
capacitance properties, useful in high transient load applications. ESR rather than absolute value defines output
ripple at 1.25MHz. Typical LT1765 applications require a
tantalum capacitor with less than 0.3Ω ESR at 22µF to
500µF, see Table 2. This ESR provides a useful zero in the
frequency response. Ceramic output capacitors with low
ESR usually require a larger VC capacitor or an additional
series R to compensate for this.
8
1765fb
WUUU
I
VVV
LfV
P
OUT IN OUT
IN
–
()(– )
()()( )2
()
()
APPLICATIO S I FOR ATIO
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
Table 2. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E Case Size ESR (Max, Ω) Ripple Current (A)
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
AVX TAJ 0.7 to 0.9 0.4
D Case Size
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
C Case Size
AVX TPS 0.2 (typ) 0.5 (typ)
Figure 3 shows a comparison of output ripple for a ceramic
and tantalum capacitor at 200mA ripple current.
V
USING 47µF, 0.1Ω
OUT
TANTALUM CAPACITOR
(10mV/DIV)
V
USING 2.2µF
OUT
CERAMIC CAPACITOR
(10mV/DIV)
V
SW
(5V/DIV)
I
OUT MAX
=
()
Continuous Mode
For VIN = 8V, V
I
OUT MAX()
= 5V and L = 3.3µH,
OUT
58 5
3
= −
2 3 3 10 1 25 10 8
()()
= − =
3 0 23 2 77
..
−
.• . •
66
A
−
()
Note that the worst case (minimum output current available) condition is at the maximum input voltage. For the
same circuit at 15V, maximum output current would be
only 2.6A.
Inductor Selection
The output inductor should have a saturation current
rating greater than the peak inductor current set by the
current comparator of the LT1765. The peak inductor
current will depend on the output current, input and output
voltages and the inductor value:
0.2µs/DIV
Figure 3. Output Ripple Voltage Waveform
1765 F03
INDUCTOR CHOICE AND MAXIMUM OUTPUT
CURRENT
Maximum output current for an LT1765 buck converter is
equal to the maximum switch rating (IP) minus one half
peak to peak inductor ripple current. The LT1765 maintains
a constant switch current rating at all duty cycles. (Patent
Pending)
For most applications, the output inductor will be in the
1µH to 10µH range. Lower values are chosen to reduce the
physical size of the inductor, higher values allow higher
output currents due to reduced peak to peak ripple current.
The following formula gives maximum output current for
continuous mode operation, implying that the peak to
peak ripple (2x the term on the right) is less than the
maximum switch current.
II
=+
PEAK OUT
VVV
OUT IN OUT
2
−
()
LfV
()()( )
IN
VIN = Maximum input voltage
f = Switching frequency, 1.25MHz
If an inductor with a peak current lower than the maximum
switch current of the LT1765 is chosen a soft-start circuit
in Figure 10 should be used. Also, short-circuit conditions
should not be allowed because the inductor may saturate
resulting in excessive power dissipation.
Also, consideration should be given to the resistance of
the inductor. Inductor conduction loses are directly proportional to the DC resistance of inductor. Sometime, the
manufacturers will also provide maximum current rating
based on the allowable losses in the inductor. Care should
be taken, however. At high input voltages and low DCR,
excessive switch current could flow during shorted output
condition.
Suitable inductors are available from Coilcraft, Coiltronics,
Dale, Sumida, Toko, Murata, Panasonic and other
manufacturers.
1765fb
9
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
WUUU
APPLICATIO S I FOR ATIO
Table 3
VALUE I
PART NUMBER (µH) (Amps) (Ω) (mm)
Coiltcraft
DO1608C-222 2.2 2.4 0.07 2.9
Sumida
CDRH3D16-1R5 1.5 1.6 0.043 1.8
CDRH4D18-1R0 1.0 1.7 0.035 2.0
CDC5D23-2R2 2.2 2.2 0.03 2.5
CR43-1R4 1.4 2.5 0.056 3.5
CDRH5D28-2R6 2.6 2.6 0.013 3.0
Toko
(D62F)847FY-2R4M 2.4 2.5 0.037 2.7
(D73LF)817FY-2R2M 2.2 2.7 0.03 3.0
RMS
DCR HEIGHT
CATCH DIODE
The diode D1 conducts current only during switch off time.
Peak reverse voltage is equal to regulator input voltage.
Average forward current in normal operation can be calculated from:
supply is used. The boost diode can be connected to the
input, although, care must be taken to prevent the 2x V
IN
boost voltage from exceeding the BOOST pin absolute
maximum rating. The additional voltage across the switch
driver also increases power loss, reducing efficiency. If
available, an independent supply can be used with a local
bypass capacitor.
A 0.18µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitable, but the ESR should be <1Ω to ensure it can be
fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
700ns on-time, 90mA boost current, and 0.7V discharge
ripple. This value is then guard banded by 2x for secondary
factors such as capacitor tolerance, ESR and temperature
effects. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve
circuit operation or efficiency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start up operation.
IVV
I
D AVG
()
OUT IN OUT
=
−
()
V
IN
The only reason to consider a larger than 3A diode is the
worst-case condition of a high input voltage and shorted
output. With a shorted condition, diode current will increase to a typical value of 4A, determined by peak switch
current limit of the LT1765. A higher forward voltage will
also limit switch current. This is safe for short periods of
time, but it would be prudent to check with the diode
manufacturer if continuous operation under these conditions must be tolerated.
BOOST PIN
For most applications, the boost components are a 0.18µF
capacitor and a CMDSH-3 diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately V
above VIN to drive the output
OUT
stage. The output driver requires at least 2.7V of headroom throughout the on period to keep the switch fully
saturated. However, the output stage discharges the boost
capacitor during this on time. If the output voltage is less
than 3.3V, it is recommended that an alternate boost
SHUTDOWN AND UNDERVOLTAGE LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1765. Typically, UVLO is used in situations where
the input supply is
current limited
, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
LT1765
V
INPUT
C1
3µA
7µA
1.33V
GND
IN
R1
SHDN
R2
Figure 4. Undervoltage Lockout
SW
V
CC
OUTPUT
+
1765 F04
1765fb
10
WUUU
APPLICATIO S I FOR ATIO
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
An internal comparator will force the part into shutdown
below the minimum VIN of 2.6V. This feature can be used
to prevent excessive discharge of battery-operated systems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3µA internal current
source defaults the open pin condition to be operating (see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
VV
−
HL
R
1
=
R
2
A
7
µ
V
133
=
VV
()
.
133
.
−
H
R
1
+µ
A
3
VH – Turn-on threshold
VL – Turn-off threshold
Example: switching should not start until the input is
above 4.75V and is to stop if the input falls below 3.75V.
VH = 4.75V
VL = 3.75V
VV
..
475 375
R
1
=
R
2
=
−
A
7
µ
V
.
133
VV
..
475 133
()
−
143
k
143
=
+µ
k
=
.
k
49 4
A
3
Keep the connections from the resistors to the SHDN pin
short and make sure that the interplane or surface capacitance to the switching nodes are minimized. If high resistor values are used, the SHDN pin should be bypassed with
a 1nF capacitor to prevent coupling problems from the
switch node.
input can be driven directly from a logic level output. The
synchronizing range is equal to
up to 2MHz. This means that
frequency is equal to the worst-case
initial
operating frequency
minimum
practical sync
high
self-oscillating
frequency (1.6MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.8MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. Shortening
this path will also reduce the parasitic trace inductance of
approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1765
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate
volt
ages across the LT1765 that may exceed its absolute
LT1765
V
IN
HIGH
V
IN
FREQUENCY
CIRCULATING
PATH
SW
L1
D1 C1C3
5V
LOAD
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscillator
to an external signal. The SYNC input must pass from a
logic level low, through the maximum synchronization
threshold with a duty cycle between 20% and 80%. The
1765 F05
Figure 5. High Speed Switching Path
1765fb
11
LT1765/LT1765-1.8/LT1765-2.5/
()
LT1765-3.3/LT1765-5
WUUU
APPLICATIO S I FOR ATIO
D2
INPUT
15V
4.7µF
CERAMIC
C3
BOOST
V
IN
LT1765-33
ONOFF
SYNC
GND
0.18µF
V
SW
FBSHDN
V
C
C
C
2.2nF
CMDSH-3
C2
L1
2.7µH
D1
B220A
OUTPUT
3.3V
2.5A
C1
4.7µF
CERAMIC
1765 F06
KELVIN
SENSE
V
OUT
V
V
L1
OUT
MINIMIZE D1, C3
LT1765 LOOP
IN
C3
D2
C2
D1
GND
C1
GND
KEEP FB AND V
COMPONENTS AND
C
C
TRACES AWAY FROM
HIGH FREQUENCY,
HIGH INPUT
COMPONENTS
PLACE FEEDTHROUGHS
UNDER AND AROUND
GROUND PAD FOR
GOOD THERMAL
CONDUCTIVITY
1765 F6a
C
Figure 6. Typical Application and Layout (Topside Only Shown)
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1765
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Board layout also has a significant effect on thermal
resistance. The exposed pad or GND pin is a continuous
copper plate that runs under the LT1765 die. This is the
best thermal path for heat out of the package as can be
seen by the low θJC of the exposed pad package. Reducing
the thermal resistance from Pin 4 or exposed pad onto the
board will reduce die temperature and increase the power
capability of the LT1765. This is achieved by providing as
much copper area as possible around this pin/pad. Also,
having multiple solder filled feedthroughs to a continuous
copper plane under LT1765 will help in reducing thermal
resistance. Ground plane is usually suitable for this purpose. In multilayer PCB designs, placing a ground plane
next to the layer with the LT1765 will reduce thermal
resistance to a minimum.
THERMAL CALCULATIONS
Power dissipation in the LT1765 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following
formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating efficiency at light
load currents.
Switch loss:
RI V
P
SW
SW OUT OUT
=
Boost current loss for V
VI
P
BOOST
=
2
()( )
V
IN
2
()
OUT OUT
V
IN
BOOST
50/
+
17
ns I V f
= V
OUT
()()()
OUT IN
:
Quiescent current loss:
PV
=
QIN
0 001.
RSW = Switch resistance (≈ 0.13Ω at hot)
17ns = Equivalent switch current/voltage overlap time
f = Switch frequency
12
1765fb
WUUU
–
+
1.2V
V
SW
V
C
LT1765
GND
1765 F07
R1
OUTPUT
ESR
C
F
C
C
R
C
500k
ERROR
AMPLIFIER
FB
R2
C1
CURRENT MODE
POWER STAGE
g
m
= 5mho
g
m
=
850µmho
+
ESL
CERAMICTANTALUM
C1
APPLICATIO S I FOR ATIO
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
Example: with VIN = 10V, V
013 2 5
.
P
PW
PW
( )()()
=
SW
=+ =
026 043 069
...
BOOST
Q
=
=
10 0 001 0 01
()
2
+
10
2
5250
()( )
/
10
=
..
Total power dissipation, P
= 5V and I
OUT
96
17 10 2 10 1 25 10
()
−
•.•
()( )
= 2A:
OUT
()
W
=
.
01
, is 0.69 + 0.1 + 0.01 = 0.8W.
TOT
Thermal resistance for the LT1765 16-lead TSSOP exposed pad package is influenced by the presence of
internal or backside planes. With a full plane under the
package, thermal resistance will be about 45°C/W. With
no plane under the package, thermal resistance will increase to about 110°C/W. For the exposed pad package
θ
JC(PAD)
= 10°C/W. Thermal resistance is dominated by
board performance. To calculate die temperature, use the
appropriate thermal resistance number and add in worstcase ambient temperature:
TJ = TA + θJA (P
TOT
)
When estimating ambient, remember the nearby catch
diode will also be dissipating power.
P
DIODE
VV V I
()
=
−
()()
F IN OUT LOAD
V
IN
VF = Forward voltage of diode (assume 0.5V at 2A)
DIE TEMPERATURE MEASUREMENT
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must first be calibrated,
with no significant output load, in an oven. An initial value
of 40k with a temperature coefficient of 0.16%/°C is
typical. The same measurement can then be used in
operation to indicate the die temperature.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the ‘LAYOUT CONSIDERATIONS’ section
first. Common layout errors that appear as stability problems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the VC compensation
to a ground track carrying significant switch current. In
addition, the theoretical analysis considers only first order
ideal component behavior. For these reasons, it is important that a final stability check is made with production
layout and components.
The LT1765 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 7,
with both tantalum and ceramic capacitor equivalent circuits. The LT1765 can be considered as two gm blocks, the
error amplifier and the power stage.
05 10 5 2
PW
DIODE
()
=
−
()()
=
05..
10
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower VF diode can improve efficiency by several percent.
Typical thermal resistance of the board θB is 35°C/W. At an
ambient temperature of 25°C,
TJ = TA + θJA(P
TJ = 25 + 45 (0.8) + 35 (0.5) = 79°C
) + θB(P
TOT
)
DIODE
Figure 7. Model for Loop Response
1765fb
13
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
WUUU
APPLICATIO S I FOR ATIO
Figure 8 shows the overall loop response with a 330pF V
C
capacitor and a typical 100µF tantalum output capacitor.
The response is set by the following terms:
Error amplifier:
DC gain set by gm and RL = 850µ • 500k = 425.
Pole set by C
Unity-gain set by C
and RL = (2π • 500k • 330p)–1 = 965Hz.
F
and gm = (2π • 330p • 850µ–1)–1 =
F
410kHz.
Power stage:
DC gain set by gm and RL (assume 5Ω) = 5 • 5 = 25.
Pole set by C
Unity-gain set by C
and RL = (2π • 100µ • 10)–1 = 159Hz.
OUT
and gm = (2π • 100µ • 5–1)–1 = 8kHz.
OUT
Tantalum output capacitor:
Zero set by C
OUT
and C
= (2π • 100µ • 0.1)–1 = 15.9kHz.
ESR
The zero produced by the ESR of the tantalum output
capacitor is very useful in maintaining stability. Ceramic
output capacitors do not have a zero due to very low ESR,
but are dominated by their ESL. They form a notch in the
1MHz to 10MHz range. Without this zero, the VC pole must
be made dominant. A typical value of 2.2nF will achieve
this.
If better transient response is required, a zero can be
added to the loop using a resistor (RC) in series with the
compensation capacitor. As the value of RC is increased,
transient response will generally improve, but two effects
limit its value. First, the combination of output capacitor
ESR and a large RC may stop loop gain rolling off
altogether. Second, if the loop gain is not rolled suffi-
ciently at the switching frequency, output ripple will
perturb the VC pin enough to cause unstable duty cycle
switching similar to subharmonic oscillation. This may
not be apparent at the output. Small signal analysis will
not show this since a continuous time system is assumed.
If needed, an additional capacitor (C
V
pin to form a pole at typically one fifth the switching
C
) can be added to the
F
frequency (If RC = ~ 5k, CF = ~ 100pF)
When checking loop stability, the circuit should be operated over the application’s full voltage, current and temperature range. Any transient loads should be applied and
the output voltage monitored for a well-damped behavior.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for example, a battery powered device with a wall adapter input,
the output of the LT1765 can be held up by the backup
supply with its input disconnected. In this condition, the
SW pin will source current into the V
pin. If the SHDN pin
IN
is held at ground, only the shutdown current of 6µA will be
pulled via the SW pin from the second supply. With the
SHDN pin floating, the LT1765 will consume its quiescent
operating current of 1mA. The VIN pin will also source
current to any other components connected to the input
line. If this load is greater than 10mA or the input could be
shorted to ground, a series Schottky diode must be added,
as shown in Figure 9. With these safeguards, the output
can be held at voltages up to the VIN absolute maximum
rating.
14
80
60
40
20
GAIN (dB)
0
–20
–40
10 1k 10k 1M100 100k
Figure 8. Overall Loop Response
V
OUT
C
OUT
= 330pF
C
C
R
C/CF
I
LOAD
FREQUENCY (Hz)
= 5V
= 100µF, 0.1Ω
= 0
= 1A
PHASE
GAIN
1765 F08
180
150
120
PHASE (DEG)
90
60
30
0
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 10 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, CSS and Q1. As
the output starts to rise, Q1 turns on, regulating switch
current via the VC pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current
through CSS defined by R4 and Q1’s VBE. Once the output
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.
1765fb
WUUU
APPLICATIO S I FOR ATIO
REMOVABLE
INPUT
MBRS330T3*
83k
28.5k
* ONLY REQUIRED IF ADDITIONAL LOADS ON THE INPUT CAN SINK >10mA
Figure 9. Dual Source Supply with 6µA Reverse Leakage
V
2.2µF
IN
SYNC
BOOST
LT1765-3.3
GND
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
CMDSH-3
0.18µF
B220A
5µH
3.3V, 2A
4.7µF
ALTERNATE
SUPPLY
1765 F09
V
SW
FBSHDN
V
C
2.2nF
D2
CMDSH-3
C2
INPUT
12V
2.2µF
0.18µF
BOOST
V
+
C3
IN
SHDN
SYNC
LT1765-5
GND
C
C
330pF
V
SW
FB
V
C
Q1
L1
5µH
C1
D1
100µF
C
SS
R3
15nF
2k
R4
47k
D1: B220A
Q1: 2N3904
OUTPUT
5V
2.5A
1765 F10
Figure 10. Buck Converter with Adjustable Soft Start
RC V
()( )( )
4
RiseTime
=
SS OUT
V
()
BE
Using the values shown in Figure 10,
47 10 15 10 5
RiseTime ms==
(• )(• )()
39
07
–
5
.
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can be
used for sequencing multiple regulator outputs.
Dual Output Converter
The circuit in Figure 11 generates both positive and
negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
standard B H Electronics inductor. The topology for the 5V
output is a standard buck converter. The –5V topology
would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates a SEPIC
(single-ended primary inductance converter) topology
which improves regulation and reduces ripple current in
L1. Without C4, the voltage swing on L1B compared to
L1A would vary due to relative loading and coupling
losses. C4 provides a low impedance path to maintain an
equal voltage swing in L1B, improving regulation. In a
flyback converter, during switch on time, all the converter’s
energy is stored in L1A only, since no current flows in L1B.
At switch off, energy is transferred by magnetic coupling
into L1B, powering the –5V rail. C4 pulls L1B positive
during switch on time, causing current to flow, and energy
to build in L1B and C4. At switch off, the energy stored in
both L1B and C4 supply the –5V rail. This reduces the
current in L1A and changes L1B current waveform from
square to triangular. For details on this circuit, including
maximum output currents, see Design Note 100.
1765fb
15
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
WUUU
APPLICATIO S I FOR ATIO
INPUT
12V
C3
2.2µF
25V
GND
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS CTX5-1A
†
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: B220A
CERAMIC
V
IN
SYNC
BOOST
LT1765-5
GND
3.3k
V
R
C
CERAMIC
V
C
4.7µF
0.18µF
SW
FBSHDN
C
C
4700pF
C4
16V
D2
CMDSH-3
C2
D1
L1A*
L1B*
CERAMIC
D3
4.7µF
6.3V
OUTPUT
5V AT 1.5A
4.7µF
6.3V
CERAMIC
OUTPUT
–5V
1765 F11a
†
AT 1.1A
Figure 11a. Dual Output Converter
Max Negative Load vs
Positive Load
1200
1000
800
600
400
MAX –5V LOAD (mA)
200
0
10 100 1000 10000
5V LOAD CURRENT (mA)
1765 F11b
Figure 11b. Dual Output Converter (Output Currents)
16
1765fb
WUUU
APPLICATIO S I FOR ATIO
INPUT
5V
22µF
V
IN
SHDN
C3
2.2µF
16V X5R
CERAMIC
L1: CDRH6D28-3R0
GND
BOOST
U1
LT1765-5
SYNC
C
C
1800pF
2.4k
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
D2
CMDSH-3
C2
0.22µF
V
SW
FB
V
C
C
R
F
100pF
C
D1
B220A
L1
3µH
D3
B220A
C1
10µF
6.3V X5R
CERAMIC
OUTPUT
–5V
1765 F12
AT 1A
OUTPUT
–9V AT 1A
Figure 12. Positive-to-Negative Low Output Ripple Converter
D2
CMDSH-3
C2
0.22µF
BOOST
V
IN
LT1765FE
SHDN
GND
SYNC
C3
22µF
16V X5R
CERAMIC
L1: CDRH5D28-2R5
BOLD LINES INDICATE HIGH CURRENT PATHS
4700pF
V
C
6.8k
SW
FB
V
C
C
C
R
F
100pF
C
U1
D1
UPS120
10k
R2
L1
2.5µH
64.9k
R1
Figure 13. Negative Boost Converter
INPUT
–5V
C1
2.2µF
6.3V X5R
1765 F13
1765fb
17
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
3.58
(.141)
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
16 1514 13 12 11
10 9
6.60 ±0.10
4.50 ±0.10
RECOMMENDED SOLDER PAD LAYOUT
0.09 – 0.20
(.0035 – .0079)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
0.45 ±0.05
0.65 BSC
4.30 – 4.50*
(.169 – .177)
0.50 – 0.75
(.020 – .030)
MILLIMETERS
(INCHES)
2.94
(.116)
1.05 ±0.10
1345678
2
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
2.94
(.116)
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
FE16 (BB) TSSOP 0204
6.40
(.252)
BSC
18
1765fb
PACKAGE DESCRIPTIO
.050 BSC
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
U
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
.045 ±.005
(4.801 – 5.004)
8
NOTE 3
7
6
5
.245
MIN
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
× 45°
.016 – .050
(0.406 – 1.270)
INCHES
(MILLIMETERS)
.160 ±.005
.228 – .244
(5.791 – 6.197)
0°– 8° TYP
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.150 – .157
(3.810 – 3.988)
NOTE 3
1
3
2
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1765fb
19
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1074/LT1074HV 4.4A (I
LT1076/LT1076HV 1.6A (I
LT1676 60V, 440mA (I
Converter SO-8
LT1765 25V, 2.75A (I
Converter SO-8, TSSOP16E
LT1766 60V, 1.2A (I
Converter TSSOP16/E
LT1767 25V, 1.2A (I
Converter MS8/E
LT1776 40V, 550mA (I
Converter N8, SO-8
LT1940 25V, Dual 1.2A (I
DC/DC Converter TSSOP16E
LT1956 60V, 1.2A (I
Converter TSSOP16/E
LT1976 60V, 1.2A (I
Converter with Burst Mode
LT3010 80V, 50mA, Low Noise Linear Regulator VIN: 1.5V to 80V, V
LTC3407 Dual 600mA (I
Converter MS10E
LTC3412 2.5A (I
LTC3414 4A (I
LT3430/LT3431 60V, 2.75A (I
DC/DC Converter TSSOP16E
LT3433 60V, 400mA (I
DC/DC Converter with Burst Mode Operation I
LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Converter VIN: 4V to 36V, V
Burst Mode is a registered trademark of Linear Technology Corporation.
), 100kHz, High Efficiency Step-Down DC/DC Converter VIN: 7.3V to 45V/64V, V
OUT
), 100kHz, High Efficiency Step-Down DC/DC Converter VIN: 7.3V to 45V/64V, V
OUT
), 100kHz, High Efficiency Step-Down DC/DC VIN: 7.4V to 60V, V
OUT
), 1.25MHz, High Efficiency Step-Down DC/DC VIN: 3V to 25V, V
OUT
), 200kHz, High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, V
OUT
), 1.25MHz, High Efficiency Step-Down DC/DC VIN: 3V to 25V, V
OUT
), 200kHz, High Efficiency Step-Down DC/DC VIN: 7.4V to 40V, V
OUT
), 1.1MHz, High Efficiency Step-Down VIN: 3V to 25V, V
OUT
), 500kHz, High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, V
OUT
), 200kHz, High Efficiency Step-Down DC/DC VIN: 3.3V to 60V, V
OUT
®
Operation TSSOP16E
= 10µA, DD5/7, TO220-5/7
I
SD
I
= 10µA, DD5/7, TO220-5/7
SD
MS8E
), 1.5MHz, Synchronous Step-Down DC/DC VIN: 2.5V to 5.5V, V
OUT
), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, V
OUT
TSSOP16E
), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.3V to 5.5V, V
OUT
TSSOP20E
), 200kHz/500kHz, High Efficiency Step-Down VIN: 5.5V to 60V, V
OUT
), 200kHz, High Efficiency Step-Up/Step-Down VIN: 4V to 60V, V
OUT
< 1µA, TSSOP16E
SD
QFN32, SSOP28
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
= 2.21V, IQ = 8.5mA,
OUT(MIN)
= 2.21V, IQ = 8.5mA,
OUT(MIN)
= 1.24V, IQ = 3.2mA, ISD < 2.5µA,
OUT(MIN)
= 1.20V, IQ = 1mA, ISD < 15µA,
= 1.20V, IQ = 2.5mA, ISD < 25µA,
OUT(MIN)
= 1.20V, IQ = 1mA, ISD < 6µA,
= 1.24V, IQ = 3.2mA, ISD < 30µA,
OUT(MIN)
= 1.2V, IQ = 3.8mA, ISD = < 1µA,
= 1.20V, IQ = 2.5mA, ISD < 25µA,
OUT(MIN)
= 1.20V, IQ = 100µA, ISD < 1µA,
OUT(MIN)
= 1.28V, IQ = 30µA, ISD < 1µA,
OUT(MIN)
= 0.6V, IQ = 40µA, ISD < 1µA,
OUT(MIN)
= 0.8V, IQ = 60µA, ISD < 1µA,
OUT(MIN)
= 0.8V, IQ = 64µA, ISD < 1µA,
OUT(MIN)
= 1.20V, IQ = 2.5mA, ISD = 30µA,
OUT(MIN)
= 3.3V to 20V, IQ = 100µA,
= 0.8V, IQ = 670µA, ISD < 20µA,
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
1765fb
LT/TP 0704 1K REV B • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2001
Loading...