Design Solutions 44
High Sensitivity Receiver Applications Benefi t
from Unique Features in 16-Bit 130Msps ADC
by Alison Smith
October 2005
RF IN
RF
BPF
IF
BPF
Driver
LO1
Figure 1. Direct IF to Digital Single Conversion Receiver
Wireless receiver design requires extreme care in dealing with noise sources that affect the Analog-to-Digital
Converter (ADC). High sensitivity receivers such as
in satellite or basestation applications demand the
highest dynamic range and therefore need to focus on
minimizing the noise contribution from every possible
source (Figure 1). These include nonlinearities in the
ADC and digital feedback from the data output bus. This
®
application note will discuss the LTC
2208 (Figure 2), a
16-bit 130Msps high performance pipelined ADC that is
ADC
DDC/DSP
ADC
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tailored for the most demanding wideband, low noise,
receivers (Figure 3). The LTC2208 ADC addresses the
key requirements for maximizing performance of high
sensitivity receivers. Here we describe the application
of its unique features to simplify receiver design and
improve overall system performance. The first is an
internal dither circuit to address ADC nonlinearity errors and the second is a digital output randomizer that
minimizes digital feedback from the data output bus.
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Figure 2. LTC2208 16-Bit 130Msps ADC Figure 3. LTC2208 64k FFT
FIN = 15.2MHz, AIN = -1dB, 2.25V
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
However,
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Design Solutions 44
Internal Transparent Dither Circuit
Multi-stage converters can potentially contain sources of
error that can signifi cantly affect the ADC’s spurious free
dynamic range (SFDR). The effect of integral non-linearity
errors (INL) can be seen as dips in the SFDR curve at more
than 10 or 20dB below full-scale (Figure 4). LTC2208 has
a linear transfer function with very low INL error; however
at these low level inputs, only a small range of the transfer
curve is utilized such that even slight linearity imperfections will generate unwanted harmonics.
To maximize SFDR for low level signals, the LTC2208 provides an on-chip dither feature to decorrelate (randomize)
the effects of linearity errors at certain locations along the
transfer curve. By dithering the input using a pseudorandom number generator driving an internal dither DAC
140
130
120
110
100
90
80
70
60
50
SFDR (dBc and dBFS)
40
30
20
10
0
–80
–70
–60
–50
INPUT LEVEL (dBFS)
DITHER OFF
–30
–40 0
–20 –10
Figure 4. SFDR vs Input Level, FIN = 15MHz
as shown in Figure 5, the ADC is forced to operate over
a wider range of the transfer curve. The pseudo-random
number is then subtracted from the ADC result with only
a small amount of dither leak-through. The correlated
spurious tones are thus converted to random noise that
can be reduced by processing gain.
The LTC2208 eliminates the complexity required by external dither circuits that consume valuable ADC bandwidth
and head room. As can be seen in Figure 6, the internal
transparent dither circuit dramatically improves the ADC’s
SFDR response well below 100dBc for low level input
signals, allowing the ADC to maintain its high dynamic
range specifi cation with only a small degradation to the
noise fl oor.
140
130
120
110
100
90
80
70
60
50
SFDR (dBc and dBFS)
40
30
20
10
0
–80
–70
–60
–50
INPUT LEVEL (dBFS)
DITHER ON
–30
–40 0
–20 –10
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2
ANALOG
INPUT
AIN
AIN
LTC2208
ENC
ANALOG
SUMMATION
∑
16-BIT
PIPELINED
ADC CORE
PRECISION
DAC
DIGITAL
SUMMATION
OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
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D15
D0
•
•
•
+
S/H
–
AMP
CLOCK/DUTY
CYCLE
CONTROL
ENC
Figure 5. Functional Block Diagram of
Internal Dither Circuit
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Design Solutions 44
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
–130
0
20
10
FREQUENCY (MHz)
30
50
40
60
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Figure 6a. A 70MHz Low Level Signal with Internal
Dither Off. Low Level Tones Are Caused by Small INL
Errors in the ADC.
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
–130
0
30
FREQUENCY (MHz)
20
10
50
40
60
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Figure 6b. The Same Conditions with Internal
Dither On. Correlated Spurious Tone Energy Has Been
Converted to Random Noise
swing: low voltage CMOS outputs or LVDS outputs. In
the CMOS digital output mode, the drivers can operate on
supply voltages as low as 0.5V without any speed penalty.
In the LVDS output mode each output bit is a differential
pair with a 0.35V
swing.
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In situations where LVDS or low voltage CMOS are still not
enough, the LTC2208 provides an optional output digital
randomizer to encode the data, the second unique feature
offered by the LTC2208. The least signifi cant bit (LSB) is
combined using an exclusive-OR function with the other
outputs before transmission. The received digital output
bus can then be easily decoded by performing the reverse
operation in the FPGA. Using this data encode scheme
reduces the residual tone caused by digital feedback by
10dB to 15dB.
CLKOUT
OF
D15
D14
D2
D1
CLKOUT
OF
D15/D0
D14/D0
D2/D0
D1/D0
Digital Output Randomizer
Another way to improve dynamic range performance is
to eliminate the generation of unwanted tones caused by
digital feedback from the ADC outputs. Digital feedback
may occur due to capacitive coupling, ground currents or
inductive coupling. While good layout can help reduce the
effects of digital coupling, it may not be enough to eliminate
the problem. One solution is to reduce the digital output
voltage swing that will correspondingly reduce digital
noise coupled into the analog circuitry. The LTC2208
offers two output modes that have reduced digital output
RAND = HIGH,
SCRAMBLE
ENABLED
RAND
Figure 7. Functional Equivalent of Digital Output
Randomizer
D0D0
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Design Solutions 44
Wide Digitizing Bandwidth
In an IF sampling receiver, the sample and hold circuit in
the ADC must have enough bandwidth and low distortion
at the Intermediate Frequency (IF) to allow the entire band
to be converted. By directly sampling an IF signal, the ADC
acts like a mixer to eliminate the second analog down
conversion stage, improving costs, system reliability and
power dissipation. The LTC2208 is designed for high IF
sampling, with an analog input bandwidth of 700MHz and
can sample IF frequencies up to 250MHz while keeping
distortion products below 83dBc.
For wideband receiver applications the LTC2208 can be
used to capture and digitize the entire cellular band (30
MHz wide) as a single block of data. This wide-band
input is likely to contain unwanted multi-carrier signals
transmitted by other wireless systems. The LTC2208’s
exceptional distortion performance and wide dynamic
range enable it to resolve low level signals in the presence of these large interferers and blockers.
The high sampling rate of the LTC2208 provides an advantage when used in oversampling applications, using
processing gain to improve the receiver’s SNR performance. Capturing a signal bandwidth of 30MHz requires
an ADC with a sample rate of at least 60Msps. However
if the signal was sampled at a higher rate of 120Msps the
broadband noise fl oor is reduced by 3dB as given by the
following equation
SNR Improvement (dB) =
10 x log (Sampling Rate/2x Signal Bandwidth)
This SNR improvement through processing gain is added
to the SNR specifi ed by the ADC.
With a sample rate of 130Msps the LTC2208 is currently
the fastest 16-bit ADC, easing stringent anti-aliasing fi lter
requirements and improving system performance through
processing gain.
PGA Input Drive
For direct sampled IF receiver systems, the required input
drive level is an important consideration. The LTC2208
features a programmable gain amplifi er (PGA) front-end
that allows the designer to select a 1.5V
input range
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and trade a little reduction in noise performance for lower
input drive, which in turn can save substantial power in
the input drive circuitry. The PGA allows the ADC reference voltage to remain at a constant voltage so that the
input range can be reduced with minimal impact to SNR.
Selecting the wider 2.25V
range will however maximize
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the SNR performance of the ADC.
Additional Benefi ts and Features
Figure 8 shows the basic features of the LTC2208. The
part is packaged in a small 9mm x 9mm QFN package and
has some integrated bypass capacitance, freeing PCB real
estate that would usually be consumed by large and costly
decoupling capacitors. In addition, the power dissipation
at 130Msps is at a comparatively low 1250mW, avoiding
the need for heat sinking.
ANALOG
INPUT
V
CM
2.2µF
AIN
AIN
COMMON MODE
+
–
1.25V
BIAS VOLTAGE
+
S/H
AMP
–
CLOCK/DUTY
CYCLE
CONTROL
ENC PGA SHDN DITH MODE LVDS RANDENC
3.3V
SENSE
INTERNAL ADC
REFERENCE
GENERATOR
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
ADC CONTROL INPUTS
OUTPUT
DRIVERS
Figure 8. LTC2208 Block Diagram
OV
DD
OGND
V
GND
OF
CLKOUT
D15
DD
0.5V TO 3.3V
1µF
CMOS
•
OR
•
LVDS
•
D0
1µF 1µF 1µF
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3.3V
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Design Solutions 44
Designed for ease of use, it requires only a single 3.3V
supply for operation and comes with a clock duty cycle
stabilizer for maintaining the ADC performance over varying duty cycles. The LTC2208 can accept high frequency,
wide dynamic range signals, offering a wide analog input
bandwidth of 700MHz.
The LTC2208 family includes speed grades of 130Msps,
105Msps, 80Msps, 65Msps, 40Msps, 25Msps and 10Msps
all with superior SFDR and SNR performance. In addition to the 16-bit ADCs, 14-bit versions of this family will
also be available. All devices are supported with demo
boards for quick device evaluation. The display from
Linear Technology’s user friendly PScope ADC software
evaluation tool is shown in Figure 9.
Conclusions
We have examined the ADC characteristics that often
pose diffi culties for high-sensitivity digital receivers and
have shown how the LTC2208 delivers the solutions to
those problems. The LTC2208 brings a new level of performance and an extensive feature-set that will help make
even higher performance digital receivers possible. This
new 16-bit family truly simplifi es design and provides the
fl exibility to improve the dynamic range performance of
the receiver system.
5
Figure 9. PScope ADC QuickEval Tool–LTC2208 Evaluation
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