Linear Technology DC252 Demo Manual

DESCRIPTIO

DEMO MANUAL DC252

DESIGN-READY SWITCHER

LTC1736 5-Bit VID Constant

Frequency Synchronous DC/DC Converter

U

Demonstration Circuit DC252 is designed for mobile 5-bit
VID-programmed notebook CPU applications using the
LTC®1736 switching regulator controller. A high perfor­mance, constant frequency current mode architecture
generates a precise low voltage CPU core supply. Protec­tion features include an externally defeatable overcurrent
latchoff and internal current foldback for overload condi­tions. A soft-latched crowbar monitors the output voltage
for overvoltage protection. OPTI-LOOPTM compensation
allows the transient response to be optimized over a wide
range of output capacitance and ESR values. The circuit
was designed for a 5V to 24V input range but allows a 4.5V
to 28V range (limited by the external MOSFETs). Strong
output drivers easily handle large power MOSFETs effi-

UW

WW

ciently. Output voltages can be configured according to
Intel mobile VID standards of 0.9V to 2.0V. An internal
power-good circuit monitors the output voltage for out-of­regulation conditions. External frequency synchronization
is provided, as are three modes of operation: Burst Mode
operation to reduce switching losses and maintain high
operating efficiencies, burst inhibit/forced continuous
mode and a low noise pulse-skipping mode that provides
constant frequency operation down to 1% maximum load
currents with low quiescent current. This results in a
power supply that has very high efficiency, low ripple and
fast transient response. Gerber files for this circuit board

are available. Call the LTC factory.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.

PERFOR A CE SU ARY

PARAMETER CONDITIONS VALUE

Input Voltage Range (Maximum Input Voltage Limited By External MOSFET and Input Capacitor) 5V to 24V
Output Output Voltage (Programmed with a 5-Bit Mobile VID Code) 0.9V to 2.0V

Max Output Current (Continuous) 11.0A
Max Output Current (Peak) 12A
Typical Output Ripple Measured with 10MHz Bandwidth (Burst Mode Operation) IO = 100mA 45mV
Typical Output Ripple Measured with 10MHz Bandwidth (Continuous) IO = 5A 20mV

V

IN

Line Regulation 5V to 24V 0.002%/V

TM

P-P

P-P

TYPICAL PERFOR A CE CHARACTERISTICS A D BOARD PHOTOS

Efficiency

100

EXTVCC = 5V

90

VIN = 5V

80

70

EFFICIENCY (%)

VIN = 24V

60

50

40

10mA 100mA 1A 10A

VIN = 15V

LOAD CURRENT (A)

252 TA01

UUW

Solder SideComponent Side

1

DEMO MANUAL DC252

DESIGN-READY SWITCHER

UW

WW

PERFOR A CE SU ARY

PARAMETER CONDITIONS VALUE

I
I

OUT

Q

Load Regulation: No Load to Full Rated Output –0.3%
Supply Current (Typical), No Load, VIN = 15V, FCB = INTV

CC

950µA

Supply Current in Shutdown (Typical), VIN = 15V 15µA

I

EXTVCC

V

RUN

Frequency Operating Frequency (Typical), C

EXTVCC Pin Current, V

= 5V, VIN = 10V, FCB = INTV

EXTVCC

No Load, V

CC,

= 1.6V 850µA

OUT

Run Pin Threshold (Typical) 1.3V

= 47pF 270kHz

OSC

WUW

PACKAGE A D SCHE ATIC DIAGRA

LTC1736CG24

TOP VIEW

PGOOD

JP3

PGOOD

1

C

OSC

2

RUN/SS

3

I

FCB/SYNC

RUN

E4

C

S1

1000pF

E3

LATCHOFF

1

2

3

4

5

6

7

8

9

10

11

12

JP2

C

OSC

RUN/SS

I

TH

FCB

SGND

PGOOD

SENSE

SENSE

V

FB

V

OSENSE

VID0

VID1

U1

LTC1736

–

+

R6

680k

BOOST

INTV

EXTV

VIDV

PGND

VID4

VID3

VID2

CF1

0.1µF

TG

SW

V

IN

CC

BG

CC

CC

RF1

4.7Ω

C

R8

4.7µF

C2

EXTV
E2

0Ω

CMDSH-3

+

CC

C

B1

0.22µF

D1

C4
1µF

24

23

22

21

20

19

18

17

16

15

14

13

M2
FDS6680A

1.2µH

M1, M3
FDS6680A
2X

MBRS340T3

22µF

30V

L1

D2

+

+

IN1

R

CS1

0.004Ω

C

IN3

22µF
30V

R
10Ω

S1

+V
E10

GND
E9

IN

+

JP1

BURST MODE

OFF

ON

INTV

CC

C

OSC1

47pF

C

SS1

0.1µF

C

C2

R

C1

330pF

33k

C

C1

47pF

E1

R1
100k

INTV

CC

C1

47pF

47pF

C3

TH

4

FCB

5

SGND

6

PGOOD

–

7

SENSE

+

8

SENSE

9

V

FB

10

V

OSENSE

11

VID0

12

VID1

24-LEAD PLASTIC SSOP

V

OUT

0.9V TO 2V/11A
E7

V

OSNS

E11

CO1, CO2, C04, C06
180µF
4V
X4

GND
E8

G PACKAGE

TG

24

BOOST

23

SW

22

V

21

IN

INTV

20

BG

19

PGND

18

EXTV

17

VIDV

16

VID4

15

VID3

14

VID2

13

CC

CC

CC

LSB MSB
JP4

B0 B4

2

R5, 10Ω

R2, 10Ω

Figure 1. Demo Board Schematic

247 F01

DEMO MANUAL DC252

DESIGN-READY SWITCHER

PARTS LIST

REFERENCE QUANTITY PART NUMBER DESCRIPTION VENDOR TELEPHONE

C1, C3 2 08055A470JAT1A 47pF 50V 5% NPO Capacitor AVX [phone]
C2 1 TACR475M010R 4.7µF 10V 20% Tantalum Capacitor AVX [phone]
C4 1 0805ZC105MAT1A 1µF 10V 20% X7R Capacitor AVX [phone]
CC1 1 08055A470JAT1A 47pF 50V 5% NPO Capacitor AVX [phone]
CC2 1 08055A331MAT1A 330pF 50V 5% NPO Capacitor AVX [phone]
CB1 1 08055A224KAT1A 0.22µF 50V 20% X7R Capacitor AVX [phone]
CF1, CSS1 2 08055A104MAT1A 0.1µF 50V 20% X7R Capacitor AVX [phone]
CIN1, CIN3 2 30SC22M 22µF 30V OS-CON Capacitor SANYO [phone]
CIN1, CIN3 OPT THCR70E1H2262T 22µF 50V 20% Y5U Capacitor MARCON [phone]
CO1, CO2, CO4, CO6 4 EEFUE0G181R 180µF 4V SP Capacitor PANASONIC [phone]
CO1, CO2, CO4 OPT T510X447MOO6AS 470µF 6.3V Low ESR Tantalum Capacitor KEMET [phone]
CO3, CO5 OPT 4SP820M 820µF 4V OS-CON Capacitor SANYO [phone]
C

OSC1

CS1 1 08055A102MAT1A 1000pF 50V 5% NPO Capacitor AVX [phone]
D1 1 CMDSH-3 BVR = 30V, 0.1A Schottky Diode CENTRAL [phone]
D2 1 MBRS340T3 BVR = 40V, 3A Schottky Diode ON SEMICONDUCTOR [phone]
E1, GND, +VIN, V
E2, E3, E4, E8, E9, GND, 8 1502-2 Turret Terminal KEYSTONE [phone]

+VIN, +V

OUT

JP1 1 2802S-03-G2 2mm 3-Pin Header COMM CON [phone]
JP2, JP3 2 2802S-02-G2 2mm 2-Pin Header COMM CON [phone]
JP4 1 2202S-05-G2 2mm Dual 5-Pin Header COMM CON [phone]
L1 1 ETQP6F1R2HFA 1.2µH Inductor PANASONIC [phone]
M1, M2, M3 3 FDS6680A 30V 0.013Ω N-Channel MOSFET FAIRCHILD [phone]
R1 1 CR10-104JM 100k 1/10W 5% Chip Resistor TAD [phone]
R2, R5, RS1 3 CR10-100FM 10Ω 1/10W, 1% Chip Resistor TAD [phone]
R6 1 CR10-685JM 680k 1/10W 5% Chip Resistor TAD [phone]
R8 1 CR10-0R0JM 0Ω 1/10W Chip Resistor TAD [phone]
RC1 1 CR10-333JM 33k 1/10W 5% Chip Resistor TAD [phone]
RCS1 1 LRF2010-01-R004F 0.004Ω 1/2W 1% Resistor IRC [phone]
RF1 1 CR10-470JM 4.7Ω 1/10W, 5% Chip Resistor TAD [phone]
U1 1 LTC1736CG IC, LTC1736CG24 LTC [phone]

OSNS

, V

OUT1

1 08055A470JAT1A 47pF 50V 5% NPO Capacitor AVX [phone]

5 1593-2 Turret Terminal (Small) KEYSTONE [phone]

8 CCIJ2mm-138-G JUMPER COMM CON [phone]

3

DEMO MANUAL DC252

DESIGN-READY SWITCHER

QUICK START GUIDE

This demonstration board is easy to set up to evaluate
the performance of the LTC1736. Please follow the
procedure outlined below for proper operation. Sol­dered wire connections are required to properly evalu­ate the performance of this switching regulator.

• Refer to Figure 2 for proper connection of monitoring
and measurement equipment.

• Connect the input power supply to the VIN and GND
terminals on the right-hand side of the board with
soldered connections. Do not increase VIN over 28V
or the MOSFET(s) WILL BE DAMAGED.

• Connect the load between the V

and GND termi-

OUT

nals on the right side of the board with soldered
connections.

• The RUN pin can be left unconnected. To shut down
the LTC1736, tie this pin to ground.

• Set jumper JP4 for the desired output voltage. (See
Table 1.)

OPTIONAL EXTERNAL

HIGH FREQUENCY

SOURCE CONNECTION

EXT CLOCK

(REMOVE JP1 IF USED)

RUN

FCB/SYNC

PGOOD

EXTV

CC

GND

VID CPU POWER CONVERTER

JP2 LATCHOFF

OFF

ON

JP1 BURST

JP3

PGOOD

LTC1736CG
DEMO CIRCUIT DC252A
[phone]

JP4

B4B0

Figure 2

• If an external 5V supply is used, connect it to EXTVCC.

• Set the jumper JP1 so that FCB selects the desired
mode:

JP1 MODE

On Burst Mode Operation, Connect PGood to FCB/Sync
Off Forced Continuous
Open Apply External Clock to FCB/Sync

• Jumper JP2 determines if the overcurrent latchoff is
enabled. With JP2 installed this function is disabled.
Remove JP2 to enable.

JP2 OVERCURRENT LATCHOFF

Installed Disabled
Removed Enabled

• Active loads can cause confusing results. Refer to the
active load discussion in the Operation section.

OUT

A
I

IN

+

–

–

+

+

V

IN

–

LOAD

I

OUT

A

252 F02

V

O

PROG

+V

IN

GND

GND

V

OSNS

+V

OUT

OPTIONAL REMOTE

SENSE CONNECTION

V

OUT

V

UU

I TRODUCTIO

The circuit in Figure 1 highlights the capabilities of the
LTC1736.

The LTC1736 is a synchronous step-down switching
regulator controller that drives external N-channel power
MOSFETs using a fixed frequency architecture with OPTI­LOOP compensation. OPTI-LOOP compensation effectively
removes the constraints placed on C

OUT

for proper operation (such as restrictions on very low
ESRs). Burst Mode operation provides high efficiency at

4

by other controllers

low load currents. Operating efficiencies typically exceed
80% over more than two decades of load current range.

Do not use spring clip leads when testing this circuit.
Soldered wire connections are required to properly test
the performance of the PC board.

This demonstration circuit is intended for the evaluation of
the LTC1736 switching regulator IC and was not designed
for any other purpose.

OPERATIO

DEMO MANUAL DC252

DESIGN-READY SWITCHER

U

The operating frequency is set by an external capacitor,
C

, allowing maximum flexibility in optimizing effi-

OSC1

ciency. In this application, the frequency is set to 270kHz.
A multifunction control pin, FCB, inhibits Burst Mode
operation (reducing noise and RF interference), as well as
allowing synchronization to an external oscillator.

Soft-start is provided by an external capacitor, C

SS1

,
which can be used to properly sequence supplies. The
operating current level is user programmable via an exter­nal current sense resistor and is set to 11A. Short-circuit
current is limited to approximately 4A by internal current
foldback.

Measuring Voltage Regulation

When trying to measure voltage regulation, remember
that all measurements must be taken at the point of
regulation. This point is where the LTC1736’s control loop
looks for the information to keep the output voltage
constant. In this demonstration board it is located be­tween Pin 5 (SGND) of the LTC1736 and the sense side of
RS1. This point corresponds to the V

terminal of the

OSNS

board. Output voltage test leads should be attached di­rectly to this terminal. The load should be placed across
the V

should not

(E7) and GND (E8) terminals. Measurements

OUT

be taken at the end of test leads at the load; refer
to Figure 2 for the proper monitoring equipment configu­ration.

This applies to line regulation (input to output voltage
regulation) as well as load regulation tests. In doing line
regulation tests, always look at the input voltage across
the input terminals.

Remote Output Voltage Sensing

Remote output voltage sensing can be accomplished by
connecting the V
to the load. A 10Ω resistor, RS1, connects V

terminal with another wire directly

OSNS

OUT

to V

OSNS

to avoid open sense conditions. Never under any circum­stance connect the load to V

OSNS

!

Output Voltage Programming

as a precision resistor voltage divider sets the output
voltage in 50mV/25mV increments according to Table 1.

Table 1. VID Output Voltage Programming

B4 B3 B2 B1 B0 V

0 0 0 0 0 2.000V
0 0 0 0 1 1.950V
0 0 0 1 0 1.900V
0 0 0 1 1 1.850V
0 0 1 0 0 1.800V
0 0 1 0 1 1.750V
0 0 1 1 0 1.700V
0 0 1 1 1 1.650V
0 1 0 0 0 1.600V
0 1 0 0 1 1.550V
0 1 0 1 0 1.500V
0 1 0 1 1 1.450V
0 1 1 0 0 1.400V
0 1 1 0 1 1.350V
0 1 1 1 0 1.300V
01111 *
1 0 0 0 0 1.275V
1 0 0 0 1 1.250V
1 0 0 1 0 1.225V
1 0 0 1 1 1.200V
1 0 1 0 0 1.175V
1 0 1 0 1 1.150V
1 0 1 1 0 1.125V
1 0 1 1 1 1.100V
1 1 0 0 0 1.075V
1 1 0 0 1 1.050V
1 1 0 1 0 1.025V
1 1 0 1 1 1.000V
1 1 1 0 0 0.975V
1 1 1 0 1 0.950V
1 1 1 1 0 0.925V
11111 **

Note: *, ** Represents codes without a defined output voltage as
specified in Intel specifcations. The LTC1736 interprets these codes as a
valid input and produces output voltage as follows: [01111] = 1.250V,
[11111] = 0.900V.

OUT

(V)

The output voltage is digitally set to levels between 0.925V
and 2.00V using the voltage identification (VID) inputs B0
to B4 set by jumper JP4. The internal 5-bit DAC configured

5

DEMO MANUAL DC252

DESIGN-READY SWITCHER

U

OPERATIO

The VID codes (00000-11110) are engineered to be com­patible with Intel Mobile Pentium® II Processor specifica­tions for output voltages from 0.925V to 2.00V.

The LSB (B0) represents 50mV increments in the upper
voltage range (2.00V to 1.30V) and 25mV increments in
the lower voltage range (1.275V to 0.925V). The MSB is
B4. When all bits are low or grounded, the output voltage
is 2.00V.

Each VID digital input is internally pulled up by a 40k
resistor in series with a diode from VIDVCC. Therefore,
digital inputs must be grounded to get a digital low input,
and digital inputs can be either left unconnected or con­nected to VIDVCC to get a digital high input. The series
diode is used to prevent the digital inputs from being
damaged or clamped if they are driven higher than VIDVCC.
The digital inputs accept CMOS voltage levels.

Maximum Input Voltage Considerations

The recommended maximum input voltage of this board
is 24V for nominal output voltages. The minimum on-time
for the LTC1736 is generally about 200ns and the operat­ing frequency for this board is set to 270kHz. This imposes
a limit on the maximum input voltage when programming
low output voltages. For output voltages below 1.2V the
maximum input voltage is limited to:

V

IN(MAX)

If a higher operating input voltage is required with V

1.2V, the operating frequency can be decreased by in­creasing C
details. If the duty cycle falls below what can be accommo­dated by the minimum on-time, the LTC1736 will begin to
skip cycles. The output voltage will continue to be regu­lated, but the ripple current and ripple voltage will in­crease.

Power-Good Output

A window comparator monitors the output voltage and its
open-drain output (E1) is pulled low when the divided
output voltage is not within ±7.5% of the reference voltage
of 0.8V. Jumper JP3 connects pull-up resistor R1 from
INTVCC to the power-good output, E1. This jumper is
provided to allow other pull-up voltages to be used. Make

< 20 (V

. Refer to the LTC1736 data sheet for

OSC1

OUT

)

OUT

<

sure the maximum voltage on PGOOD is less than 7V.
During shutdown, the PGOOD output is pulled low.

INTVCC Regulator

An internal, P-channel, low dropout regulator produces
the 5.2V supply that powers the drivers and internal
circuitry within the LTC1736. The INTVCC pin can supply
up to 50mA (this includes the gate-drive currents). Exter­nal loading of the INTVCC pin can be thermally limited
(allow 10mA to 20mA for gate-drive currents). At high
input voltages, the maximum junction temperature rating
for the LTC1736 may be exceeded if too large an external
load is placed on INTVCC. See the LTC1736 data sheet for
details.

EXTVCC Connection

The LTC1736 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
The switch closes and supplies the INTVCC power when­ever the EXTVCC pin is above 4.7V; it remains closed until
EXTVCC drops below 4.5V. This allows the MOSFET driver
and control power to be derived from the EXTVCC pin
instead of VIN. Do not apply greater than 7V to the EXTV
pin and ensure that EXTVCC < VIN. Additional efficiency
gains can be realized by powering INTVCC from other high
efficiency sources, such as a 5V system power supply.

The following list describes the most common possible
connections for EXTVCC for low output voltage applica­tions:

1. EXTVCC left open (or grounded); this will cause INTV
to be powered from the internal 5.2V regulator resulting in
an efficiency penalty at low load currents and high input
voltages.

2. EXTVCC connected to an external supply ; if an external,
high efficiency supply is available in the 5V to 7V range
(EXTV
an efficiency boost. The typical connection in a notebook
CPU power solution is to connect it to the main 5V system
power supply.

Pentium is registered trademark of Intel Corportion.

< VIN), it may be used to power EXTVCC, providing

CC

CC

CC

6

OPERATIO

DEMO MANUAL DC252

DESIGN-READY SWITCHER

U

Low Current Modes and Synchronization

The FCB input pin, set by jumper JP1 and FCB/Sync
terminal E4, allows the selection of the low current oper­ating mode and external frequency synchronization of the
switching regulator.

Tying the FCB pin to ground with JP1 forces the controller
into PWM or forced continuous mode. In forced continu­ous mode, the output MOSFETs are always driven, regard­less of output loading conditions. Operating in this mode
allows the switching regulator to source or sink current—
but be careful; when the output stage sinks current, power
is transferred back into the input supply terminals and the
input voltage rises.

Burst Mode operation is enabled when the voltage applied
to the FCB pin is greater than 0.8V (i.e., JP1 tied to INTVCC)
or if the pin is left open. A comparator with a precision 0.8V
threshold allows the pin to be used to regulate a secondary
winding on the switching regulator’s output. A small
amount of hysteresis is included in the design of the
comparator to facilitate clean secondary operation. When
the resistively divided secondary output voltage falls be­low the 0.8V threshold, the controller operates in the
forced continuous operating mode for as long as it takes
to bring the secondary voltage above the 0.8V + hysteresis
level.

maximum designed load current in order to maintain
proper output voltage.

The range of synchronization is from 240kHz to 350kHz
with C

= 47pF. Attempting to synchronize to a higher

OSC

frequency than 350kHz can result in inadequate slope
compensation and cause loop instability with high duty
cycles. If loop instability is observed while synchronized,
additional slope compensation can be obtained by simply
decreasing C

OSC

.

The following table summarizes the possible states avail­able on the FCB/Sync pin:

FCB/SYNC PIN CONDITION

DC Voltage: 0V to 0.7V Burst Disabled/Forced Continuous

Current Reversal Enabled

DC Voltage: ≥ 0.9V Burst Mode Operation,

No Current Reversal
Feedback Resistors Regulating a Secondary Winding
Ext Clock: (0V to V

(V

FCB/SYNC

) Burst Mode Operation Disabled

FCB/SYNC

> 1.5V) No Current Reversal

DC252 Modifications (MOSFETs)

The DC252 demo board has various modification provi­sions. Additional pad locations are available for adding
extra output capacitors together with an extra footprint for
a parallel topside MOSFET.

The internal LTC1736 oscillator can be synchronized to an
external oscillator by clocking the FCB pin with a signal
above 1.5V

(Remember to remove jumper JP1). When

P-P

the LTC1736 is synchronized to an external frequency,
Burst Mode operation operation is disabled but cycle
skipping is allowed at low load currents, since current
reversal is inhibited. The bottom gate will come on every
10 clock cycles to ensure that the bootstrap capacitor C
is kept charged. The rising edge of an external clock
applied to the FCB pin starts a new cycle.

When the LTC1736 is synchronized to an external clock,
burst inhibit mode allows heavily discontinuous, low
audio noise, constant frequency operation down to ap­proximately 1% of maximum designed load current. This
mode results in the elimination of switching frequency
subharmonics over 99% of the output load range. Switch­ing cycles start to be dropped at approximately 1% of

When operating at high input voltages, the transition
losses of the topside MOSFET (M2) become very signifi­cant. Be sure to consider power loss due to transition
losses as well as R

losses. Don’t over specify the

DS(ON)

topside MOSFET. (Refer to the LTC1736 data sheet for
details.)

Refer to the LTC1736 data sheet for further information on

B1

the internal operation and functionality descriptions of the
IC.

DC252 Modifications (Output Capacitors)

Four Matsushita SP output capacitors are installed on the
demo board. Other output capacitors may freely be substi­tuted provided they meet the load transient requirements.
OPTI-LOOP compensation allows the transient response
to be optiumized over a wide range of output capacitance
and ESR values while minimizing output capacitance.

7

DEMO MANUAL DC252

DESIGN-READY SWITCHER

U

OPERATIO

The output capacitors are generally determined by ESR
(effective series resistance) and voltage rating rather than
capacitance. The ESR must be small enough that output
ripple voltage and any voltage droop due to high load
current transients stay within the specifications of the
CPU. The output capacitance must be large enough to hold
up the output voltage until the inductor current has ramped
up or down to its new value. With proper OPTI-LOOP
compensation components, the response time is opti­mized and the output capacitance is minimized. The com­pensation components installed on the demo board are
appropriate for the output capacitors specified in the parts
list.

Additional mounting locations exist for through hole Sanyo
OS-CON output capacitors, should they be desired. Com­binations of different types of capacitors have proved to
yield cost effective solutions. ESL (equivalent series in­ductance), typically not specified, can reduce the effec­tiveness of the ESR at high load current slew rates, so be
careful in specifying the output capacitor.

Overcurrent Protection

The RUN/SS capacitor, C
limit the inrush current of the controller. After the control­ler has been started and given adequate time to charge the
output capacitor and provide full load current, C
as a short-circuit time-out circuit. If the output voltage falls
to less than 70% of its nominal value, C
charging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condition
lasts for a long enough period, as determined by the size
of C
pin voltage is recycled. This built-in latchoff can be over­ridden by providing >5µA pull-up at a compliance of 4V to
the RUN/SS pin by installing jumper JP2. This current
shortens the soft-start period but also prevents net dis­charge of the RUN/SS capacitor during an overcurrent
and/or short-circuit condition.

Foldback current limiting is activated when the output
voltage falls below 70% of its nominal level, whether or not
the short-circuit latchoff circuit is enabled.

, the controller will be shut down until the RUN/SS

SS1

is used initially to turn on and

SS1,

SS1

begins dis-

SS1

is used

cycle the run pin to start. Refer to the LTC1736 data sheet
for details.

Overvoltage Protection

The output is protected from overvoltage by a “soft-latch.”
When the output voltage exceeds the regulation value by
more than 7.5%, the synchronous MOSFET turns on, and
remains on for as long as the overvoltage condition is
present. If the output voltage returns to a safe level, normal
operation resumes. This self-resetting action prevents
"nuisance trips" due to momentary transients and elimi­nates the need for the Schottky diode that is necessary
with conventional OVP to prevent V

Because of the inherent self-resetting action of the soft­latch, dynamic changing of the VID control bits does not
latch off the LTC1736. When a new output voltage is set via
the VID bits, the control loop simply adjusts the output
voltage and the overvoltage protection threshold to this
new level without causing a fault.

The overvoltage threshold tracks the new output voltage,
protecting the load at all times. Figure 3a and Figure 3b
both show an example of a dynamic VID code change
resulting in a programmed output voltage change from

1.5V to 1.3V at a constant 5 ampere load current. At the
instant the VID code is changed, the control loop begins to
respond to the new output voltage, and the power-good
output is asserted low since the new programmed output
voltage is outside the 7.5% window. When the new output
voltage is within 7.5% of its new programmed value, the
power-good signal goes high. Figure 3a shows a VID code
change with the FCB pin low (Burst Mode operation
disabled). Figure 3b shows a dynamic VID code change
with Burst Mode operation active. If dynamic VID changes
are required and Burst Mode operation is desired, connect
the PGOOD output (E1) to the FCB/Sync input (E4) and
remove jumper JP1. This connection automatically forces
continuous operation whenever the power-good output is
low, providing fast response to VID changes regardless of
load current.

Active Loads— Beware

reversal.

OUT

With the overcurrent latchoff enabled, a slow ramp on the
input voltage may cause the circuit to latch off. Simply re-

8

Beware of active loads! They are convenient but problem­atic. Some active loads do not turn on until the applied

OPERATIO

252 F03b

PGOOD

5V/DIV

V

OUT

100mV/

DIV

I

L

5A/DIV

V

OUT

100mV/

DIV

I

L

5A/DIV

U

PGOOD

5V/DIV

DEMO MANUAL DC252

DESIGN-READY SWITCHER

252 F03a

Figure 3a. Dynamic VID Change, Burst Mode Operation Defeated Figure 3b. Dynamic VID Change, Burst Mode Operation Enabled

voltage rises above 0.1V to 0.8V. The turn-on may be
delayed as well. A switching regulator with soft-start may
appear to start up, then shut down and, eventually, reach
the correct output voltage. What happens is as follows: at
switching regulator turn-on, the output voltage is below
the active load’s turn-on requirements. The switching
regulator’s output rises to the correct output voltage level
due to the inherent delay in the active load. The active load
turns on after its internal delay and then pulls down the

testing, the active load should be initially programmed to
a much lower current value until the switching regulator’s
soft-start interval has passed and then increased to the
higher level. The switching regulator will supply the in­creased current required according to the transient re­sponse of the switching regulator. Output capacitance
needs to be sufficient to accommodate the current step
during the transient period, keeping the output voltage at
or above the foldback threshold of 70%.

switching regulator’s output because the switcher is in its
soft-start interval. The switching regulator’s output may
come up at some later time when the soft-start interval has
passed.

A switching regulator with foldback current limit will also
have difficulty with the unrealistic I-V characteristic of the
active load. Foldback current limiting will reduce the
output current available as the output voltage drops below
a threshold level (this level is 70% of nominal V

OUT

for the
LTC1736). This reduction in available output current will
result in the active load immediately pulling down the
output because the active load’s current demand remains
constant as the output voltage decreases. Most actual
loads do not behave like the active load I-V characteristics.
Actual loads normally have a VIN • C • f dependency, where
C is internal chip capacitance and f is the frequency of
operation. To alleviate the active-load problem during

Checking Transient Response

OPTI-LOOP compensation effectively removes the con­straints placed on C

by other controllers (such as

OUT

restrictions on very low ESRs). The output capacitors
used in this demo board have very low ESRs; other types
may be substituted but be carefull to measure the load step
transient response and verify the specfications on output
voltage continue to be met during transients.

A partial list of low ESR capacitors that are suitable for this
application is included in the parts list. Each has its own
cost, size, ESL and other performance trade offs. Combi­nations of capacitors have been shown to work well, too,
so feel free to experiment. An example of a combination
that works well is an OS-CON, 820µF/4V capacitor in
parallel with a 180µF/4V Matsushita SP series capacitor.
The SP capacitor tames the ESL-induced characteristic of

9

DEMO MANUAL DC252

252 F04b

V

OUT

50mV/DIV

I

L

5A/DIV

DESIGN-READY SWITCHER

U

OPERATIO

the otherwise low ESR OS-CON. The ITH OPTI-LOOP
compensation components shown in Figure 1’s circuit will
provide an adequate starting point for most applications.

The load-step response with the output voltage set to 1.6V
is shown in Figures 4a and 4b using four 180µF/4V
Matsushita SP series for the output capacitors. Figure␣ 4a
is a 0A to 12A load step with Burst Mode operation
inhibited (FCB = 0V). Figure 4b shows the load step
response for a 10mA to 12A load current transition with
Burst Mode operation enabled (FCB = 5V).

The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

, generating the feedback error signal that

OUT

(ESR), where ESR is the effective

LOAD

OUT

. ∆I

also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and
return V
time, V

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be
optimized over a wide range of output capacitances and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed-loop-response test
point. The DC step, rise time and settling at this test point
truly reflect the closed-loop response. Assuming a pre­dominantly first order system, phase margin and/or damp­ing factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.

The I

series RC1–C

TH

C2, CC1

filter sets the dominant pole­zero loop compensation. The values can be modified
slightly (from 0.5 to 2 times their suggested values) to
optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
decided upon because the various types and values deter­mine the loop feedback factor gain and phase. An output
current pulse of 20% to 100% of full load current having
a rise time of 1µs to 10µs will produce output voltage and

V

OUT

50mV/DIV

I

L

5A/DIV

Figure 4a. Load Step Response with
Burst Mode Operation Disabled

10

252 F04a

Figure 4b. Load Step Response with
Burst Mode Operation Enabled

OPERATIO

DEMO MANUAL DC252

DESIGN-READY SWITCHER

U

ITH pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The AC gain
of the loop will be increased by increasing RC1 and the
bandwidth of the loop will be increased by decreasing CC2.
If RC1 is increased by the same factor that CC2 is de­creased, the zero frequency will be kept the same, thereby
keeping the phase the same in the most critical frequency
range of the feedback loop. The output voltage settling

UW

PCB LAYOUT A D FIL

behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. Capacitor CC2 provides some high frequency
decoupling against transients. Be carefull not to overspecify
its value, as the response time to a load step will be
degraded. Again, monitoring the ITH pin will show any slew
rate limitations due to CC1. For further explanation of
optimizing loop response, refer to Application Note 76.

Component Side Silkscreen Component Side Copper (Layer 1)

Internal Copper (Layer 2) Internal Copper (Layer 3)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

11

DEMO MANUAL DC252

DESIGN-READY SWITCHER

UW

PCB LAYOUT A D FIL

Bottom Side SilkscreenBottom Side Copper (Layer 4)

Bottom Side Paste Mask Component Paste Mask

U

PC FAB DRAWI G

2.75"

A

E
E

A

E
E
E

C

E
E

A

A

EE

10 PLCS

B

G
G

G

G

GG

EEE

F

G

G

G

G

G

G

Linear Technology Corporation

12

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

E

D

E

DDD

D

D

D

C

D

GG

E

DD

DDDD

●

www.linear-tech.com

D

E

D

G

D

NOTES: UNLESS OTHERWISE SPECIFIED

B

E

A

C

E

E

F

D

A

C

E

2.10"

A

C

A

1. ALL DIMENSIONS ARE IN INCHES, ±0.003. FINISHED HOLE SIZES ARE +0.003/–0.

2. FINISHED MATERIAL IS FR4, 0.062 THICK, 1 OZ Cu, 4 LAYERS.
PLATED HOLE WALL THICKNESS 0.001 MIN. INTERNAL LAYERS 1 OZ Cu.

3. PROCESS AND PLATING: SMOBC

4. SOLDERMASK BOTH SIDES USING GLOSSY GREEN LPI.

5. SILKSCREEN WHITE NONCONDUCTIVE INK BOTH SIDES.

SYMBOL DIAMETER OF HOLES PLATED

A 0.100 8 YES
B 0.070 2 NO
C 0.065 5 YES
D 0.045 18 YES
E 0.035 25 YES
F 0.025 2 YES
G 0.020 15 YES

NUMBER

252 PC Fab Dwg

dc252f LT/TP 1199 500 • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1999