DEMO MANUAL DC1996A
LTC2323/LTC2321
Dual 16-Bit/14-Bit/12-Bit,
DESCRIPTION
Demonstration circuit 1996A features the LTC®2323 family.
With up to 5Msps, these differential, dual channel, 16-bit,
serial, high speed successive approximation register
(SAR) ADCs are available in a 28-lead QFN package. The
LTC2323 family has an internal 20ppm/°C reference and
an SPI-compatible serial interface that supports CMOS
and LVDS logic. Note the demo board is configured for
CMOS operation by default; see the note under JP3 for
LVDS operation. The following text refers to the LTC2323,
but applies to all members of the family, the only differ
ence being the sample rate and the number of bits. The
BOARD PHOTO
5Msps/2Msps, Serial,
High Speed SAR ADCs
DC1996A demonstrates the DC and AC performance of
the LTC2323 in conjunction with the DC890 PScope™
data collection board. Alternatively, by connecting the
DC1996A into a customer application, the performance
of the LTC2323 can be evaluated directly in that circuit.
Design files for this circuit board are available at
http://www.linear.com/demo
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
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BPF
HP8642B
DC POWER SUPPLY
–9.5V
GND 9.5V
DC
DC
DC890
TO PC USB PORT
dc1996a F02
BPF
HP8642B
Figure 1. DC1996A Connection Diagram
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DEMO MANUAL DC1996A
ASSEMBLY OPTIONS
Table 1. DC1996A Assembly Options
VERSION U1 PART NUMBER MAX CONVERSION RATE # OF BITS MAX CLOCK FREQUENCY
DC1996A-A LTC2323CUFD-16#PBF 5Msps 16 110MHz
DC1996A-B LTC2321CUFD-16#PBF 2Msps 16 64MHz
DC1996A-C LTC2323CUFD-14#PBF 5Msps 14 110MHz
DC1996A-D LTC2321CUFD-14#PBF 2Msps 14 62MHz
DC1996A-E LTC2323CUFD-12 #PBF 5Msps 12 95MHz
DC1996A-F LTC2321CUFD-12#PBF 2Msps 12 58MHz
QUICK START PROCEDURE
Demonstration circuit 1996A is easy to set up and evaluate
for performance. Refer to Figure 1 and follow the proce
dure below.
n
Connect the DC1996A to a DC890 USB high speed data
collection board using edge connector P1.
n
Connect the DC890 to a host PC with a standard USB
A/B cable.
n
Apply a low jitter signal source to J2 to test channel
2, or to J4 to test channel 1. Note that the DC1996A
is capable of accepting a differential input signal as
well as a single-ended signal. See the Hardware Setup
section for the jumper positions that correspond to
these configurations.
n
As a clock source, apply a low jitter 10dBm sine wave or
square wave to connector J1. See Table 1 for maximum
clock frequencies. Note that J1 has a 50Ω termination
resistor to ground.
n
Run the PScope software (Pscope.exe version K73,
or later) supplied with the DC890 or download it from
www.linear.com/software. Complete software doc-
umentation is available from the Help menu. Updates
can be downloaded from the Tools menu. Check for
updates periodically, as new features may be added.
The PScope software should recognize
-
and configure itself automatically.
n
Click the Collect button (Figure 2) to begin acquiring
the DC1996A
data. The Collect button then changes to Pause, which
can be used to stop data acquisition.
Figure 2. DC1996A PScope Screenshot
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dc1996afb
HARDWARE SETUP
DEMO MANUAL DC1996A
SIGNAL CONNECTIONS
J1 CLK IN: This input has a 50Ω termination resistor,
and is intended to be driven by a low jitter 10dBm sine or
square wave. To achieve the full AC performance of this
part, the clock jitter should be kept under 2ps. This input
is capacitively coupled so that the input clock can be either
0V to 3.3V or ±1.65V. This eliminates the need for level
shifting. To run at the maximum conversion rate, apply
the frequency specified in the Table 1.
J2 Ch2+ Input: In the single-ended configuration, this is
the channel 2 signal input. For differential operation, this
serves as the positive channel 2 signal input.
J3 Ch2– Input: This input is used only for differential
operation. It serves as the negative channel 2 signal input.
J4 Ch1+ Input: In the single-ended configuration, this is
the channel 1 signal input. For differential operation, this
serves as the positive channel 1 signal input.
J5 Ch1– Input: This input is used only for differential
operation. It serves as the negative channel 1 signal input.
J6 FPGA Program: Factory use only.
J7 JTAG: Factory use only.
JP1 +IN2 Coupling: Use this jumper to select AC- or DC-
coupling of the signal applied to J2.
is DC. At very low input frequencies, using AC-coupling
may degrade the distortion performance.
JP2 Mode: Use this jumper to select the signal input mode
for the channel 2 input of the LTC2323. The default setting
is Diff. The Diff setting accepts a single-ended signal from
J2 and applies it as a differential signal to channel 2 of the
LTC2323. The Bip setting accepts a single-ended signal
from J2 and applies it as a single-ended bipolar signal to
channel 2 of the LTC2323. The Uni setting also accepts a
single-ended signal from J2, but applies it as a unipolar
signal to channel 2 of the LTC2323.
The default setting
JP3 Data Out: Use this jumper to select the data output
format from the LTC2323. The default setting is CMOS.
The output data will not be valid if the jumper is moved
to the LVDS position unless the following changes have
been made:
Install 100Ω S0402 resistors at R26, 75, 76, 99
Reprogram the CPLD through J6 using the program
ming file LTC2323.pof found at:
http://www.linear.com/demo/DC1996A
Move JP3 to the LVDS position.
JP4 –IN2 Coupling: Use this jumper to select AC- or DCcoupling of the signal applied to J3. The default setting
is DC. At very low input frequencies, using AC-coupling
may degrade the distortion performance.
JP5 +IN1 Coupling: Use this jumper to select AC- or DCcoupling of the signal applied to J4. The default setting
is DC. At very low input frequencies, using AC-coupling
may degrade the distortion performance.
JP6 CM1: Use this jumper to set the DC bias point for the
signal applied to J4 when JP5 (+IN1 coupling) is in the
AC position. The default setting is ADC. The EXT setting
allows the use of an externally applied common mode
voltage applied at E1 (EXT_CM1).
JP7 CM2: Use this jumper to set the DC bias point for the
signal applied to J2 when JP1 (+IN2 coupling) is in the
AC position. The default setting is ADC. The EXT setting
allows the use of an externally applied common mode
voltage applied at E2 (EXT_CM2).
JP8 Mode: Use this jumper to select the signal input mode
for the channel 1 input of the LTC2323. The default setting
is Diff. The Diff setting accepts a single-ended signal from
J4 and applies it as a differential
LTC2323. The Bip setting accepts a single-ended signal
from J4 and applies it as a single-ended bipolar signal to
channel 1 of the LTC2323. The Uni setting also accepts a
single-ended signal from J4, but applies it as a unipolar
signal to channel 1 of the LTC2323.
signal to channel 1 of the
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DEMO MANUAL DC1996A
HARDWARE SETUP
JP9 –IN1 Coupling: Use this jumper to select AC- or DCcoupling of the signal applied to J5. The default setting
is DC. At very low input frequencies, using AC-coupling
may degrade the distortion performance.
JP10 VCCIO: Use this jumper to select the VCCIO sup
ply voltage. The default setting is 2.5V. The 1.8V setting
selects a 1.8V supply voltage.
JP11 VDD: Use this jumper to select the VDD supply voltage. The default setting is 5V. The 3.3V setting selects a
3.3V supply voltage.
JP12 EEPROM: Factory use only.
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JP13 OSC: Use this jumper to enable the onboard encode
clock source. The default setting
is OFF. The ON setting
energizes this source. Refer to the DC1996A schematic for
additional passive elements required to use the onboard
source.
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 20 C1, C2, C4, C5, C9, C11, C13, C18, C19,
C22, C23, C29, C37, C51, C52, C58, C59,
C82, C129, C130
2 24 C3, C6, C16, C17, C20, C21, C24-C26,
C28, C30, C34, C47-C50, C53, C54, C57,
C61, C70, C76, C79, C81
3 0 C7, C8, C10, C14, C27, C35, C36, C40,
C41, C60
4 2 C12, C41 CAP., NPO, 200pF, 16V, 5%, 0603 MURAA, GRM1885C1H201JA01D
5 12 C15, C32, C38, C39, C43, C45, C65, C67,
C68, C71, C74, C77
6 6 C31, C33, C55, C56, C106, C119 CAP., X5R, 4.7µF, 6.3V, 10%, 0603 AVX, 06036D475K AT2A
7 2 C42, C44 CAP., X5R, 2.2µF, 10V, 10%, 0603 MURATA, GRM188R61A225KE34D
8 1 C62 CAP., X7R, 47µF, 10V, 10%, 1210 MURATA, GRM32ER71A476KE15L
9 5 C63, C69, C72, C75, C78 CAP., X7R, 0.01µF, 6.3V, 10%, 0603 MURATA, GRM188R70J103KA01D
10 3 C64, C66, C73 CAP., X7R, 10µF, 10V, 10%, 0805 MURATA, GRM21BR71A106KE51L
11 1 C80 CAP., X5R, 3.3µF
12 28 C83-C104, C108, C122-C126 CAP., X7R, 0.1µF, 16V, 10%, 0402 NIC, NMC0402X7R104K16TRPF
13 1 C105 CAP., X5R, 47µF, 6.3V, 20%, 0805 TAIYO YUDEN, JMK212BJ476MG-T
14 3 C107, C120, C121 CAP., X7R, 0.01µF, 16V, 10%, 0402 NIC, NMC0402X7R103K16TRPF
15 1 C109 CAP., X7R, 1nF, 16V, 10%, 0402 AVX, 0402YC102K AT2A
16 3 C110, C111, C112 CAP., X7R, 22nF, 16V, 10%, 0402 AVX, 0402YC223K AT2A
17 2 C113, C128 CAP., X7R, 4.7nF, 16V, 10%, 0402 AVX, 0402YC472KAT2A
18 4 C114, C115, C116, C117 CAP., NP0, 10pF, 16V, 10%, 0402 AVX, 0402YA100KAT2A
19 1 C118 CAP., TANT, 470µF 10V, 20%, 7343 AVX, TPSE477M010R0050
20 1 C127 CAP., X7R, 2.2nF, 16V, 10%, 0402 AVX, 0402YC222KAT2A
21 4 D1, D2, D3, D4 DIODE, SCHOTTKY, 30V, 200mW SOD-323 DIODE INC., BAT54WS-7-F
22 9 E1-E3, E5, E8-E12 TEST POINT, TURRET, 0.064" MILL-MAX, 2308-2-00-80-00-00-07-0
23 3 E4, E6, E7 TEST POINT, TURRET, 0.094" MILL-MAX, 2501-2-00-80-00-00-07-0
CAP., X7R, 0.1µF, 16V, 10%, 0603 NIC, NMC0603X7R104K16TRPF
CAP., X5R, 10µF, 6.3V, 20%, 0603 NIC, NMC0603X5R106M6.3TRPF4KF
CAP., 0603 OPT
CAP., X7R, 1µF, 25V, 10%, 0603 TDK, C1608X7R1E105K
, 6.3V, 10%, 0603 AVX, 06036D335K AT2A
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