Linear Technology DC1281A Demo Manual

DESCRIPTION

DEMO MANUAL DC1281A

LTC2209

16-Bit, 160Msps/180Msps/

185Msps ADCs

Demonstration circuit 1281A supports a family of 16­bit 160Msps/180Msps/185Msps ADCs. Each assem-

®

bly features one of the following devices: LTC

2209,
LTC2209#3BC, or LTC2209#3CD high speed, high dynamic
range ADC.

Other members of this family include the LTC2208 which
is a 130Msps 16-bit version of this device. The LTC2208 is
supported on the DC854 (CMOS) and the DC996 (LVDS).
Lower speed, single-ended clock versions are also sup­ported on the DC918 and DC919.

Table 1. DC1281A Variants

DC1281A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY SUPPLY VOLTAGE

1281A-A LTC2209 16-Bit 160Msps 1MHz to 80MHz 3.3V

1281A-B LTC2209 16-Bit 160Msps 80MHz to 160MHz 3.3V

1281A-E LTC2209#3BCPBF 16-Bit 180Msps 1MHz to 80MHz 3.6V

1281A-F LTC2209#3BCPBF 16-Bit 180Msps 80MHz to 160MHz 3.6V

1281A-G LTC2209#3CDPBF 16-Bit 185Msps 1MHz to 80MHz 3.6V

1281A-H LTC2209#3CDPBF 16-Bit 185Msps 80MHz to 160MHz 3.6V

Several versions of the 1281A demo board supporting
the LTC2209 16-bit series of A/D converters are listed in
Table 1. Depending on the required resolution, sample rate
and input frequency, the DC1281A is supplied with the
appropriate ADC and with an optimized input circuit. The
circuitry on the analog inputs is optimized for analog input
frequencies below 80MHz or from 80MHz to 160MHz. For
higher input frequencies, contact the factory for support.

Design files for this circuit board are available at
http://www.linear.com/demo

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks; QuikEval
and PScope are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.

PERFORMANCE SUMMARY

PARAMETER CONDITION VALUE

Supply Voltage – LTC2209 Depending on Sampling Rate and the A/D Converter Provided, This Supply Must

Supply Voltage – LTC2209#3BC
and LTC2209#3CD

Analog Input Range Depending on PGA Pin Voltage 1.5V
Logic Input Voltages Minimum Logic High

Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load)

Sampling Frequency (Convert
Clock Frequency)

Convert Clock Level 50Ω Source Impedance, AC-Coupled or Ground Referenced (Convert Clock Input Is

Resolution See Table 1
Input Frequency Range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet

Provide Up to 700mA.
Depending on Sampling Rate and the A/D Converter Provided, This Supply Must

Provide Up to 700mA.

Maximum Logic Low

Minimum Logic Levels (100Ω Load)
See Table 1

Capacitor Coupled on Board and Terminated with 50Ω).

(TA = 25°C)

Optimized for 3.3V
[3.15V⇔3.45V min/max]

Optimized for 3.6V
[3.5V⇔3.78V min/max]

to 2.25V

P-P

2V

0.8V
350mV/2.1V Common Mode

247mV/2.1V Common Mode

⇔2.5V

2V

P-P

Square wave

P-P

Sine Wave or

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DEMO MANUAL DC1281A

QUICK START PROCEDURE

Demonstration circuit 1281A is easy to set up to evaluate
the performance of the LTC2209 A/D converters. Refer to
Figure 1 for proper measurement equipment setup and
follow the procedure below:

Setup

If a DC890 QuikEval™ II Data Acquisition and Collection
System was supplied with the DC1281A demonstration
circuit, follow the DC890 Quick Start Guide to install the
required software and for connecting the DC890 to the
DC1281A and to a PC.

3.6V OR 3.3V

RAND

PGA

DC1281A Demonstration Circuit Board Jumpers

The DC1281A demonstration circuit board should have
the following jumper settings as default: (as per Figure 1):

J2: Mode (VCC) 2’s Complement DCS Off

J3: SHDN: (Run) Dither (Off)

J4: RAND (Off) PGA 1x

J9: Unused Power Connector

MODE

ANALOG

INPUT

DITHER

SHDN

ENCODE CLOCK

Figure 1. DC1281A Setup (Zoom for Detail)

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QUICK START PROCEDURE

DEMO MANUAL DC1281A

Applying Power and Signals to the DC996
Demonstration Circuit

If a DC890 is used to acquire data from the DC1281A, the
DC890 must first be connected to a powered USB port
or provided an external 6V to 9V before applying 3.3V or

3.6V across the pins marked +3.3V and PWR GND on the
DC1281A. The LTC2209#3BC and LTC2209#3CD require

3.6V for proper operation. The DC1281A demonstration
circuit requires up to 700mA depending on the sampling
rate and the A/D converter supplied.

The DC890 data collection board is powered by the USB
cable and does not require an external power supply unless
it must be connected to the PC through an unpowered hub
in which case it must be supplied an external 6V to 9V on
turrets G7(+) and G1(–) or the adjacent 2.1mm power jack.

Analog Input Network

For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen­cies above 160MHz use demonstration circuit 1281A.
Other input networks may be more appropriate for input
frequencies less that 5MHz.

In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.

The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.

If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC-based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.

Encode Clock

Note: This is not a logic-compatible input. It is terminated
with 50Ω. Apply an encode clock to the SMA connector

on the DC1281A demonstration circuit board marked
J7 ENCODE INPUT. This is a transformer-coupled input,
terminated on the secondary side in two steps, 100Ω at
the transformer with final termination at the ADC at 100Ω.

For the best noise performance, the ENCODE INPUT must
be driven with a very low jitter source. When using a si­nusoidal generator, the amplitude should often be as large
as possible, up to 3V
on the clock and the analog input will improve the noise
performance by reducing the wideband noise power of the
signals. Data sheet FFT plots are taken with 10-pole LC
filters made by TTE (Los Angeles, CA) to suppress signal
generator harmonics, non-harmonically related spurs and
broadband noise. Low phase noise Agilent 8644B genera­tors are used with TTE bandpass filters for both the clock
input and the analog input.

Apply the analog input signal of interest to the SMA connec­tors on the DC1281A demonstration circuit board marked
J5 ANALOG INPUT. These inputs are capacitive coupled to
Balun transformers ETC1-1-13, or directly coupled through
Flux-coupled transformers ETC1-1T.

An internally generated conversion clock output is available
on J1 which could be collected via a logic analyzer, or other
data collection system if populated with a SAMTEC MEC8­150 type connector or collected by the DC890 QuikEvalII
Data Acquisition Board using PScope™ software.

Software

The DC890 is controlled by the PScope system software
provided or downloaded from the Linear Technology
website at
was provided, follow the DC890 Quick Start Guide and
the instructions below.

To start the data collection software if PScope.exe is in­stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.

http://www.linear.com/software/. If a DC890

or 15dBm. Using bandpass filters

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