Linear Technology LTM4636, Analog Devices LTM4636-1 User Manual

LTM4636

4.70V TO

VIN ≤ 5.5V, TIE VIN, INTVCC AND PV

40A

PINS NOT USED IN THIS CIRCUIT:
CLKOUT, GMON, PGOOD, PHMODE, PWM,
SW, TEST1, TEST2, TEST3, TEST4, TMON

OUTPUT CURRENT (A)

EFFICIENCY (%)

100

4636 TA01b

40

40A DC/DC µModule

Regulator

FeaTures

n

Stacked Inductor Acts as Heat Sink

n

Wide Input Voltage Range: 4.7V to 15V

n

0.6V to 3.3V Output Voltage Range

n

±1.3% Total DC Output Voltage Error Over Line,

Load and Temperature (–40°C to 125°C)

n

Differential Remote Sense Amplifier for Precision

Regulation

n

Current Mode Control/Fast Transient Response

n

Frequency Synchronization

n

Parallel Current Sharing (Up to 240A)

n

Internal or External Compensation

n

88% Efficiency (12VIN, 1V

n

Overcurrent Foldback Protection

n

16mm × 16mm × 7.07mm BGA Package

OUT

) at 40A

applicaTions

n

Telecom Servers and Networking Equipment

n

Industrial Equipment and Medical Systems

DescripTion

The LTM®4636 is a 40A step-down µModule (power
module) switching regulator with a stacked inductor as a
heat sink for quicker heat dissipation and cooler operation
in a small package. The exposed inductor permits direct
contact with airflow from any direction. The LTM4636
can deliver 40W (12V

IN

, 1V
40°C rise over the ambient temperature. Full-power 40W
is delivered, up to 83°C ambient and half-power 20W is
supported at 110°C ambient.

The LTM4636 operates at 92%, 90% and 88% efficiency,
delivering 15A, 30A and 40A, respectively, to a 1V load

). The µModule regulator is scalable such that four

(12V

IN

µModules in current sharing mode deliver 160W with only
40°C rise and 88% efficiency (12V
The LTM4636 is offered in a 16mm × 16mm × 7.07mm
BGA package.

L, LT, LT C , LT M , PolyPhase, Burst Mode, µModule, Linear Technology, LTpowerCAD and the
Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 5481178,
5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643.

, 40A, 200LFM) with only

OUT

IN

, 1V

, 400LFM).

OUT

Typical applicaTion

> 5.5V, THEN OPERATE AS SHOWN

V

IN

15V

+

100µF
25V

1V, 40A DC/DC µModule Regulator

TOGETHER, TIE RUNP TO GND.

PV

22µF
16V
×5

34.8k

OPTIONAL TEMP MONITOR

CC

15k

0.1µF

INTV

CC

CC

RUNC

RUNP
HIZREG

FREQ
TRACK/SS
MODE/PLLIN

SNSP1
SNSP2

COMPA
COMPB

TEMP

PV

CC

INTV

CC

V

INTV

IN

+

PV

CC

CC

LTM4636

V

OUT

+

V

OUTS1

–

V

OUTS1

V

TEMP–SGND

For more information www.linear.com/LTM4636

FB

PGND

7.5k

22µF

1V

+

470µF

6.3V
×3

4636 TA01a

V

OUT

1V,

100µF

6.3V
×4

95

90

85

80

75

70

0

12VIN , 1V

OUT

vs Output Current

20 30

15 25

5 10

Efficiency

35

4636f

1

LTM4636

TOP VIEW

×

SNSP2

TEST4 (FLOAT PIN)

absoluTe MaxiMuM raTings

(Note 1)

VIN, SW, HZBREG, RUNP ........................... –0.3V to 16V

V

.......................................................... –0.3V to 3.5V

OUT

PGOOD, RUNC, TMON, PV
FREQ, TRACK/SS, TEST1, TEST2, V

, MODE/PLLIN, PHMODE,

CC

OUTS1

–

, V

OUTS1

+

,

SNSP1, SNSP2, TEST3, TEST4 .....–0.3V to INTVCC (5V)

VFB, COMPA, COMPB (Note 7) .................. –0.3V to 2.7V

PVCC Additional Output Current ................ 0mA to 50mA

Note: PWM, CLKOUT, and GMON are outputs only.

pin conFiguraTion

+

TEST2

HIZREG

SNSP1

TRACK/SS

RUNC

PGOOD

SGND

CLKOUT

MODE/PLLIN

T

θ

–

V

OUTS1

1

2 3 4 5 6 7 8 9 10 11 12

A

B

C

D

E

F

G

TEST3

H

J

K

GND

L

M

= 125°C, θJA = 7.5°C/W, θ

JMAX

= DERIVED FROM 95mm × 76mm PCB WITH 6 LAYERS, WEIGHT = 3.95g

JA

θ VALUES DETERMINED PER JESD51-12

COMPB

V

OUTS1

COMPA

V

FB

INTV

FREQ

TEST1

144-LEAD (16mm

BGA PACKAGE

JCbottom

V

OUT

GND

CC

GND

PWM

V

IN

16mm × 7.07mm)

= 3°C/W, θ

TMON

NC

JCtop

GND

= 15°C/W, θ

TEMP+, TEMP– .......................................... –0.3V to 0.8V

INTVCC Peak Output Current (Note 6) ....................20mA

Internal Operating Temperature Range

(Note 2) .................................................. –40°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Reflow (Peak Body) Temperature ..........................250°C

PHASMD
RUNP
PV

CC

–

TEMP

+

TEMP
GMON

SW

= 12°C/W

JBA

Note: θJA = (θ

orDer inForMaTion

PART NUMBER PAD OR BALL FINISH

LTM4636EY#PBF

LTM4636IY#PBF –40°C to 125°C

• Device temperature grade is indicated by a label on the shipping

container.

• Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Terminal Finish Part Marking: www.linear.com/leadfree

• This product is not recommended for second side reflow. For more

JCbottom

+ θ

)||θ

; θ

JBA

JCtop

is Board to Ambient

JBA

http://www.linear.com/product/LTM4636#orderinfo

PART MARKING*

SAC305 (RoHS) LTM4636 BGA

• Recommended BGA PCB Assembly and Manufacturing Procedures:

www.linear.com/BGA-assy

• BGA Package and Tray Drawings: www.linear.com/packaging

• This product is moisture sensitive. For more information, go to:

www.linear.com/BGA-assy

PACKAGE

TYPE

MSL

RATING

TEMPERATURE RANGE
(SEE NOTE 2)DEVICE FINISH CODE

–40°C to 125°C

information, go to www.linear.com/BGA-assy

2

For more information www.linear.com/LTM4636

4636f

LTM4636

elecTrical characTerisTics

The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the Typical Application in Figure 20.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

V

OUT

V

OUT(DC)

Input DC Voltage VIN ≤ 5.5V, Tie VIN, INTVCC and PVCC Together, Tie RUNP

to GND

V

Range

OUT

DC Output Voltage, Total
Variation with Line and Load

C

= 22µF × 5

IN

= 100µF × 4 Ceramic, 470µF POSCAP × 3

C

OUT

= 40.2k, MODE_PLLIN = GND

R

FB

= 4.75V to 15V, I

V

IN

= 0A to 40A (Note 4)

OUT

Input Specifications

V

RUNC

V

RUNCHYS

V

RUNP

RUNC Pin On Threshold V
RUNC Pin On Hysteresis 150 mV
RUNP Pin On Threshold RUNP Pin Rising

Rising 1.1 1.22 1.35 V

RUNC

RUNP HYS RUNP Pin Hysteresis 60 mV
HIZREG HIZREG Input Threshold V
HIZREG HYS HIZREG Hysteresis V
I

Q(VIN)

I

S(VIN)

Input Supply Bias Current VIN = 12V, V

Input Supply Current VIN = 5V, V

= 12V, RUNC = 5V, RUNP = VIN, V

IN

= 12V, RUNC = 5V, RUNP = VIN, V

IN

= 1.5V, Burst Mode Operation, I

= 12V, V

V

IN

= 12V, V

V

IN

Shutdown, RUN = 0, V

= 12V, V

V

IN

OUT

= 1.5V, Pulse-Skipping Mode, I

OUT

= 1.5V, Switching Continuous, I

OUT

OUT

OUT

= 1.5V, I

IN

= 1.5V, I

= 12V

= 40A

OUT

OUT

= 40A

= 1.5V 2.3 V

OUT

= 1.5V 0.8 V

OUT

= 0.1A

OUT

= 0.1A

OUT

= 0.1A

OUT

Output Specifications

I

OUT(DC)

∆V

OUT

V
∆V

OUT

V
V

OUT(AC)

∆V

OUT(START)

t

START

∆V

OUTLS

t

SETTLE

I

OUTPK

(Line)

OUT

(Load)

OUT

Output Continuous Current
Range

Line Regulation Accuracy V

Load Regulation Accuracy V

Output Ripple Voltage

Turn-On Overshoot

Turn-On Time

Peak Deviation for Dynamic
Load

Settling Time for Dynamic
Load Step

Output Current Limit VIN = 12V, V

VIN = 12V, V

= 1.5V, VIN from 4.75V to 15V

OUT

= 0A

I

OUT

= 1.5V, I

OUT

I

= 0A, C

OUT

= 12V, V

V

IN

C

= 100µF × 4 Ceramic, 470µF × 3 POSCAP,

OUT

= 1.5V, I

V

OUT

C

= 100µF × 3 Ceramic, 470µF × 3 POSCAP,

OUT

No Load, TRACK/SS = 0.001µF, V

= 1.5V (Note 4) 0 40 A

OUT

= 0A to 40A, VIN = 12V (Note 4)

OUT

= 100µF × 3 Ceramic, 470µF × 3 POSCAP,

OUT

= 1.5V

OUT

= 0A, VIN = 12V, TRACK/SS = 0.1µF

OUT

= 12V

IN

Load: 0% to 50% to 0% of Full Load

= 100µF × 4 Ceramic, 470µF × 3 POSCAP,

C

OUT

= 12V, V

V

IN

= 1.5V, CFF = 22pF

OUT

Load: 0% to 50% to 0% of Full Load, VIN = 5V,

= 100µF × 4 Ceramic, 470µF × 3 POSCAP,

C

OUT

= 12V, V

V

IN

= 5V, V

V

IN

= 1.5V, CFF = 22pF

OUT

= 1.5V

OUT

= 1.5V

OUT

Control Section

V

FB

I

FB

V

OVL

I

TRACK/SS

t

ON(MIN)

R

FBHI

Voltage at VFB Pin I
Current at VFB Pin (Note 6) –30 –100 nA
Feedback Overvoltage

Lockout
Track Pin Soft-Start Pull-Up

Current
Minimum On-Time (Note 3) 100 ns
Resistor Between V

Pins

and V

FB

OUTS1

= 0A, V

OUT

Measure at V

OUT

OUTS1

= 1.5V

TRACK/SS = 0V, Default 750µs Turn on with TRACK/SS
Tied to INTV

CC

l

4.7 15 V

l

0.6 3.3 V

l

1.4805 1.5 1.5195 V

l

0.7 0.8 0.9 V

16
23

105

30

14.7

5.66

l

l

0.02 0.06 %/V

0.2 0.35 %

15 mV

5 mV

50 ms

45 mV

25 µs

54
54

l

0.594 0.600 0.606 V

l

5 7.5 10 %

1.1 1.35 1.6 µA

4.99 kΩ

mA
mA
mA

µA

P-P

4636f

A
A

A
A

For more information www.linear.com/LTM4636

3

LTM4636

elecTrical characTerisTics

The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 20.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Remote Sense Amplifier

A

V(VFB)

Path Gain Bandwidth Product (Note 5) 4 MHz

GBP V

FB

General Control or Monitor Pins

I

TMON

I

TMON(SLOPE)

V

PGOOD

V

PGL

t

PGOOD

I

PGOOD(OFF)

V

PG1(HYST)

Linear Regulator

INTV

CC

V

INTVCC

Load Reg INTVCC Load Regulation ICC = 0mA to 10mA 0.5 %

V

INTVCC

UVLO HYS Controller UVLO Hysteresis (Note 6) 0.5 V
PV

CC(UVLO)

PV

CC(HYS)

PV

CC

Oscillator and Phase-Locked Loop

f

OSC

I

FREQ

R

MODE/PLLIN

V

MODE/PLLIN

V

CLKOUT

PWM-CLKOUT PWM to Clockout Phase Delay

PWM/PWMEN Outputs

PWM PWM Output High Voltage

VFB Differential Gain (Note 6) 1 V/V

Temperature Monitor Current, TJ = 25°C Into 25kΩ
Temperature Monitor Current, T

Temperature Monitor Current Slope, R

= 150°C Into 25kΩ

J

= 25kΩ 0.144 µA/°C

TMON

PGOOD Trip Level VFB With Respect to Set Output

V

Ramping Negative

FB

V

Ramping Positive

FB

PGOOD Voltage Low I
V

High-to-Low Delay 65 µs

PGOOD

PGOOD Leakage Current V

= 2mA 0.2 0.4 V

PGOOD

= 5V –2 2 µA

PGOOD

PGOOD Trip Level

38 40.3 5844 µA

µA

–7.5

7.5

2.5 %

Hysteresis

Internal VCC Voltage Source 6V < VIN < 15V 5.3 5.5 5.7 V

Drivers and Power

PVCC Rising 3.5 3.8 4.1 V

MOSFETs UVLO
PVCC UVLO Hysteresis 0.45 V
Power Stage Bias 12V Input, PVCC Load = 50mm 5.0 V

Oscillator Frequency
V

= 0V

PHSMD

FREQ Pin Output Current V
MODE_PLLIN Input

= 30.1kΩ

R

FREQ

R

= 47.5kΩ

FREQ

R

= 54.9kΩ

FREQ

R

= 75.0kΩ

FREQ

Maximum Frequency
Minimum Frequency

= 0.8V 19 20 21 µA

FREQ

l
l

210
540
625
945

1.2

250
600
750

1.05

290
660
825

1.155

0.2

250 kΩ

kHz
kHz

kHz
MHz
MHz
MHz

Resistance
PLLIN Input Threshold V

Low Output Voltage
High Output Voltage

PWM Output Low Voltage

MODE/PLLIN

V

MODE/PLLIN

Verified Levels
Measurements on CLKOUT

V

PHSMD

V

PHSMD

V

PHSMD

V

PHSMD

V

PHSMD

I

LOAD

I

LOAD

Rising
Falling

2

1.2

0.2

5.2

= 0V
= 1/4 INTVCC
= Float
= 3/4 INTVCC
= INTV

CC

90
90

120

60

180

Deg
Deg
Deg
Deg
Deg

= 500µA 5.0 V
= –500µA 0.5 V

%
%

V
V

V
V

4

4636f

For more information www.linear.com/LTM4636

LTM4636

4636 G01

4636 G02

50mV/DIV

4636 G06

elecTrical characTerisTics

The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 20.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Temperature Diode

Diode V

F

Diode Forward Voltage I = 100µA, TEMP+ to TEMP

TC Temperature Coefficient

–

l

0.598 V
–2.0 mV/°C

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTM4636 is tested under pulsed load conditions such that
T

≈ TA. The LTM4636E is guaranteed to meet performance specifications

J

over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4636I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the

maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.

Note 3: The minimum on-time condition is specified for a peak-to-peak
inductor ripple current of ~40% of I
Information section)

Note 4: See output current derating
Note 5: Guaranteed by design.
Note 6: 100% tested at wafer level.

Typical perForMance characTerisTics

Efficiency vs Load Current
with 5V

100

95

90

85

EFFICIENCY (%)

80

75

70

0

IN

OUTPUT CURRENT (A)

3.3V

, 500kHz

OUT

, 500kHz

2.5V

OUT

, 450kHz

1.8V

OUT

, 425kHz

1.5V

OUT

, 300kHz

1.2V

OUT

, 300kHz

1V

OUT

2515 35

4020105 30

Efficiency vs Load Current with
8V

IN

100

95

90

85

3.3V

EFFICIENCY (%)

80

75

70

0

OUTPUT CURRENT (A)

OUT

2.5V

OUT

1.8V

OUT

1.5V

OUT

1.2V

OUT

1V

OUT

2515 35

, 700kHz
, 600kHz
, 500kHz
, 450kHz
, 400kHz

, 350kHz

Load. (See the Applications

MAX

, V

curves for different V

and TA.

IN

OUT

Efficiency vs Load Current with
12V

IN

100

95

90

85

3.3V

, 750kHz

EFFICIENCY (%)

80

75

4020105 30

70

0

OUTPUT CURRENT (A)

OUT

, 650kHz

2.5V

OUT

, 600kHz

1.8V

OUT

, 550kHz

1.5V

OUT

, 400kHz

1.2V

OUT

, 350kHz

1V

OUT

2515 35

4020105 30

4636 G03

Burst Mode Efficiency
vs Load Current

100

Burst Mode OPERATION

12V

V

IN

90

1.5V

V

OUT

80

70

EFFICIENCY (%)

60

50

40

0

OUTPUT CURRENT (A)

32 4

4636 G04

51

1V Transient Response 1.2V Transient Response

50mV/DIV

50µs/DIV

10A/DIV

18A/µs

STEP

12V TO 1V TRANSIENT RESPONSE

= 4 × 100µF CERAMIC, 3 × 470µF 2.5V

C

OUT

POSCAP 5mΩ

= 22pF, SW FREQ = 400kHz

C

FF

For more information www.linear.com/LTM4636

4636 G05

50µs/DIV

10A/DIV

18A/µs

STEP

12V TO 1.2V TRANSIENT RESPONSE

= 4 × 100µF CERAMIC, 3 × 470µF 2.5V

C

OUT

POSCAP 5mΩ

= 22pF, SW FREQ = 400kHz

C

FF

= 100pF

C

COMP

4636f

5

LTM4636

0.5V/DIV

4636 G11

0.5V/DIV

4636 G12

100µs/DIV

200mA/DIV

4636 G13

OUT

0.5V/DIV

4636 G14

100µs/DIV

200mA/DIV

4636 G15

COMP

50mV/DIV

4636 G07

COMP

100µs/DIV

4636 G08

COMP

100mV/DIV

4636 G09

COMP

100mV/DIV

4636 G10

Typical perForMance characTerisTics

1.5V Transient Response

50µs/DIV

10A/DIV

18A/µs

STEP

12V TO 1.5V TRANSIENT RESPONSE

= 4 × 100µF CERAMIC, 3 × 470µF 2.5V

C

OUT

POSCAP 5mΩ

= 22pF, SW FREQ = 425kHz

C

FF

= 100pF

C

3.3V Transient Response

100µs/DIV

10A/DIV

18A/µs

STEP

12V TO 3.3V TRANSIENT RESPONSE

= 6 × 100µF CERAMIC, 2 × 470µF 4V

C

OUT

POSCAP 5mΩ

= 22pF, SW FREQ = 750kHz

C

FF

= 100pF

C

50mV/DIV

10A/DIV

18A/µs

STEP

V

OUT

5V/DIV

1.8V Transient Response

12V TO 1.8V TRANSIENT RESPONSE

= 6 × 100µF CERAMIC, 2 × 470µF 4V

C

OUT

POSCAP 5mΩ

= 22pF, SW FREQ = 500kHz

C

FF

= 100pF

C

Start-Up with Soft-Start No-Load

V

IN

20ms/DIV

RUN PIN CAPACITOR = 0.1µF
TRACK/SS CAPACITOR = 0.1µF

= 4 × 100µF CERAMIC AND 3 × 470µF

C

OUT

POSCAP

100µs/DIV

10A/DIV

18A/µs

STEP

5V/DIV

2.5V Transient Response

12V TO 2.5V TRANSIENT RESPONSE

= 6 × 100µF CERAMIC, 2 × 470µF 4V

C

OUT

POSCAP 5mΩ

= 22pF, SW FREQ = 650kHz

C

FF

= 100pF

C

Start-Up with Soft-Start Full Load

V

OUT

V

IN

20ms/DIV

RUN PIN CAPACITOR = 0.1µF
TRACK/SS CAPACITOR = 0.1µF

= 4 × 100µF CERAMIC AND 3 × 470µF

C

OUT

POSCAP

6

40A Load Short-Circuit

V

OUT

0.5V/DIV

L

IN

Start-Up with 0.5V Output Pre-Bias

V

OUT

V

IN

5V/DIV

RUN PIN CAPACITOR = 0.1µF
TRACK/SS CAPACITOR = 0.1µF

= 4 × 100µF CERAMIC AND 3 × 470µF

C

For more information www.linear.com/LTM4636

20ms/DIV

No-Load Short-Circuit

V

OUT

0.5V/DIV

L

IN

4636f

pin FuncTions

LTM4636

PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.

V

(A1-A12, B1-B12, C1-C12, D1-D2, D11-D12): Power

OUT

Output Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance
between these pins and GND pins. Review Table 4.

MODE_PLLIN (H3): Forced Continuous Mode, Burst Mode
Operation, or

Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this

pin to INTV

to enable pulse-skipping mode

CC

of operation. Connect to ground to enable forced continuous
mode of operation. Floating this pin will enable Burst Mode
operation. A clock on this pin will enable synchronization
with forced continuous operation. See the Applications
Information section.

–

V

(D3): VOUT Sense Ground for the Remote Sense

OUTS1

Amplifier. This pin connects to the ground remote sense
point. Connect to ground when not used. See the Applica

-

tions Information section.

+

V

(D4): This pin should connect to V

OUTS1

connected to V

through a 4.99k resistor. This pin is

FB

OUT

and is

used to connect to a remote sense point of the load for
accurate voltage sensing. Either connect to remote sense
point or directly to V

. See the Applications Information

OUT

section for details.

COMPB (D5): Internal

compensation network provided that

coincides with proper stability utilizing the values in Table

5. Just connect this pin to COMPA for internal compensa

­tion. In parallel operation with other LTM4636 devices,
connect COMPA and COMPB pins together for internal
compensation, then connect all COMPA pins together.

GND (D6-D10, E6-E10, E12, F7, F8, F10-F12, G1-G2, G6
G10, H1, H10-H12, J1-J3, J8-J12, K1-K3, K9-K10, K12,
L1-L3, L9-L10, L12, M1-M3, M9-M12): Ground Pins for

Both Input and Output Returns.

PGOOD (E1): Output Voltage Power Good Indicator. Open­drain logic output is pulled to ground when the output
voltage exceeds a ±7.5% regulation window.

RUNC (E2): Run Control Pin. A voltage above 1.35V will
turn on the control section of the module. A 10k resistor
to ground is internal to the module for setting the RUN
pin threshold with a resistor to 5V, and allowing a pull­up resistor to PV

for enabling the device. See Figure 1

CC

Block Diagram.

TRACK/SS (E3): Output Voltage Tracking Pin and Soft-Start
Inputs. The pin has a 1.25µA pull-up current source. A
capacitor from this pin to ground

In tracking, the regulator output can be tracked to a

rate.

will set a soft-start ramp

different voltage. The different voltage is applied to a voltage
divider then to the slave output’s track pin. This voltage
divider is equal to the slave output’s feedback divider for
coincidental tracking. Default soft-start of 750µs with
TRACK/SS pin connected to INTV
tions Information

section. In PolyPhase® applications tie

pin. See the Applica-

CC

the TRACK/SS pins together.

(E4): The Negative Input of the Error Amplifier. Inter-

V

FB

nally, this pin

is connected to V

with a 4.99k precision

OUTS1

resistor. Different output voltages can be programmed
with an additional resistor between V
PolyPhase operation, tying the V

FB

and V

FB

OUTS1

pins together allows for

parallel operation. See the Applications Information section.

COMPA (E5): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. Tie all COMPA pins
together for parallel operation. This pin allows external
compensation. See the Applications Information section.

SNSP2 (F1): Current Sense Signal Path. Connect this pin
to SNSP1 (F2).

SNSP1 (F2): Current Sense Signal Path. Connect this pin
to SNSP2 (F

1). Both pins are used to calibrate current

sense matching and current limit at final test.

HIZREG

(F3): When this pin is pulled low the power stage

is disabled into high impedance. Tie this pin to V

for normal operation.

TV

CC

IN

–

. In

or in

For more information www.linear.com/LTM4636

4636f

7

LTM4636

pin FuncTions

SGND (F4, G4): Signal Ground Pin. Return ground path for
all analog and low power circuitry. Tie a single connection
to the output capacitor GND in the application. See layout
guidelines in Figure 18.

INTV

Circuitry in the LTM4636. INTV
when RUNC is activated high. Tie to V
≤ 5.5V, minimum V

(F6): Internal 5.5V LDO for Driving the Control

CC

is controlled and enabled

CC

, when 4.7V ≤ VIN

IN

= 4.2V.

IN

FREQ (G5): A resistor can be applied from this pin to
ground to set the operating frequency. This pin sources
20µA. See the Applications Information section.

PHASMD (G7): This pin can be voltage programmed to
change the phase relationship of the CLKOUT pin with
reference to the internal clock or an input synchronized
clock. The INTV

(5.5V) output can be voltage divided

CC

down to the PHASMD pin to set the particular phase. The
Electrical Characteristics show the different settings to
select a particular phase. See the Applications Informa

-

tion section.

RUNP (

can be connected to V
PV
RUNC. A 15k resistor

G8): This pin enables the PV

, or tie to ground when connecting

IN

to VIN ≤ 5.5V. RUNP needs to sequence up before

CC

from PVCC to RUNC with a 0.1µF

supply. This pin

CC

capacitor will provide enough delay. In parallel operation
with multiple LTM4636s, the resistor can be reduced in
value by N times and the 0.1µF can be increased N times.
See Applications Information section. RUNP can be used to
set the minimum UVLO with a voltage divider. See Figure 1.

NC (G9): No Connection.

(F9): 5V Power Output and Power for Internal Power

PV

CC

MOSFET Drivers. The regulator can power 50mA of external
sourcing for additional use. Place a 22µF ceramic filter
capacitor on this pin to ground. When V

< 5.5V, tie VIN

IN

and PV
GND. If V

together along with INTVCC. Then tie RUNP to

CC

> 5.5V then operate PVCC regulator as normal.

IN

See the Typical Application examples.

+

TEMP

(G12): Temperature Monitor. An internal diode

connected NPN transistor. See the Applications Informa­tion section.

–

TEMP

(G11): Low Side of the Internal Temperature

Monitor.

CLKOUT (G3): Clock out signal that can be phase selected
to the main internal clock or synchronized clock using
the PHASMD pin. CLKOUT can be used for multiphase
applications. See the Applications Information section.

TEST1 (H4), TEST2 (F5), TEST3 (H2), TEST4 (E

11), GMON

(H9):These are test pins used in the final production test

of the part. Leave floating.

(H5-H6, J4-J7, K4-K8, L4-L8, M4-M8): Power Input

V

IN

Pins. Apply input voltage between these pins and GND
pins. Recommend placing input decoupling capacitance
directly between V

and GND pins.

IN

PWM (H7): PWM output that drives the power stage.
Primarily used for test, but can be monitored in debug
or testing.

TMON (H8): Temperature Monitor Pin. Internal temperature
monitor, varies from 1V at 25°C to 1.44V at 150°C, disables
power stage at 150°C. If this feature is not desired, then
tie the TMON pin to GND.

SW (L11, K11): These are pin connections to the internal
switch node for test evaluation and monitoring. An R-C
snubber can be placed from the switch pins to GND to
eliminate any high frequency ringing. See the Applications
Information section.

8

4636f

For more information www.linear.com/LTM4636

block DiagraM

15k = (PV

V

UVLO

4636 F01

0.85V

IN

EXAMPLE

– 0.85V) (15K)

IN

(V

R1 =

CC

PV

15k

22µF

R1

RUNP

,

IN

CC

AND PV

CC

≤ 5.5V, TIE TO V

IN

INTV

VIN4.70V TO 15V

V

TOGETHER,TIE RUNP

IN

C

+

IN

V

> 5.5V

IN

OPERATE AS SHOWN

TO GND. V

2.2Ω, 0805

LTM4636

2200pF

1.5V AT 40A

OUT

V

OUT

C

+

GND

OUT

V

SW

2.2Ω

SNSP2

–

TEMP

+

TEMP

–

TEMP

GMON

TMON

–

+

PWM

OUTS1

OUTS1

V

V

TEST4

> 0.85V = ON

IN

V

5V

CC

PV

INTERNAL 5V REGULATOR

1µF

1µF

M1

TDRV

PWM LOGIC CONTOL,

POWER MOSFET DRIVERS,

POWER MOSFET

0.18µH

CONTROL

OPTIMIZED

DEAD TIME

PWM INPUT

PWM

CURRENT

DIFF

FB

V

POWER CONTROL

–

NETWORK

DCR SENSE

M2

BDRV

150C DISABLE

DISABLE

SENSE

AMP

SNS

SNSP2

TEMP MONITOR

CURRENT

+
–

–

–
+

SGND

CONNECT

TO SNSP1

IMON

40µA AT 25°C

60µA AT 150°C

SNSP1

SNS

SNSP1 AND SNSP2

CONNECTED AT PCB

24.9k

0.1µF

470pFQ1

1%

4.99k 0.5%

Figure 1. Simplified LTM4636 Block Diagram

TEST1

TEST2

INTV

CC

TEST3

PV

10k

CC

10k

PGOOD

RUNC

0.1µF

15k

≥ 5V

PV

> 1.35V = ON

UVLO EXAMPLE

– 1.35V)(10k)/1.35V

DISABLES AT ~ 3.75V

CC

10pF

1%

COMP

INTERNAL

FREQ

FREQ

R

TRACK/SS

40k

SOFT-START

PHMODE

HIZREG

CLKOUT

SGND

COMPB

COMPA

CC

INTV

CC

MODE_PLLIN

INTVCC 5.5V

4.7µF

SNSP1

FB

V

R6

3.32k

4636f

For more information www.linear.com/LTM4636

9

LTM4636

Decoupling requireMenTs

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

C

IN

C

OUT

External Input Capacitor Requirement
(V

= 4.70V to 16V, V

IN

External Output Capacitor Requirement
(V

= 4.70V to 16V, V

IN

OUT

OUT

= 1.5V)

= 1.5V)

I

OUT

(See Table 4)

I

OUT

TA = 25°C. Use Figure 1 configuration.

= 40A, 6 × 22µF Ceramic X7R Capacitors

= 40A (See Table 4) 1000 µF

100 µF

operaTion

Power Module Description

The LTM4636 is a high efficiency regulator that can provide
a 40A output with few external input and output capacitors.
This module provides precisely regulated output voltages
programmable via external resistors from 0.6V DC to 3.3V
DC over a 4.70V to 15V input range. The Typical Applica
tion schematic is shown in Figure 20.

The LTM4636 has an integrated constant-frequency cur­rent mode
protection

regulator, power MOSFETs, 0.18µH inductor,

circuitry, 5V regulator and other supporting
discrete components. The switching frequency range is
from 250kHz to 770kHz, and the typical operating frequency
is 400kHz. For switching noise-sensitive applications, it
can be externally synchronized from 250kHz to 800kHz,
subject to minimum on-time limitations and limiting the
inductor ripple current to less than 40% of maximum
output current.

A single resistor is used to program the frequency. See
the Applications Information section.

With current mode control
compensation,
ity margins
range

of output capacitors, even with all ceramic output

the LTM4636 module has sufficient stabil-

and good transient performance with a wide

and internal feedback loop

capacitors. An option has been provided for external loop

®

compensation. LTpowerCAD

can be used to optimize
the external compensation option. See the Applications
Information section.

Current mode control provides cycle-by-cycle fast current
limit in an overcurrent condition. An internal overvoltage

monitor feedback pin referred will attempt to protect the
output voltage in the event of an overvoltage >10%. The
top MOSFET is turned off and the bottom MOSFET is
turned on until the output is cleared.

Pulling the RUNC pin below 1.1V forces the regulator con
troller into

­programming

a shutdown state. The TRACK/SS pin is used for

the output voltage ramp and voltage tracking

during start-up. See the Applications Information section.

The LTM4636 is internally compensated to be stable over
all operating conditions. Table 5 provides a guideline for
input and output capacitances for several operating condi
tions. LTpowerCAD is available for transient and stability
analysis. This tool can be used to optimize the regulators
loop response.

A remote sense amplifier is provided for accurately sensing
output voltages at the load point.

Multiphase operation can be easily employed with the
internal clock source or a synchronization clock applied
to the MODE/PLLIN input using an external clock source,
and connecting the CLKOUT pins. See the Applications
Information section. Review Figure 4.

High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE_PLLIN
pin. These light load features will accommodate battery
operation. Efficiency graphs
eration

A

in the Typical Performance Characteristics section.

+

TEMP

and TEMP– pins are provided to allow the internal

are provided for light load op-

device temperature to be monitored using an onboard
diode connected NPN transistor.

-

-

10

4636f

For more information www.linear.com/LTM4636

applicaTions inForMaTion

4.99k+ R

FB

4.99k /N

0.6V

V

I

LTM4636

The typical LTM4636 application circuit is shown in
Figure 20. External component selection

is primarily
determined by the maximum load current and output
voltage. Refer to Table 5 for specific external capacitor
requirements for particular applications.

to V

V

IN

There are restrictions in the V

Step-Down Ratios

OUT

IN

to V

step-down ratio that

OUT

can be achieved for a given input voltage. The maximum
duty cycle is 94% typical at 500kHz operation. The V

minimum dropout is a function of load current and

V

OUT

IN

to

operation at very low input voltage and high duty cycle
applications. At very low duty cycles the minimum 100ns
on-time must be maintained. See the Frequency Adjust

-

ment section and temperature derating curves.

Output V

oltage Programming

The PWM controller has an internal 0.6V ±1% reference
voltage. As shown in the Block Diagram, a 4.99k internal

+

feedback resistor connects the V
gether. When
and V

OUTS1

the remote sensing is used, then V

–

are connected to the remote V

points. If no remote sense the V

OUTS1

OUTS1

and VFB pins to-

OUTS1

and GND

OUT

+

connects to V

+

OUT

The output voltage will default to 0.6V with no feedback
resistor. Adding

a resistor R

from VFB to ground pro-

FB

grams the output voltage:

V

= 0.6V •

OUT

Table 1. VFB Resistor Table vs Various Output Voltages

V

(V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3

OUT

(k) Open 7.5 4.99 3.32 2.49 1.58 1.1

R

FB

FB

R

For parallel operation of N LTM4636s, the following
equation can be used to solve for R

FB

:

Or use V

on one channel and connect all feedback

OUTS1

pins together utilizing a single feedback resistor.

Tie the VFB pins together for each parallel output. The COMP
pins must be tied together also. See Typical Application
section examples.

Input Capacitors

The LTM4636 module should be connected to a low AC­impedance DC source. Additional input capacitors are
needed for the RMS input ripple current rating. The I
equation which follows can be used to calculate the input
capacitor requirement. Typically 22µF X7R ceramics are a
good choice with RMS ripple current ratings of ~4A each.
A 47µF to 100µF surface mount aluminum electrolytic bulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedance is compromised by long inductive leads, traces
or not enough source capacitance. If low impedance power
planes are used, then this bulk capacitor is not needed.

For a buck converter, the switching duty cycle can be
estimated as:

.

D=

OUT

V

IN

Without considering the inductor ripple current, for each
output the RMS current of the input capacitor can be
estimated as:

I

CIN(RMS)

OUT(MAX )

=

η%

• D•(1–D)

where η% is the estimated efficiency of the power mod­ule. The bulk capacitor can be a switcher-rated aluminum
electrolytic capacitor or a Polymer capacitor.

CIN(RMS)

RFB=

V

OUT

–1

For more information www.linear.com/LTM4636

4636f

11

LTM4636

applicaTions inForMaTion

Output Capacitors

The LTM4636 is designed for low output voltage ripple
noise. The bulk output capacitors defined as C
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient require
ments. C
ESR Polymer capacitor or ceramic capacitors. The typi­cal output
Additional
designer if further reduction of output ripple or dynamic
transient spikes is required. Table 5 shows a matrix of dif
ferent output
the voltage droop and overshoot during a 15A/µs tran­sient. The
bulk

capacitance to optimize the transient performance.
Stability criteria are considered in the Table 5 matrix, and
LTpowerCAD is available for stability analysis. Multiphase
operation will reduce effective output ripple as a function
of the number of phases. Application Note 77 discusses
this noise reduction versus output ripple current cancel
lation, but the output capacitance should be considered
carefully
LTpowerCAD can be used to calculate the output ripple
reduction as the number
by N times. External loop compensation can be used for
transient response optimization.

can be a low ESR tantalum capacitor, low

OUT

capacitance range is from 400µF to 1000µF.

output filtering may be required by the system

voltages and output capacitors to minimize

table optimizes total equivalent ESR and total

as a function of stability and transient response.

of implemented phases increases

OUT

are

-

-

-

age current is greater than the load requirement. As the
COMP

A voltage drops below 0.5V, the burst comparator
trips, causing the internal sleep line to go high and turn
off both power MOSFETs.

In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMPA to rise, the internal
sleep line goes low, and the LTM4636 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.

Pulse-Skipping Mode Operation

In applications where low output ripple and high efficiency
at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4636 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTV
operation. With pulse-skipping mode at light load, the
internal current comparator may remain tripped for several
cycles, thus skipping operation cycles. This mode has
lower ripple than Burst Mode operation and maintains a
higher frequency operation than Burst Mode operation.

Forced Continuous Operation

enables pulse-skipping

CC

Burst Mode Operation

The LTM4636 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enable Burst Mode operation, simply float the MODE_PLLIN
pin. During Burst Mode operation, the peak current of the
inductor is set to approximately 30% of the maximum
peak current value in normal operation even though the
voltage at the COMPA pin indicates a lower value. The
voltage at the COMPA pin drops when the inductor’s aver

12

For more information www.linear.com/LTM4636

-

In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to ground. In this
mode, inductor current is allowed to reverse during low
output loads, the COMPA voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled

prevented from reversing until the LTM4636’s output

is
voltage is in regulation.

and inductor current

4636f

FREQV

applicaTions inForMaTion

0.9

RMS INPUT RIPPLE CURRENT

0.60

LTM4636

Multiphase Operation

For outputs that demand more than 40A of load current,
multiple LTM4636 devices can be paralleled to provide more
output current without increasing input and output ripple
voltage. The MODE_PLLIN pin allows the LTM4636 to be
synchronized to an external clock and the internal phase­locked loop allows the LTM4636 to lock onto input clock
phase as well. The FREQ resistor is selected for normal
frequency, then the incoming clock can synchronize the
device over the specified range.

A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca

­pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used. See Application Note 77.

The LTM4636 device is an inherently current mode con­trolled device,

so parallel modules will have good current

sharing. This will balance the thermals in the design. Tie the

COMPA to COMPB and then tie the COMPA pins together,

pins of each LTM4636 together to share the cur-

tie V

FB

rent evenly. Figure 21 shows a schematic of the parallel
design.

For external compensation and parallel operation

only tie COMP A pins together with external compensation.

Input RMS Ripple Current Cancellation

Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can­cellation mathematical
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases
(see Figure 2).

PLL, Frequency Adjustment and Synchronization

The LTM4636 switching frequency is set by a resistor (R
from the FREQ pin to signal ground. A 20µA current

) flowing out of the FREQ pin through R

I

(

FREQ

a voltage on the FREQ pin. R

R

FREQ

=

20µA

derivations are presented, and a

FREQ

develops

FREQ

can be calculated as:

FREQ

)

1 PHASE

0.55

0.50

0.45

0.40

0.35

0.30

0.25

DC LOAD CURRENT

0.20

0.15

0.10

0.05

0

Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases)

2 PHASE
3 PHASE
4 PHASE
6 PHASE

DUTY CYCLE (V

OUT/VIN

0.70.650.60.550.50.450.40.350.30.250.20.150.1

0.8

0.85

)

0.75

4636 F02

4636f

For more information www.linear.com/LTM4636

13

LTM4636

FREQUENCY (kHz)

1300

4636 F03

1.8

applicaTions inForMaTion

The relationship of FREQV voltage to switching frequency
is shown in Figure 3. For low output voltages from 0.6V
to 1.2V, 350kHz operation is an optimal frequency for the
best power conversion efficiency while maintaining the
inductor current to about 45% of maximum load current.
For output voltages from 1.5V to 1.8V, 500kHz is optimal.
For output voltages from 2.5V to 3.3V, 700kHz is optimal.
See efficiency graphs for optimal frequency set point. Limit
the 2.5V and 3.3V outputs to 35A.

The LTM4636 can be synchronized from 200kHz to
1200kHz with an input clock that has a high level above
2V and a low level below 1.2V. See the Typical Applica

­tions section for synchronization examples. The LTM4636
minimum on-time is limited to approximately 100ns. The
on-time can be calculated as:

t

ON(MIN)

=

1

FREQ



•







V

OUT



V



IN

The LTM4636's CLKOUT pin phase difference from V

OUT

can be programmed by applying a voltage to the PHMODE
pin. This voltage can be programmed using the 5.5V INTV

CC

pin. Most of the phase selections can be programmed by
either grounding, floating, or tying this pin to INTV
60 degree phase shift will require 3/4 INTV

and can be

CC

programmed with a voltage divider from the INTV

CC

CC

. The

pin.
See Figure 4 for phase programming and the 2 to 6 phase
connections. See Figure 27 for example design.

Output Voltage Tracking

Output voltage tracking can be programmed externally
using the

TRACK

/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4636 uses an

1100

900

700

500

300

100

0.4

0.6 0.8

Figure 3. FREQ Voltage to Switching Frequency

1.2 1.6

1.0 1.4
V

(V)

FREQ

14

4636f

For more information www.linear.com/LTM4636

applicaTions inForMaTion

LTM4636

accurate 4.99k resistor internally for the top feedback
resistor. Figure 5 shows an example of coincident tracking.

V

TRACK

V

TRACK

V



OUT(SLAVE)

= 1+





is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.6V, or the internal

4.99k
R

TA



• V

TRACK





reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue
to its final value from the slave’s regulation point (see
Figure 6). Voltage tracking is disabled when V

PHASE SELECTION

V

CLKOUT

PHASE

90
90

120

60

180

PHMODE

(V)

0

1/4 INTV

FLOAT

3/4 INTV

INTV

MODE_PLLIN

CC

CC

CC

MODE_PLLIN

PHMODE

CC

0 PHASE

LTM4636

PHMODE

CLKOUT

OUT

PHASE

0
0
0
0
0

V

TRACK

0 PHASE

LTM4636

OUT

is

CLKOUT

V

OUT

more than 0.6V. R

in Figure 5 will be equal to RFB for

TA

coincident tracking.

The

TRACK

/SS pin of the master can be controlled by an
external ramp or the soft-start function of that regulator can
be used to develop that master ramp. The LTM4636 can
be used as a master by setting the ramp rate on its track
pin using a soft-start capacitor. A 1.25µA current source
is used to charge the soft-start capacitor. The following
equation can be used:

TWO PHASE

FLOATINTV

THREE PHASE

120 PHASE

MODE_PLLIN

LTM4636

PHMODE

t

SOFT-START

MODE_PLLIN

PHMODE

CLKOUT

V

OUT

= 0.6V •

180 PHASE

LTM4636

MODE_PLLIN

PHMODE

CLKOUT

V

OUT

240 PHASE






LTM4636

1.25µA

CLKOUT



C

SS





V

OUT

INTV

CC

R2
10k

R1

30.1k

3/4 INTV

3/4 INTV

MODE_PLLIN

PHMODE

MODE_PLLIN

CC

PHMODE

MODE_PLLIN

PHMODE

CC

0 PHASE

LTM4636

LTM4636

180 PHASE

LTM4636

CLKOUT

V

0 PHASE

FOUR PHASE

CLKOUT

V

OUT

SIX PHASE

60 PHASE

MODE_PLLIN

LTM4636

PHMODE

240 PHASE

MODE_PLLIN

LTM4636

PHMODE

OUT

CLKOUT

V

CLKOUT

V

OUT

OUT

90 PHASE

MODE_PLLIN

LTM4636

PHMODE

3/4 INTV

CC

3/4 INTV

CC

Figure 4. Phase Selection Examples

MODE_PLLIN

PHMODE

CLKOUT

V

OUT

CLKOUT

V

OUT

180 PHASE

LTM4636

3/4 INTV

3/4 INTV

CLKOUT

V

OUT

CC

CC

MODE_PLLIN

PHMODE

120 PHASE

MODE_PLLIN

LTM4636

PHMODE

300 PHASE

MODE_PLLIN

LTM4636

PHMODE

270 PHASE

LTM4636

CLKOUT

V

OUT

CLKOUT

V

OUT

CLKOUT

V

OUT

4636 F04

4636f

For more information www.linear.com/LTM4636

15

LTM4636

4.7V TO

5V PV

applicaTions inForMaTion

15V

INTV

+

100µF
25V

22µF
16V
×5

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

22µF
16V
×5

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

5V

PV

CC1

15k

INTV

0.1µF

40.2k

1.5V
R7B

15k

0.1µF

4.99k

R7A

4.99k

INTV

40.2k

5V

PV

CC2

C

SS

0.1µF

CC1

CC2

COMPA
COMPB
TRACK/SS

RUNC
RUNP
HIZREG

FREQ

TEMP+TEMP–SNSP1 SNSP2 SGND

COMPA
COMPB
TRACK/SS

RUNC
RUNP
HIZREG

FREQ

TEMP+TEMP–SNSP1 SNSP2 SGND

V

IN

V

IN

INTV

INTV

INTV

CC1

CC

LTM4636

CC2

CC

LTM4636

PV

PV

CC1

22µF

CC

TMON

SW

V

OUT

V

OUTS1

V

OUTS1

V

PGND

5V PV

CC

TMON

SW

V

OUT

V

OUTS1

V

OUTS1

V

PGND

VOLTAGE OUT TEMP MONITOR

2.2Ω, 0805

1.5V AT 40A

+

+

470µF

6.3V

+

470µF

–

FB

CC2

+

–

FB

6.3V

R

FB

3.32k

22µF

VOLTAGE OUT TEMP MONITOR

2.2Ω, 0805

1.2V AT 40A

+

470µF

6.3V

+

470µF

6.3V

R

FB1

4.99k

4636 F05

+

+

2200pF

470µF

6.3V

100µF ×4

6.3V

2200pF

470µF

6.3V

100µF ×4

6.3V

16

PINS NOT USED IN THIS CIRCUIT:
CLKOUT, GMON, MODE/PLLIN, PGOOD,
PHMODE, PWM, TEST1, TEST2, TEST3, TEST4

Figure 5. Dual Outputs (1.5V and 1.2V) with Tracking

MASTER OUTPUT

OUTPUT

VOLTAGE

SLAVE OUTPUT

TIME

4636 F06

Figure 6. Output Voltage Coincident Tracking Characteristics

For more information www.linear.com/LTM4636

4636f

applicaTions inForMaTion

MR

SR

0.6V

FB1

TB

k • T

η •k

I

LTM4636

Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the master’s
TRACK/SS pin. As mentioned above, the TRACK/SS pin
has a control range from 0V to 0.6V. The master’s
TRACK/SS pin
output slew rate in volts/time. The equation:

• 4.99k = R

slew rate is directly equal to the master’s

TB

where MR is the master’s output slew rate and SR is the
slave’s output slew rate in volts/time. When coincident
tracking is desired, then MR and SR are equal, thus R
is equal to 4.99k. R

RTA=

V

FB

4.99k

is derived from equation:

TA

FB

–

V

TRACK

R

V

+

R

TB

where VFB is the feedback voltage reference of the regula­tor, and V

is 0.6V. Since RTB is equal to the 4.99k

TRACK

top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then R

= V

V

FB

. Therefore RTB = 4.99k, and RTA = 4.99k in

TRACK

is equal to RFB with

TA

Figure 5.

In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. R

can be solved for when SR

TB

is slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach its final value before the master output.

For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then

= 6.19k. Solve for RTA to equal 4.22k.

R

TB

For applications that do not require tracking or sequenc­ing, simply tie the TRACK/SS pin to INTV

to let RUN

CC

control the turn on/off. When the RUN pin is below
its threshold or the V

undervoltage lockout, then

IN

TRACK/SS is pulled low.

output voltage will force the top MOSFET off and the bottom
MOSFET on until the condition is cleared. Foldback current
limiting is disabled during soft-start or tracking start-up.

Temperature Monitoring

Measuring the absolute temperature of a diode is pos
sible due
and

to the relationship between current, voltage

temperature described by the classic diode equation:

ID= IS•e






V

D

η •V






T

or

I

V

= η• VT•In

D

D

I

S

where ID is the diode current, VD is the diode voltage, η
is the ideality factor (typically close to 1.0) and I

S

tion current) is a process dependent parameter. V
be broken out to:

VT=

q

where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. V
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable tem
perature sensors.
the extrapolated current through a diode junction when

The IS term in the previous equation is

the diode has zero volts across the terminals. The I
varies from process to process, varies with temperature,
and by definition must always be less than I

. Combining

D

all of the constants into one term:

KD=

q

(satura-

can

T

is

T

term

S

-

-

Default Overcurrent and Overvoltage Protection

The LTM4636 has overcurrent protection (OCP) in a
short circuit. The internal current comparator threshold
folds back during

a short to reduce the output current. An

overvoltage condition (OVP) above 10% of the regulated

For more information www.linear.com/LTM4636

where KD = 8.62−5, and knowing ln(ID/IS) is always posi­tive because I

is always greater than IS, leaves us with

D

the equation that:

VD= T KELVIN

( )

•KD•In

D

I

S

4636f

17

LTM4636

I

S

I

S

198µV

K

∆V

D

applicaTions inForMaTion

where VD appears to increase with temperature. It is com­mon knowledge

that a silicon diode biased with a current
source has an approximate –2mV/°C temperature rela­tionship (Figure 7), which is
fact, the I
ln(I

D/IS

term increases with temperature, reducing the

S

) absolute value yielding an approximate –2mV/°C

at odds with the equation. In

composite diode voltage slope.

0.8

0.7

0.6

0.5

DIODE VOLTAGE (V)

0.4

0.3
–50 –25

Figure 7. Diode Voltage VD vs Temperature T(°C)

0

TEMPERATURE (°C)

50

25

75

100

125

4636 F07

Solving for temperature:

T(KELVIN)=

D

(°CELSIUS)= T(KELVIN)–273.15

K'

where

300°K = 27°C

means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198μV per Kelvin of the junction with
a zero intercept at 0 Kelvin.

The diode connected NPN transistor at the TEMP pin can be
used to monitor the internal temperature of the LTM4636.

V

IN

12 1 40 200 LFM

V

OUT

I

OUT

AIR FLOW

To obtain a linear voltage proportional to temperature
we cancel the I
remove the I

variable in the natural logarithm term to

S

dependency from the equation 1. This is

S

accomplished by measuring the diode voltage at two cur­rents I

, and I2, where I1=10•I2) and subtracting we get:

1

∆VD= T(KELVIN)•KD•IN

1

– T(KELVIN)•KD•IN

I

2

I

Combining like terms, then simplifying the natural log
terms yields:

∆V

= T(KELVIN)•KD•lN(10)

D

and redefining constant

K'D= KD•IN(10) =

yields

∆V

= K'D•T(KELVIN)

D

8a.

V

IN

12 3.3 35 200 LFM

Figure 8. The Tw o Images Show the LTM4636 Operating at 1V at
40A and 3.3V at 35A from a 12V Input. Both Images Reflect Only
a 40°C to 45°C Rise Above Ambient at Full Load Current with
200LFM.

V

OUT

8b.

I

OUT

AIR FLOW

4636f

18

For more information www.linear.com/LTM4636

applicaTions inForMaTion

LTM4636

Overtemperature Protection

The LTM4636 has an overtemperature enhanced protec­tion features
The

overtemperature feature uses the TMON pin voltage
to monitor temperature. This pin varies from 0.994V at
25°C to 1.494 at 150°C, and will tripoff at ≥ 150°C. Tying
TMON to ground disable this feature.

RUNP and RUNC Enable

The RUNP pin is used to enable the 5V PV
powers the power driver stage and enables the power
stage ~1ms later. The RUNC pin is used to enable the
control section that drives the power stage. The RUNP
needs to be enabled first, and then RUNC. RUNP has a

0.85V threshold and can be connected to the input volt
age and RUNC has a 1.35V threshold and a 10k resistor
to ground. See the Block Diagram for details. A 0.1µF
capacitor from the RUNC pin to ground is used to set the
delay for RUNC enable.

INTV

CC

The LTM4636 has an internal low dropout regulator from

called INTVCC. This regulator output has a 4.7μF

V

IN

ceramic capacitor internal. This regulator powers the
control section. The PV
to the power MOSFET driver
can be used from this 5V PV
The input supply source resistance needs to be very low
in order to minimize IR drops when operating from a 5V
input source. Depending on the output voltage and current,
the input supply can source large current,and PV
regulator needs a minimum 4.70V supply. Additional
input capacitance maybe needed for 5V inputs to limit
the input droop.

Stability Compensation

The LTM4636 has already been internally compensated
when COMPB is tied to COMPA for all output voltages.
Table 5 is provided for most application requirements.
For specific optimized requirements, disconnect COMPB
from COMPA, and use LTpowerCAD to perform specific
control loop optimization. Then select the desired external
compensation and output capacitance for the desired
optimized response.

that can be used to detect overtemperature.

supply that

CC

and PVCC Regulators

5V regulator supplies power

CC

stage. An additional 50mA

supply for other needs.

CC

CC

-

5V

SW Pins

The SW pins are generally for testing purposes by moni
toring these
out

switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combina
tion is used called a snubber circuit. The resistor will
dampen
only affect the high frequency
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usually easier to predict. It combines the power path board
inductance in combination with the MOSFET interconnect
bond wire inductance.

First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre
quency can be measured for its value. The impedance Z
can be calculated:

Z(L) = 2πfL,

where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: Z(C) = 1/(2πfC). These values are a good
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss. A recommended value of 2.2Ω in
series with 2200pF to ground should work for most ap
plications. See Figure 19 for guideline. The 2.2Ω resistor
should be an 0805 size.

Thermal Considerations and Output Current Derating

The

thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those
eters defined by JESD51-12 and are intended for use with
finite
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients
in found in JESD51-12 (“Guidelines for Reporting and
Using Electronic Package Thermal Information”).

pins. These pins can also be used to dampen

the resonance and the capacitor is chosen to

ringing across

element analysis (FEA) software modeling tools that

the resistor.

-

-

-

-

param-

4636f

For more information www.linear.com/LTM4636

19

LTM4636

applicaTions inForMaTion

Many designers may opt to use laboratory equipment and a
test vehicle such as the demo board to predict the µModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
section are, in and of themselves, not relevant to providing
guidance of thermal performance; instead, the derating
curves provided in this data sheet can be used in a man
ner that
application

yields insight and guidance pertaining to one’s

usage, and can be adapted to correlate thermal

-

performance to one’s own application.

The Pin Configuration section gives four thermal coeffi
cients explicitly

defined in JESD51-12; these coefficients

-

are quoted or paraphrased below:

, the thermal resistance from junction to ambient, is

1. θ

JA

the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo

­sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.

2. θ

JCbottom

, the thermal resistance from junction to the

bottom of the product case, is determined with all of

component power dissipation flowing through the

the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack

-

age, but there is always heat flow out into the ambient
environment.

As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.

3 θ

, the thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ

JCbottom

, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.

, the thermal resistance from junction to the printed

4 θ

JB

circuit board, is the junction-to-board thermal resistance
where almost all of the heat flows through the bottom
of the µModule package and into the board, and is really
the sum of the θ

JCbottom

and the thermal resistance of
the bottom of the part through the solder joints and a
portion of the board. The board temperature is measured
a specified distance from the package.

A graphical representation of the aforementioned ther
mal resistances

is given in Figure 9; blue resistances are

-

contained within the µModule regulator, whereas green
resistances are external to the µModule package.

20

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION A

µMODULE DEVICE

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

For more information www.linear.com/LTM4636

CASE (BOTTOM)-TO-BOARD

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4637 F09

t

4636f

applicaTions inForMaTion

LTM4636

As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal op
erating conditions
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally con­duct exclusively
the bottom of the µModule package—as the standard
defines
power loss is thermally dissipated in both directions away
from the package—granted, in the absence of a heat sink
and airflow, a majority of the heat flow is into the board.

Within the LTM4636, be aware there are multiple power
devices and components dissipating power, with a con
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—but
also not ignoring practical realities—an approach has been
taken using FEA software modeling along with laboratory
testing in a controlled-environment chamber to reason
ably define and correlate the thermal resistance values
supplied
used to accurately build the mechanical geometry of the
LTM4636 and the specified PCB with all of the correct
material coefficients along with accurate power loss source
definitions; (2) this model simulates a software-defined
JEDEC environment consistent with JESD51-12 to predict
power loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-defined
thermal resistance values; (3) the model and FEA software
is used to evaluate the LTM4636 with heat sink and airflow;
(4) having solved for and analyzed these thermal resis
tance values and simulated various operating conditions
in the software model, a thorough laboratory evaluation
replicates the simulated conditions with thermocouples
within a controlled-environment chamber while operat
ing the device at the same power loss as that which was
simulated.
yields the set of derating curves shown in this data sheet.

for θ

in this data sheet: (1) Initially, FEA software is

The outcome of this process and due diligence

of a µModule regulator. For example,

through the top or exclusively through

JCtop

and θ

JCbottom

, respectively. In practice,

-

-

-

-

-

The power loss curves in Figures 10 to 12 can be used
in coordination with the load current derating curves
in Figures 13 to 18 for calculating an approximate θ
thermal resistance for the LTM4636 with various airflow
conditions
temperature and can be increased with a multiplicative
factor according to the junction temperature, which is
~1.4 for 120°C. The derating curves are plotted with
the output current starting at 40A and the ambient
temperature increased. The output voltages are 1V,

2.5V and 3.3V. These are chosen to include the lower,
middle and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived
from several temperature measurements in a controlled
temperature chamber along with thermal modeling
analysis. The junction temperatures are monitored while
ambient temperature is increased with and without airflow.
The power lo
is factored into the derating curves. The junctions are
maintained at ~125°C maximum while lowering output
current or power with increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The monitored junction temperature of 125°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example, in
Figure 14 the load current is derated to ~30A at ~94°C
with no air flow and the power loss for the 12V to 1.0V
at 30A output
with the ~3W room temperature loss from the 12V to

1.0V power loss curve at 30A, and the 1.4 multiplying
factor at 125°C junction. If the 94°C ambient temperature
is subtracted from the 125°C junction temperature, then
the difference of 31°C divided by 4.2W equals a 7.4 °C/W

thermal resistance. Table 2 specifies a 7.2° C/W value

θ

JA

which is very close. Tables 2, 3, and 4 provide equivalent
thermal resistances for 1V, 1.5V and 3.3V outputs with
and without airflow and heat sinking. The derived thermal
resistances in Tables 2 thru 4 for the various conditions
can be multiplied by the calculated power loss as a function
of ambient temperature to derive temperature rise above

. The p

ower loss curves are taken at room

ss increase with ambient temperature change

is about

4.2W. The 4.2W loss is calculated

JA

For more information www.linear.com/LTM4636

4636f

21

LTM4636

LOAD CURRENT (A)

45

120

4636 F13

45

120

4636 F14

LOAD CURRENT (A)

45

120

4636 F15

LOAD CURRENT (A)

45

120

4636 F16

LOAD CURRENT (A)

45

120

4636 F17

LOAD CURRENT (A)

45

120

4636 F18

LOAD CURRENT (A)

4636 F10

4636 F11

4636 F12

applicaTions inForMaTion

8

7

6

5

4

WATTS (W)

3

2

1

0

3.3V

, 500kHz

OUT

, 500kHz

2.5V

OUT

, 450kHz

1.8V

OUT

, 425kHz

1.5V

OUT

, 300kHz

1.2V

OUT

, 300kHz

1V

OUT

0

20105 30

OUTPUT CURRENT (A)

2515 4035

Figure 10. 5V Input Power Loss Curves

40

35

30

25

20

15

10

5

0

0LFM
200LFM
400LFM

0

4020 80 100

AMBIENT TEMPERATURE (°C)

60

8

7

6

5

4

WATTS (W)

3

2

1

0

3.3V

, 700kHz

OUT

, 600kHz

2.5V

OUT

, 500kHz

1.8V

OUT

, 450kHz

1.5V

OUT

, 400kHz

1.2V

OUT

, 350kHz

1V

OUT

0

OUTPUT CURRENT (A)

2515 4035

20105 30

Figure 11.8V Input Power Loss Curves

40

35

30

25

20

15

10

5

0

0LFM
200LFM
400LFM

0

4020 80 100

AMBIENT TEMPERATURE (°C)

60

7

6

5

4

3

WATTS (W)

2

1

0

3.3V

, 750kHz

OUT

, 650kHz

2.5V

OUT

, 600kHz

1.8V

OUT

, 550kHz

1.5V

OUT

, 350kHz

1V

OUT

0

20105 30 35

OUTPUT CURRENT (A)

2515 40

Figure 12. 12V Input Power Loss Curves

40

35

30

25

20

15

10

5

0

0LFM
200LFM
400LFM

0

4020 80 100

AMBIENT TEMPERATURE (°C)

60

Figure 13. 5VIN, 1V
Curve

40

35

30

25

20

15

10

5

0

0LFM
200LFM
400LFM

0

4020 80 100

AMBIENT TEMPERATURE (°C)

Figure 16. 12VIN, 1.5V
Curve

60

OUT

Derate

Derate

OUT

Figure 14. 12V
Curve

40

35

30

25

20

15

10

5

0

0LFM
200LFM
400LFM

0

4020 80 100

AMBIENT TEMPERATURE (°C)

Figure 17. 5VIN, 3.3V
Curve

IN

, 1V

60

OUT

OUT

Derate

Derate

Figure 15. 5VIN, 1.5V
Curve

40

35

30

25

20

15

10

5

0

0LFM
200LFM
400LFM

0

4020 80 100

AMBIENT TEMPERATURE (°C)

Figure 18. 12VIN, 3.3V
Curve

Derate

OUT

60

Derate

OUT

4636f

22

For more information www.linear.com/LTM4636

applicaTions inForMaTion

Table 2. 1V Output

DERATING

CURVE V

Figures 13, 14 5V, 12V Figure 10, 12 0 7.2

Figures 13, 14 5V, 12V Figure 10, 12 200 5.4

Figures 13, 14 5V, 12V Figure 10, 12 400 4.8

Table 3. 1.5 V Output

DERATING

CURVE V

Figures 15, 16 5V, 12V Figure 10, 12 0 7. 4

Figures 15, 16 5V, 12V Figure 10, 12 200 5.0

Figures 15, 16 5V, 12V Figure 10, 12 400 4.5

Table 4. 3.3V

DERATING

CURVE V

Figures 17, 18 12V Figure 10, 12 0 7. 4

Figures 17, 18 12V Figure 10, 12 200 5.0

Figures 17, 18 12V Figure 10, 12 400 4.4

IN

IN

IN

POWER LOSS

CURVE

POWER LOSS

CURVE

POWER LOSS

CURVE

LTM4636

AIRFLOW

(LFM) θJA (°C/W)

AIRFLOW

(LFM) θJA (°C/W)

AIRFLOW

(LFM) θJA (°C/W)

Table 5. LTM4636 Capacitor Matrix, All Below Parameters are Typical and are Dependent on Board Layout

Taiyo Yuden 22µF, 25V C3216X7S0J226M Panasonic SP 470µF 2.5V EEFGX0E471R Sanyo 20SEP100M 100µF 20V

Murata 22µF, 25V GRM31CR61C226KE15L Sanyo POSCAP 470µF 2R5 2R5TPD470M5

Murata 100µF, 6.3V GRM32ER60J107M Sanyo POSCAP 470µF 6.3V 6TPD470M5

AVX 100µF, 6.3V 18126D107MAT

Taiyo Yuden 220µF, 4V

Murata 220µF, 4V

4636f

For more information www.linear.com/LTM4636

23

LTM4636

applicaTions inForMaTion

V

OUT

(V)

0.9

0.9

0.9
1
1
1

1.2

1.2

1.2

1.5

1.5

1.5

1.8

1.8

1.8

2.5

2.5

3.3

3.3

CIN

(CERAMIC)

22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF × 5
22µF
22µF × 5
22µF × 5
22µF × 5

22µF

22µF

22µF

CIN

(BULK)

100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF

× 5

100µF 100µF, 470µF None 220 5,12 95 197 24 15 2.49 500
100µF
100µF

100µF

× 5

100µF

× 5

100µF 100µF, 470µF None 220 5,12 140 280 30 15 1.1 750 (12V)

× 5

C

(CERAMIC) AND

OUT1

C

(CERAMIC AND BULK)

OUT2

100µF × 8, 470µF × 3
220µF × 6, 470µF × 2

220µF × 10, 470µF
100µF × 4, 470µF × 3
100µF × 6, 470µF × 2
100µF × 8, 470µF × 2
100µF × 4, 470µF × 3
100µF × 6, 470µF × 2

220µF × 4, 470µF
100µF × 4, 470µF × 3
100µF × 4, 470µF × 2

100µF × 3, 470µF

100µF × 3, 470µF

220µF × 2, 470µF

100µF × 2, 470µF

100µF × 6, 470µF

100µF × 4

VIN

C

C

FF

COMP

(pf)

(pf)

22 100 5,12 38 76 40 15 10 350

68 100 5,12 40 80 30 15 10 350
None 220 5,12 40 80 30 15 10 350
None 100 5,12 40 80 30 15 7.5 350
None 100 5,12 50 100 30 15 7.5 350
None 150 5,12 55 105 30 15 7.5 350
None 100 5,12 45 90 35 15 4.99 350
None 100 5,12 45 90 35 15 4.99 400
None 100 5,12 50 104 30 15 4.99 400
None 100 5,12 60 120 35 15 3.32 425
None 100 5,12 56 110 35 15 3.32 425
None 100 5,12 75 150 25 15 3.32 425
None 220 5,12 90 180 25 15 2.49 500

None 220 5,12 90 180 20 15 2.49 500
None 220 5,12 120 220 30 15 1.58 650 (12V)

22 220 5,12 87 174 40 15 1.58 650 (12V)

220 220 5,12 130 260 25 15 1.1 750 (12V)

DROOP

(V)

(mV)

PEAK-TO-PEAK

DEVIATION

(mV)

RECOVERY

TIME (µs)

LOAD

STEP

(A/µs)

RFB

(kΩ)

FREQ
(kHz)

500 (5V)

500 (5V)

500 (5V)

500 (5V)

Table 6. Enhanced External Compensation, Lower Voltage Transition During Transient. Careful Power Integrity Layout Required

V

CIN

OUT

(V)

(CERAMIC)

0.9

22µF × 5

1

22µF × 5

1.2

22µF × 5

†

Bulk capacitance is optional if VIN has very low input impedance.

C

is a capacitor from V

FF

24

CIN

(BULK)

100µF
100µF
100µF

OUT

C

(CERAMIC) AND

OUT1

†

C

(CERAMIC AND BULK)

OUT2

220µF × 10, 470µF
220µF × 10, 470µF
220µF × 10, 470µF

to VFB pin.

C

FF

(pf)

47 100 5, 12 25 50 26 15 10 350 15k 1000
47 100 5, 12 28 55 25 15 7.5 350 15k 1000
47 100 5, 12 33 66 30 15 4.99 350 15k 1000

For more information www.linear.com/LTM4636

C

VIN

COMP

(pf)

DROOP

(V)

(mV)

PEAK-TO-PEAK

DEVIATION (mV)

RECOVERY

TIME (µs)

LOAD

STEP

(A/µs)

RFB

(kΩ)

FREQ

(kHz)

R

COMP

(k)

C

COMP

(pF)

4636f

applicaTions inForMaTion

LTM4636

ambient, thus maximum junction temperature. Room
temperature power loss curves are provided in Figures 10
through 12. The printed circuit board is a 1.6mm thick six
layer board with two ounce copper for all layers and one
ounce copper for the two inner layers. The PCB dimensions
are 95mm × 76mm.

Safety Considerations

The LTM4636 does not provide galvanic isolation from V
to V
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure.

The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET
fails, then turning it off will not resolve the overvoltage,
thus the internal bottom MOSFET will turn on indefinitely
trying to protect the load. Under this fault condition, the
input voltage will source very large currents to ground
through the failed internal top MOSFET and enabled internal
bottom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker
us
LTM4636 has the enhanced over temperature protection
discussed earlier and schematic applications will be shown
at the end of the data sheet.

. There is no internal fuse. If required, a slow blow

OUT

ed as a secondary fault protector in this situation. The

IN

can be

Layout Checklist/Example

The high integration of the LTM4636 makes the PCB
board layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout
considerations are still necessary.

• Use large PCB copper areas for high current paths,
including V
PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output
capacitors next to the V
minimize high frequency noise.

• Place a dedicated power ground layer underneath the
unit.

• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.

• Do not put vias directly on the pad, unless they are
capped or plated over.

• Place test points on signal pins for testing.

• Use a separated SGND ground copper area for

components connected to signal pins. Connect the
SGND to GND underneath the unit.

• For parallel modules, tie the
Use an internal layer to closely connect these pins
together.

, GND and V

IN

. It helps to minimize the

OUT

, GND and V

IN

COMP and

OUT

VFB pins together.

pins to

• R

Figure 19 gives a good example of the recommended layout.

For more information www.linear.com/LTM4636

and C

SNUB

switch ringing.

(2.2Ω and 2200pf) values to dampen

SNUB

4636f

25

LTM4636

4636 F19

applicaTions inForMaTion

1

2 3 4 5 6 7

RUNC

RUNCTK/SS

C

R

C

OUT1

V

GND

GND

OUT

C

OUT2

A

B

C

D

E

F

G

H

J

K

L

M

V

OUT

8 9 10 11 12

FB

R

VCC CAP

P

R

FREQ

C

IN2

V

IN

C

IN1

C

IN4

C

IN3

V

OUT

C

OUT3COUT4

TEMP SENSE

GND

R
0805

C
0603

GND

SNUB

SNUB

Figure 19. Recommended PCB Layout

26

4636f

For more information www.linear.com/LTM4636

Typical applicaTions

4.70V TO 14V

4

VIN ≤ 5.5V, TIE VIN, INTVCC AND PVCC TOGETHER, TIE RUNP TO GND.

> 5.5V, THEN OPERATE AS SHOWN

V

IN

22µF
16V

+

100µF
25V

×5

5V PV

0.1µF

OPTIONAL TEMP MONITOR

CC

15k

34.8k

SGND

100pF

SGND

INTV

V

COMPA
COMPB

TK/SS

C

SS

0.1µF

RUNC
RUNP
HIZREG

CC

FREQ
MODE/PLLIN

TEMP+TEMP–SNSP1 SNSP2 SGND

IN

INTV

INTV

CC

CC

LTM4636

SGND

LTM4636

5V PV

CC

2.2Ω, 0805

+

470µF

6.3V

R

FB2

7.5k

22µF

1V AT 40A

+

470µF

6.3V

2200pF

+

470µF

6.3V

100µF ×

6.3V

PV

CC

SW

V

OUT

+

V

OUTS1

–

V

OUTS1

V

FB

PGND

4636 F20

PINS NOT USED IN CIRCUIT LTM4636:
CLKOUT, GMON, PGOOD, PHMODE, PWM,
TEST1, TEST2, TEST3, TEST4, TMON

Figure 20. 4.70V to 15V, 1V at 40A Design

For more information www.linear.com/LTM4636

4636f

27

LTM4636

80A

V

≤ 5.5V, TIE VIN, INTV

AND PVCC TOGETHER, TIE RUNP TO GND.

Typical applicaTions

4.70V TO 15V

+

4.70V TO 15V

IN

> 5.5V, THEN OPERATE AS SHOWN

V

IN

22µF
16V
×4

100pF

100µF
25V

34.8k

SGND

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

22µF

5V, PV

16V
×4

0.47µF

FOR TELEMETRY READBACK ICs

CC2

7.5k
TK/SS

C

SS

0.22µF
RUNC

RUNP

34.8k

SGND

OPTIONAL TEMP MONITOR

COMP
TK/SS

RUNC

RUNP
INTV
INTV

COMP

INTV

CC

INTV

CC1

V

INTV

IN

CC

COMPA
COMPB
TK/SS

RUNC
RUNP
HIZREG

CC1

PHMODE

CC1

FREQ
MODE/PLLIN
CLKOUT

CLK

TEMP+TEMP–SNSP1 SNSP2 SGND

V

COMPA
COMPB
TK/SS

SGND

RUNC
RUNP
HIZREG

CC2

FREQ

MODE/PLLIN

CLK

+

TEMP

TEMP–SNSP1 SNSP2 SGND

PINS NOT USED IN CIRCUIT LTM4636 U1:
GMON, PGOOD, PWM, TEST1, TEST2, TEST3,
TEST4, V

OSNS1

U1

LTM4636

INTV

CC2

INTV

IN

CC

U2

LTM4636

SGND

SGND

5V PV

CC1

PV

CC

TMON

SW

V

OUT

–

V

OUTS1

V

FB

PGND

5V PV

CC2

PV

CC

TMON

SW

V

OUT

+

V

OUTS1

–

V

OUTS1

V

FB

PGND

22µF

VOLTAGE OUT
TEMP MONITOR

2.2Ω, 0805

+

470µF

6.3V

V

FB

22µF

VOLTAGE OUT TEMP MONITOR

2.2Ω, 0805

470µF

6.3V

V

FB

R

FB2

7.5k

2200pF

+

2200pF

++

4636 F21

470µF

6.3V

470µF

6.3V

100µF

6.3V
×4

1V

100µF

6.3V
×4

28

PINS NOT USED IN CIRCUIT LTM4636 U2:
GMON, PGOOD, PHMODE, PWM, TEST1, TEST2,
TEST3, TEST4

Figure 21. 2-Phase 1V, 80A Regulator Design

4636f

For more information www.linear.com/LTM4636

Typical applicaTions

INTV

5V PV

PINS NOT USED IN CIRCUIT LTM4636 U1:
GMON
TEST2, TEST3, TEST4, V

PINS NOT USED IN CIRCUIT LTM4636 U2:
GMON
TEST2, TEST3, TEST4

PINS NOT USED IN CIRCUIT LTM4636 U3:
GMON
TEST2, TEST3, TEST4, V

SGND

LTM4636

, PGOOD, PHMODE, PWM, TEST1,

, PGOOD, PHMODE, PWM, TEST1,

, PGOOD, PHMODE, PWM, TEST1,

OUTS1

OUTS1

7V TO 12V

, CLKOUT

22µF
16V
×3

+

100µF
25V

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

22µF
16V
×3

0.47µF

+

100µF
25V

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

22µF
16V
×3

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

34.8k

SGND

4.99k

0.22µF
RUNC

RUNP

34.8k

SGND

100pF

TK/SS

C

SS

34.8k

SGND

COMP
TK/SS

INTV

COMP

INTV

COMP
TK/SS

INTV

RUNC
RUNP

CC1

CLK

SGND

CC2

CLK

CLK1

RUNC
RUNP

CC3

CLK1

CC1

INTV

V

IN

COMPA
COMPB
TK/SS

RUNC
RUNP
HIZREG

FREQ
MODE/PLLIN
CLKOUT

TEMP+TEMP–SNSP1 SNSP2 SGND

COMPA
COMPB
TK/SS

RUNC
RUNP
HIZREG

FREQ
MODE/PLLIN
CLKOUT

TEMP+TEMP–SNSP1 SNSP2 SGND

COMPA
COMPB
TK/SS

RUNC
RUNP
HIZREG

FREQ
MODE/PLLIN

TEMP+TEMP–SNSP1 SNSP2 SGND

CC

U1

LTM4636

INTV

CC2

INTV

V

IN

CC

U2

LTM4636

INTV

CC3

V

INTV

IN

CC

U3

LTM4636

SGND

SGND

CC1

PV

CC

TMON

2.2Ω, 0805

SW

V

OUT

–

V

OUTS1

PGND

5V PV

PV

CC

TMON

V

OUTS1

V

OUTS1

PGND

5V PV

PV

CC

TMON

V

OUTS1

PGND

VFBV

CC2

SW

+

V

OUT

–

V

FB

CC3

SW

V

OUT

–

V

FBVFB

V

OUTS1

FB

2.2Ω, 0805

V

FB

R

10k

2.2Ω, 0805

V

4636 F22

22µF

VOLTAGE OUT
TEMP MONITOR

2200pF

+

–

22µF

VOLTAGE OUT TEMP MONITOR

2200pF

+

470µF

6.3V

FB3

22µF

VOLTAGE OUT
TEMP MONITOR

2200pF

+

–

OUTS1

470µF

6.3V

0.9V AT 120A

+

470µF

6.3V

+

470µF

6.3V

+

470µF

6.3V

470µF

6.3V

100µF

6.3V
×3

100µF

6.3V
×3

100µF

100µF

6.3V
×3

Figure 22. 3-Phase 0.9V at 120A with Protection

For more information www.linear.com/LTM4636

4636f

29

LTM4636

EFFICIENCY (%)

95

4636 F25

120

40mV DROOP

FURTHER OPTIMIZATION CAN BE UTILIZED WITH EXTERNAL COMP

Typical applicaTions

Figure 23. Demo Board

90

85

80

75

70

65

60

0

10

50 60 70 90 100 1104020 30 80

LOAD CURRENT (A)

Figure 25. Efficiency, 12V to 0.9V at 120A

4636 F23

30A/µs STEP

Figure 24. Thermal Plot, 12V to 0.9V at
120A, 400LFM Air Flow

V

OUT

INTERNAL COMPENSATION

= 6X 470µf 6V TPD POS CAP, 12 × 100µf CERAMIC

C

OUT

4636 F26

Figure 26. 12V to 0.9V 30A/µs Load Step

4636 F24

30

4636f

For more information www.linear.com/LTM4636

Typical applicaTions

7V TO 14V

INTV

5V PV

FOR TELEMETRY READBACK ICs

SGND

LTM4636

22µF
16V

+

150µF
35V

PINS NOT USED IN CIRCUIT U2:
PGOOD, TEST1, TEST2, TEST3,
TEST4, V

PINS NOT USED IN CIRCUIT U1:
PGOOD, TEST1, TEST2, TEST3,
TEST4, GMON

PINS NOT USED IN CIRCUIT U3:
PGOOD, TEST1, TEST2, TEST3,
TEST4, V

PINS NOT USED IN CIRCUIT U4:
PGOOD, TEST1, TEST2, TEST3,
TEST4, V

22µF
16V

22µF
16V

22µF
16V

12V

12V

12V

OUTS1

OUTS1

OUTS1

, GMON

22µF
16V

22µF
16V

, GMON

22µF
16V

, GMON

22µF
16V

22µF
16V

22µF
16V

22µF

22µF

16V

16V

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

22µF
16V

5V

PV

CC1

4.99k

0.47µF

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

22µF
16V

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

22µF
16V

OPTIONAL TEMP MONITOR

22µF
16V

34.8k

SGND

100pf

SGND

34.8k

SGND

C

0.47µF

SGND

34.8k

SGND

34.8k

SGND

COMP
TK/SS

INTV

COMP

SS

INTV

COMP

TK/SS

INTV

COMP
TK/SS

INTV

V

COMPA
COMPB
TK/SS

RUNC

RUNC

RUNP

RUNP
HIZREG

CC2

PHMODE
FREQ
MODE/PLLIN

CLK1
CLK2

CLKOUT

TEMP+TEMP–SNSP1 SNSP2 SGND

V

COMPA
COMPB

TK/SS

TK/SS

RUNC

RUNC

RUNP

RUNP
HIZREG

CC1

PHMODE
FREQ
MODE/PLLIN

CLK1

CLKOUT

TEMP+TEMP–SNSP1 SNSP2 SGND

V

COMPA
COMPB
TK/SS

RUNC

RUNC

RUNP

RUNP
HIZREG

CC3

PHMODE
FREQ
MODE/PLLIN

CLK2
CLK3

CLKOUT

TEMP+TEMP–SNSP1 SNSP2 SGND

V

COMPA
COMPB
TK/SS

RUNC

RUNC

RUNP

RUNP
HIZREG

CC4

PHMODE
FREQ
MODE/PLLIN

CLK3

TEMP+TEMP–SNSP1 SNSP2 SGND

CC2

INTV

IN

CC

U2

LTM4636

SGND

INTV

CC1

INTV

IN

CC

U1

LTM4636

SGND

INTV

CC3

INTV

IN

CC

U3

LTM4636

SGND

INTV

CC4

INTV

IN

CC

U4

LTM4636

CC2

VOLTAGE OUT
TEMP MONITOR

PWM2 TP

GND_SNS

V

FB

VOLTAGE OUT
TEMP MONITOR

PWM1 TP

R

FB

2.5k

SGND

VOLTAGE OUT
TEMP MONITOR

PWM3 TP

2200pf

GND_SNS

VOLTAGE OUT
TEMP MONITOR

PWM4 TP

2200pf

GND_SNS

V

FB

22µf

2200pf

470µF

+

6.3V

SGND

22µf

2200pf

470µF

+

6.3V

SGND

GND_SNS

22µf

470µF

6.3V

+

SGND

22µf

470µF

+

6.3V

SGND

470µF

+

6.3V

POWER GND

0.9V AT 160A

470µF

+

6.3V

470µF

6.3V

+

470µF

6.3V

+

100µF

6.3V
×4

100µF

6.3V
×4

100µF

6.3V
×4

100µF

6.3V
×4

4636 F27

PV

CC

TMON

PWM

2.2Ω, 0805

SW

V

OUT

V

OUT

–

V

OUTS1

V

FB

PGND

5V PV

CC1

PV

CC

TMON

PWM

2.2Ω, 0805

SW

V

OUT

+

V

OUTS1

–

V

OUTS1

V

FB

V

FB

PGND

5V PV

CC3

PV

CC

TMON

PWM

2.2Ω, 0805

SW

V

OUT

–

V

OUTS1

V

FBVFB

PGND

5V PV

CC4

PV

CC

TMON

PWM

2.2Ω, 0805

SW

V

OUT

–

V

OUTS1

V

FB

PGND

Figure 2 7. Four Phase 0.9V at 160A Design

For more information www.linear.com/LTM4636

4636f

31

LTM4636

EFFICIENCY (%)

95

4636 F30

160

31mV DROOP

FURTHER OPTIMIZATION CAN BE UTILIZED WITH EXTERNAL COMP

Typical applicaTions

Figure 28. DC2448A Demo Board

4636 F28

4636 F29

Figure 29. Thermal Plot, 12V to 0.9V at
160A, 400LFM Air Flow

90

85

80

75

70

65

60

0

60 1004020 80

LOAD CURRENT (A)

120 140

V

OUT

30A/µs STEP

INTERNAL COMPENSATION

= 8X 470µF 6V TPD POS CAP, 16 × 100µF CERAMIC

C

OUT

4636 F31

Figure 31. 12 to 0.9V 30A/µs Load Step

Figure 30. Efficiency, 12V to 0.9V at 160A

32

4636f

For more information www.linear.com/LTM4636

LTM4636

package DescripTion

PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.

Pin Assignment Table (Arranged by Pin Number)

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

A1 V

A2 V

A3 V

A4 V

A5 V

A6 V

A7 V

A8 V

A9 V

A10 V

A11 V

A12 V

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

B1 V

B2 V

B3 V

B4 V

B5 V

B6 V

B7 V

B8 V

B9 V

B10 V

B11 V

B12 V

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

C1 V

C2 V

C3 V

C4 V

C5 V

C6 V

C7 V

C8 V

C9 V

C10 V

C11 V

C12 V

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

D1 V

D2 V

D3 V

D4 V

D5 COMPB E5 COMPA F5 TEST2

D6 GND E6 GND F6 INTV

D7 GND E7 GND F7 GND

D8 GND E8 GND F8 GND

D9 GND E9 GND F9 PVCC

D10 GND E10 GND F10 GND

D11 V

D12 V

OUT

OUT

–

OUTS1

+

OUTS1

OUT

E12 GND F12 GND

OUT

E1 PGOOD F1 SNSP2

E2 RUNC F2 SNSP1

E3 TRACK/SS F3 HIZREG

E4 V

FB

F4 SGND

E11 TEST 4 F11 GND

CC

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND

G2 GND H2 TEST3 J2 GND K2 GND L2 GND M2 GND

G3 CLKOUT H3 MODE/PLLIN J3 GND K3 GND L3 GND M3 GND

G4 SGND H4 TEST1

G5 FREQ H5 V

G6 GND H6 V

IN

IN

J4 V

J5 VIN K5 VIN L5 VIN M5 V

J6 VIN K6 V

G7 PHASMD H7 PWM J7 VIN K7 V

G8 RUNP H8 TMON J8 GND K8 V

K4 VIN L4 VIN M4 V

IN

IN

IN

IN

L6 V

L7 V

L8 V

IN

IN

IN

M6 V

M7 V

M8 V

IN

IN

IN

IN

IN

G9 NC H9 GMON J9 GND K9 GND L9 GND M9 GND

G10 GND H10 GND J10 GND K10 GND L10 GND M10 GND

–

G11 TEMP

G12 TEMP

H11 GND J11 GND K11 SW L11 SW M11 GND

+

H12 GND J12 GND K12 GND L12 GND M12 GND

For more information www.linear.com/LTM4636

4636f

33

LTM4636

TOP VIEW

M

package DescripTion

1 2 3 4 5 6 7

A

V

OUT

B

C

V

OUT

V

OUTS1

–

V

OUTS1

COMPB

+

D

PGOOD

RUNC

TRACK/SS COMPA

V

FB

E

SNSP2 SNSP1

HIZREG

SGND

TEST2

F

CLKOUT SGND

FREQ

G

GND

H

J

GND

GND

V

IN

K

8 9 10 11 12

GND

TEST4

SW

SW

V

OUT

V

OUT

+

V

OUT

V

OUT

GND

INTV

CC

GND

V

IN

GND

PHASMD RUNP TEMP–TEMP

PWMTEST3 MODE/PLLIN TEST1 TMON GMON

V

IN

GND

PV

CC

GND

NC

GND

L

GND

package phoTo

GND

V

IN

V

IN

GND

4636f

34

For more information www.linear.com/LTM4636

package DescripTion

BGA 144 1016 REV D

BEVEL

PACKAGE IN TRAY LOADING ORIENTATION

0.630 ±0.025 Ø 144x

BGA Package

SEE NOTES

Please refer to http://www.linear.com/product/LTM4636#packaging for the most recent package drawings.

7

PIN 1

A

BDC

2 14 356712 891011

G

F

E

H

M

L

K

J

e

G

LTM4636

DETAIL A

b

Z

A2

A

Z

A1

b1

ccc Z

(Reference LTC DWG # 05-08-1937 Rev D)

144-Lead (16mm × 16mm × 7.07mm)

aaa Z

(2.4)

(10.0)

MOLD

H3

PACKAGE BOTTOM VIEW

b

DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR

MARKED FEATURE

4

3

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE

F

e

3

SEE NOTES

BALL DESIGNATION PER JEP95

5. PRIMARY DATUM -Z- IS SEATING PLANE

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY

!

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu

OR Sn Pb EUTECTIC

µModule

PIN “A1”

COMPONENT

TRAY PIN 1

DETAIL B

NOTES

BALL HT

BALL DIMENSION

0.70

0.60

0.50

A1

2.51

2.41

2.31

A2

4.4450

PAD DIMENSION

0.90

0.66

0.75

0.63

16.00

0.60

0.60

b

D

b1

1.9050

3.1750

16.00

E

0.6350

Y

E

PACKAGE TOP VIEW

aaa Z

PACKAGE SIDE VIEW

DIMENSIONS

DETAIL A

6.9850

5.7150

4.4450

3.1750

1.9050

0.6350

0.0000

0.6350

1.9050

3.1750

4.4450

5.7150

6.9850

7.42

MAX

7.07

NOM

MIN

6.57

A

SYMBOL

6.9850

5.7150

EPOXY/SOLDER

H1

SUBSTRATE

H2

CAP

D

(11.20)

DETAIL B

// bbb Z

X YZddd

Zeee

M

M

Øb (144 PLACES)

(3.0)

(2.4)

(3.0)

X

1.27

e

0.0000

0.6350

13.97

F

13.97

G

1.9050

SUBSTRATE THK

MOLD CAP HT

INDUCTOR HT

0.46

2.05

4.21

0.41

2.00

4.06

0.36

1.95

3.76

H1H2H3

3.1750

4.4450

0.15

aaa

5.7150

0.10

bbb

0.20

0.30

0.15

TOTAL NUMBER OF BALLS: 144

ccc

eee

ddd

6.9850

TOP VIEW

SUGGESTED PCB LAYOUT

4

CORNER

PIN “A1”

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTM4636

4636f

35

LTM4636

INTV

47pF

PINS NOT USED IN CIRCUIT LTM4636:
CLKOUT
SW, TEST1, TEST2, TEST3, TEST4

SGND

Typical applicaTion

5V to 2.5V at 35A Design

CC

5V

22µF

16V

+

100µF
25V

, GMON, PGOOD, PHMODE, PWM,

22µF

16V

22µF
16V

22µF

16V

0.1µF

15k

C

0.1µF

SS

47k

SGND

INTV

SGND

CC

22µF
16V

OPTIONAL TEMP MONITOR

FOR TELEMETRY READBACK ICs

Design resources

SUBJECT DESCRIPTION

µModule Design and Manufacturing Resources Design:

µModule Regulator Products Sear

ch 1. Sort table of products by parameters and download the result as a spread sheet.

 •Selector Guides

•Demo Boards and Gerber Files





•Free Simulation Tools

2. Search using the Quick Power Search parametric table.

INTV

V

IN

COMPA
COMPB
TK/SS

RUNC
RUNP
HIZREG

FREQ
MODE/PLLIN

TEMP+TEMP–SNSP1 SNSP2 SGND

CC

LTM4636

Manufacturing:





PV

CC

TMON

V

OUT

+

V

OUTS1

–

V

OUTS1

V

FB

PGND

22µF

VOLTAGE OUT TEMP MONITOR

2.5V AT 35A

470µF
4V

+

100µF ×3

6.3V

470µF
4V

+

4636 TA02

R

FB

1.58k

C

FF

•Quick Start Guide

•PCB Design, Assembly and Manufacturing Guidelines

•Package and Board Level Reliability

TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products.

Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LTM4650/
LTM4650-1

LTM4630/
LTM4630-1/
LTM4630A

LTM4647 Smaller Package Up to 30A µModule Regulator

36

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

More Current Up to 50A µModule Regulator

Less Current Up to 36A µModule Regulator

For more information www.linear.com/LTM4636

●

www.linear.com/LTM4636

Dual 25A or Single 50A, 4.5V ≤ V

≤ 15V, 0.6V ≤ V

IN

× 5.01mm BGA

LTM4650 Pin-Compatible; Same V

and V

IN

Range; LTM4630A 0.6V ≤ V

OUT

≤ 5.3V, 16mm × 16mm × 4.41mm LGA 5.01mm BGA

Single 30A, 4.7V ≤ V

≤ 15V, 0.6V ≤ V

IN

OUT

≤ 1.8V, 9mm × 15mm × 5.01mm BGA

 LINEAR TECHNOLOGY CORPORATION 2016

≤ 1.8V, 16mm × 16mm

OUT

LT 1216 • PRINTED IN USA

OUT

4636f