Linear Technology Analog Devices LT8708-1 Datasheet

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Page 1

RVS (0V)

DB2

80V Synchronous 4-Switch Buck-Boost DC/DC

BAT2

= 13.5V

BAT2

CHARGING CURRENT = 30A

BAT1

(V)

101214

169495

100

Efﬁciency

87081 TA01b

Slave Controller for LT8708 Multiphase System

FEATURES DESCRIPTION

Slave Chip of LT8708 to Deliver Additional Power

Good Current Matching to the Average Output Current of LT8708 Through Current Regulation

Easily Paralleled with LT8708 Through Four Pins

Synchronized Start-Up with LT8708

Same Conduction Modes as LT8708

Synchronous Rectification: Up to 98% Efficiency

Frequency Range: 100kHz to 400kHz

Available in 40-Lead (5mm × 8mm) QFN with High Voltage Pin Spacing

APPLICATIONS

High Voltage Buck-Boost Converters

Bidirectional Charging Systems

Automotive 48V Systems

All registered trademarks and trademarks are the property of their respective owners.

The LT®8708-1 is a high performance buck-boost switching regulator controller that is paralleled with the LT8708 to add power and phases to an LT8708 system. The LT8708-1 always operates as a slave to the master LT8708 and has the capability of delivering as much current or power as the master. One or more slaves can be connected to a single master, proportionally increasing power and current capability of the system.

The LT8708-1 has the same conduction modes as LT8708, allowing the LT8708-1 to conduct current and power in the same direction(s) as the master. The master controls the overall current and voltage limits for an LT8708 multiphase system, and the slaves comply with these limits.

LT8708-1s can be easily paralleled with the LT8708 by connecting four signals together. Two additional current limits (forward VIN current and reverse VIN current) are available on each slave that can be set independently.

LT8708-1

TYPICAL APPLICATION

The LT8708-1 Two-Phase 12V Bidirectional Dual Battery System with FHCM and RHCM Efficiency

ICP ICN

BAT1

TO DIODE

DB1

TG1 BOOST1 SW1 BG1 CSP CSN

CSNIN

CSPIN V

INCHIP

SHDN

SWEN

RVSOFF

SYNC ICP ICN

VINHIMON

DIR

FBIN

LD033

MASTER

*REFER TO LT8708 DATA SHEET FOR MASTER SETUP

FWD (3V)

POWER TRANSFER

DECISION LOGIC

10V TO 16V

BATTERY

LT8708*

RVSOFF

CLKOUT

DIR

LD033

SWEN

LD033

MODE

GND BG2 SW2 BOOST2 TG2

LT8708-1

SLAVE

SSRT

TO DIODE

CLKOUT

120kHz

DB2

CSPOUT

CSNOUT

EXTV

VOUTLOMON

INTV

GATEV

IMON_OP

IMON_ON IMON_INP IMON_INN

FBOUT

BAT2

10V TO 16V BATTERY

LD033

DB1

BOOST1TOBOOST2

87081 TA01a

Rev 0

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Page 2

LT8708-1

TABLE OF CONTENTS

Features ..................................................... 1

Applications ................................................ 1

Typical Application ........................................ 1

Description.................................................. 1

Absolute Maximum Ratings .............................. 3

Order Information .......................................... 3

Pin Configuration .......................................... 3

Electrical Characteristics ................................. 4

Typical Performance Characteristics ................... 8

Pin Functions .............................................. 10

Block Diagram ............................................. 13

Operation................................................... 14

Common LT8708-1 and LT8708 Features ............... 14

Adding Phases to an LT8708 Application ................ 14

Adding Phases: The Master LT8708 .................... 14

Adding Phases: The Slave LT8708-1 .................... 16

Start-Up .................................................................. 17

Start-Up: SWEN Pin .............................................. 17

Start-Up: Soft-Start of Switching Regulator ......... 18

Control Overview .................................................... 18

Power Switch Control ............................................ 19

Unidirectional and Bidirectional Conduction ........... 19

Error Amplifiers ...................................................... 19

Transfer Function: I

OUT(SLAVE)

Vs I

OUT(MASTER)

......20

Transfer Function: CCM ........................................21

Transfer Function: DCM, HCM and Burst Mode

Operation ............................................................ 21

Current Monitoring and Limiting .............................21

Monitoring: I

OUT(SLAVE)

Monitoring and Limiting: I

.........................................21

IN(SLAVE)

......................21

Multiphase Clocking ............................................... 22

Applications Information ................................ 23

Quick-Start Multiphase Setup ................................. 23

Quick Setup: Design the Master Phase ................. 23

Quick Setup: Design the Slave Phase(s) ............... 23

Quick Setup: Evaluation ........................................ 23

Choosing the Total Number of Phases .................... 23

Operating Frequency Selection ............................... 24

CIN and C

Selection ...........................................24

OUT

Selection: VIN Capacitance .............. 24

OUT

Selection: V

OUT

Capacitance ........... 25

OUT

VINHIMON, VOUTLOMON and RVSOFF .................. 25

Configuring the I Regulating I

OUT(SLAVE)

: Circuit Description ............................. 26

: Configuration .................................... 28

IN(SLAVE)

Current Limits ................ 26

............................................ 26

Loop Compensation ................................................ 28

Voltage Lockouts .................................................... 29

Circuit Board Layout Checklist ............................... 29

Design Example ..................................................... 29

Typical Applications ...................................... 31

Package Description ..................................... 35

Typical Application ....................................... 36

Related Parts .............................................. 36

Rev 0

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Page 3

(Note 1)

CSP

CSPOUT

– V

CSN

, V

– V

CSPIN CSNOUT

CSNIN

............................... –0.3V to 0.3V

CSP, CSN Voltage ......................................... –0.3V to 3V

VC Voltage (Note 2) ................................... –0.3V to 2.2V

RT, FBOUT, SS Voltage ................................ –0.3V to 5V

IMON_INP, IMON_INN, IMON_OP,

IMON_ON, ICP, ICN Voltage ..................... –0.3V to 5V

SYNC Voltage ............................................ –0.3V to 5.5V

INTVCC, GATEVCC Voltage ............................ –0.3V to 7V

BOOST1

– V

SW1

, V

BOOST2

– V

................ –0.3V to 7V

SW2

SWEN, RVSOFF Voltage ............................... –0.3V to 7V

SWEN Current .......................................................0.5mA

RVSO FF Current .......................................................1mA

FBIN, SHDN Voltage .................................. –0.3V to 30V

VINHIMON Voltage ..................................... –0.3V to 30V

VOUTLOMON Voltage .................................. –0.3V to 5V

DIR, MODE Voltage ...................................... –0.3V to 5V

CSNIN, CSPIN, CSPOUT, CSNOUT Voltage ...–0.3V to 80V V

, EXTVCC Voltage ............................ –0.3V to 80V

INCHIP

SW1, SW2 Voltage ..................................... 81V (Note 6)

BOOST1, BOOST2 Voltage ......................... –0.3V to 87V

BG1, BG2, TG1, TG2 ........................................... (Note 5)

LDO33, CLKOUT ................................................ (Note 8)

Operating Junction Temperature Range

LT8708-1E (Notes 3, 8) .......................–40°C to 125°C

LT8708-1I (Notes 3, 8) ........................ –40°C to 125°C

LT8708-1H (Notes 3, 8) .......................–40°C to 150°C

Storage Temperature Range ...................–65°C to 150°C

LT8708-1

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

TOP VIEW

LDO33

IMON_ON

IMON_OP

MODE

SWEN

40 39 38 37 36 35 34

1CLKOUT

SHDN

CSN

CSP

ICN

DIR

FBIN

FBOUT

IMON_INP

IMON_INN

SYNC

15 16 17 18

GND

40-LEAD (5mm × 8mm) PLASTIC QFN

= 150°C, θJA = 36°C/W, θJC = 38°C/W

JMAX

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

GND

BG1

BG2

GATEV

UHG PACKAGE

19 20 21

INTVCC

TG2

BOOST2

INCHIP

SW2

CSPIN

CSNIN

CSNOUT

CSPOUT

EXTV

ICP

VINHIMON

VOUTLOMON

RVSOFF

BOOST1

TG1

SW1

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT8708EUHG-1#PBF LT8708EUHG-1#TRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C

LT8708IUHG-1#PBF LT8708IUHG-1#TRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C

LT8708HUHG-1#PBF LT8708HUHG-1#TRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 150°C

Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev 0

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Page 4

LT8708-1

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Voltage Supplies and Regulators

Operating Voltage Range EXTVCC = 0V

INCHIP

Quiescent Current Not Switching, V

INCHIP

Quiescent Current in Shutdown V

INCHIP

EXTVCC Switchover Voltage I

EXTVCC Switchover Hysteresis 0.2 V

INTVCC Current Limit Max Current Draw from INTVCC and LDO33 Pins

INTVCC Voltage Regulated from V

INTVCC Load Regulation I

INTVCC, GATEVCC Undervoltage Lockout INTVCC Falling, GATEVCC Connected to INTV

INTVCC, GATEVCC Undervoltage Lockout Hysteresis GATEVCC Connected to INTV

INTVCC Regulator Dropout Voltage V

LDO33 Pin Voltage 5mA from LDO33 Pin

LDO33 Pin Load Regulation I

LDO33 Pin Current Limit SYNC = 3V

LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V

LDO33 Pin Undervoltage Lockout Hysteresis 35 mV

Switching Regulator Control

Maximum Current Sense Threshold (V

CSP

CSN

CSP

– V

) Boost Mode, Minimum M3 Switch Duty Cycle

CSN

– V

) Buck Mode, Minimum M2 Switch Duty Cycle

CSP

– V

) Boost Mode, Minimum M3 Switch Duty Cycle

CSP

– V

) Buck Mode, Minimum M2 Switch Duty Cycle

CSN

Gain from VC to Max Current Sense Voltage (V

– V

CSP

) (A5 in the Block Diagram)

CSN

SHDN Input Voltage High SHDN Rising to Enable the Device SHDN Input Voltage High Hysteresis 40 mV SHDN Input Voltage Low Device Disabled, Low Quiescent Current

SHDN Pin Bias Current V

SWEN Rising Threshold Voltage

SWEN Threshold Voltage Hysteresis 22 mV

SWEN Output Voltage Low I

SWEN Internal Pull-Down Release Voltage SHDN = 3V

EXTVCC = 7.5V

SWEN = 3.3V SWEN = 0V

= 0V 0 1 µA

SHDN

= –20mA, V

INTVCC

Combined. Regulated from V INTVCC = 5.25V INTVCC = 4.4V

Regulated from EXTVCC (12V), I

= 0mA to 50mA –0.5 –1.5 %

INTVCC

– V

INCHIP

= 0.1mA to 5mA –0.25 –1 %

LDO33

Boost Mode Buck Mode

(LT8708E-1, LT8708I-1) (LT8708H-1)

= 3V

SHDN

= 12V

SHDN

= 200µA

SWEN

SHDN = 0V or V SHDN = 3V

=12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3).

INCHIP

5.5

2.8

EXTVCC

= 0

4.7

2.45

6.15 6.4 6.6 V

127

6.1

6.3

6.1

6.3

4.45 4.65 4.85 V

160 mV

3.23 3.295 3.35 V

12 17.25 22 mA

76 93 110 mV

68 82 97 mV

79 93 108 mV

72 84 96 mV

INTVCC

Rising

EXTVCC

or EXTVCC (12V)

INCHIP

, I

INCHIP

, I

INTVCC

= 20mA

INTVCC

= 20mA

= 20mA 245 mV

135

–135

1.175 1.221 1.275 V

l l

0.35

141 22

1.156 1.208 1.256 V

INCHIP

= 0V

l l

0.75 0.8 V

0.9

0.2

80 80

7.5

4.5

165

6.5

0.3

1.1

0.5

mA mA

mV/V mV/V

µA µA

V V

Rev 0

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Page 5

LT8708-1

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

MODE Pin Continuous Conduction Mode (CCM) Threshold

MODE Pin Hybrid DCM/CCM Mode (HCM) Range

MODE Pin Discontinuous Conduction Mode (DCM) Range

MODE Pin Burst Mode Operation Threshold

DIR Pin Forward Operation Threshold

DIR Pin Reverse Operation Threshold

RVSOFF Output Voltage Low I RVSOFF Falling Threshold Voltage RVSOFF Threshold Voltage Hysteresis 165 mV

Soft-Start Charging Current VSS = 0V

IMON_ON Rising Threshold for FDCM Operation MODE = 1V (HCM), DIR = 3.3V

IMON_ON Falling Threshold for CCM Operation MODE = 1V (HCM), DIR = 3.3V

IMON_INP Rising Threshold for RDCM Operation MODE = 1V (HCM), DIR = 0V

IMON_INP Falling Threshold for CCM Operation MODE = 1V (HCM), DIR = 0V

ICP Rising Threshold for Start Switching

ICN Rising Threshold for Start Switching

ICP Rising Threshold for Enabling Non-CCM Offset Current

ICP Falling Threshold for Disabling Non-CCM Offset Current

ICN Rising Threshold for Enabling Non-CCM Offset Current

ICN Falling Threshold for Disabling Non-CCM Offset Current

Voltage Regulation Loops (Refer to Block Diagram to Locate Amplifiers)

Regulation Voltage for FBOUT Regulate VC to 1.2V

Regulation Voltage for FBIN Regulate VC to 1.2V

Line Regulation for FBOUT and FBIN Error Amp ReferenceVoltage V

FBOUT Pin Bias Current Current Out of Pin 15 nA

FBOUT Error Amp EA4 g

FBOUT Error Amp EA4 Voltage Gain 245 V/V

VOUTLOMON Voltage Activation Threshold Falling

VOUTLOMON Threshold Voltage Hysteresis 24 mV

VOUTLOMON Pin Bias Current V

FBIN Pin Bias Current Current Out of Pin 10 nA

FBIN Error Amp EA3 g

FBIN Error Amp EA3 Voltage Gain 150 V/V

VINHIMON Voltage Activation Threshold Rising

VINHIMON Threshold Voltage Hysteresis 24 mV

VINHIMON Pin Bias Current V

= 200µA

RVSOFF

VSS = 0.5V

= 12V to 80V, Not Switching 0.002 0.005 %/V

INCHIP

VOUTLOMON

VINHIMON

=12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3).

INCHIP

0.4 V

0.8 1.2 V

1.6 2.0 V

1.6 V

= 1.24V, Current Into Pin = 1.17V, Current Into Pin

= 1.17V, Current Into Pin = 1.24V, Current Out of Pin

0.08 0.5 V

1.155 1.209 1.275 V

13 2119 3125

235 255 280 mV

185 205 235 mV

235 255 280 mV

185 205 235 mV

485 510 536 mV

680 704 730 mV

500 530 560 mV

680 704 730 mV

500 530 560 mV

1.193 1.207 1.222 V

1.184 1.205 1.226 V

345 µmho

1.185 1.207 1.225 V

0.01 1

0.8

235 µmho

1.185 1.207 1.23 V

0.01 1

0.8

2.4 V

1.2 V

µA

1.2

µA

µA µA

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Rev 0

Page 6

LT8708-1

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Current Regulation Loops (Refer to Block Diagram to Locate Amplifiers)

Regulation Voltages for IMON_INP and IMON_OP VC = 1.2V

Regulation Voltages for IMON_INN VC = 1.2V

Line Regulation for IMON_INP, IMON_INN and IMON_OP Error Amp Reference Voltage

CSPIN Bias Current V

CSNIN Bias Current BOOST Capacitor Charge Control Block Not Active

CSPIN, CSNIN Common Mode Operating Voltage Range

CSPIN, CSNIN Differential Mode Operating Voltage Range

IMON_INP Output Current V

IMON_INN Output Current V

IMON_INP and IMON_INN Max Output Current

IMON_INP Error Amp EA5 g

IMON_INP Error Amp EA5 Voltage Gain 130 V/V

IMON_INN Error Amp EA1 g

IMON_INN Error Amp EA1 Voltage Gain FBIN = 0V, FBOUT = 3.3V 130 V/V

CSPOUT Bias Current V

CSNOUT Bias Current BOOST Capacitor Charge Control Block Not Active

CSPOUT, CSNOUT Common Mode Operating Voltage Range

CSPOUT, CSNOUT Differential Mode Operating Voltage Range

IMON_ON Output Current V

IMON_ON Max Output Current

CSPOUT–CSNOUT Regulation Voltage Regulate VC to 1.2V

= 12V to 80V 0.002 0.005 %/V

INCHIP

= 12V

CSPIN

= 1.5V

CSPIN

= 3.3V, V

SWEN

= 3.3V, V

SWEN

= 0V

SWEN

– V

CSPIN

– V

CSPIN

– V

CSPIN

– V

CSPIN

– V

CSNIN

– V

CSNIN

– V

CSNIN

– V

CSNIN

FBIN = 0V, FBOUT = 3.3V 190 µmho

= 12V

CSPOUT

= 1.5V

CSPOUT

= 3.3V, V

SWEN

= 3.3V, V

SWEN

= 0V

SWEN

– V

CSNOUT

– V

CSNOUT

– V

CSNOUT

– V

CSNOUT

– V

CSNOUT

– V

CSNOUT

IMON_OP

= 12V

CSNOUT

=12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3).

INCHIP

1.185 1.209 1.231 V

1.185 1.21 1.24 V

0.01

CSPIN CSPIN

= V = V

CSNIN CSNIN

= 12V = 1.5V

4.25

0.01

0 80 V

–100 100 mV

CSNIN CSNIN CSNIN CSNIN

CSPIN CSPIN CSPIN CSPIN

= 50mV, V = 50mV, V = 5mV, V = 5mV, V

CSNIN

CSNIN CSNIN CSNIN

CSNIN

CSNIN CSNIN CSNIN

= 5V

= 5V = 5V = 5V

= 5V

= 5V = 5V = 5V

64.5

22.5

70 25

120 µA

190 µmho

0.01

CSPOUT CSPOUT

= V = V

CSNOUT CSNOUT

= 12V = 1.5V

4.25

0.01

0 80 V

–100 100 mV

CSPOUT CSPOUT CSPOUT CSPOUT CSPOUT CSPOUT

= 17.4kΩ

= 50mV, V = 50mV, V = 5mV, V = 5mV, V = −5mV, V = −5mV, V

ICP = 1.218V, ICN = 0V

ICP = 0V, ICN = 1.218V

ICP = ICN = 0.348V

CSNOUT

CSNOUT CSNOUT CSNOUT

CSNOUT

= 5V

= 5V = 5V = 5V

= 5V

22.5

20.5

12.5

10.5

25 25 15 15

120 µA

43 50 55 mV

–55 –50 –44 mV

–6 0 6 mV

75.5

27.5 30

74 75

30.5 32

73 75

27.5 29

17.5

19.5

µA µA

µA µA µA

µA µA µA µA

µA µA

µA µA µA

µA µA µA µA µA µA

Rev 0

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Page 7

LT8708-1

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

NMOS Gate Drivers

TG1, TG2 Rise Time C

TG1, TG2 Fall Time C

BG1, BG2 Rise Time C

BG1, BG2 Fall Time C

TG1 Off to BG1 On Delay C

BG1 Off to TG1 On Delay C

TG2 Off to BG2 On Delay C

BG2 Off to TG2 On Delay C

Min On-Time for Main Switch in Boost Operation (t

ON(M3,MIN)

Min On-Time for Synchronous Switch in Buck Operation (t

) Switch M3, C

ON(M2,MIN)

Min Off-Time for Main Switch in Steady-State Boost Operation Switch M3, C

Min Off-Time for Synchronous Switch in Steady-State Buck Operation Switch M2, C

Oscillator

Switch Frequency Range SYNCing or Free Running 100 400 kHz

Switching Frequency, f

OSC

SYNC High Level for Synchronization

SYNC Low Level for Synchronization

SYNC Clock Pulse Duty Cycle V

Recommended Min SYNC Ratio f

SYNC/fOSC

CLKOUT Output Voltage High V

CLKOUT Output Voltage Low 1mA Into CLKOUT Pin 25 100 mV

CLKOUT Duty Cycle TJ = –40°C

CLKOUT Rise Time C

CLKOUT Fall Time C

CLKOUT Phase Delay SYNC Rising to CLKOUT Rising, f

= 3300pF (Note 4) 20 ns

LOAD

= 3300pF (Note 4) 20 ns

LOAD

= 3300pF (Note 4) 20 ns

LOAD

= 3300pF (Note 4) 20 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

= 3300pF Each Driver 80 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

= 3300pF Each Driver 80 ns

LOAD

) Switch M2, C

RT = 365k RT = 215k RT = 124k

= 0V to 2V 20 80 %

SYNC

– V

LDO33

= 0µA

LDO33

TJ = 25°C TJ = 125°C

= 200pF 20 ns

LOAD

= 200pF 20 ns

LOAD

=12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3).

INCHIP

= 3300pF 200 ns

LOAD

= 3300pF 200 ns

LOAD

= 3300pF 230 ns

LOAD

= 3300pF 230 ns

LOAD

102

l l

120

170

202

310

350

1.3 V

3/4

, 1mA Out of CLKOUT Pin,

CLKOUT

100 250 mV

22.7

44.1 77

= 100kHz

OSC

160 180 200 Degree

142 235 400

kHz kHz kHz

0.5 V

% % %

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: Do not force voltage on the VC pin. Note 3: The LT8708E-1 is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8708I-1 is guaranteed over the full –40°C to 125°C junction temperature range. The LT8708H-1 is guaranteed over the full –40°C to 150°C operating junction temperature range.

Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels.

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Note 5: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur.

Note 6: Negative voltages on the SW1 and SW2 pins are limited, in an application, by the body diodes of the external NMOS devices, M2 and M3, or parallel Schottky diodes when present. The SW1 and SW2 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design.

Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.

Note 8: Do not force voltage or current into these pins.

Rev 0

Page 8

LT8708-1

OUT

(A)

0.01

0.1110

010203040

708090

100

EFFICIENCY (%)

87081 G01

VIN = 11.5V

OUT

= 14.5V

HCM

DCM

CCM

OUT

(A)

0.01

0.1110

3001020304050

60708090100

EFFICIENCY (%)

87081 G02

VIN = 16V

OUT

= 12V

HCM

DCM

CCM

VIN = 14.5V

OUT

= 14.5V

HCM

DCM

CCM

OUT

(A)

0.01

0.1110

300102030

405060708090100

EFFICIENCY (%)

87081 G03

VC ≅ 1.3V

TEMPERATURE (°C)

–50

–30

–101030507090110

130

1502030

4050607080

87081 G04

ICP = ICN = 0.348V

CSPOUT–CSNOUT (mV)

–150

–75075

150

–103070

110

150

190

230

87081 G06

TJ = 25°C

MAXIMUM V

MINIMUM V

ICP/ICN VOLTAGE (V)

0.25

0.50

0.7511.25

0.5

1.0

1.5

2.0

2.5

(V)

87081 G07

TJ = 25°C

MAXIMUM V

MINIMUM V

SS (V)00.511.5

0.5

1.0

1.5

2.0

2.5

(V)

87081 G08

TJ = 25°C

MAXIMUM V

MINIMUM V

SS (V)

0.25

0.50

0.7510

0.5

1.0

1.5

2.0

2.5

(V)

87081 G09

VC = ~1.3V

TEMPERATURE (°C)

–50

–30

–101030507090110

130

15020304050

607080

87081 G05

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Output Current (Boost Region – Page 32)

CSPOUT – CSNOUT Voltages (ICP=1.218V, ICN = 0V) (Five Parts)

Efficiency vs Output Current (Buck Region – Page 32)

CSNOUT – CSPOUT Voltages (ICP=1.218V, ICN = 0V) (Five Parts)

TA = 25°C, unless otherwise noted.

Efficiency vs Output Current (Buck-Boost Region – Page 32)

IMON_OP Output Current

Maximum and Minimum VC vs ICP_ICN (SS = 0)

Maximum and Minimum VC vs SS (ICP = ICN =0.348V)

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Maximum and Minimum VC vs SS (ICP or ICN = 1V)

Rev 0

Page 9

LT8708-1

87081 G10

LT8708-1 I

BATTERY DISCONNECTED

LT8708-1 I

BATTERY DISCONNECTED

LT8708-1 I

BATTERY DISCONNECTED

LT8708-1 I

BATTERY DISCONNECTED

TYPICAL PERFORMANCE CHARACTERISTICS

Load Step (Page 32) VIN = 12V V

= 14.5V

OUT

LT8708 I

10A/DIV

= 12V, V

BAT1

LOAD STEP = 10A TO 25A LOAD APPLIED AT V

BAT2

Load Step (Page 32) VIN = 16V V

= 14.5V

OUT

LT8708 I

10A/DIV

500μs/DIV

REGULATED TO 14.5V

WITH

BAT2

Load Step (Page 32) VIN = 14.5V V

OUT

LT8708 I

10A/DIV

BAT1

LOAD STEP = 10A TO 25A LOAD APPLIED AT V

Load Step (Page 33) VIN = 48V V

OUT

LT8708 I

20A/DIV

TA = 25°C, unless otherwise noted.

= 14.5V

87081 G11

= 14.5V, V

500μs/DIV

REGULATED TO 14.5V

BAT2

WITH

BAT2

= 14.5V

PHASE 1

PHASE 2

PHASE 3

PHASE 4

500μs/DIV

= 16V, V

BAT1

LOAD STEP = 10A TO 25A LOAD APPLIED AT V

REGULATED TO 14.5V

BAT2

WITH

87081 G12

500μs/DIV

= 48V, V

BAT1

LOAD STEP = 20A TO 55A LOAD APPLIED AT V

REGULATED TO 14.5V

BAT2

87081 G13

WITH

Rev 0

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Page 10

LT8708-1

PIN FUNCTIONS

CLKOUT (Pin 1): Clock Output Pin. Use this pin to synchronize one or more compatible switching regulator ICs. CLKOUT toggles at the same frequency as the internal oscillator or as the SYNC pin, but is approximately 180° out of phase. CLKOUT may also be used as a temperature monitor since the CLKOUT duty cycle varies linearly with the part’s junction temperature. The CLKOUT pin can drive capacitive loads up to 200pF.

SS (Pin 2): Soft-Start Pin. Place a capacitor from this pin to ground. A capacitor identical to the SS pin capacitor used on the master LT8708 is recommended. Upon startup, this pin will be charged by an internal resistor to 3.3V.

SHDN (Pin 3): Shutdown Pin. Tie high to enable chip. Ground to shut down and reduce quiescent current to a minimum. Do not float this pin.

CSN (Pin 4): The (–) Input to the Inductor Current Sense and DCM Detect Comparator.

CSP (Pin 5): The (+) Input to the Inductor Current Sense and DCM Detect Comparator. The VC pin voltage and builtin offsets between CSP and CSN pins, in conjunction with the R It is recommended to use the same value R master LT8708.

ICN (Pin 6): Negative V voltage on this pin determines the negative V for LT8708-1 to regulate to. Connect this pin to the master LT8708’s ICN pin. See the Applications Information section for more information.

value, set the inductor current trip threshold.

SENSE

Current Command Pin. The

OUT

as the

current

FBOUT (Pin 9): V to the input of error amplifier EA4. Typically, connect this pin to GND to disable the EA4.

VC (Pin 10): Error Amplifier Output Pin. Tie external compensation network to this pin.

IMON_INP (Pin 11): Positive VIN Current Monitor and Limit Pin. The current out of this pin is 20µA plus a current proportional to the positive average VIN current. IMON_INP also connects to error amplifier EA5 and can be used to limit the maximum positive VIN current. See the Applications Information section for more information.

IMON_INN (Pin 12): Negative VIN Current Monitor and Limit Pin. The current out of this pin is 20µA plus a current proportional to the negative average VIN current. IMON_INN also connects to error amplifier EA1 and can be used to limit the maximum negative VIN current. See the Applications Information section for more information.

RT (Pin 13): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency. It is recommended to use the same value RT resistor as the master LT8708. Do not float this pin.

SYNC (Pin 14): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less than 0.5V. In a two-phase system, connect this pin to the master LT8708’s CLKOUT pin to have a 180° phase shift. See the Applications Information section for more information.

Feedback Pin. This pin is connected

OUT

DIR (Pin 7): Direction pin when MODE is set for DCM (discontinuous conduction mode) or HCM (hybrid conduction mode) operation. Otherwise this pin is ignored. Connect the pin to GND to process power from the V to VIN. Connect the pin to LDO33 to process power from the VIN to V signal, or connect this pin to the same voltages as the master LT8708.

FBIN (Pin 8): VIN Feedback Pin. This pin is connected to the input of error amplifier EA3. Typically, connect this pin to LDO33 to disable the EA3.

. Drive this pin with the same control

OUT

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OUT

BG1, BG2 (Pin 16, Pin 18): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFETs between ground and GATEVCC.

GATEVCC (Pin 17): Power supply for bottom gate drivers. Must be connected to the INTVCC pin. Do not power from any other supply. Locally bypass to GND. It is recommended to use the same value bypass cap as the master LT8708.

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Page 11

PIN FUNCTIONS

LT8708-1

BOOST1, BOOST2 (Pin 24, Pin 19): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor connects here. The BOOST1 pin swings from a diode voltage below GATEVCC up to V

+ GATEVCC. The BOOST2

pin swings from a diode voltage below GATEVCC up to V

+ GATEVCC.

OUT

TG1, TG2 (Pin 23, Pin 20): Top Gate Drive. Drives the top N-channel MOSFETs with voltage swings equal to GATEVCC superimposed on the switch node voltages.

SW1, SW2 (Pin 22, Pin 21): Switch Nodes. The (–) terminals of the bootstrap capacitors connect here.

RVSOFF (Pin 25): Reverse Conduction Disable Pin. This is an input/output open-drain pin that requires a pull-up resistor. Pulling this pin low disables reverse current operation. Typically, connect this pin to the LT8708’s RVSOFF pin. See the Unidirectional and Bidirectional Conduction section for more information.

VOUTLOMON (Pin 26): V Pin. Connect a ±1% resistor divider between V

Low Voltage Monitor

OUT

, VOUTLOMON and GND to set an undervoltage level on V

. When V

OUT

tion is disabled to prevent drawing current from V

is lower than this level, reverse conduc-

OUT

. See

the Applications Information section for more information.

CSPOUT (Pin 30): The (+) Input to the V

Current

OUT

Monitor Amplifier. This pin and the CSNOUT pin measure the voltage across the sense resistor, R the V same value R

current signals. It is recommended to use the

OUT

SENSE2

between the CSPOUT and CSNOUT

SENSE2

, to provide

pins as the master LT8708. See Applications Information section for proper use of this pin.

CSNOUT (Pin 31): The (–) Input to the V

Current

OUT

Monitor Amplifier. See Applications Information section for proper use of this pin.

CSNIN (Pin 32): The (–) Input to the VIN Current Monitor Amplifier. This pin and the CSPIN pin measure the voltage across the sense resistor, R

SENSE1

, to provide the VIN current signals. Connect this pin to VIN when not in use. See Applications Information section for proper use of this pin.

CSPIN (Pin 33): The (+) Input to the VIN Current Monitor Amplifier. Connect this pin to VIN when not in use. See Applications Information section for proper use of this pin.

(Pin 34): Main Input Supply Pin for the LT8708-1.

INCHIP

It must be locally bypassed to ground. It is recommended to use the same value bypass cap as the master LT8708.

VINHIMON (Pin 27): VIN High Voltage Monitor Pin. Connect a ±1% resistor divider between VIN, VINHIMON and GND in order to set an overvoltage level on VIN. When VIN is higher than this level, reverse conduction is disabled to prevent current flow into VIN. See the Applications Information section for more information.

ICP (Pin 28): Positive V The voltage on this pin determines the positive V

Current Command Pin.

OUT

current for LT8708-1 to regulate to. Connect this pin to LT8708’s ICP pin. See the Applications Information section for more information.

EXTVCC (Pin 29): External VCC Input. When EXTVCC exceeds 6.4V (typical), INTVCC will be powered from this pin. When EXTVCC is lower than 6.4V, the INTVCC will be powered from V

. It is recommended to use the same

INCHIP

value bypass cap as the master LT8708.

INTVCC (Pin 35): 6.35V Regulator Output. Must be connected to the GATEVCC pin. INTVCC is powered from EXTVCC when the EXTVCC voltage is higher than 6.4V, otherwise INTVCC is powered from V

Bypass this

INCHIP.

pin to ground with a minimum 4.7µF ceramic capacitor. It is recommended to use the same value bypass cap as the master LT8708.

SWEN (Pin 36): Switching Regulator Enable Pin. Tie high through a resistor to enable the switching. Ground to disable switching. This pin is pulled down during shutdown, a thermal lockout or when an internal UVLO (Under Voltage Lockout) is detected. Do not float this pin. Connect this pin to the LT8708’s SWEN pin for synchronized start-up. See the Start-Up: SWEN Pin section for more details.

Rev 0

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Page 12

LT8708-1

PIN FUNCTIONS

MODE (Pin 37): Conduction Mode Select Pin. The voltage applied to this pin sets the conduction mode of the controller. Apply less than 0.4V to enable continuous conduction mode (CCM). Apply 0.8V to 1.2V to enable the hybrid conduction mode (HCM). Apply 1.6V to 2.0V to enable the discontinuous conduction mode (DCM). Apply more than

2.4V to enable Burst Mode operation. It is recommended to drive this pin with the same control signal, or connect this pin to the same value resistor dividers or voltages as the master LT8708.

IMON_OP (Pin 38): Average V Pin. This pin servos to 1.207V to regulate the average output current based on the ICP and ICN voltages. Always connect a 17.4k resistor in parallel with a compensation network from this pin to GND. See the Applications Information section for more information.

Current Regulation

OUT

IMON_ON (Pin 39): Negative V The current out of this pin is 20µA plus a current proportional to the negative average V Applications Information section for more information.

LDO33 (Pin 40): 3.3V Regulator Output. Bypass this pin to ground with a minimum 0.1µF ceramic capacitor. It is recommended to use the same value bypass cap as the master LT8708.

GND (Pin 15, Exposed Pad Pin 41): Ground. Tie directly to local ground plane.

Current Monitor Pin.

OUT

current. See the

OUT

Rev 0

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Page 13

TO LT8708’s V

87081 F01

BLOCK DIAGRAM

SENSE1

CSN CSP

–

LT8708’s CLKOUT

LDO33

SHDN1

SHDN2

CSNIN

CSPIN

INCHIP

IMON_INN

IMON_INP

CLKOUT

SYNC

DIR

MODE

3.3V

SHDN

1.221V

EXTV

INTV

LDO33

–

6.3V LDO REG

6.4V

–

OSC

RVS

UV_INTVCCOT

UV_LDO33 UV_GATEV

–

SENSE

–

START-UP LOGIC

UV_V

6.3V

LDO REG

INTERNAL

SUPPLY2

INTERNAL SUPPLY1

LDO33

TO LT8708’s SWEN

SWEN

3.3V LDO REG

LT8708-1

D2 (OPT)

D4 (OPT)

TO LT8708’s V

OUT

LOMON1

LOMON2

FBOUT1

FBOUT2

D1 (OPT)

D3 (OPT)

HIMON1

HIMON2

BOOST1

–

CONTROL

RVS

AND

STATE

LOGIC

BOOST CAPACITOR CHARGE CONTROL

–

1.207V

EA7

1.207V

TG1

SW1

GATEV

BG1

GND

BG2

SW2

TG2

BOOST2

RVSOFF

VINHIMON

VOUTLOMON

IMON_OP

TO LT8708’s R

RVSOFF

HIMON3

LOMON3

–

CSPOUT

CSNOUT

IMON_ON

1.21V

IMON_INN

FBOUT

ICN

ICP

FBIN

SENSE2

TO LT8708’s ICN

TO LT8708’s ICP

TO LT8708’s V

FBIN1

FBIN2

–

EA8

EA6

–

1.209V

EA5

IMON_INP

–

EA3

1.205V

–

1.207V

EA4

–

EA1

Figure1. Block Diagram

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Page 14

LT8708-1

OPERATION

The LT8708-1 is a high performance 4-switch buck-boost slave controller that is paralleled with the master LT8708 to increase power capability. Using LT8708-1(s) with the LT8708, an application can command power to be delivered from VIN to V

or from V

OUT

to VIN as needed.

OUT

COMMON LT8708-1 AND LT8708 FEATURES

The LT8708-1 and LT8708 share many common functions and features that are already documented in the LT8708 data sheet. Table1 lists the LT8708 data sheet sections that also apply to the LT8708-1. For some of these features, additional LT8708-1 specific information is provided in this data sheet, as indicated in Table1.

The focus of this data sheet is on how to use the LT8708-1 to increase the number of switching phases in an LT8708-based application. As such, functionality that is identical in both the LT8708 and LT8708-1 will not necessarily be repeated here. It is assumed that readers of this data sheet are already familiar with the LT8708.

ADDING PHASES TO AN LT8708 APPLICATION

In a multiphase LT8708 application, a single LT8708 is the master of the system. One or more LT8708-1s are slaves that provide additional current as needed. As the master of the multiphase system, the LT8708 and its respective error amplifiers, determine the current necessary to regulate the VIN voltage, V V

current. The slave LT8708-1 operates by sensing

OUT

the I

OUT(MASTER)

tional amount of I proportional to I

(see Figure2) and delivering a propor-

OUT(SLAVE)

OUT(MASTER)

voltage, VIN current and

OUT

. Again, since I

OUT(SLAVE)

, the master LT8708 is in

control of setting regulation voltages and current limits to the system.

Each LT8708 and LT8708-1, connected in parallel, is hereon referred to as a phase, the master and slave VIN current is referred to as I

IN(MASTER)

and I

IN(SLAVE)

, respectively. For multiphase operation, the LT8708 should be configured according to the LT8708 data sheet. Configuration of LT8708-1s should follow instructions in this data sheet. Figure2 shows a simplified drawing of a multiphase system with one LT8708 and multiple

Table1. LT8708 Data Sheet Sections that Apply to the LT8708-1

ADDITIONAL INFORMATION

LT8708 DATA SHEET SECTION

Operation

Start-Up: SHDN Pin

Power Switch Control

Unidirectional and Bidirectional Conduction Yes

INTVCC/EXTVCC/GATEVCC/LDO33 Power

CLKOUT and Temperature Sensing

Applications Information

Internal Oscillator

SYNC Pin and Clock Synchronization

CLKOUT Pin and Clock Synchronization

Inductor Current Sensing and Slope Compensation

Selection and Maximum Current

SENSE

Filtering

SENSE

Inductor (L) Selection

Power MOSFET Selection

Schottky Diode (D1, D2, D3, D4) Selection

Topside MOSFET Driver Supply (CB1, DB1, CB2, DB2)

VINHIMON, VOUTLOMON and RVSOFF Yes

INTVCC Regulators and EXTVCC Connection

LDO33 Regulator

Voltage Lockouts Yes

Junction Temperature Measurement

Thermal Shutdown

Efficiency Considerations

Circuit Board Layout Checklist Yes

IN THIS DATA SHEET

LT8708-1s. It illustrates the basic connections needed to add LT8708-1s to a multiphase system.

Adding Phases: The Master LT8708

The master controls the overall current delivered by the multiphase system. For example, the LT8708 controls the VIN and V

regulation voltages through its FBIN and

OUT

FBOUT pins. Since the slaves primarily duplicate the master’s I

OUT(MASTER)

current, the slave’s FBIN and FBOUT pins and related circuitry are typically not used. See the Error Amplifiers section on how they can affect VC and how to disable them.

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OPERATION

OUT(SLAVE)

IN(SLAVE)

OUT

LT8708-1

CSNOUT

CSPOUT

OUT(MASTER)

OUT

IN(MASTER)

RVS (<1.2)

LD033

CSNIN

CSPIN

INCHIP

FBIN

LD033

DIR

SWEN

FWD (>1.6V)/

4-SWITCH BUCK-BOOST

RVSOFFSWEN

SWEN

DIR

INCHIP

CSPIN

CSNIN

LT8708

MASTER

SYNCRVSOFF ICP ICN

LD033LD033

CLK1

CLK2

SYNCRVSOFF ICP ICN

LT8708-1

SLAVE

CSPOUT

CSNOUT

FBOUT

IMON_OP

IMON_ON

IMON_INP

IMON_INN

ICNICP

IMON_OP

4-SWITCH BUCK-BOOST

IN(SLAVE)

CLKnRVSOFF ICP ICNSWEN

SWEN

DIR

INCHIP

CSPIN

CSNIN

4-SWITCH BUCK-BOOST

SYNCRVSOFF ICP ICN

IMON_OP

LT8708-1

SLAVE

CSNOUT

CSPOUT

Figure2. Simplified Multiphase Configuration Diagram

OUT

OUT(SLAVE)

OUT

87081 F01

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Page 16

LT8708-1

OPERATION

As another example, the master LT8708’s current regulation pins (IMON_INP, IMON_INN, IMON_OP, IMON_ON) monitor and limit the per-phase VIN current and V

OUT

current. The LT8708-1 complies with these limits by regulating the I

OUT(SLAVE)

proportionally. The slave’s IMON pins are typically used differently than on the LT8708. See the I

OUT(SLAVE)

: Configuration section and the Current

Monitoring and Limiting section for more information.

Finally, the VINHIMON and VOUTLOMON pins can be used to set up VIN overvoltage and V

undervoltage lockouts

OUT

on both the LT8708 and the LT8708-1. Typically, however, divider networks are only necessary on the master LT8708 since activation of the VINHIMON or VOUTLOMON comparator, on any phase, is communicated to all phases through the shared RVSOFF pin connection. Utilizing the VINHIMON and VOUTLOMON pins on additional phases offers redundancy for those functions. See the VINHIMON, VOUTLOMON and RVSOFF section for more details.

Adding Phases: The Slave LT8708-1

Further information about the LT8708-1 in Figure2 is asfollows:

• The ICP and ICN signals connect between the LT8708

and all the LT8708-1s. They are used to deliver the positive and negative I

OUT(MASTER)

information from the LT8708 to the LT8708-1(s), and hence set the average regulated I

OUT(SLAVE)

• Typically, the LT8708-1 operates by regulating its I

OUT(SLAVE)

to a proportion of the I

OUT(MASTER)

. The LT8708-1’s IMON_OP pin regulates to 1.209V as a part of this regulation. This IMON_OP function differs from the LT8708 in that the LT8708-1’s IMON_OP is not part of the positive I

OUT(SLAVE)

monitor function. Always connect a 17.4k resistor in parallel with a compensation network from this pin to ground on the LT8708-1.

• The IMON_ON pin is used to monitor the negative I

OUT(SLAVE)

. The current limiting function of this pin on LT8708-1 is disabled and is instead controlled by the master LT8708.

• The LT8708 and LT8708-1 employ different soft-start mechanisms, and the SS pins ramp up differently. See the Start-Up: Soft-Start of Switching Regulator section for more details.

Apart from the information explained above from Figure2, a few other pins also need to be considered when configuring a multiphase system. A summary of pins and their recommended usage is provided in Table2.

Table2. Summary of Pin Connections

SHORT PINS

BETWEEN LT8708

AND LT8708-1 PIN NAME(S) NOTES

SWEN, RVSOFF Open-drain communication

between all phases. Keeps LT8708/

YES

MAYBE

ICP, ICN Send LT8708’s I

MODE, DIR Typically, pins are driven to the

FBOUT,

IMON_INN

IMON_INP If using RHCM, connect a

VINHIMON,

VOUTLOMON

IMON_OP On LT8708-1, connect a 17.4k

IMON_ON Limiting function is disabled

SS, RT Use same value capacitor,

LDO33,

INTVCC,

GATEV

LT8708-1(s) in same states.

information to LT8708-1.

same states as LT8708.

Disable these error amps on LT8708-1(s), or set to same or higher limits than LT8708 if used for secondary limits.

17.4k resistor and parallel filter capacitor from this pin to ground. Otherwise, disable this error amp or set to same or higher limit than LT8708 if used for secondary I

Comparator states are shared between LT8708/ LT8708-1(s) through RVSOFF pins. Pins on LT8708-1 can be disabled or used as redundant detectors.

resistor and a compensation network from this pin to ground.

on LT8708-1. If using FHCM, connect a 17.4k resistor in parallel with a filter capacitor from this pin to ground to properly detect light load.

resistor as LT8708.

Typically would have same capacitors as LT8708.

IN(SLAVE)

OUT(SLAVE)

limit.

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OPERATION

LDO33 > 3.075V AND SWEN > 1.208V

< 160°C AND SHDN > 1.221V AND V

> 2.5V AND

SHDN < 1.181V OR

87081 F02

LT8708-1

In addition, all LT8708-1s’ VIN and V nected to the LT8708’s VIN and V

OUT

should be con-

OUT

, respectively.

See the Quick-Start Multiphase Setup Guidelines section in the Applications Information for a step-by-step design procedure to add LT8708-1s to your system.

START-UP

Figure3 illustrates the start-up sequence for the LT8708-1.

Start-Up: SWEN Pin

The LT8708-1 and LT8708’s SWEN pins share the same functionality. Refer to Start-Up: SWEN Pin of the LT8708

JUNCTION

INCHIP

JUNCTION

CHIP OFF

• SWITCHER OFF

• LDOs OFF

• SWEN PULLED LOW

< 2.5V OR

> 165°C

data sheet for more details. SWEN is internally pulled down by the LT8708 and/or LT8708-1(s) when the respective switching regulator is unable or not ready to operate (see CHIP OFF and SWITCHER OFF 1 states in Figure3).

In a multiphase system, the SWEN pins are connected between all phases. Due to the internal SWEN pull-down on the LT8708 and LT8708-1, the external pull-up for the common SWEN node should always have a current limiting resistor. Typically, the common SWEN node is pulled up, through a resistor, to the LT8708’s LDO33 pin. In other cases, the common SWEN node can be digitally driven through a current limiting resistor.

((INTV

• SWITCHER DISABLED

• INTV

AND LDO33 OUTPUTS ENABLED

• SWEN AND SS PULLED LOW

AND GATEVCC < 4.65V)

OR LDO33 < 3.04V)

SWITCHER OFF 1

(INTV

LDO33 > 3.075V AND SWEN < 0.8V

INCHIP

AND GATEVCC > 4.81V) AND

SOFT-START 2

• SS CHARGES UP

ICP AND ICN < 510mV

SS > 0.8V

SWITCHER OFF 2

• SWITCHER DISABLED

• INTV

AND LDO33 OUTPUTS ENABLED

• SS PULLED LOW

(INTV

INITIALIZE

• SS PULLED LOW

• V

FORCED TO COMMAND NEAR ZERO

CURRENT LIMIT

SS < 50mV

SOFT-START 1

• SS CHARGES UP

ICP OR ICN > 510mV

SOFT-START 3

• SS CHARGES UP

• SWITCHER ENABLED

• M1, M4 ON-TIME SOFT-START

• V

IS FREE TO SLEW

SS > 1.8V

NORMAL MODE

• NORMAL OPERATION

AND GATEVCC > 4.81V) AND

Figure3. Start-Up Sequence (All Values are Typical)

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Page 18

LT8708-1

OPERATION

SWEN is used to synchronize the start-up between all phases of the system. If one or more of the phases is unable to operate, SWEN is pulled low by those chips, thus preventing the entire system from starting. After all phases are ready to operate and SWEN has been pulled down below 0.8V (typical) SWEN rises, due to the pullup resistor, and start-up proceeds, for all phases, to the SWITCHER OFF 2 state.

When the common SWEN node rises above 1.208V (typical), all the phases proceed to the INITIALIZE state at the same time.

Start-Up: Soft-Start of Switching Regulator

The soft-start sequence, described in this section, happens independently and in parallel for each phase since each phase has its own SS pin, external capacitor and related circuitry. The remaining discussion concerns the LT8708-1 soft-start behavior. The LT8708 soft-start differs slightly.

In the INITIALIZE state, the SS pin is pulled low to prepare for soft-starting the switching regulator. Also, VC is forced to command near zero current, and IMON_OP is forced to ~1.209V (typical) to improve the transient behavior when the LT8708-1 subsequently starts switching.

After SS has been discharged to less than 50mV, the SOFT-START 1 state begins. In this state, an integrated 180k (typical) resistor from 3.3V pulls SS up. The rising ramp rate of the SS pin voltage is set by this 180k resistor and the external capacitor connected to this pin.

After SS reaches 0.2V (typical), the LT8708-1’s integrated pull-up resistor is reduced from 180k to 90k to increase the rising ramp rate of the SS pin voltage. This ensures that the slave chip enters the normal mode in Figure3 before the master chip, preventing saturation of the regulation loop during start-up.

Switching remains disabled until either (1) ICP or ICN voltage becomes higher than 510mV (typical) (SOFTSTART3) or (2) SS reaches 0.8V (typical) (SOFT-START2). As soon as switching is enabled, VC is free to slew under the control of the internal error amplifiers (EA1–EA6). This allows the average I age I

OUT(MASTER)

without saturating the slave’s regulation

OUT(SLAVE)

to quickly follow the aver-

loop. During soft-start the LT8708-1 employs the same

switch control mechanism as the LT8708. See the Switch Control: Soft-Start section of the LT8708 data sheet for more information.

When SS reaches 1.8V (typical), the LT8708-1 exits soft-start and enters normal mode. Typical values for the external soft-start capacitor range from 220nF to 2µF. It is recommended to use the same brand and value SS capacitor for all the synchronized LT8708/ LT8708-1(s). Using a slave SS capacitor value significantly higher than the master SS capacitor value can result in undesirable start-up behavior.

CONTROL OVERVIEW

The LT8708-1 is a slave current mode controller that regulates the average I

OUT(SLAVE)

based on the master’s ICP and ICN voltages, or equivalently, the average I

OUT(MASTER)

Figure1). In a simple example of I the CSPOUT–CSNOUT pins receive the I

. The main regulation loop involves EA6 (see

OUT(SLAVE)

regulation,

OUT(SLAVE)

feedback signal which is summed with the ICP and ICN signals from the LT8708 to generate the IMON_OP voltage using A1 (see Figure1). The IMON_OP voltage is compared to the internal reference voltage using EA6. Low IMON_OP voltages raise VC, which causes I

OUT(SLAVE)

to become more positive (or less negative) and increases the current out of the IMON_OP pin. Conversely, higher IMON_OP voltages reduce VC, which causes I

OUT(SLAVE)

to become less positive (or more negative) and reduces the current flowing out of the IMON_OP pin.

The VC voltage typically has a Min to Max range of about

1.2V. The maximum VC voltage commands the most positive inductor current, and thus, commands the most power flow from VIN to V

. The minimum VC voltage

OUT

commands the most negative inductor current, and thus, commands the most power flow from V

OUT

to VIN.

VC is the combined output of five internal error amplifiers EA1–EA6 as shown in Table3. In a common application, I

OUT(SLAVE)

would be regulated using the main regulation error amplifier EA6, while error amplifiers EA1 and EA5 are monitoring for excessive input current and EA3 and EA4 are disabled.

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OPERATION

TG1

BG1

BG2

87081 F03

LT8708-1

Table3. Error Amplifiers (EA1–EA6)

AMPLIFIER

NAME PIN NAME USED TO LIMIT OR REGULATE

EA1 IMON_INN Negative I

EA3 FBIN VIN Voltage

EA4 FBOUT V

EA5 IMON_INP Positive I

EA6 IMON_OP I

IN(SLAVE)

Voltage

OUT

IN(SLAVE)

OUT(SLAVE)

Note that the current and power flow can also be restricted to one direction, as needed, by the selected conduction mode discussed in the Unidirectional and Bidirectional Conduction section.

POWER SWITCH CONTROL

The LT8708-1 employs the same power switch control as the LT8708 (see Power Switch Control section of the LT8708 data sheet). Figure4 shows a simplified diagram of how the four power switches are connected to the inductor, VIN, V

Figure4. Simplified Diagram of the Buck-Boost Switches

and ground.

OUT

SW1 SW2

OUT

SENSE

TG2

UNIDIRECTIONAL AND BIDIRECTIONAL CONDUCTION

As with the LT8708, the LT8708-1 has one bidirectional and three unidirectional current conduction modes (CCM, HCM, DCM and Burst Mode operation, respectively). The LT8708-1’s MODE, DIR and RVSOFF pins operate in the same way as in the LT8708 to select the desired conduction modes. (See the Unidirectional and Bidirectional Conduction section of the LT8708 data sheet for details). In general, it is highly recommended to keep all phases of an LT8708 system in the same conduction mode. This is done by setting all MODE and DIR pins to the same states, or shorting all MODE pins together and all DIR

pins together. In addition, the RVSOFF pins of all phases should be connected together.

Note that when operating in the forward hybrid conduction mode (FHCM), the LT8708-1 operation differs slightly from the LT8708. Instead of measuring the ICN pin voltage for light load detection, the LT8708-1 measures the IMON_ON pin. Light load is detected when IMON_ON is above 245mV (typical). Therefore, FHCM operation requires a 17.4k resistor, and a parallel filter capacitor, from ground to the IMON_ ON pin of the LT8708-1. Reverse hybrid conduction mode (RHCM) operates identically in the LT8708 and LT8708-1. See the Unidirectional and Bidirectional Conduction: HCM section of the LT8708 data sheet for details.

ERROR AMPLIFIERS

Five internal error amplifiers combine to drive VC according to Table4, with the highest priority being at the top.

Table4. Error Amp Priorities

TYPICAL CONDITION PURPOSE

if IMON_INN > 1.21V

else

FBIN < 1.205V or

FBOUT > 1.207V or

IMON_INP > 1.209V or to Reduce Positive I

IMON_OP > 1.209V to Reduce Positive I

then VC

Rises

then VC

Falls

Rises

to Reduce Negative I

to Reduce Positive I

Increase Negative I

to Reduce Positive I

or Increase Negative I

OUT(SLAVE)

Default

IN(SLAVE)

Note that certain error amplifiers are disabled under the conditions shown in Table5. A disabled error amplifier is unable to affect VC and can be treated as if its associated row is removed from Table4.

Table5. Automatically Disabled Error Amp Conditions

ERROR

AMP PIN NAME

EA1 IMON_INN

EA3 FBIN 2*

EA4 FBOUT 1* 3*

EA5 IMON_INP

EA6 IMON_OP

VOUTLOMON

ASSERTED

VINHIMON ASSERTED

RDCM or

RHCM

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Page 20

LT8708-1

(CSPOUT–CSNOUT)M

(mV)

01020304050607080010

87081 F06

(CSPOUT–CSNOUT)M

(mV)

–80

–60

–40

–20020406080–80

–60

–40

–20020

406080

87081 F05

OPERATION

A 1* to 3* indicates that the error amplifier listed for that row is disabled under that column’s condition. The purposes of disabling the respective amplifiers are:

1* This improves transient response when VOUTLOMON

de-asserts.

2* This improves transient response when VINHIMON

de-asserts.

3* Since power can only transfer from V

prevents higher FBOUT/V

voltages from interfer-

OUT

to VIN, this

OUT

ing with the FBIN/VIN voltage regulation.

The primary regulation loop for the LT8708-1 involves EA6, which regulates the average I

OUT(SLAVE)

based on the ICP and ICN input voltages. Therefore, the IMON_OP pin must always have a proper compensation network connected. See the Loop Compensation section for more information.

The remaining error amplifiers can be disabled or used to limit their respective voltages or currents. When unused, the respective input pin(s) should be driven so that they do not interfere with the operation of the remaining amplifiers. Use Table6 as a guide.

Table6. Disabling Unused Amplifiers

AMPLIFIER

NAME PIN NAME

EA1 IMON_INN < 0.9V GND

EA3 FBIN > 1.5V LDO33

EA4 FBOUT

EA5 IMON_INP

TRANSFER FUNCTION: I

The LT8708-1 regulates I I

OUT(MASTER)

following the transfer functions1 shown in

TIE TO

DISABLE

< 0.9V GND

OUT(SLAVE)

VS I

proportionally to

EXAMPLE DISABLED

PIN CONNECTION

OUT(MASTER)

Figure5 and Figure6. The currents are measured (sensed) by the differential CSPOUT–CSNOUT pin voltages for each phase and the information is sent from the master to the slaves via the ICP and ICN pins. The transfer functions are represented by the slave’s current sense voltage (V

(CSPOUT–CSNOUT)S

age (V

(CSPOUT–CSNOUT)M

and Figure6 to I

) vs the master’s current sense volt-

). To convert the axes of Figure5

OUT(SLAVE)

vs I

OUT(MASTER)

, simply divide

Figure5. Typical V V

(CSPOUT–CSNOUT)M

Figure6. Typical V in FDCM, FHCM and Burst Mode Operation

(CSPOUT–CSNOUT)S

and master’s R

(CSPOUT–CSNOUT)S

and V

SENSE2

(CSPOUT–CSNOUT)S

in CCM

(CSPOUT–CSNOUT)M

values, respectively.

vs V

(CSPOUT–CSNOUT)M

by the slave’s

Figure 5 shows that increasing the master’s average current sense voltage V

(CSPOUT–CSNOUT)M

above ±60mV results in no additional current from the slave LT8708-1. As such, the average of V

(CSPOUT–CSNOUT)M

should be limited to ±50mV by connecting appropriate resistors from the IMON_OP and IMON_ON pins of the LT8708 to ground (see the IIN and I

Current Monitoring and

OUT

Limiting section of the LT8708 data sheet).

1. The ICP and ICN pins must be connected between the master and slave chips. 17.4k resistors and appropriate parallel capacitors are also required from those pins to ground.

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OPERATION

LT8708-1

Transfer Function: CCM

Figure5 shows the transfer function of the slave’s regulated current sense voltage (V

(CSPOUT–CSNOUT)S

master’s current sense voltage (V

(CSPOUT–CSNOUT)M)

) vs the

when the MODE pin is selecting CCM operation.

At light current levels (|V I

OUT(SLAVE)

is regulated slightly lower than I

(CSPOUT–CSNOUT)M

|<20mV),

OUT(MASTER)

. This ensures that the LT8708-1 delivers zero current when the master is delivering zero current and also ensures a smooth transition from positive to negative I

At high current levels (|V I

OUT(SLAVE)

is regulated to be the same as I

(CSPOUT–CSNOUT)M

OUT

|>20mV),

OUT(MASTER)

, offering good current sharing and thermal balance between the phases.

Note: If the LT8708-1 is configured to be in CCM while RVSOFF is being pulled low, use the FDCM transfer function in the next section.

Transfer Function: DCM, HCM and Burst Mode Operation

Figure6 shows the transfer function of the slave’s regulated current sense voltage (V master’s current sense voltage (V

(CSPOUT–CSNOUT)S

(CSPOUT–CSNOUT)M

) vs the

) when the MODE pin is selecting FDCM, FHCM or BurstMode operation.

The transfer function, in the non-CCM modes, is shown in Figure6 and has three distinct regions:

1. V

(CSPOUT–CSNOUT)M

< 10mV: In this region, where the master’s current is relatively small, the slave phases deliver zero current.

2. 10mV < V

(CSPOUT–CSNOUT)M

< 20.5mV: In this region, where the master’s current is moderate, the slave phases deliver less current than the master. The transfer function is hysteretic in this region. Therefore, the slave current will operate from 0mV to 13.5mV or from 6.7mV to 20.5mV if the master’s V

CSNOUT)M

was most recently below 10mV or above

(CSPOUT–

20.5mV, respectively.

3. V

(CSPOUT–CSNOUT)M

> 20.5mV: In this region of moderate to high current from the master, the slave delivers the same current as the master.

The transfer function is a mirror image of Figure6 when operating in the RDCM and RHCM conduction modes for V

(CSPOUT–CSNOUT)M

< 0mV. Simply multiply the values on the X and Y axes of Figure6 by –1 to illustrate the transfer function.

CURRENT MONITORING AND LIMITING

Monitoring: I

The LT8708-1 can monitor V

OUT(SLAVE)

current (I

OUT

OUT(SLAVE)

) in the negative direction. An external resistor is connected from the IMON_ON pin to ground, and the resulting voltage is linearly proportional to negative I

OUT(SLAVE)

. Unlike the LT8708’s IMON_ON pin, the LT8708-1’s IMON_ON pin does not regulate or limit I tive direction. See the IIN and I

OUT(SLAVE)

Current Monitoring

OUT

in the nega-

and Limiting section of the LT8708 data sheet for how to configure the IMON_ON current monitoring.

Monitoring and Limiting: I

IN(SLAVE)

The LT8708-1 can monitor VIN current (I

IN(SLAVE)

) in both the positive and negative directions by measuring the voltage across a current sense resistor R

SENSE1

using the CSPIN and CSNIN pins. The voltage is amplified and a proportional current is forced out of the IMON_INP and IMON_INN pins to allow for monitoring and limiting. This function is identical to the LT8708 and more information can be found in the Current Monitoring and Limiting section of the LT8708 data sheet.

As described above, the LT8708-1 has circuitry allowing for independent input current limiting of each phase. This per-phase current limiting is intended to be secondary to the limits imposed by the master. Typically, the master is configured to limit its own input current (I

IN(MASTER)

) thus limiting the command current to the slave. However, since the slave has its own independent input current sensing

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Page 22

LT8708-1

OPERATION

and limiting circuitry, it can be configured with redundant current limiting. It is recommended to set the slave input current limit magnitudes to be the same or higher than those set by the master. See the Applications Information section for more information about the I monitoring and limiting.

As with the LT8708, the LT8708-1 requires a 17.4k resistor and parallel filter capacitor to be connected from ground to the IMON_INP pin when using the RHCM conduction mode. If, in this case, it is also desired to set the LT8708-1’s positive I the LT8708’s positive I of the LT8708-1’s R LT8708’s R Current Limits section for details.

SENSE1

IN(SLAVE)

IN(MASTER)

SENSE1

value. See Configuring the I

current limit higher than

resistor as compared to the

IN(SLAVE)

limit, reduce the value

current

IN(SLAVE)

MULTIPHASE CLOCKING

A multiphase application usually has switching regulators operating at the same frequency but at different phases to reduce voltage and current ripple. The SYNC pin can be used to synchronize the LT8708-1’s switching frequency at a specific phase relative to the master LT8708 chip. A separate clock chip, e.g., LTC6902, LTC6909 etc., can be used to generate the clock signals and drive the SYNC pins of the LT8708 and LT8708-1(s). If only two phases are needed for the multiphase application, i.e., 0° and 180°, the LT8708-1’s SYNC pin can be connected to the LT8708’s CLKOUT pin to obtain the 180° phase shift. The master LT8708 can be synchronized to an external source or can be free-running based on the external RT resistor. It is recommended that the LT8708-1 is always synchronized to the same frequency as the LT8708 through the SYNC pin.

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APPLICATIONS INFORMATION

LT8708-1

This Applications Information section provides additional details for setting up a multiphase application using the LT8708-1(s) and LT8708. Topics include quick multiphase setup guidelines, choosing the total number of phases, clock synchronization, and selection of various external components. In addition, more information is provided about voltage lockouts, current monitoring, PCB layout considerations. This section wraps up with a design example.

QUICK-START MULTIPHASE SETUP

This section provides a step-by-step summary on how to setup a multiphase system using the LT8708-1(s) and LT8708.

Quick Setup: Design the Master Phase

Design the LT8708 application circuit according to the LT8708 data sheet. Make sure the maximum CSPOUT– CSNOUT current sense voltage is limited to ±50mV by setting the IMON_OP and IMON_ON resistor values equal to or higher than 17.4k. This is the master phase.

Quick Setup: Design the Slave Phase(s)

Step 1 – Power Stage: Apply the same power stage design

from the LT8708 application circuit to the LT8708-1 circuit. This includes the inductor, power MOSFETs and their gate resistors, R R tering, topside MOSFET driver supply (CB1, DB1, CB2, DB2) and Schottky diodes D1, D2, D3, D4 (if used). See the CIN and C capacitor values.

Step 2 – Peripheral Pins: The following components should be identical on the LT8708 as the LT8708-1:

• RT resistor

• SS pin capacitor

• INTVCC, GATEVCC, V

, CSPIN–CSNIN filtering, CSPOUT–CSNOUT fil-

SENSE2

Selection section on how to optimize the

OUT

capacitors

SENSE

, R

INCHIP

filtering, R

SENSE

and LDO33 pin bypass

SENSE1

Connect identical resistor divider networks on SHDN as well as on VINHIMON and VOUTLOMON (if used). If not used, connect VINHIMON to GND and/or VOUTLOMON to the LT8708-1’s LDO33. Connect the LT8708-1’s FBOUT pin to GND and the FBIN pin to the LT8708-1’s LDO33 node.

Step 3 – Interconnect: Connect the LT8708-1’s ICP, ICN, EXTVCC, SWEN and RVSOFF pins to their counterparts on the LT8708. Connect the same control signals, or connect the same value resistor dividers or voltages to the MODE pins and the DIR pins of the LT8708 and LT8708-1, respectively. Connect the LT8708’s CLKOUT signal or a clock chip’s phase shifted clock to the LT8708-1’s SYNCpin.

Step 4 – Regulation and Limiting: Connect a 17.4k resistor in parallel with a compensation network from IMON_OP to GND. Connect a resistor in parallel with a filter capacitor from IMON_ON to GND for current monitoring. Connect resistors in parallel with filter capacitors from IMON_INP and IMON_INN to GND, respectively, to set the magnitudes of the I equal to or higher than their counterparts on the LT8708.

Step 5: Repeat steps 1 through 4 to add any additional LT8708-1 phases.

Quick Setup: Evaluation

Test and optimize the stability of the multiphase system. See the Loop Compensation section for more details.

CHOOSING THE TOTAL NUMBER OF PHASES

In general, the number of phases needed is selected to meet a multiphase system’s total power requirement as well as each phase’s thermal requirement. In general, for a given application, the more phases that the system has, the less power that each phase needs to deliver, and the better the thermal performance that each phase has. In many cases, the total number of phases is selected to optimize the total input or output RMS current ripple. See the CIN and C

OUT

IN(SLAVE)

Selection section for more details.

current limits to be

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LT8708-1

OUT/VIN

0.9

0.60

APPLICATIONS INFORMATION

OPERATING FREQUENCY SELECTION

1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85

). The graph can be used in place of tedious

OUT

OUT/VIN

(IN,RMS)

is normal-

= n/N

OUT

The LT8708-1 uses a constant frequency architecture operating between 100kHz and 400kHz. The LT8708-1 should be synchronized to the same frequency as the LT8708 by connecting a clock signal to the SYNC pin. An appropriate resistor must be placed from the RT pin to ground. In general, use the same value RT resistor for all the synchronized LT8708 and LT8708-1(s). See the Operating Frequency Selection section of the LT8708 data sheet on how to select the LT8708’s switching frequency.

CIN AND C

VIN and V

SELECTION

OUT

capacitance is necessary to suppress volt-

OUT

age ripple caused by discontinuous current moving in and out of the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low ESR (equivalent series resistance). Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available.

Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. A ceramic capacitor, of at least 1µF at the maximum V from V

operating voltage, should also be placed

INCHIP

to GND as close to the LT8708-1 pins as

INCHIP

possible. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many ceramic capacitors,

0.55

0.50

0.45

0.40

0.35

OUT

0.30

(IN,RMS)

0.25

0.20

0.15

0.10

0.05

Figure7. Normalized Total Input RMS Ripple Current vs V for One to Six Phases in Buck Operation

The total input RMS ripple current I ized against the total output current of the multiphase system (I calculations. From the graph, the minimum total input RMS ripple current can be achieved when the product of the number of phases (N) and the output voltage V is approximately equal to integer multiples of the input voltage VIN or:

OUT/VIN

where n = 1, 2,…, N-1

Therefore, the number of phases can be chosen to minimize the input capacitance for given input and output voltages.

particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage.

Figure7 also shows the maximum total normalized input RMS current for one to six phases. Choose an adequate

CIN and C

Selection: VIN Capacitance

OUT

Discontinuous VIN current is highest in the buck region due to the M1 switch toggling on and off. Ensure that the CIN capacitor network has low enough ESR and is sized to handle the maximum RMS current. Figure7 shows the total input capacitor RMS ripple current for one to six phases with the V

to VIN ratios in buck operation.

OUT

CIN capacitor network to handle this RMS current.

CIN is also necessary to reduce the VIN voltage ripple caused by discontinuities and ripple of IIN. The effects of ESR and the bulk capacitance must be considered when choosing the correct capacitor for a given VIN ripple. A low ESR input capacitor sized for the maximum RMS current must be used. Add enough ceramic capacitance to

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TYPICAL APPLICATIONS

1–PHASE

2–PHASE

3–PHASE

4–PHASE

6–PHASE

OUT

– VIN)/V

OUT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.5

1.0

1.5

2.0

2.5

3.0

3.5

(OUT,RMS)

87081 F08

make sure VIN voltage ripple is adequately low for the application.

LT8708-1

CIN and C

Discontinuous V

Selection: V

OUT

Capacitance

OUT

current is highest in the boost region due to the M4 switch toggling on and off. Make sure that the C

capacitor network has low enough ESR and

OUT

is sized to handle the maximum RMS current. Figure8 shows the output capacitor RMS ripple current for one to six phases with the (V operations. The total output RMS ripple current I

– VIN) to V

OUT

ratios in boost

OUT

(OUT,RMS)

is normalized against the total output current of the multiphase system (I

). The graph can be used in place

OUT

of tedious calculations. From the graph, the minimum total output RMS ripple current can be achieved when the product of the number of phases (N) and duty cycle (V

OUT

– VIN)/V

OUT

is approximately equal to integers or:

OUT

= n/N

OUT

where n = 1,2,…, N-1

Therefore, the number of phases be chosen to minimize the output capacitance for given input and output voltages.

Figure8 also shows the maximum total normalized output RMS current for one to six phases. Choose an adequate C

capacitor network to handle this RMS current.

OUT

is also necessary to reduce the V

OUT

by discontinuities and ripple of I

OUT

ripple caused

OUT

. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given V

ripple. A low ESR

OUT

input capacitor sized for the maximum RMS current must be used. Add enough ceramic capacitance to make sure V

voltage ripple is adequate for the application.

OUT

Figure7 and Figure8 show that the peak total RMS input current in buck operation and the peak total RMS output current in boost operation are reduced linearly, inversely proportional to the number of phases used. It is important to note that the ESR-related power loss is proportional to the RMS current squared, and therefore a 3-phase implementation results in 90% less power loss when compared to a single-phase design. Battery/input protection fuse resistance (if used) PCB trace and connector resistance losses are also reduced by the reduction of the ripple

Figure8. Normalized Output RMS Ripple Current vs (V

)/VIN for One to Six Phases in Boost Operation

OUT–VIN

current in a multiphase system. The required amount of input and output capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses.

VINHIMON, VOUTLOMON AND RVSOFF

VINHIMON and VOUTLOMON offer the identical functions on the LT8708 and LT8708-1(s). See the VINHIMON, VOUTLOMON and RVSOFF section of the LT8708 data sheet for more details. If the VINHIMON and VOUTLOMON functions are used on the LT8708-1(s) as redundant monitoring functions, in general use the same value resistor dividers as on the LT8708. If the VINHIMON and/or VOUTLOMON functions are not used on the LT8708-1(s), tie VINHIMON to GND and/or VOUTLOMON to the respective LT8708-1’s LDO33 pin.

The RVSOFF pin has an internal comparator with a rising threshold of 1.374V (typical) and a falling threshold of 1.209V (typical). A low state on this pin inhibits reverse current and power flow. It is recommended to tie the RVSOFF pins of all the synchronized LT8708 and LT8708-1(s) together. In a multiphase system, if one or

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LT8708-1

CONTROLLER

APPLICATIONS INFORMATION

more chips’ VINHIMON or VOUTLOMON comparator is triggered, the RVSOFF pin is pulled low to prevent the entire multiphase system from delivering reverse current and power. The multiphase system will exit the RVSOFF operation when all the VINHIMON and VOUTLOMON comparators are de-asserted.

CONFIGURING THE I

IN(SLAVE)

As discussed in the Monitoring and Limiting: I

CURRENT LIMITS

IN(SLAVE)

section, the LT8708-1 can monitor and limit the input current independently of the master. The current limiting discussed in this section is intended to be secondary, or redundant, since the master is primarily in control of the amount of current commanded from the slave.

As shown in Figure9, the LT8708-1 measures I

IN(SLAVE)

with the CSPIN and CSNIN pins and can independently monitor and limit the current in both positive and negative directions. The operation of the input current monitor circuits is identical to the LT8708. More information about configuring these circuits can be found in the IIN and I

Current Monitoring and Limiting section of the

OUT

LT8708 data sheet.

When setting the I

IN(SLAVE)

current limits, it is recommended to set them equal to or higher than the magnitudes of the I

IN(MASTER)

limits. Consider that if the slave

reaches input current limiting before the master, the slave can no longer deliver additional current as requested by the master. With equal I

IN(SLAVE)

and I

IN(MASTER)

limits, slight output current mismatch, and hence slight thermal imbalance can still happen due to device tolerance. Bench evaluation should be carried out to ensure the selected I

IN(SLAVE)

limits meet the application’s thermal and stabil-

ity requirements.

REGULATING I

OUT(SLAVE)

: Circuit Description

This section describes the control circuitry in the LT8708-1 that regulates the output current I

OUT(SLAVE)

. The master LT8708 sends the ICP and ICN control signals to the slave LT8708-1 to set I Function: I

OUT(SLAVE)

vs I

OUT(MASTER)

OUT(SLAVE)

. See the Transfer

section for related

information.

Figure10 shows the primary LT8708-1 circuits involved in the regulation of I in Figure1. I

OUT(SLAVE)

. Additional circuitry is shown

is regulated by a feedback loop with ICP and ICN setting the desired current. The feedback loop involves the following sections:

• The VC pin controls the inductor current, thus indi-

rectly controlling I

OUT(SLAVE)

. Higher VC voltage

FROM

SYSTEM

LT8708-1

IMON_INN

20μA

Figure9. I

20μA

IMON_INN

SENSE1

IN(SLAVE)

CSPIN

gm = 1m

–

IMON_INPIMON_INN

IMON_INP

IN(SLAVE)

TO CONTROLLER V

CSNIN

–

1.21V

EA1

–

1.209V

EA5

–

IMON_INP

Current Monitor and Limit

FROM

OUT

LT8708-1

TO INDUCTOR

CURRENT CONTROL

87081 F08

Figure10. I

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SENSE2

OUT(SLAVE)

CSPOUT

–

70μA

IMON_OP

17.4k

OUT(SLAVE)

TO SYSTEM V

OUT

ICP

ICN

FROM

MASTER

CSNOUT

IMON_OP

–

1.209V

IMON_OP

ICP ICN

EA6

–

TO INDUCTOR

CURRENT CONTROL

Current Regulation and Monitor

87081 F09

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Page 27

10mΩ

TYPICAL APPLICATIONS

(CSPOUT–CSNOUT)M

(mV)

–80

–60

–40

–200204060

–1.6

–1.2

–0.8

–0.4

0.0

0.4

0.8

1.2

1.6

2.0

–80

–60

–40

–20

100

ICP, ICN VOLTAGE (V)

(CSPOUT–CSNOUT)S

(mV)

87081 F11

(CSPOUT–CSNOUT)S

ICN

ICP

(CSPOUT–CSNOUT)S

ICN

ICP

(CSPOUT–CSNOUT)M

(mV)

01020304050607080

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0102030405060

100

ICP, ICN VOLTAGE (V)

(CSPOUT–CSNOUT)S

(mV)

87081 F12

LT8708-1

results in higher I

OUT(SLAVE)

VC is driven by error amplifier EA6 during I

current and vice versa.

OUT(SLAVE)

regulation.

• During regulation, the IMON_OP voltage is very close to the EA6 reference of 1.209V. Small changes in IMON_OP voltage make large adjustments to VC, and thus the I

• Resistor R

OUT(SLAVE)

SENSE2

converts the I

current.

OUT(SLAVE)

current into a voltage that can be measured by amplifier A1. This voltage is denoted as V

(CSPOUT–CSNOUT)S

in Figure10.

• Transconductance amplifier A1 makes sure that I

OUT(SLAVE)

and ICN signals. If I

is equal to the current set by the ICP

OUT(SLAVE)

becomes higher than requested by ICP and ICN, additional current is delivered out of A1. This raises IMON_OP which reduces VC and reduces I

OUT(SLAVE)

. Conversely, if I

OUT(SLAVE)

becomes lower than requested by ICP and ICN, the current out of A1 is reduced. This lowers IMON_OP which raises VC and increases I

OUT(SLAVE)

Figure11 illustrates, in CCM mode, the typical relationship between the master’s output current I

OUT(MASTER)

, the resulting ICP and ICN control voltages, and the further resulting I

OUT(SLAVE)

current. Figure11 can best be

explained with a few examples.

In these examples, the output current sense resistors are R First, assume the master’s output current I

= 10mΩ for the master and the slave devices.

SENSE2

OUT(MASTER)

is4A. This results in the master LT8708 measuring a

current sense voltage of V

(CSPOUT–VCSNOUT)M

= 4A • 10mΩ = 40mV. Locate 40mV along the X-axis of Figure11. The corresponding ICP and ICN voltages are ~1V and 0V, respectively. These ICP and ICN voltages are sent from the LT8708 to the LT8708-1. As a result, the LT8708-1 regulates I

OUT(SLAVE)

40mV (from Figure 10)

to:

(CSPOU T – CSNOUT)S

SENSE 2

= 4A

Alternatively, if the master’s output current I

OUT(MASTER)

is –2A. Then the master LT8708 will measure a current sense voltage of V

(CSPOUT–VCSNOUT)M

= –2A • 10mΩ = –20mV. Locate –20mV along the X-axis of Figure11. The corresponding ICP and ICN voltages are 0V and ~0.7V, respectively. These ICP and ICN voltages are sent from the LT8708 to the LT8708-1. As a result, the LT8708-1 regulates I

OUT(SLAVE)

–20mV (from Figure 10)

to:

(CSPOU T – CSNOUT)S

SENSE2

= – 2A

Figure12 illustrates the relationship between I ICP, ICN and I

OUT(SLAVE)

in FDCM, FHCM and Burst Mode

OUT(MASTER)

operation. Use Figure12, instead of Figure11, to understand the control voltage relationships when operating in FDCM, FHCM or Burst Mode Operation. Figure12 can

Figure11. I

OUT(SLAVE)

Control Voltage Relationships (CCM)

For more information www.analog.com

Figure12. I

OUT(SLAVE)

Control Voltage Relationships

(FDCM, FHCM and Burst Mode Operation)

Rev 0

Page 28

LT8708-1

APPLICATIONS INFORMATION

also be used to understand RDCM and RHCM operation by multiplying the V

CSNOUT)S

axis values by –1.

(CSPOUT–CSNOUT)M

and the V

(CSPOUT–

As mentioned previously, 17.4k resistors must be connected from the ICP and ICN pins to ground. Proper resistor connections are required to produce the correct ICP and ICN voltages, and result in the correct I

OUT(SLAVE)

currents.

OUT(SLAVE)

: Configuration

regulation is the main regulation loop for the LT8708-1 and should always be enabled. Therefore, always connect a 17.4k resistor in parallel with a compensation network from the IMON_OP pin to ground. Note that the IMON_OP pin cannot be used for monitoring the I

OUT(SLAVE)

current.

Figure5 and Figure11 show that increasing the master’s average current sense voltage V

(CSPOUT–CSNOUT)M

above ±60mV results in no additional current from the slave LT8708-1. As such, the target average of V

CSNOUT)M

should be limited to ±50mV by connecting

(CSPOUT–

appropriate resistors from the IMON_OP and IMON_ON pins of the LT8708 to ground (see the IIN and I

OUT

Current

Monitoring and Limiting section of the LT8708 data sheet).

In addition, the instantaneous differential voltage V

(CSPOUT–CSNOUT)S

should remain between –100mV and 100mV due to the limited current that can be driven out of IMON_OP. If the instantaneous V

(CSPOUT–CSNOUT)S

age V

(CSPOUT–CSNOUT)S

exceeds these limits but the aver-

is between –50mV and 50mV, consider including the current sense filter described in the IIN and I

Current Monitoring and Limiting sec-

OUT

tion of the LT8708 data sheet. The filter can reduce the instantaneous voltage while preserving the average. In general, use the same value current sense filter for all the synchronized LT8708 and LT8708-1(s).

Finally, IMON_OP should be compensated and filtered with capacitor C

IMON_OP

. At least a few nF of capacitance

is usually necessary.

LOOP COMPENSATION

To compensate a multiphase system of the LT8708 and LT8708-1(s), most of the initial compensation component selection can be done by analyzing the individual voltage regulator and/or current regulator(s) independently of each other. Use the total input and output bulk capacitance of the multiphase system in the stability analysis for each of the following steps.

1. Analyze the stability of the LT8708 as a single phase without any additional LT8708-1 phases included. This includes all the regulation loops that will be used by the master LT8708, such as voltage regulation (FBOUT, FBIN) and/or current regulation (IMON_INP, IMON_INN, IMON_OP, IMON_ON). Determine the initial values for the VC pin compensation network, and the relevant IMON_XX pin capacitors for the master LT8708. Further adjustment of these values will be done in Step 4. Adjustment to CIN and C

may also

OUT

be necessary as part of this analysis. See the Loop Compensation section of the LT8708 data sheet for more details. LTspice® transient simulation can be helpful for this step.

2. Analyze the stability of the I

OUT(SLAVE)

current regulation loop of a standalone LT8708-1 phase. Adjust the VC and IMON_OP compensation networks of the LT8708-1 to achieve stability and maximum bandwidth. Bench stability evaluation of a standalone LT8708-1 can be carried out by driving the ICP and ICN pins with external voltage sources.

A similar approach to that used for analyzing the

LT8708 in constant-current regulation can be employed in compensating the standalone LT8708-1 current regulator. An IMON_OP capacitor of at least a few nF is necessary to maintain I

OUT(SLAVE)

regulation loop stability. In addition, adding a resistor of a few hundred Ohms in series with this capacitor can often provide additional phase margin.

If any of the I

IN(SLAVE)

regulation loops, i.e. IMON_INP and IMON_INN, is used for secondary or redundant current limiting, carry out the corresponding stability analysis on the standalone LT8708-1. Use the same

Rev 0

For more information www.analog.com

Page 29

TYPICAL APPLICATIONS

LT8708-1

approach that is used for compensating the LT8708’s input current regulation loops.

3. Complete the multiphase system with the LT8708 and LT8708-1(s). A few nF of capacitance should be placed on the ICP and ICN pins near the LT8708 for proper compensation. In addition, adding a few hundred Ohms in series with these capacitors can often provide extra phase margin to the multiphase system. See Figure2 as an example.

4. Perform the loop stability analysis in simulation and/ or on the bench. Primarily, adjust the LT8708’s VC compensation network for stability. A trim pot and selectable capacitor bank can be used on the VC pin to determine the optimal values. Typically, the LT8708 should be adjusted to have lower bandwidth than the LT8708-1 phases. This can be achieved by increasing the capacitance and/or reducing the series resistance of the LT8708’s VC compensation network.

If the LT8708 operates in constant current limit, as

set by one or more of the IMON_xx pins, adjust the respective LT8708 IMON_xx filter capacitors as well to achieve optimal loop stability.

CIRCUIT BOARD LAYOUT CHECKLIST

The LT8708’s circuit board layout guidelines also apply to the LT8708-1(s). Refer to the Circuit Board Layout Checklist section of the LT8708 data sheet for details.

In addition:

• Route the ICP and ICN traces together with minimum PCB trace spacing from the LT8708 to the LT8708-1(s). Avoid having these traces pass through noisy areas, such as switch nodes.

• Star connect the VIN and V

power buses as well

OUT

as the power GND bus to each LT8708/ LT8708-1(s). Minimize the voltage difference between local VIN, V

and power GNDs, respectively.

OUT

DESIGN EXAMPLE

In this section, we start with the Design Example in the LT8708 data sheet, and expand it into a 2-phase regulator. The design requirements from the LT8708 data sheet are listed below with the total output current (I

OUT

) and the total input current (IIN) specifications doubled for two phases.

VOLTAGE LOCKOUTS

The LT8708-1 offers the same voltage detectors as the LT8708 to make sure the chip is under proper operating conditions. See the Voltage Lockouts section of the LT8708 data sheet for more details.

Although allowed with a standalone LT8708, a resistor divider connected to the SWEN pins should never be used for undervoltage detection in a multiphase system (see the Start-Up: SWEN Pin section for proper ways to connect or drive the SWEN pin in a multiphase system). Instead, an external comparator chip can be used to monitor undervoltage conditions, and its output drives the common SWEN node in a multiphase system through a current limiting resistor.

VIN = 8V to 25V

= 12V (VIN regulation voltage set by LT8708

IN_FBIN

FBIN loop)

OUT_FBOUT

= 12V (V

regulation voltage set by

OUT

LT8708 FBOUT loop)

OUT(MAX, FWD)

IN(MAX, RVS)

= 10A

= 6A

f =150kHz

This design operates in CCM.

Maximum ambient temperature = 60°C

Use the same RT, R

SENSE

, R

SENSE2

resistors, inductor, external MOSFETs and capacitors from the Design Example of the LT8708 data sheet for LT8708-1.

SYNC Pin: Since this is a 2-phase system, the slave chip operates 180° out of phase from the master chip. Connect the LT8708’s CLKOUT pin to the LT8708-1’s SYNC pin.

Rev 0

For more information www.analog.com

Page 30

LT8708-1

• V

APPLICATIONS INFORMATION

MODE Pin: Connect the MODE pin to GND for CCM operation.

SWEN and RVSOFF Pins: Connect the SWEN and RVSOFF pins together for the LT8708 and LT8708-1, respectively. This synchronizes the start-up and operation mode between the two chips.

ICP and ICN Pins: Connect two 17.4k resistors from the ICP and ICN pins to GND, respectively. Place them next to the LT8708 chip and route the ICP and ICN traces to the LT8708-1’s counterparts, respectively.

IMON_OP

Selection: Connect 17.4k from IMON_OP to

GND for the LT8708-1.

IMON_ON

to monitor the I

Selection: LT8708-1’s IMON_ON is only used

OUT(SLAVE)

in the reverse direction. A same value resistor of 24.9k from the LT8708 design example is selected here to provide an IMON_ON reading on the same scale as the one on the LT8708.

SENSE1

, R

IMON_INP

, R

IMON_INN

selection: IMON_INP

and IMON_INN are used to provide current limits for the LT8708-1 only. They are set to be equal to the maximum per phase VIN current in the forward and reverse directions, respectively.

The maximum slave VIN current in the forward directionis:

And the maximum slave VIN current in the reverse direction is:

IN(M AX,RVS,SLAVE)

Choose R

IMON_INP

LT87081’s V R

is calculated to be:

SENSE1

SENSE 1

Using the equation given in the IIN and I

= I

IN(IMON_ON ,MASTER)

= 3.6A

to be around 17.4k, so that the

CSPIN–CSNIN

50mV

limit becomes 50mV, and the

≅ 6mΩ

OUT

Current Monitoring and Limiting section of the LT8708 data sheet, R

IMON_INP

And R

is recalculated to be:

IMO N_INP

IMO N_INN

IMON_INN

IN(M AX, FW D,SLAV E)

is calculated to be:

IN(M AX, RVS,SLAVE)

1.209

• 1m

1.21

• 1m

• R

SEN SE2

• R

SEN SE2

+ 20µA

Ω ≅ 16.2kΩ

+ 20µA

Ω ≅ 2 9.4kΩ

FBOUT Pin: Connect FBOUT pin to GND to disable the FBOUT pin.

FBIN Pin: Connect FBIN pin to LDO33 of the LT8708-1 to disable the FBIN pin.

IN(M AX,FWD,SLAVE)

6A • 12V

(IMON_OP,MASTER)

= 9A

IN,MIN

OUT

For more information www.analog.com

Rev 0

Page 31

IN2

IN7

OUT1

OUT5

*SEE THE UNI AND

BIDIRECTIONAL

CONDUCTION

SECTION OF THE LT8708

DATA SHEET

POWER TRANSFER

TYPICAL APPLICATIONS

2-Phase 12V Bidirectional Dual Battery System with FHCM and RHCM

10V TO 16V

BATTERY

–

OUT4

OUT2

OUT3

×2

OUT1

TO DIODE

4.7μF

12.1k

133k

20k

154k

100k

100nF

47nF

100Ω

1Ω

0.22μF

1Ω2mΩ

CSPOUT

EXTV

CSNOUT

ICP

ICN

FBOUT

VOUTLOMON

INTV

OUT

BAT2

2mΩ

4.7μF

GATEV

IMON_OP

3.3Ω

23.7k

IMON_ON

IMON_INP

200Ω

47nF

17.4k

4.7nF

CLKOUTSYNC

IMON_INN

17.4k

4.7nF

17.4k

23.7k

47nF

4.7nF

BOOST2

LT8708’S

BOOST1

LT8708’S

LT8708-1

3.3Ω

4.7μF

17.4k200Ω

OUT7

×2

IMON_OP

IMON_ON

IMON_INP

IMON_INN

17.4k

4.7nF

CLKOUTSYNC

OUT6

2mΩ

OUT5

M11

TO DIODE

100nF

4.7μF

47nF

100Ω

1Ω

0.22μF

1Ω2mΩ

CSPOUT

EXTV

CSNOUT

ICP

ICN

INTV

GATEV

4.7nF

17.4k

4.7nF

BOOST2

LT7081’S

BOOST1

LT8708-1’S

10nF

120kHz

87081 TA03a

: SUNCON, 18μF, 40V

OUT6

, C

OUT4

C ,

IN5

, C

IN4

40HVP18M

M5–M7: T2N7002AK, TOSHIBA

SWEN

LD033

LDO33

LD033

20k

27.4k

100k

SSRT

CMODE

RVSOFF

12.1k

127k

365k 1μF

1nF 33nF

10k

54.9k

4.7μF

220pF

68.1k

XOR

3.3μH

2mΩ

1nF

10Ω

M9 M10

TO DIODE

IN7

1μF

IN6

IN5

×2

GND BG2SW2 BOOST2 TG2

10Ω

M2 M3

IN1

IN4

×2

IN3

10V TO 16V

10Ω

TO DIODE

IN2

–

BATTERY

1nF

1Ω

0.22μF

1Ω

TG1 BOOST1 SW1 BG1 CSP CSN

CSNIN

100nF

47nF

100Ω

1μF

665k

100k

DECISION LOGIC

CSPIN

FWD (3V)RVS (0V)

INCHIP

93.1k

SHDN

FBIN

DIR_CTRL

LT8708

VINHIMON

DIR

3.3μH

2mΩ

BAT1

GND BG2SW2 BOOST2 TG2

10Ω

1nF

LT8708-1

1Ω

0.22μF

1Ω

TG1 BOOST1 SW1 BG1 CSP CSN

INCHIP

CSPIN

SHDN

FBIN

VOUTLOMON

FBOUT

VINHIMON

SWEN

LD033

665k

100nF

100Ω

CSNIN

47nF

100k

DIR

LDO33

LD033

100k

SSRT

CMODE

RVSOFF

127k

365k 1μF

470pF 8.2nF

10k

54.9k

4.7μF

: 10µF, 50V, X7R

, C

: 470μF, 50V

C ,

IN3

, C

OUT3

M1–M4, M8–M11: INFINEON BSC010N04LS

: CENTRAL SEMI CMMR1U-02-LTE

, D

L1, L2: 3.3μH, WURTH 701014330

XOR: DIODES INC. 74AHC1G86SE-7

Rev 0

For more information www.analog.com

Page 32

LT8708-1

3μs/DIV

87081 TA03b

LT8708-1 SW1

3μs/DIV

LT8708-1 SW1

60ms/DIV

20A/DIV

TYPICAL APPLICATIONS

2-Phase 12V Bidirectional Dual Battery System with FHCM and RHCM

IL1 AND I

10A/DIV

LT8708 SW1

10V/DIV

Forward Conduction V ~12V, V

BAT2

= ~14V, I

BAT1

= ~30A

OUT

Direction Change with V

DIR

5V/DIV

~12V, V

BAT2

= ~12V

IL1 AND I

LT8708 SW1

BAT1

Reverse Conduction V ~12V, V

BAT2

10A/DIV

10V/DIV

87081 TA03d

BAT1

= ~14V, IIN = ~30A

87081 TA03c

Rev 0

For more information www.analog.com

Page 33

LT8708-1

IN2

IN7

OUT1

OUT5

*SEE THE UNI AND

BIDIRECTIONAL

CONDUCTION

SECTION OF THE LT8708

DATA SHEET

POWER TRANSFER

TYPICAL APPLICATIONS

4-Phase 48V to 12V Bidirectional Dual Battery System with FHCM and RHCM

87081 TA04a

200Ω

17.4k

200Ω

23.7k

200Ω

17.4k

4.7nF

CLKOUTSYNC

IMON_INP

IMON_INN

SSRT

CMODE

RVSOFF

100k

18.2k

100k

22nF

127k

17.4k

13.3k

30.1k

47nF

10k

4.7nF

BOOST2

LT8708’S

BOOST1

LT8708’S

4.7nF

120kHz

365k 1μF

1nF 68nF

54.9k

4.7μF

220pF

68.1k

XOR

BOOST2

3.3Ω

4.7μF

OUT7

×2

OUT6

2mΩ

OUT5

M11

TO DIODE

10Ω

L2, 10μH

M9 M10

TO DIODE

IN7

5mΩ

IN6

IN5

×2

100nF

4.7μF

47nF

100Ω

1Ω

0.22μF

1Ω

1.5mΩ

10Ω

1nF

3.3nF

1Ω

0.22μF

1Ω

100nF

100Ω

1μF

340k

GND BG2SW2 BOOST2 TG2

TG1 BOOST1 SW1 BG1 CSP CSN

20k

CSPOUT

CSNOUT

CSNIN

47nF

EXTV

INCHIP

CSPIN

ICP

SHDN

ICN

INTV

LT8708-1

FBIN

VOUTLOMON

FBOUT

VINHIMON

LD033

GATEV

IMON_OP

SWEN

DIR

IMON_ON

LD033

LT7081’S

LT8708-1’S

17.4k200Ω

4.7nF

10nF

17.4k

4.7nF

17.4k

4.7nF

120kHz

CLKOUTSYNC

IMON_INP

IMON_INN

SSRT

365k 1μF

470pF 12nF

10k

CMODE

54.9k

LDO33

RVSOFF

4.7μF

127k

100k

**4-PHASE CLOCK

SIGNALS FROM

CLOCK CHIP

SUCH AS LTC6909

BOOST1

PHASE 2

CLK1

CLK2

CLK3

PHASE 3

CLK4

: SUNCON, 18μF, 40V

OUT7

, C

OUT6

C ,

IN5

, C

IN4

40HVP18M

M5–M7: T2N7002AK, TOSHIBA

PHASE 4

: 10µF, 50V, X7R

, C

: 470μF, 50V

C ,

IN3

, C

OUT3

M1–M4, M8–M11: INFINEON BSC010N04LS

: CENTRAL SEMI CMMR1U-02-LTE

, D

L1, L2: 10μH, COILCRAFT SER2918H-103KL

XOR: DIODES INC. 74AHC1G86SE-7

10V

TO 16V

BATTERY

–

OUT3

OUT4

×2

OUT2

OUT1

M2 M3

IN1

IN4

×2

IN3

24V TO 55V

TO DIODE

1nF

10Ω

TO DIODE

IN2

–

BATTERY

4.7μF

3.3Ω

12.1k

133k

12.1k

93.1k

17.8k

100nF

47nF

100Ω

1Ω

0.22μF

1Ω

1.5mΩ

10Ω

1nF

3.3nF

1Ω

0.22μF

1Ω

100nF

100Ω

1μF

340k

EXTV

CSPOUT

CSNOUT

GND BG2SW2 BOOST2 TG2

TG1 BOOST1 SW1 BG1CSP CSN

CSNIN

CSPIN

47nF

20k

FWD (3V)RVS (0V)

DECISION LOGIC

FBOUT

VOUTLOMON

INCHIP

SHDN

340k

ICP

ICN

INTV

LT8708

FBIN

VINHIMON

DIR_CTRL

DIR

4.7μF

GATEV

IMON_OP

SWEN

LD033

IMON_ON

LDO33

LD033

20k

16.9k

OUT

BAT2

2mΩ

10μH

5mΩ

BAT1

Rev 0

For more information www.analog.com

Page 34

LT8708-1

56ms/DIV

87081 TA04b

PHASE 1 I

PHASE 2 I

PHASE 3 I

2μs/DIV

87081 TA04c

PHASE 1 TO

TYPICAL APPLICATIONS

4-Phase 48V to 12V Bidirectional Dual Battery System with FHCM and RHCM

Direction Change Phase 1 to 4 Inductor Current

DIR

5V/DIV

20A/DIV

PHASE 4 I

5A/DIV

Rev 0

For more information www.analog.com

Page 35

PACKAGE DESCRIPTION

NOTE:

1. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES IN DEGREES.

2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08MM.

3. WARPAGE SHALL NOT EXCEED 0.10MM.

4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S).

UHG Package

LT8708-1

40-Lead Plastic QFN (5mm × 8mm)

(Reference LTC DWG # 05-08-1528 Rev A)

0.70 ±0.05

8.00 ±0.10

5.50 ±0.05

4.10 ±0.05

PIN 1 TOP MARK

3.50 REF

5.00 ±0.10

5.85 ±0.10

3.10 ±0.10

0.25 ±0.05

6.50 REF

7.10 ±0.05

8.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.00 TYP

0.75 TYP × 4

PACKAGE OUTLINE

C 0.35

4034

0.40 ±0.05

133

0.25 ±0.05

0.50 BSC

0.75 ±0.05

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

5.85 ±0.10

0.675

2222

REF

DETAIL A

0.20 REF

0.00 – 0.05

2115

0.203 ±0.008

DETAIL A

0.00 – 0.05

5. REFER JEDEC M0-220.

0.55 REF

0.203 +0.058, –0.008 TERMINAL THICKNESS

1.00 TYP

BOTTOM VIEW—EXPOSED PAD

For more information www.analog.com

3.10 ±0.10

R = 0.125 TYP

DETAIL B

(UHG) QFN 0417 REV A

DETAIL B

0.08 REF

0.31 REF

Rev 0

Page 36

LT8708-1

IN2

IN7, COUT1

OUT5

TYPICAL APPLICATION

4-Phase 48V to 12V Bidirectional Dual Battery System with FHCM and RHCM

BAT1

24V TO 55V

BATTERY

–

POWER TRANSFER

DECISION LOGIC

FWD (3V)RVS (0V)

DIR_CTRL

*SEE THE UNI AND BIDIRECTIONAL CONDUCTION SECTION OF THE LT8708 DATA SHEET

220pF

68.1k

**4-PHASE CLOCK SIGNALS FROM CLOCK CHIP SUCH AS LTC6909

, DB2, DB3, DB4: CENTRAL SEMI CMMR1U-02-LTE

L1, L2: 10μH, COILCRAFT SER2918H-103KL XOR: DIODES INC. 74AHC1G86SE-7

CLK1 CLK2 CLK3 CLK4

XOR

IN4

100k

340k

20k

IN1

×2

1μF

340k

100Ω

20k

340k

16.9k

IN5

×2

20k

18.2k M7

IN6

1μF

100Ω

LD033

M1–M4, M8–M11: INFINEON BSC010N04LS C

, C

OUT3

, C

IN3

LD033

5mΩ

: 470μF, 50V

IN3

LD033

100k

127k

4.7μF

LD033

100k

127k

4.7μF

100nF

47nF

100nF

47nF

, C

IN2

CSNIN

CSPIN V

SHDN

FBIN VINHIMON

DIR

SWEN

LDO33

RVSOFF

IN7

CSNIN

CSPIN V

SHDN

VOUTLOMON FBIN FBOUT VINHIMON

SWEN DIR

LDO33

RVSOFF

TO DIODE

1Ω

TG1 BOOST1 SW1 BG1CSP CSN

INCHIP

TO DIODE

1Ω

TG1 BOOST1 SW1 BG1 CSP CSN

INCHIP

: 10µF, 50V, X7R

54.9k

0.22μF

CMODE

1Ω

3.3nF

10k

1nF 68nF

1Ω

3.3nF

10k

470pF 12nF

10μH

M2 M3

10Ω

1nF

1.5mΩ

1Ω

1nF

10Ω

LT8708

365k 1μF

L2, 10μH

M9 M10

10Ω

1nF

10Ω

LT8708-1

365k 1μF

M5–M7: T2N7002AK, TOSHIBA C

, C

IN4

IN5, COUT6

40HVP18M

0.22μF

GND BG2SW2 BOOST2 TG2

SSRT

1Ω

1.5mΩ

0.22μF

GND BG2SW2 BOOST2 TG2

SSRT

PHASE 3

PHASE 4

, C

: SUNCON, 18μF, 40V

OUT7

TO DIODE

CSPOUT

CSNOUT

EXTV

VOUTLOMON

FBOUT

INTV

GATEV

IMON_OP IMON_ON IMON_INP

IMON_INN

CLKOUTSYNC

120kHz

TO DIODE

CSPOUT

CSNOUT

EXTV

INTV

GATEV

IMON_OP IMON_ON IMON_INP

IMON_INN

CLKOUTSYNC

120kHz

2mΩ

OUT2COUT4

OUT1

47nF

4.7nF

30.1k

2mΩ

OUT5

47nF

4.7μF

4.7nF

17.4k

100nF

17.8k

17.4k

13.3k

OUT6COUT7

100nF

17.4k

×2

93.1k

12.1k

4.7μF

200Ω

23.7k

22nF

4.7nF

×2

TO LT8708’S BOOST1

17.4k200Ω

4.7nF LT8708-1’S

10nF

BOOST1

ICP ICN

M11

ICP ICN

CC CC

47nF

PHASE 2

1Ω

100Ω

1Ω

100Ω

4.7nF

SEE MORE DETAILS OF THIS APPLICATION ON PAGE 33.

133k

12.1k

3.3Ω

DB1D

LT8708’S

BOOST2

4.7μF

OUT

BAT2

OUT3

10V TO 16V BATTERY

–

4.7μF

200Ω

17.4k

3.3Ω

LT7081’S BOOST2

17.4k

4.7nF

87081 TA02a

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≤ 150V, Up to 99% Efficiency Drives Logic-Level

OUT

or STD Threshold MOSFETs, TSSOP-38 Package

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Range: 0.8V to 60V, Boost V

OUT

Up to 60V

OUT

Up to 60V,

OUT

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0.8V ≤ V

≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40μA,

OUT

4mm × 5mm QFN-24, TSSOP-24, TSSOP-38(31) Packages

VIN/V

Up to 100V, Ideal for High Power 48V/12V Automotive Battery

OUT

Applications

D16899-0-6/18(0)

www.analog.com

Rev 0

Linear Technology Analog Devices LT8708-1 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

APPLICATIONS

TYPICAL APPLICATION

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS

PIN FUNCTIONS

BLOCK DIAGRAM

OPERATION

COMMON LT8708-1 AND LT8708 FEATURES

ADDING PHASES TO AN LT8708 APPLICATION

Operation

Adding Phases: The Master LT8708

Adding Phases: The Slave LT8708-1

START-UP

Start-Up: SWEN Pin

Start-Up: Soft-Start of Switching Regulator

CONTROL OVERVIEW

POWER SWITCH CONTROL

UNIDIRECTIONAL AND BIDIRECTIONAL CONDUCTION

ERROR AMPLIFIERS

Transfer Function: CCM

Transfer Function: DCM, HCM and Burst Mode Operation

CURRENT MONITORING AND LIMITING

MULTIPHASE CLOCKING

APPLICATIONS INFORMATION

QUICK-START MULTIPHASE SETUP

Quick Setup: Design the Master Phase

Quick Setup: Design the Slave Phase(s)

Quick Setup: Evaluation

CHOOSING THE TOTAL NUMBER OF PHASES

OPERATING FREQUENCY SELECTION

VINHIMON, VOUTLOMON AND RVSOFF

LOOP COMPENSATION

CIRCUIT BOARD LAYOUT CHECKLIST

DESIGN EXAMPLE

VOLTAGE LOCKOUTS

TYPICAL APPLICATIONS

PACKAGE DESCRIPTION

TYPICAL APPLICATION

RELATED PARTS