Linear Technology Analog Devices LT8708 Datasheet

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BAT2

= 13.5V

OUT

= 15A

BAT1

(V)

101214

100

EFFICIENCY (%)

EFFICIENCY

8708 TA01b

RVS (0V)

BATTERY

80V Synchronous 4-Switch Buck-Boost DC/DC

Controller with Flexible Bidirectional Capability

FEATURES DESCRIPTION

LT8708

Single Inductor Allows VIN Above, Below, or Equalto V

Six Independent Forms of Regulation

VIN Current (Forward and Reverse)

VIN and V

Forward and Reverse Discontinuous Conduction

OUT

Current (Forward and Reverse)

OUT

Voltage

OUT

Mode Supported

Supports MODE and DIR Pin Changes While Switching

Synchronous Rectification: Up to 99% Efficiency

Available in 40-Lead (5mm × 8mm) QFN with High

Range 2.8V (Need EXTVCC > 6.4V) to 80V

INCHIP

Range: 1.3V to 80V

OUT

Voltage Pin Spacing

APPLICATIONS

High Voltage Buck-Boost Converters

Bidirectional Charging System

Automotive 48V Systems

The LT®8708 is a high performance buck-boost switching regulator controller that operates from an input voltage that can be above, below or equal to the output voltage. Features are included to simplify bidirectional power conversion in battery/capacitor backup systems and other applications that may need regulation of V

OUT

, VIN, I

OUT

, and/or IIN. Forward and reverse current can be monitored and limited for the input and output sides of the converter. All four current limits (forward input, reverse input, for ward output and reverse output) can be set independently using four resistors on the PCB.

The MODE pin can select between discontinuous conduction mode (DCM), continuous conduction mode (CCM), hybrid conduction mode (HCM) and Burst Mode® operation. In combination with the DIR (direction) pin, the chip can be configured to process power only from VIN to V from V

to VIN. With a wide 2.8V to 80V input and 1.3V

OUT

or only

to 80V output range, the LT8708 is compatible with most solar, automotive, telecom and battery-powered systems.

All registered trademarks and trademarks are the property of their respective owners.

TYPICAL APPLICATION

12V Bidirectional Dual Battery System with FHCM and RHCM

BAT1

10V

TO 16V

BATTERY

–

POWER TRANSFER

DECISION LOGIC

FWD (3V)

LD033

Document Feedback

LIM

CSNIN

CSPIN V

SHDN

FBIN VINHIMON

DIR

SWEN LDO33

RVSOFF

TO DIODE

TG1 BOOST1 SW1 BG1 CSPCSN

INCHIP

CMODE

TO DIODE

GND BG2SW2 BOOST2 TG2

LT8708

SSRT

CSPOUT

CSNOUT

EXTV

VOUTLOMON

FBOUT

INTV

GATEV IMON_OP IMON_ON

IMON_INP IMON_INN

CLKOUTSYNC

8708 TA01a

126kHz

ICN ICP

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LIM

DB1D

BOOST1TOBOOST2

BAT2

10V

TO 16V

–

Efficiency

Rev 0

LT8708

TABLE OF CONTENTS

Features ..................................................... 1

Applications ................................................ 1

Typical Application ........................................ 1

Description.................................................. 1

Absolute Maximum Ratings .............................. 3

Order Information .......................................... 3

Pin Configuration .......................................... 3

Electrical Characteristics ................................. 4

Typical Performance Characteristics ................... 9

Typical Performance Characteristics .................. 11

Pin Functions .............................................. 13

Block Diagram ............................................. 15

Operation................................................... 16

Typographical Conventions ..................................... 16

Start-Up .................................................................. 16

Start-Up: SHDN Pin ............................................ 16

Start-Up: SWEN Pin ............................................16

Start-Up: Soft-Start of Switching Regulator ....... 17

Control Overview .................................................... 17

Power Switch Control ............................................ 18

Switch Control: Buck Region (VIN >> V

Switch Control: Buck-Boost (VIN ≅ V

Switch Control: Boost Region (VIN << V

OUT

) ......... 19

OUT

) ....... 19

) ...... 20

Switch Control: Soft-Start .................................. 20

Uni and Bidirectional Conduction ............................20

Bidirectional Conduction: CCM .......................... 21

Unidirectional Conduction: DCM .........................21

Unidirectional Conduction: HCM .........................22

Unidirectional Conduction: Burst Mode .............. 22

Error Amplifiers ......................................................22

Regulation and Sensing .................................23

OUT

: Regulation .................................................23

OUT

: Above Regulation ...................................... 23

OUT

: Below Regulation and Undervoltage .........23

OUT

VIN Regulation and Sensing .................................... 24

VIN: Regulation ................................................... 24

VIN: Above Regulation and Overvoltage .............. 24

VIN: Below Regulation ......................................... 24

Current Monitoring and Limiting .............................24

Monitoring and Limiting: IMON Pins ..................24

Monitoring: ICP and ICN Pins .............................25

INTVCC/EXTVCC/GATEVCC/LDO33 Power ............... 25

CLKOUT and Temperature Sensing ......................... 25

Applications Information ................................ 26

Verify the Power Flow Conditions ........................... 26

Operating Frequency Selection ............................... 26

Internal Oscillator ................................................... 27

SYNC Pin and Clock Synchronization ..................... 27

CLKOUT Pin and Clock Synchronization ................. 27

Inductor Current Sensing and Slope Compensation .... 27

Selection and Maximum Current ................28

SENSE

Selection: Max R

SENSE

in the

Boost Region ...................................................... 28

Selection: Max R

SENSE

in the

Buck Region ....................................................... 30

SENSE

Selection: Final R

SENSE

Value .................31

SENSE

Filtering ......................................................32

Inductor (L) Selection ............................................ 32

L Selection: Load Current in Buck and

Boost Regions .................................................... 32

L Selection: Subharmonic Oscillations ...............33

L Selection: Maximum Current Rating ................ 33

Power MOSFET Selection ....................................... 34

CIN and C

Selection ........................................... 37

OUT

Schottky Diode (D1, D2, D3, D4) Selection .............38

Topside MOSFET Driver Supply (CB1,DB1,CB2,DB2) ... 39

Top Driver: Boost Cap Charge Control Block ......39

Top Driver: Boost Diodes DB1 and D

B2 ...................

VINHIMON, VOUTLOMON and RVSOFF .................. 39

IIN and I

Current Monitoring and Limiting .........42

OUT

Loop Compensation ................................................44

INTVCC Regulators and EXTVCC Connection ........... 45

LDO33 Regulator .................................................... 45

Voltage Lockouts .................................................... 46

Junction Temperature Measurement ......................46

Thermal Shutdown .................................................47

Efficiency Considerations ......................................47

Circuit Board Layout Checklist ............................... 47

Hot Plugging Considerations .................................49

Design Example ...................................................... 49

Typical Applications ...................................... 55

Package Description ..................................... 63

Typical Application ....................................... 64

Related Parts .............................................. 64

Rev 0

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(Note 1)

CSP

– V

CSPOUT

CSN

, V

– V

CSPIN CSNOUT

CSNIN

............................... –0.3V to 0.3V

CSP, CSN Voltage ......................................... –0.3V to 3V

VC Voltage (Note 2) .................................. –0.3V to 2.2V

RT, FBOUT, SS Voltage ................................ –0.3V to 5V

IMON_INP, IMON_INN, IMON_OP, IMON_ON,

ICP, ICN Voltage ....................................... –0.3V to 5V

SYNC Voltage ............................................ –0.3V to 5.5V

INTVCC, GATEVCC Voltage ............................ –0.3V to 7V

BOOST1

– V

SW1

, V

BOOST2

– V

................ –0.3V to 7V

SW2

SWEN, RVSOFF Voltage ............................... –0.3V to 7V

SWEN Current .......................................................0.5mA

RVSO FF Current .......................................................1mA

FBIN, SHDN Voltage .................................. –0.3V to 30V

VINHIMON Voltage ..................................... –0.3V to 30V

VOUTLOMON Voltage .................................. –0.3V to 5V

DIR, MODE Voltage ...................................... –0.3V to 5V

CSNIN, CSPIN, CSPOUT, CSNOUT Voltage –0.3V to 80V V

, EXTVCC Voltage ............................ –0.3V to 80V

INCHIP

SW1, SW2 Voltage ..................................... 81V (Note 6)

BOOST1, BOOST2 Voltage ......................... –0.3V to 87V

BG1, BG2, TG1, TG2 .......................................... (Note 5)

LDO33, CLKOUT ............................................... (Note 8)

Operating Junction Temperature Range

LT8708E (Notes 3, 8) ........................ –40°C to 125°C

LT8708I (Notes 3, 8) ......................... –40°C to 125°C

LT8708H (Notes 3, 8) ....................... –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

LT8708

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

TOP VIEW

LDO33

IMON_ON

IMON_OP

MODE

SWEN

40 39 38 37 36 35 34

1CLKOUT

SHDN

CSN

CSP

ICN

DIR

FBIN

FBOUT

IMON_INP

IMON_INN

SYNC

15 16 17 18

GND

40-LEAD (5mm × 8mm) PLASTIC QFN

= 150°C, θJA = 36°C/W, θJC = 3.8°C/W

JMAX

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

GND

BG1

BG2

GATEV

UHG PACKAGE

19 20 21

INTVCC

TG2

BOOST2

INCHIP

SW2

CSPIN

CSNIN

CSNOUT

CSPOUT

EXTV

ICP

VINHIMON

VOUTLOMON

RVSOFF

BOOST1

TG1

SW1

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT8708EUHG#PBF LT8708EUHG#TRPBF 8708 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C

LT8708IUHG#PBF LT8708IUHG#TRPBF 8708 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C

LT8708HUHG#PBF LT8708HUHG#TRPBF 8708 40-Lead (5mm × 8mm) Plastic QFN –40°C to 150°C

Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev 0

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LT8708

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Voltage Supplies and Regulators

Operating Voltage Range EXTVCC = 0V

INCHIP

Quiescent Current Not Switching, V

INCHIP

Quiescent Current in Shutdown V

INCHIP

EXTVCC Switchover Voltage I

EXTVCC Switchover Hysteresis 0.2 V

INTVCC Current Limit Maximum Current Draw from INTVCC and LDO33 Pins

INTVCC Voltage Regulated from V

INTVCC Load Regulation I

INTVCC, GATEVCC Undervoltage Lockout INTVCC Falling, GATEVCC Connected to INTV

INTVCC, GATEVCC Undervoltage Lockout Hysteresis GATEVCC Connected to INTV

INTVCC Regulator Dropout Voltage V

LDO33 Pin Voltage 5mA from LDO33 Pin

LDO33 Pin Load Regulation I

LDO33 Pin Current Limit SYNC = 3V

LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V

LDO33 Pin Undervoltage Lockout Hysteresis 35 mV

Switching Regulator Control

Maximum Current Sense Threshold (V

CSP

CSN

CSP

– V

Gain from VC to Maximum Current Sense Voltage (V

– V

CSP

) (A5 in the Block Diagram)

CSN

SHDN Input Voltage High SHDN Rising to Enable the Device SHDN Input Voltage High Hysteresis 40 mV SHDN Input Voltage Low Device Disabled, Low Quiescent Current

SHDN Pin Bias Current V

SWEN Rising Threshold Voltage

SWEN Threshold Voltage Hysteresis 22 mV

SWEN Output Voltage Low I

EXTVCC = 7.5V

SWEN = 3.3V SWEN = 0V

= 0V 0 1 μA

SHDN

= –20mA, V

INTVCC

Combined. Regulated from V INTV INTV

= 5.25V

= 4.4V

Regulated from EXTVCC (12V), I

= 0mA to 50mA –0.5 –1.5 %

INTVCC

– V

INCHIP

LDO33

) Boost Mode, Minimum M3 Switch Duty Cycle

CSN

) Buck Mode, Minimum M2 Switch Duty Cycle

CSP

) Boost Mode, Minimum M3 Switch Duty Cycle

CSP

) Buck Mode, Minimum M2 Switch Duty Cycle

CSN

INTVCC

= 0.1mA to 5mA –0.25 –1 %

Boost Mode Buck Mode

(LT8708E, LT8708I) (LT8708H)

= 3V

SHDN

= 12V

SHDN

= 200μA

SWEN

SHDN = 0V or V SHDN = 3V

= 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3).

INCHIP

5.5

2.8

EXTVCC

= 0V

3.9

2.45

Rising

EXTVCC

or EXTVCC (12V)

INCHIP

, I

INCHIP

, I

INTVCC

= 20mA

INTVCC

= 20mA

= 20mA 220 mV

6.15 6.4 6.6 V

6.1

4.45 4.65 4.85 V

127

6.3

170 mV

3.23 3.295 3.35 V

12 17.25 22 mA

76 93 110 mV

68 82 97 mV

79 93 108 mV

72 84 96 mV

135

–135

1.175 1.221 1.275 V

l l

1.156 1.208 1.256 V

INCHIP

= 0V

l l

0.9

0.2

80 80

6.5

4.5

165

6.5

0.35

0.3

1.1

0.5

mA mA

mV/V mV/V

μA μA

V V

Rev 0

For more information www.analog.com

LT8708

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

SWEN Internal Pull-Down Release Voltage SHDN = 3V

MODE Pin Continuous Conduction Mode (CCM) Threshold

MODE Pin Hybrid DCM/CCM Mode (HCM) Range

MODE Pin Discontinuous Conduction Mode (DCM) Range

MODE Pin Burst Mode Operation Threshold

DIR Pin Forward Operation Threshold

DIR Pin Reverse Operation Threshold

RVSOFF Output Voltage Low I RVSOFF Falling Threshold Voltage RVSOFF Threshold Voltage Hysteresis 165 mV

Soft-Start Charging Current VSS = 0V 13 19 25 μA

ICN Rising Threshold for FDCM Operation MODE = 1V (HCM), DIR = 3.3V

ICN Falling Threshold for CCM Operation MODE = 1V (HCM), DIR = 3.3V

IMON_INP Rising Threshold for RDCM Operation MODE = 1V (HCM), DIR = 0V

IMON_INP Falling Threshold for CCM Operation MODE = 1V (HCM), DIR = 0V

Voltage Regulation Loops (Refer to Block Diagram to Locate Amplifiers)

Regulation Voltage for FBOUT Regulate VC to 1.2V

Regulation Voltage for FBIN Regulate VC to 1.2V

Line Regulation for FBOUT and FBIN Error Amp Reference Voltage

FBOUT Pin Bias Current Current Out of Pin 15 nA

FBOUT Error Amp EA4 g

FBOUT Error Amp EA4 Voltage Gain 245 V/V

VOUTLOMON Voltage Activation Threshold Falling

VOUTLOMON Threshold Voltage Hysteresis 24 mV

VOUTLOMON Pin Bias Current V

FBIN Pin Bias Current Current Out of Pin 10 nA

FBIN Error Amp EA3 g

FBIN Error Amp EA3 Voltage Gain 150 V/V

VINHIMON Voltage Activation Threshold Rising

VINHIMON Threshold Voltage Hysteresis 24 mV

VINHIMON Pin Bias Current V

Current Regulation Loops (Refer to Block Diagram to Locate Amplifiers)

Regulation Voltages for IMON_INP and IMON_OP VC = 1.2V

Regulation Voltages for IMON_INN and IMON_ON VC =1.2V

= 200μA

RVSOFF

= 12V to 80V. Not Switching 0.002 0.005 %/V

INCHIP

VOUTLOMON

VINHIMON

=1.24V, Current Into Pin =1.17V, Current Into Pin

= 1.17V, Current Out of Pin = 1.24V, Current Out of Pin

= 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3).

INCHIP

0.75 0.8 V

0.4 V

0.8 1.2 V

1.6 2.0 V

1.6 V

1.155 1.209 1.275 V

235 255 280 mV

185 205 235 mV

235 255 280 mV

185 205 235 mV

1.193 1.207 1.222 V

1.184 1.205 1.226 V

1.185 1.207 1.225 V

0.8

1.185 1.207 1.23 V

0.8

1.185 1.209 1.231 V

1.185 1.21 1.24 V

0.08 0.5 V

345 μmho

0.01 1

235 μmho

0.03 1

2.4 V

1.2 V

1.2

μA μA

For more information www.analog.com

Rev 0

LT8708

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Line Regulation for IMON_INP, IMON_INN, IMON_OP and IMON_ON Error Amp Reference Voltage

CSPIN Bias Current V

CSNIN Bias Current BOOST Capacitor Charge Control Block Not Active

CSPIN, CSNIN Common Mode Operating Voltage Range

CSPIN, CSNIN Differential Mode Operating Voltage Range

IMON_INP Output Current V

IMON_INN Output Current V

IMON_INP and IMON_INN Max Output Current

IMON_INP Error Amp EA5 g

IMON_INP Error Amp EA5 Voltage Gain 130 V/V

IMON_INN Error Amp EA1 g

IMON_INN Error Amp EA1 Voltage Gain FBIN = 0V, FBOUT = 3.3V 130 V/V

CSPOUT Bias Current V

CSNOUT Bias Current BOOST Capacitor Charge Control Block Not Active

CSPOUT, CSNOUT Common Mode Operating Voltage Range

CSPOUT, CSNOUT Differential Mode Operating Voltage Range

IMON_OP, ICP Output Current V

IMON_ON, ICN Output Current V

= 12V to 80V 0.002 0.005 %/V

INCHIP

= 12V

CSPIN

= 1.5V

CSPIN

V V V

CSPIN

CSNIN

SWEN SWEN SWEN

– V – V – V – V

= 3.3V, V = 3.3V, V = 0V

CSNIN

= 50mV, V

CSNIN

= 5mV, V

CSNIN

= 5mV, V

CSNIN

= 50mV, V

CSPIN

= 50mV, V

CSPIN

= 5mV, V

CSPIN

= 5mV, V

CSPIN

FBIN = 0V, FBOUT = 3.3V 190 μmho

= 12V

CSPOUT

= 1.5V

CSPOUT

V V V

CSPOUT

CSNOUT

SWEN SWEN SWEN

– V – V – V – V – V – V

= 3.3V, V = 3.3V, V = 0V

CSNOUT CSNOUT CSNOUT CSNOUT CSNOUT CSNOUT

CSPOUT CSPOUT CSPOUT CSPOUT CSPOUT CSPOUT

= 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3).

INCHIP

0.01

CSPIN CSPIN

= V = V

CSNIN CSNIN

= 12V = 1.5V

4.25

0.01

0 80 V

–100 100 mV

= 50mV, V

CSNIN

CSNIN CSNIN CSNIN

CSNIN

CSNIN CSNIN CSNIN

= 5V

= 5V = 5V = 5V

= 5V

= 5V = 5V = 5V

64.5

22.5

65 19

120 μA

70 70 25 25

190 μmho

0.01

CSPOUT CSPOUT

= V = V

CSNOUT

= 12V = 1.5V

4.25

0.01

0 80 V

–100 100 mV

= 50mV, V = 50mV, V = 5mV, V = 5mV, V = –5mV, V = –5mV, V

CSNOUT

CSNOUT CSNOUT CSNOUT

CSNOUT

CSNOUT CSNOUT CSNOUT

CSNOUT

= 5V

= 5V = 5V = 5V

= 5V

= 5V = 5V = 5V

= 5V

67 65

22.5

20.5

12.5

10.5

67 65

22.5

20.5

12.5

10.5

70 70 25 25 15 15

μA

75.5

27.5 30

74 75

30.5 32

73 76

27.5 29

17.5

19.5

73 75

27.5 29

17.5

19.5

μA

μA μA μA

μA μA μA μA

μA μA

μA μA μA

μA μA μA μA μA μA

Rev 0

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LT8708

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

IMON_OP, IMON_ON, ICP and ICN Max Output Current

IMON_OP Error Amp EA6 g

IMON_OP Error Amp EA6 Voltage Gain 130 V/V

IMON_ON Error Amp EA2 gm FBIN = 0V, FBOUT = 3.3V 190 μmho

IMON_ON Error Amp EA2 Voltage Gain FBIN = 0V, FBOUT = 3.3V 130 V/V

NMOS Gate Drivers

TG1, TG2 Rise Time C

TG1, TG2 Fall Time C

BG1, BG2 Rise Time C

BG1, BG2 Fall Time C

TG1 Off to BG1 On Delay C

BG1 Off to TG1 On Delay C

TG2 Off to BG2 On Delay C

BG2 Off to TG2 On Delay C

Minimum On-Time for Main Switch in Boost Operation (t

ON(M3,MIN)

Minimum On-Time for Synchronous Switch in Buck Operation (t

ON(M2,MIN)

Minimum Off-Time for Main Switch in Steady-State Boost Operation

Minimum Off-Time for Synchronous Switch in Steady-State Buck Operation

Oscillator

Switch Frequency Range SYNCing or Free Running 100 400 kHz

Switching Frequency, F

SYNC High Level for Synchronization

SYNC Low Level for Synchronization

SYNC Clock Pulse Duty Cycle V

Recommended Min SYNC Ratio F

CLKOUT Output Voltage High V

CLKOUT Output Voltage Low 1mA Into CLKOUT Pin 25 100 mV

CLKOUT Duty Cycle TJ = –40°C

)

OSC

SYNC/FOSC

= 3300pF (Note 4) 20 ns

LOAD

= 3300pF (Note 4) 20 ns

LOAD

= 3300pF (Note 4) 20 ns

LOAD

= 3300pF (Note 4) 20 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

= 3300pF Each Driver 80 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

= 3300pF Each Driver 80 ns

LOAD

Switch M3, C

Switch M2, C

Switch M3, C

Switch M2, C

LOAD

RT = 365k RT = 215k RT = 124k

= 0V to 2V 20 80 %

SYNC

– V

LDO33

CLKOUT

= 0μA

TJ = 25°C TJ = 125°C

= 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3).

INCHIP

120 μA

190 μmho

= 3300pF 200 ns

= 3300pF 230 ns

102

170

310

1.3 V

120 202 350

142 235 400

kHz kHz kHz

0.5 V

3/4

, 1mA Out of CLKOUT Pin,

100 250 mV

22.7

44.1 77

% % %

For more information www.analog.com

Rev 0

LT8708

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

CLKOUT Rise Time C

CLKOUT Fall Time C

CLKOUT Phase Delay SYNC Rising to CLKOUT Rising, f

= 200pF 20 ns

LOAD

= 200pF 20 ns

LOAD

= 100kHz

OSC

= 12V, SHDN = 3V, DIR = 3V unless otherwise noted (Note 3).

INCHIP

160 180 200 degrees

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: Do not force voltage on the VC pin. Note 3: The LT8708E is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8708I is guaranteed over the full –40°C to 125°C junction temperature range. The LT8708H is guaranteed over the full –40°C to 150°C operating junction temperature range.

Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels.

Note 5: Do not apply a voltage or current source to these pins. They mustbe connected to capacitive loads only, otherwise permanent damage may occur.

Note 6: Negative voltages on the SW1 and SW2 pins are limited, in an application, by the body diodes of the external NMOS devices, M2 and M3, or parallel Schottky diodes when present. The SW1 and SW2 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design.

Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair devicereliability.

Note 8: Do not force voltage or current into these pins.

Rev 0

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TYPICAL PERFORMANCE CHARACTERISTICS

LOAD CURRENT (A)

0.01

0.11100102030

405060708090100

EFFICIENCY (%)

8708 G01

HCM

DCM

CCM

VIN = 38V

OUT

= 47.4V

LOAD CURRENT (A)

0.01

0.111001020304050

60708090100

EFFICIENCY (%)

8708 G02

HCM

DCM

CCM

VIN = 51.5V

OUT

= 47.4V

LOAD CURRENT (A)

0.01

0.11100102030

405060708090100

EFFICIENCY (%)

8708 G03

HCM

DCM

CCM

VIN = 48V

OUT

= 47.4V

VC = 1.2V

FBOUT

FBIN

IMON_INP

IMON_INN

IMON_ON

IMON_OP

TEMPERATURE (°C)

–45

–205305580

105

130

155

1.17

1.18

1.19

1.20

1.21

1.22

1.23

PIN VOLTAGE (V)

Feedback Voltages

8708 G04

VC = 1.2V

TEMPERATURE (°C)

–45

–205305580

105

130

155

1.17

1.18

1.19

1.20

1.21

1.22

1.23

PIN VOLTAGE (V)

8708 G05

RT = 124k

RT = 215k

RT = 365k

TEMPERATURE (°C)

–45

–205305580

105

130

155

100

150

200

250

300

350

400

Oscillator Frequency

8708 G06

BUCK REGION

BOOST REGION

M2 OR M3 DUTY CYCLE (%)

020406080

100

120

140

|CSP–CSN| (mV)

8708 G07

BUCK REGION

BOOST REGION

VC (V)

0.511.5

–100

–80

–60

–40

–20

406080

100

–100

–80

–60

–40

–20020

406080

100

CSP–CSN (mV)

8708 G08

BUCK REGION

BOOST REGION

TEMPERATURE (°C)

–45

–205305580

105

130

1550204060

100

120

|CSP–CSN| (mV)

Voltage at Minimum Duty Cycle

8708 G09

LT8708

Efficiency vs Output Current (Boost Region – Page 59)

Efficiency vs Output Current (Buck Region – Page 59)

Efficiency vs Output Current (Buck–Boost Region – Page 59)

Feedback Voltages Feedback Voltages (Five Parts) Oscillator Frequency

Maximum Inductor Current Sense Voltage vs Duty Cycle

Inductor Current Sense Voltage at Minimum Duty Cycle

For more information www.analog.com

Maximum Inductor Current Sense Voltage at Minimum Duty Cycle

Rev 0

LT8708

BUCK REGION

BOOST REGION

M2 OR M3 DUTY CYCLE (%)

020406080

100

–140

–120

–100

–80

–60

–40

–20

–|CSP–CSN| (mV)

8708 G10

VIN (V)4681012141618

4.0

4.5

5.0

5.5

6.0

6.5

7.0

8708 G11

BUCK REGION

BOOST REGION

TEMPERATURE (°C)

–45

–205305580

105

130

155

–120

–100

–80

–60

–40

–20

8708 G12

BUCK REGION

BOOST REGION

MINIMUM V

MAXIMUM V

TJ = 25°C

SS (V)

0.3

0.6

0.9

1.2

1.5

0.5

1.0

1.5

2.0

2.5

(V)

Maximum and Minimum V

vs SS

EXTVCC RISING

EXTVCC FALLING

EXTVCC (V)

4681012

5.5

6.0

6.5

7.0

8708 G14

CSPIN–CSNIN (mV)

CSPOUT–CSNOUT (mV)

–200

–1000100

200

–25.0

25.0

50.0

75.0

100.0

125.0

150.0

175.0

200.0

225.0

250.0

IMONX, ICX CURRENT (µA)

8708 G15

IMON_INN IMON_ON ICN

IMON_INP IMON_OP ICP

TEMPERATURE (°C)

–45

–205305580

105

130

155

020406080

100

DUTY CYCLE (%)

CLKOUT Duty Cycle

8708 G16

150°C

–45°C

25°C

INTVCC (V)

2.533.544.555.566.5

1.5

2.0

2.5

3.0

3.5

8708 G17

150°C

–45°C

25°C

VIN (V)

520355065

0.5

1.0

1.5

2.0

2.5

3.0

3.5

(mA)

8708 G18

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum Inductor Current Sense Voltage vs Duty Cycle

Maximum and Minimum VC vs SS

INTVCC Line Regulation (EXTVCC = 0V)

Minimum Inductor Current Sense Voltage at Minimum Duty Cycle

INTVCC Line Regulation (VIN = 12V) IMONx, ICx Output Current

CLKOUT Duty Cycle

LDO33 Pin Regulation (I

= 1mA)

LDO33

For more information www.analog.com

VIN Supply Current vs Voltage (Not Switching)

Rev 0

TYPICAL PERFORMANCE CHARACTERISTICS

SHDN

PIN VOLTAGE (V)

036912151821242730

8708 G19

RISING

FALLING

SHDN

SWEN

TEMPERATURE (°C)

–45

–205305580

105

130

155

1.10

1.12

1.14

1.16

1.18

1.20

1.22

1.24

1.26

1.28

1.30

PIN THRESHOLD VOLTAGE (V)

8708 G20

TEMPERATURE (°C)

–45

–205305580

105

130

155

0.5

1.0

1.5

2.0

2.5

3.0

8708 G21

RISING

FALLING

VINHIMON

VOUTLOMON

TEMPERATURE (°C)

–45

–205305580

105

130

155

1.10

1.12

1.13

1.15

1.16

1.18

1.20

1.21

1.23

1.24

1.26

PIN THRESHOLD VOLTAGE (V)

8708 G22

VINHIMON = 1.24V, OUT OF PIN

VOUTLOMON = 1.17V, INTO PIN

TEMPERATURE (°C)

–45

–205305580

105

130

155

0.2

0.4

0.7

0.9

1.1

8708 G23

SHDN Pin Current

Internal V

UVLO

LT8708

SHDN and SWEN Pin Thresholds vs Temperature

VINHIMON and VOUTLOMON Pin Thresholds vs Temperature

VINHIMON and VOUTLOMON Pin Hysteresis Current vs Temperature

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Rev 0

LT8708

8708 G24

20V/DIV

LOAD

8708 G25

20V/DIV

LOAD

8708 G26

20V/DIV

LOAD

8708 G27

20V/DIV

8708 G28

500mV/DIV

LOAD STEP = 2A TO 4A

8708 G29

500mV/DIV

LOAD STEP = 2A TO 4A

500mV/DIV

LOAD STEP = 2A TO 4A

TYPICAL PERFORMANCE CHARACTERISTICS

Discontinuous Mode (Page 59) Continuous Mode (Page 59)

SW1

SW2

5A/DIV

= 38V

BAT

= 47.4V

5μs/DIV

SW1

SW2

5A/DIV

= 48V

BAT

= 47.4V

Continuous Mode (Page 59) Load Step (Page 59)

SW1

SW2

5A/DIV

5μs/DIV

LOAD

5A/DIV

Continuous Mode (Page 59)

SW1

SW2

5A/DIV

= 52V

BAT

= 47.4V

5μs/DIV

V V

BAT LOAD

= 38V

= 47.4V

5μs/DIV

V V

BAT LOAD

= 38V

= 47.4V

Load Step (Page 59) Load Step (Page 59)

LOAD

5A/DIV

V V

BAT LOAD

= 52V

= 47.4V

5ms/DIV

LOAD

5A/DIV

= 48V

BAT

= 47.4V

LOAD

5ms/DIV

8708 G30

Rev 0

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PIN FUNCTIONS

LT8708

CLKOUT (Pin 1): Clock Output Pin. Use this pin to synchronize one or more compatible switching regulator ICs to the LT8708. CLKOUT toggles at the same frequency as the internal oscillator or as the SYNC pin, but is approximately 180° out of phase. CLKOUT may also be used as a temperature monitor since the CLKOUT duty cycle varies linearly with the part’s junction temperature. The CLKOUT pin can drive capacitive loads up to 200pF.

SS (Pin 2): Soft-Start Pin. Place at least 220nF of capacitance here. Upon start-up, this pin will be charged by an internal resistor to 3.3V.

SHDN (Pin 3): Shutdown Pin. Tie high to enable chip. Ground to shut down and reduce quiescent current to a minimum. Don’t float this pin.

CSN (Pin 4): The (–) Input to the Inductor Current Sense and DCM Detect Comparator.

CSP (Pin 5): The (+) Input to the Inductor Current Sense and DCM Detect Comparator. The VC pin voltage and builtin offsets between CSP and CSN pins, in conjunction with the R

ICN (Pin 6): Negative V

value, set the inductor current trip threshold.

SENSE

Current Monitor. The current

OUT

out of this pin is 20μA plus a current proportional to the negative average V

current. See the Applications

OUT

Information section for more information.

DIR (Pin 7): Direction pin when MODE is set for DCM (discontinuous conduction mode) or HCM (hybrid conduction mode) operation. Otherwise this pin is ignored. Connect the pin to GND to process power from the V

OUT

to VIN. Connect the pin to LDO33 to process power from the VIN to V

OUT

FBIN (Pin 8): VIN Feedback Pin. This pin is connected to the input of error amplifier EA3 and is used to detect and/ or regulate low VIN voltage.

FBOUT (Pin 9): V

Feedback Pin. This pin is connected

OUT

to the input of error amplifier EA4 and is used to detect and/or regulate high V

voltage.

OUT

VC (Pin 10): Error Amplifier Output Pin. Tie external compensation network to this pin.

IMON_INP (Pin 11): Positive VIN Current Monitor and Limit Pin. The current out of this pin is 20μA plus a current proportional to the positive average VIN current. IMON_INP also connects to error amplifier EA5 and can be used to limit the maximum positive VIN current. See the Applications Information section for more information.

IMON_INN (Pin 12): Negative VIN Current Monitor and Limit Pin. The current out of this pin is 20μA plus a current proportional to the negative average VIN current. IMON_INN also connects to error amplifier EA1 and can be used to limit the maximum negative VIN current. See the Applications Information section for more information.

RT (Pin 13): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency. Do not float this pin.

SYNC (Pin 14): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less than 0.5V. Drive this pin to less than 0.5V to revert to the internal free-running clock. See the Applications Information section for more information.

BG1, BG2 (Pin 16, Pin 18): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFETs between ground and GATEVCC.

GATEVCC (Pin 17): Power supply for bottom gate drivers. Must be connected to the INTVCC pin. Do not power from any other supply. Locally bypass to GND.

BOOST1, BOOST2 (Pin 24, Pin 19): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor connects here. The BOOST1 pin swings from a diode voltage below GATEVCC up to VIN + GATEVCC. The BOOST2 pin swings from a diode voltage below GATEVCC up to V

+ GATEVCC.

OUT

TG1, TG2 (Pin 23, Pin 20): Top Gate Drive. Drives the top N-channel MOSFETs with voltage swings equal to GATEV

superimposed on the switch node voltages.

SW1, SW2 (Pin 22, Pin 21): Switch Nodes. The (–) terminals of the bootstrap capacitors connect here.

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Rev 0

LT8708

PIN FUNCTIONS

RVSOFF (Pin 25): Reverse Conduction Disable Pin. This is an input/output open-drain pin that requires a pull up resistor. Pulling this pin low disables reverse current operation. See the Uni and Bidirectional Conduction section for more information.

VOUTLOMON (Pin 26): V Connect a ±1% resistor divider between V LOMON and GND to set an undervoltage level on V When V

is lower than this level, reverse conduction is

OUT

disabled to prevent drawing current from V

Low Voltage Monitor Pin.

OUT

, VOUT-

OUT

. See the

OUT

Applications Information section for more information.

VINHIMON (Pin 27): VIN High Voltage Monitor Pin. Con- nect a ±1% resistor divider between VIN, VINHIMON and GND in order to set an overvoltage level on VIN. When V

is higher than this level, reverse conduction is disabled to prevent current flow into VIN. See the Applications Information section for more information.

ICP (Pin 28): Positive V

Current Monitor Pin. The cur-

OUT

rent out of this pin is 20μA plus a current proportional to the positive average V

current. See the Applications

OUT

Information section for more information.

EXTVCC (Pin 29): External VCC Input. When EXTVCC ex- ceeds 6.4V (typical), INTVCC will be powered from this pin. When EXTVCC is lower than 6.4V, the INTVCC will be powered from V

CSPOUT (Pin 30): The (+) Input to the V

INCHIP

Current Moni-

OUT

tor Amplifier. This pin and the CSNOUT pin measure the voltage across the sense resistor, R V

current signals. Connect this pin to V

OUT

, to provide the

SENSE2

when not

OUT

in use. See Applications Information section for proper use of this pin.

CSNOUT (Pin 31): The (–) Input to the V Amplifier. Connect this pin to V

OUT

Current Monitor

OUT

when not in use. See

Applications Information section for proper use of this pin.

CSNIN (Pin 32): The (–) Input to the VIN Current Monitor Amplifier. This pin and the CSPIN pin measure the voltage across the sense resistor, R

, to provide the VIN cur-

SENSE1

rent signals. Connect this pin to VIN when not in use. See Applications Information section for proper use of this pin.

CSPIN (Pin 33): The (+) Input to the VIN Current Monitor Amplifier. Connect this pin to VIN when not in use. See Applications Information section for proper use of this pin.

(Pin 34): Main Input Supply Pin for the LT8708.

INCHIP

It must be locally bypassed to ground.

INTVCC (Pin 35): 6.3V Regulator Output. Must be connected to the GATEVCC pin. INTVCC is powered from EXTVCC when the EXTVCC voltage is higher than 6.4V, otherwise INTVCC is powered from V

. Bypass this pin to ground with

INCHIP

a minimum 4.7μF ceramic capacitor.

SWEN (Pin 36): Switching Regulator Enable Pin. Tie high through a resistor to enable the switching. Ground to disable switching. This pin is pulled down during shutdown, a thermal lockout or when an internal UVLO (undervoltage lockout) is detected. Don’t float this pin. See the Start-Up: SWEN Pin section for more details.

MODE (Pin 37): Conduction Mode Select Pin. The voltage applied to this pin sets the conduction mode of the controller. Apply less than 0.4V to enable continuous conduction mode (CCM). Apply 0.8V to 1.2V to enable the hybrid conduction mode (HCM). Apply 1.6V to 2.0V to enable the discontinuous conduction mode (DCM). Apply more than 2.4V to enable Burst Mode operation.

IMON_OP (Pin 38): Positive V

Current Monitor and

OUT

Limit Pin. The current out of this pin is 20μA plus a current proportional to the positive average V

current.

OUT

IMON_OP also connects to error amplifier EA6 and can be used to limit the maximum positive V

current. See

OUT

the Applications Information section for more information.

IMON_ON (Pin 39): Negative V

Current Monitor and

OUT

Limit Pin. The current out of this pin is 20μA plus a current proportional to the negative average V

current.

OUT

IMON_ON also connects to error amplifier EA2 and can be used to limit the maximum negative V

current. See

OUT

the Applications Information section for more information.

LDO33 (Pin 40): 3.3V Regulator Output. Bypass this pin to ground with a minimum 0.1μF ceramic capacitor.

GND (Pin 15, Exposed Pad Pin 41): Ground. Tie directly to local ground plane.

Rev 0

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BLOCK DIAGRAM

8708 F01

SENSE1

LT8708

SENSE

LDO33

SHDN1

SHDN2

CSNIN

CSPIN

INCHIP

IMON_INN

IMON_INP

CLKOUT

SYNC

DIR

MODE

3.3V

SHDN

1.234V

EXTV

INTV

LDO33

–

6.3V LDO REG

6.4V

CSN CSP

–

OSC

RVS

SWEN

D2 (OPT)

LDO33

D4 (OPT)

D1 (OPT)

D3 (OPT)

HIMON1

HIMON2

BOOST1

TG1

SW1

–

GATEV

CONTROL

RVS

AND STATE LOGIC

BOOST CAPACITOR CHARGE CONTROL

–

1.207V

EA7

1.207V

BG1

GND

BG2

SW2

TG2

BOOST2

RVSOFF

VINHIMON

VOUTLOMON

IMON_OP

RVSOFF

LOMON3

HIMON3

–

EA5

EA3

EA4

EA6

–

IMON_INP

1.205V

1.207V

1.209V

EA2

EA1

UV_INTVCCOT

START-UP LOGIC

UV_V

UV_LDO33 UV_GATEV

3.3V

LDO

–

REG

6.3V LDO REG

INTERNAL

SUPPLY2

INTERNAL SUPPLY1

LDO33

REG

CSPOUT

CSNOUT

–

ICN

ICP

IMON_ON

SENSE2

OUT

LOMON1

LOMON2

FBIN

FBIN1

FBIN2

FBOUT1

FBOUT2

–

1.21V

IMON_INN

FBOUT

Figure 1. Block Diagram

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Rev 0

LT8708

OPERATION

TYPOGRAPHICAL CONVENTIONS

The LT8708 is a high performance 4-switch buck-boost controller that includes features to facilitate bidirectional current and power flow. Using the LT8708, an application can command power to be delivered from VIN to V from V

to VIN as needed. Some terms, listed below, are

OUT

used throughout this data sheet in reference to the direction of current and power flow. In order to clarify these directionbased concepts, these terms are defined as follows:

VIN and IIN: The VIN side of circuits drawn in this data

sheet will always be on the left. VIN is connected to the SW1 side of the buck-boost inductor through M1. IIN is the VIN current.

V I

OUT

and

The V sheet will always be on the right. V

side of circuits drawn in this data

OUT

connected to the SW2 side of the buck-boost

Supply (Input):

inductor through M4. I Power Source. The power source is most

commonly applied to VIN. However, V

OUT

is the V

OUT

current.

OUT

can be a Supply (or Input) when power is

Load (Output):

being delivered from V Devices that are consuming the power. The

Load is most commonly connected to V

OUT

to VIN.

OUT

. However, VIN can connect to the Load (or Output) when power is being delivered from V

to VIN.

OUT

Forward Conduction:

Current or power flowing from the VIN or SW1 node (or side) to the V

or SW2 node

OUT

(or side) of the circuit. This is generally left to right on schematics.

Reverse Conduction:

Current or power flowing from the V

OUT

or SW2 node (or side) to the VIN or SW1 node (or side) of the circuit. This is general right to left on schematics.

Positive Current:

Current that flows from the SW1 side of the buck-boost inductor to the SW2 side. Also refers to current that flows from VIN and/

Reverse Current:

or into V Current that flows from the SW2 side of the

buck-boost inductor to the SW1 side. Also refers to current that flows from V

OUT

and/

OUT

or into VIN.

Refer to the Block Diagram (Figure 1) when reading the following sections about the operation of the LT8708.

START-UP

Figure 2 illustrates the start-up sequence for the LT8708.

Start-Up: SHDN Pin

The master shutdown pin for the chip is SHDN. When driven below 0.35V (LT8708E, LT8708I) or 0.3V (LT8708H), the chip is disabled (CHIP OFF state) and quiescent current is minimal. Increasing the SHDN voltage can increase quiescent current but will not enable the chip until SHDN is driven above 1.221V (typical) after which the INTVCC and LDO33 regulators are enabled (SWITCHER OFF 1 state). External devices powered by LDO33 can become active at this time if enough voltage is available on V

INCHIP

or EXTVCC

to raise INTVCC, and thus LDO33, to an adequate voltage.

Start-Up: SWEN Pin

The SWEN pin is used to enable the switching regulator after the chip has also been enabled by driving SHDN high. SWEN must be pulled high through a resistor to enable the switching regulator. The typical activation threshold is

1.208V as shown in the Electrical Characteristics section. When the SWEN pin voltage is below the activation threshold, the CSP-CSN, CSPIN-CSNIN and CSPOUT-CSNOUT current sense circuits on the chip are disabled.

SWEN has an internal pull-down that is activated when the switching regulator is unable to operate (see CHIP OFF and SWITCHER OFF 1 states in Figure 2). After the chip is able to operate and SWEN is internally pulled down below

0.8V (typical), the internal SWEN pull-down is disabled and start-up can proceed past the SWITCHER OFF1 state.

LDO33 or INTVCC are convenient nodes to pull SWEN up to. Choose a pull-up resistor value that limits the current to less than 200μA when SWEN is pulled low. The SWEN pin can also be digitally driven through a current limiting resistor. Note in the Electrical Characteristics section, the SWEN output low voltage is 0.9V (typical) when SHDN is low and/or V is 0.2V when SHDN is 3V and V

is unpowered. The SWEN output low

INCHIP

is powered.

INCHIP

Rev 0

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OPERATION

LT8708

SHDN < 1.181V OR

< 2.5V OR

INCHIP

> 165°C

JUNCTION

CHIP OFF

• SWITCHER OFF

• LDOs OFF

• SWEN PULLED LOW

< 160°C AND SHDN > 1.221V AND V

JUNCTION

((INTV

OR LDO33 < 3.04V)

• SWITCHER DISABLED

• INTV

AND LDO33 OUTPUTS ENABLED

• SWEN AND SS PULLED LOW

• SWITCHER DISABLED

• INTV

AND LDO33 OUTPUTS ENABLED

• SS PULLED LOW

• V

FORCED TO COMMAND NEAR ZERO

CURRENT LIMIT

• SS CHARGES UP

• WHEN SS > 0.2V ...

• SWITCHER ENABLED

• V

SOFT-START

• M1, M4 ON-TIME SOFT-START

AND GATEVCC < 4.65V)

SWITCHER OFF 1

(INTV LDO33 > 3.075V AND SWEN < 0.8V

SWITCHER OFF 2

(INTV LDO33 > 3.075V AND SWEN > 1.208V

INITIALIZE

SS < 50mV

SOFT-START

SS > 1.8V

INCHIP

AND GATEVCC > 4.81V) AND

> 2.5V AND

• NORMAL OPERATION

Figure 2. Start-Up Sequence (All Values are Typical)

Start-Up: Soft-Start of Switching Regulator

In the INITIALIZE state, the SS (soft-start) pin is pulled low to prepare for soft-starting the switching regulator. After SS has been discharged to less than 50mV, the SOFT-START state begins. In this state, as SS gradually rises, the soft-start circuitry provides a gradual ramp of VC and the inductor current in the appropriate direction (refer to the VC vs SS Voltage graph in the Typical Performance Characteristics section). This prevents abrupt surges of inductor current and helps the output voltage ramp smoothly into regulation. See the Switch Control: Soft-Start section for information about the power switch control during soft-start.

During soft-start, an integrated 180k (typical) resistor pulls SS up to 3.3V. The rising ramp rate of the SS pin voltage is set by this 180k resistor and the external capacitor

NORMAL MODE

8708 F02

connected to this pin. When SS reaches 1.8V (typical), the LT8708 exits soft-start and enters normal operation. Typical values for the external soft-start capacitor range from 220nF to 2μF. A minimum of 220nF is recommended.

CONTROL OVERVIEW

The LT8708 is a current mode controller that provides an output voltage above, below or equal to the input voltage. It also provides bidirectional current monitoring and regulation capabilities at both the input and the output.

The ADI proprietary control architecture employs an inductor current-sensing resistor (R

) in buck, boost or buck-

SENSE

boost regions of operation. The inductor current is controlled by the voltage on the VC pin, which is the combined output of six internal error amplifiers EA1–EA6. These amplifiers

Rev 0

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LT8708

OPERATION

can be used to limit or regulate their respective voltages or currents as shown in Table 1.

Table 1. Error Amplifiers (EA1 − EA6)

AMPLIFIER NAME PIN NAME USED TO LIMIT OR REGULATE

EA1 IMON_INN Negative I

EA2 IMON_ON Negative I

EA3 FBIN VIN Voltage

EA4 FBOUT V

EA5 IMON_INP Positive I

EA6 IMON_OP Positive I

OUT

Voltage

OUT

The VC voltage typically has a min-max range of about 1.2V. The maximum VC voltage commands the most positive inductor current and, thus, commands the most power flow from VIN to V

The minimum VC voltage commands

OUT.

the most negative inductor current and, thus, commands the most power flow from V

In a simple example of V receives the V

voltage feedback signal which is com-

OUT

to VIN.

OUT

regulation, the FBOUT pin

OUT

pared to the internal reference voltage using EA4. Low V

voltage raises VC and, thus, more current flows into

OUT

. Conversely, higher V

OUT

the current into V from V

OUT

or even drawing current and power

OUT

reduces VC, thus, reducing

OUT

with constant current (EA6) to a maximum voltage (EA4) and also reversed, at times, to supply power back to V

using the other error amplifiers to regulate VIN and limit the maximum current.

POWER SWITCH CONTROL

The following discussions about the power switch control assume that the LT8708 is operating in the continuous conduction mode (see Bidirectional Conduction: CCM). Other conduction modes have slight differences that are discussed later in their respective Conduction sections.

Figure 3 shows a simplified diagram of how the four power switches are connected to the inductor, VIN, V

OUT

and ground. Figure 4 shows the regions of operation for the LT8708 as a function of V

– VIN or switch duty cycle

OUT

(DC). The power switches are properly controlled so the transfer between modes is continuous.

TG1

BG1

SW1 SW2

OUT

TG2

BG2

Note that the current and power flow can also be restricted to one direction, as needed, by the selected conduction mode discussed in the Uni and Bidirectional Conduction section.

As mentioned previously, the LT8708 also provides bidirectional current regulation capabilities at both the input and the output. The V

current can be regulated

OUT

or limited in the forward and reverse directions (EA6 and EA2, respectively). The VIN current can also be regulated or limited in the forward direction and reverse directions (EA5 and EA1, respectively).

In a common application, V

might be regulated using

OUT

EA4, while the remaining error amplifiers are monitoring for excessive input or output current or an input undervoltage condition. In other applications, such as a battery backup system, a battery connected to V

might be charged

OUT

SENSE

8708 F03

Figure 3. Simplified Diagram of the Buck-Boost Switches

SWITCH M3 DC

MAX

BOOST REGION

-V 0

BUCK/BOOST REGION

OUT

BUCK REGION

Figure 4. Operating Regions vs V

M1 ON, M2 OFF PWM M3, M4 SWITCHES

4-SWITCH PWM

M4 ON, M3 OFF PWM M1, M2 SWITCHES

8708 F04

OUT

− V

SWITCH M3 DC

SWITCH M2 DC

MIN

MAX

Rev 0

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OPERATION

⎝

⎠

OUT

LT8708

Switch Control: Buck Region (VIN >> V

When VIN is significantly higher than V

)

OUT

, the part will run

OUT

in the buck region. In this region M3 is always off and switch M4 is always on. At the start of every cycle, synchronous switch M2 is turned on first. Inductor current is sensed by amplifier A4 while switch M2 is on. A slope compensation ramp is added to the sensed voltage which is then compared by A5 to a reference that is proportional to VC. After the sensed inductor current falls below the reference, switch M2 is turned off and switch M1 is turned on for the remainder of the cycle. Switches M1 and M2 will alternate, behaving like a typical synchronous buck regulator. Figure 5 shows the switching waveforms in the buck region.

CLOCK

SWITCH M1

SWITCH M2

SWITCH M3

SWITCH M4

Figure 5. Buck Region (VIN >> V

OUT

)

OFF

8708 F05

When VIN is much higher than V

, the duty cycle of

OUT

switch M2 will increase, causing the M2 switch off-time to decrease. The M2 switch off-time should be kept above 230ns (typical, see Electrical Characteristics) to maintain steady-state operation and avoid duty cycle jitter, increased output ripple and reduction in maximum output current.

Switch Control: Buck-Boost (VIN ≅ V

When VIN is close to V

, the controller operates in the

OUT

)

buck-boost region. Figure 6 shows typical waveforms in this region. Every cycle, if the controller starts with switches M2 and M4 turned on, the controller first operates as if in the buck region. When A5 trips, switch M2 is turned off and M1 is turned on until the middle of the clock cycle. Next, switch M4 turns off and M3 turns on. The LT8708 then operates as if in boost mode until A2 trips. Finally, switch M3 turns off and M4 turns on until the end of the cycle.

If the controller starts with switches M1 and M3 turned on, the controller first operates as if in the boost region. When A2 trips, switch M3 is turned off and M4 is turned on until the middle of the clock cycle. Next, switch M1

The part will continue operating in the buck region over a range of switch M2 duty cycles. The duty cycle of switch M2 in the buck region is given by:

(M2,BUCK)

As VIN and V

⎛ ⎜

= 1–

⎜

get closer to each other, the duty cycle

OUT

⎞ ⎟

•100%

⎟

decreases until the minimum duty cycle of the converter, in the buck region, reaches DC cycle becomes lower than DC

(ABSMIN,M2,BUCK)

. If the duty

the part will

move to the buck-boost region.

(ABSMIN,M2,BUCK )

≅ t

ON(M2,MIN)

• ƒ • 100%

where:

ON(M2,MIN)

is the minimum on-time for the synchronous switch in buck operation (200ns typical, see Electrical Characteristics).

ƒ is the switching frequency.

CLOCK

SWITCH M1

SWITCH M2

SWITCH M3

SWITCH M4

CLOCK

SWITCH M1

SWITCH M2

SWITCH M3

SWITCH M4

6(a) Buck-Boost Region (VIN ≥ V

6(a) Buck-Boost Region (VIN ≤ V

Figure 6. Buck-Boost Region

OUT

8708 F06a

)

8708 F06b

)

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LT8708

OUT

⎝

⎠

OPERATION

turns off and M2 turns on. The LT8708 then operates as if in buck mode until A5 trips. Finally, switch M2 turns off and M1 turns on until the end of the cycle.

Switch Control: Boost Region (VIN << V

When V

is significantly higher than VIN, the part oper-

OUT

)

ates in the boost region. In this region switch M1 is always on and switch M2 is always off. At the start of every cycle, switch M3 is turned on first. Inductor current is sensed by amplifier A4 while switch M3 is on. A slope compensation ramp is added to the sensed voltage which is then compared (A2) to a reference that is proportional to VC. After the sensed inductor current rises above the reference voltage, switch M3 is turned off and switch M4 is turned on for the remainder of the cycle. Switches M3 and M4 will alternate, behaving like a typical synchronous boost regulator.

The part will continue operating in the boost region over a range of switch M3 duty cycles. The duty cycle of switch M3 in the boost region is given by:

(M3,BOOST)

As VIN and V

⎛ ⎜

= 1–

⎜

get closer to each other, the duty cycle

OUT

⎞

⎟

•100%

⎟

decreases until the minimum duty cycle of the converter, in the boost region, reaches DC duty cycle becomes lower than DC

(ABSMIN,M3,BOOST)

. If the

, the

part will move to the buck-boost region.

(ABSMIN,M3,BOOST)

≅ t

ON(M3,MIN)

• ƒ • 100%

where:

ON(M3,MIN)

is the minimum on-time for the main switch in boost operation (200ns typical, see Electrical Characteristics).

CLOCK

SWITCH M1

SWITCH M2

SWITCH M3

SWITCH M4

Figure 7. Boost Region (VIN << V

OUT

)

OFF

8708 F07

Switch Control: Soft-Start

During soft-start, the LT8708 operates in the same three regions discussed above (buck, buck-boost and boost). However, a few differences in switch control happen during soft-start.

First, M1 and M4 are not turned on simultaneously while SS ramps up to 0.8V (typical). When M1 and M4 would normally both be on, they are instead turned off, leaving all four switches off. After SS rises above 0.8V, during the time when M1 and M4 would normally both be on, they are turned on briefly instead. This brief amount of time increases as SS rises until M1 & M4 are allowed to remain on as long as the normal switching sequence requires.

Second, M2 and M3 will occasionally turn on together for one cycle to refresh both boost capacitors. This refresh cycle happens because M1 and M4 switch more frequently during soft-start than in normal operation. As such, the Boost Capacitor Charge Control block (see Figure 1) cannot always keep the boost capacitors charged. M2 and M3 are turned on when either BOOSTx-SWx voltage drops below 5V (typical). Note that during the refresh cycle, the inductor current slope is nearly zero, thus the boost capacitors can be refreshed without much disturbance to the ongoing switching operations.

ƒ is the switching frequency.

When V

is much higher than VIN, the duty cycle of

OUT

switch M3 will increase, causing the M3 switch off-time to decrease. The M3 switch off-time should be kept above 230ns (typical, see Electrical Characteristics) to maintain steady-state operation and avoid duty cycle jitter, increased output ripple and reduction in maximum output current.

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UNI AND BIDIRECTIONAL CONDUCTION

The LT8708 has one bidirectional and three unidirectional current conduction modes, primarily selected by the MODE pin. The bidirectional mode (CCM: continuous conduction mode) allows current and power to flow from V

to V

OUT

or vice versa, under control of the VC pin. The unidirectional

Rev 0

OPERATION

LT8708

modes (DCM: discontinuous conduction mode, HCM: hybrid current mode and Burst Mode operation) only allow current and power to flow in one direction. Unidirectional settings override the VC pin’s attempt to direct current and power opposite to the selected direction.

The DIR pin selects the allowed power direction when using the DCM and HCM unidirectional modes. The Burst Mode operation only operates in the forward direction and is not affected by the DIR pin. In DCM and HCM modes, driving DIR > 1.6V (typical) selects forward operation which only allows power flow from VIN to V

. Driving

OUT

DIR < 1.2V (typical) selects reverse operation which only allows power flow from V

OUT

to VIN.

Next, a low state on the RVSOFF pin inhibits reverse current and power flow. RVSOFF is an open-drain pin that requires a pull-up resistor. LDO33 or INTVCC are convenient nodes to pull RVSOFF up to. Normally, RVSOFF is only pulled low in response to a low V

voltage (via the VOUTLOMON

OUT

comparator) or a high VIN voltage (via the VINHIMON comparator). However, external devices are permitted to pull RVSOFF low as needed. More information is available in the VINHIMON, VOUTLOMON and RVSOFF section.

The conduction configuration can be changed during operation, as needed, with the following restrictions:

1. Before transitioning from MODE = Burst Mode operation to MODE = CCM, the DIR pin must be driven to the Hi (Forward) state.

2. Avoid control pulses on the MODE and DIR pins narrower than 15 LT8708 clock cycles.

Note: The VC pin may be railed at the moment the DIR pin

or MODE pin changes state. The railed VC voltage corresponds to zero current in one direction and maximum current in the other. Therefore, if a small value R

SENSE

resistor is used, the chip may momentarily command high inductor current immediately after the DIR or MODE pin change. An undersized inductor may become saturated in this case. An edge detector on the DIR and/or MODE pin can be used to reset the chip, forcing a soft-start and limiting the initial current. See the 48V to 14V Bidirectional Dual Battery System with FHCM & RHCM in the Typical Applications section as an example.

More details about each of the four conduction modes are provided in the following sub-sections.

Table 2 summarizes selection of the various conduction modes. See the Electrical Characteristics for the voltage thresholds of the DIR, VINHIMON, VOUTLOMON and RVSOFF pins.

Table 2. Conduction Configurations

MODE PIN

<0.4V –

0.8V to

1.2V

1.6V to

2.0V

>2.4V –

DIR PIN

STATE

Hi –

RVSOFF

PIN STATE

Hi CCM

Lo DCM Forward

Hi Reverse

Lo – None

Hi Reverse

Lo – None

CONDUCTION

MODE

Forward and

HCM

DCM

Burst Mode

Operation

POSSIBLE

DIRECTION

Reverse

Forward

Bidirectional Conduction: CCM

The continuous conduction mode allows the inductor current to flow in the forward or reverse direction, depending on the VC voltage. When CCM is selected, high VC voltage causes current and power to flow from VIN to V VC voltage causes current and power to flow from V

and low

OUT

to VIN. At very light load currents the inductor current may ripple positive and negative as the appropriate average current is delivered to the appropriate output.

Unidirectional Conduction: DCM

The discontinuous conduction mode restricts the inductor current so that it can only flow in one direction, positive towards V

(Forward DCM) or negative towards VIN

OUT

(Reverse DCM). The forward/reverse selection is made by driving the DIR pin as desired.

When FDCM is selected, higher VC voltage increases the power flowing from VIN to V

. Lower VC voltage reduces

OUT

or stops the flow. When RDCM is selected, lower VC voltage

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LT8708

OPERATION

increases the power flowing from V

into VIN. Higher

OUT

VC voltage reduces or stops the flow.

Forward (or reverse) DCM affects the power switches as follows. Under light loading conditions, in FDCM (or RDCM), synchronous switch M4 (or M1) is turned off whenever instantaneous reverse (or forward) current in the inductor is detected. This is to prevent drawing current from V

(or VIN) and feeding current into VIN (or V

OUT

). Under very light loads, the current comparator may also remain tripped for several cycles and force switches M1 (or M2) and M3 (or M4) to stay off for the same number of cycles i.e., skipping pulses. Synchronous switch M2 (or M3) will remain on during the skipped cycles, but since switch M4 (or M1) is off, the inductor current will not reverse directions.

Unidirectional Conduction: HCM

Large inductor current ripple can sometimes result in high power dissipation of the M4 (or M1) junction diode during the FDCM (or RDCM) operation described above. This can happen, for example, when VIN >> V average V

current is relatively high, but M4 is turned

OUT

and the

OUT

off to block negative components of the AC inductor current. The hybrid current mode (or HCM) is an alternative to DCM that often reduces the maximum M4 (or M1) heating in such cases.

The hybrid current mode is a mixture of the light load DCM operation and CCM operation, but only allows average current flow in one direction. As such, it is possible to have the lower portions of the inductor current ripple flow opposite to the selected direction while the average current remains in the selected direction. The DIR pin is used to select the desired forward (or FHCM) or reverse (or RHCM) direction of average current flow.

HCM works by measuring the average forward V

OUT

current and the average reverse VIN current indicated on ICN and IMON_INP, respectively. In FHCM (or RHCM), light load is detected when ICN (or IMON_INP) is above 255mV (typical). As a result, M4 (or M1) is turned off to prevent average current flow opposite to the desired direction. Heavy load is detected when ICN (or IMON_INP) is below 205mV (typical). As a result, CCM operation is enabled,

allowing M4 (or M1) to turn on and reduce the diode’s power dissipation.

NOTE: In FHCM operation connect a 17.4k resistor from

ground to the ICN pin, and in RHCM operation, connect a 17.4k resistor from ground to the IMON_INP pin.

Unidirectional Conduction: Burst Mode

In Burst Mode operation, a VC voltage is set, with about 25mV of hysteresis, below which switching activity is inhibited and above which switching activity is re-enabled. A typical example is when, at light output currents, V

OUT

rises and forces the VC pin below the threshold that temporarily inhibits switching. After V

drops slightly and

OUT

VC rises ~25mV, the switching is resumed, initially in the buck-boost region. Burst Mode operation can increase efficiency at light load currents by eliminating unnecessary switching activity and related power losses. In Burst Mode operation, inductor current is only allowed in the forward direction, regardless of the voltage on the DIR pin. Burst Mode operation handles reverse-current detection similar to forward DCM. The M4 switch is turned off when reverse inductor current is detected.

ERROR AMPLIFIERS

The six internal error amplifiers combine to drive VC according to Table 3, with the highest priority being at the top.

Table 3. Error Amp Priorities

TYPICAL CONDITION PURPOSE

IMON_INN > 1.21V or

IMON_ON > 1.21V to Reduce Negative I

FBIN < 1.205V or

else

else VC Rises Default

FBOUT > 1.207V or

IMON_INP > 1.209V or to Reduce Positive I

IMON_OP > 1.209V to Reduce Positive I

then VC

Rises

then VC

Falls

to Reduce Negative I

to Reduce Positive IIN or

Increase Negative I

to Reduce Positive I

Increase Negative I

OUT

Note that certain error amplifiers are disabled under the conditions shown in Table 4. A disabled error amplifier is unable to affect VC and can be treated as if its associated row is removed from Table 3.

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⎠

OPERATION

Table 4. Automatically Disabled Error Amp Conditions

RDCM or RHCM

ERROR

AMP PIN NAME

EA1 IMON_INN 4*

EA2 IMON_ON 4*

EA3 FBIN 2* 4*

EA4 FBOUT 1* 3* 4*

EA5 IMON_INP 4*

EA6 IMON_OP 4*

A 1* – 4* indicates that the error amplifier listed for that row is disabled under that column’s condition. The purposes of disabling the respective amplifiers are listed below.

1* This improves transient response when VOUTLOMON deasserts.

2* This improves transient response when VINHIMON deasserts.

3* Since power can only transfer from V prevents higher FBOUT/V with the FBIN/VIN voltage regulation.

4* No switching occurs in this condition. Disabling the error amplifiers improves transient response when resuming switching operation.

Some applications don’t require the use of all six error amplifiers. When unused, the respective input pin(s) should be driven so that they don’t interfere with the operation of the remaining amplifiers. Use Table 5 as a guide.

Table 5. Disabling Unused Amplifiers

AMPLIFIER

NAME PIN NAME TIE TO DISABLE

EA1 IMON_INN

EA2 IMON_ON

EA3 FBIN > 1.5V LDO33

EA4 FBOUT

EA6 IMON_OP

REGULATION AND SENSING

OUT

Two pins, FBOUT and VOUTLOMON, are provided to sense the V

voltage and issue the appropriate response to

OUT

the switching regulator.

VOUTLOMON

ASSERTED

OUT

VINHIMON ASSERTED

voltages from interfering

< 0.9V GND

< 0.9V GNDEA5 IMON_INP

to VIN, this

OUT

RVSOFF

–

<1.207V

EXAMPLE DISABLED

PIN CONNECTION

LT8708

: Regulation

OUT

is regulated, subject to the priorities in Table 3, us-

OUT

ing a resistor divider between V FBOUT connects to the EA4 amplifier to drive VC. When FBOUT rises near or above the EA4 reference (1.207V typical), VC typically falls, commanding less current into V

OUT

. The V

OUT

regulation voltage is given by the equation:

OUT

⎛

⎜

= 1.207V • 1+

FBOUT1

⎜

FBOUT2

where:

: Above Regulation

OUT

FBOUT1

and R

are shown in Figure 1.

FBOUT2

When the FBOUT pin and EA4 detect that V cantly above regulation, VC typically falls to its minimum voltage. The LT8708 responds to the minimum VC voltage according to the conduction mode enabled by MODE, DIR and RVSOFF. If reverse conduction is not allowed (FDCM, FHCM and Burst Mode operation) then switching will stop and current won’t be delivered to VIN. If reverse conduction is allowed (CCM, RDCM and RHCM), then current and power will flow from V

: Below Regulation and Undervoltage

OUT

When the FBOUT pin and EA4 detect V tion, VC typically rises. If forward conduction is enabled (CCM, FDCM, FHCM and Burst mode), then current and power will flow from VIN to V

A resistor divider between V is used to detect V

OUT

reverse conduction, from V

OUT,

undervoltage. This function prevents

OUT

down lower than desired. When undervoltage is detected by VOUTLOMON, RVSOFF is pulled low to disable reverse current and power. This function can be used as a UVLO (undervoltage lockout), for example, when a battery or supercapacitor, connected to V to VIN. See the VINHIMON, VOUTLOMON and RVSOFF section for more detailed information.

, FBOUT and ground.

OUT

⎞ ⎟ ⎟

⎟

is signifi-

OUT

to VIN.

is below regula-

OUT

VOUTLOMON and ground

to VIN, from drawing V

, is supplying power

OUT

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LT8708

⎝

⎠

OPERATION

VIN REGULATION AND SENSING

Two pins, FBIN and VINHIMON, are provided to sense the VIN voltage and issue the appropriate response to the switching regulator.

VIN: Regulation

Subject to the priorities in Table 3, a resistor divider between VIN, FBIN and ground can be used to regulate VIN or serve an undervoltage lockout function. A few application examples are as follows:

• For VIN supplies with high source impedance (i.e., a

solar panel), VIN regulation can prevent the supply voltage from dropping too low under high V

OUT

load

conditions.

• For VIN supplies with low source impedance (i.e.,

batteries and voltage supplies), the FBIN pin can be used to stop switching activity when the VIN supply voltage gets too low for proper system operation.

• VIN can also be regulated to a maximum voltage when

power is flowing from V

to VIN, such as in a battery

OUT

backup application.

When FBIN falls near or below the EA3 reference (1.205V typical), the VC voltage falls and reduces current draw from VIN. The VIN regulation voltage is given by the equation:

VIN = 1.205V • 1+

⎛

⎜ ⎜

⎜

FBIN1

FBIN2

⎞ ⎟ ⎟

⎟

where:

FBIN1

and R

are shown in Figure 1.

FBIN2

VIN: Above Regulation and Overvoltage

When the FBIN pin and EA3 detect VIN is above regulation, VC is allowed to rise. If forward conduction is enabled (CCM, FDCM, FHCM and Burst Mode operation), then current and power can flow from VIN to V

. If only reverse conduc-

OUT

tion is enabled (RDCM and RHCM), then switching will stop and current won’t be delivered into VIN. NOTE: This above-regulation condition is required to allow forward conduction in an application.

A resistor divider between VIN, VINHIMON and ground is used to detect VIN overvoltage. This function prevents reverse conduction, from V

to VIN, from forcing VIN

OUT

higher than desired. When overvoltage is detected by VINHIMON, RVSOFF is pulled low to disable reverse current and power. This function can be used as an OVLO (over voltage lockout), for example, when a battery, connected to VIN, is being charged from V

. See the VINHIMON,

OUT

VOUTLOMON and RVSOFF section for more detailed information.

VIN: Below Regulation

When the FBIN pin and EA3 detect that VIN is significantly below regulation, VC may fall to its minimum voltage. The LT8708 responds to the minimum VC voltage according to the conduction mode enabled by MODE, DIR and RVSOFF. If only forward conduction is allowed (FDCM, FHCM and Burst Mode operation) then switching will stop and current won’t be drawn from V

. If reverse conduction is

OUT

allowed (CCM, RDCM and RHCM), then current and power will flow from V

OUT

to VIN.

UVLO functions are available to detect low VIN voltage. These functions are discussed in the Voltage Lockouts section.

CURRENT MONITORING AND LIMITING

Monitoring and Limiting: IMON Pins

The LT8708 can monitor VIN and V I

) in both the positive and negative directions. The

OUT

current (IIN and

OUT

CSPIN and CSNIN pins connect across a current sense resistor to monitor IIN. External resistors are connected from the IMON_INP and IMON_INN pins to GND. Their resulting voltages are linearly proportional to positive IIN and negative IIN respectively. See amplifier A3 in the Block Diagram.

Similarly, an I and CSNOUT, is used to monitor the V

sense resistor, measured by CSPOUT

OUT

current. External

OUT

resistors are connected from the IMON_OP and IMON_ON pins to GND. Their resulting voltages are linearly proportional to positive I

and negative I

OUT

respectively. See

OUT

amplifier A1 in the Block Diagram.

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OPERATION

LT8708

The IIN and I

currents can be limited and regulated to

OUT

independent maximum positive values. When IIN causes IMON_INP to rise near or above 1.209V (typical), EA5 typically causes VC to pull down and limit/regulate the maximum current. Similarly, when I

causes IMON_OP

OUT

to rise near or above 1.209V (typical), EA6 typically causes VC to pull down and limit/regulate the maximum current. See Table 3 for error amplifier priorities.

The IIN and I

currents can also be limited and regu-

OUT

lated to independent maximum negative values. When IIN causes IMON_INN to rise near or above 1.21V (typical), EA1 causes VC to pull up and limit the maximum current. Similarly, when I

causes IMON_ON to rise near or

OUT

above 1.21V (typical), EA2 causes VC to pull up and limit the maximum current.

The IIN and I

current limits can provide many benefits.

OUT

They can be used to prevent overloading the input supply, allow for constant-current battery and supercapacitor charging and can also serve as short-circuit protection for constant-voltage regulators. See the Applications Information section for more information about the current monitors and the current regulation and limiting.

Monitoring: ICP and ICN Pins

ICP and ICN are additional current monitor pins with output currents typically equal to those of IMON_OP and IMON_ON, respectively.

In contrast to IMON_OP, ICP is internally pulled to ~0.6V (typical) when VC is at its minimum and the conduction mode is either RDCM or RHCM. Also, in contrast to IMON_ON, ICN is internally pulled to ~0.6V (typical) when VC is at its maximum and the conduction mode is FDCM, FHCM or Burst Mode operation.

INTVCC/EXTVCC/GATEVCC/LDO33 POWER

Power for the top and bottom MOSFET drivers, the LDO33 pin and most internal circuitry is derived from the INTV

pin. INTVCC is regulated to 6.3V (typical) from either the V

or EXTVCC pin. When the EXTVCC pin is left open

INCHIP

or tied to a voltage less than 6.2V (typical), an internal low dropout regulator regulates INTVCC from V

INCHIP

. If EXTVCC is taken above 6.4V (typical), another low dropout regulator will instead regulate INTVCC from EXTVCC. Regulating INTVCC from EXTVCC allows the power to be derived from the lowest supply voltage (highest efficiency) such as the LT8708 switching regulator output (see INTV

Regulators

and EXTVCC Connection in the Applications Information section for more details).

The GATEVCC pin directly powers the bottom MOSFET drivers for switches M2 and M3 (see Figure 3). GATEVCC should always be connected to INTVCC and should not be powered or connected to any other source. Undervoltage lockouts (UVLOs) monitoring INTVCC and GATEVCC disable the switching regulator when the pins are below

4.65V (typical).

The LDO33 pin can provide power to external components such as a microcontroller and/or can provide an accurate bias voltage. Load current is limited to 17.25mA (typical). As long as SHDN is high, the LDO33 output is linearly regulated from the INTVCC pin and is not affected by the INTVCC or GATEVCC UVLOs or the SWEN pin voltage. LDO33 remains regulated as long as SHDN is high and sufficient voltage is available on INTVCC (typically > 4.0V). An undervoltage lockout monitoring LDO33 will disable the switching regulator when LDO33 is below 3.04V (typical).

CLKOUT AND TEMPERATURE SENSING

Always connect a 17.4k resistor from ICP to ground and from ICN to ground.

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The CLKOUT pin toggles at the LT8708’s internal clock frequency whether the internal clock is synchronized to an external source or is free-running based on the external RT resistor. The CLKOUT pin can be used to synchronize other devices to the LT8708’s switching frequency. Also, the duty cycle of CLKOUT is proportional to the die temperature and can be used to monitor the die for thermal issues.

Rev 0

LT8708

APPLICATIONS INFORMATION

This Applications Information section provides additional details for setting up an application using the LT8708. Topics include verifying the power flow conditions, selection of various external components including the switching MOSFETs, sensing resistors, filter capacitors, diodes and the primary inductor among others. In addition, more information is provided about voltage lockouts, current monitoring, PCB layout and efficiency considerations. This section wraps up with a design example to illustrate the use of the various design equations presented here.

VERIFY THE POWER FLOW CONDITIONS

Due to the configurability of the LT8708, a methodical approach should be used to verify that power will flow, as intended, under all relevant conditions. Table 6(a) and 6(b) are provided to help with this verification.

First, using Table 6(a), note which VIN and V

combina-

OUT

tions are used in the application. For example, print a copy of Table 6(a) and highlight or circle the applicable cells.

In Table 6(a):

Table 6. Power Flow Verification Table 6(a)

OUT/VIN

VIN < V

IN_FBIN

VIN > V

IN_VINHIMON

6(b)

A Power Flows from VIN to V

D Power Flows from VIN to V

IN_FBIN

VIN <

VIN >

MODE =

BURST MODE = CCM

No Power

Flow

OUT

OUT_VOUTLOMON

No Power

Transfer

A D C

A D

Power Flows

from V

OUT

to V

OUT

OUT_VOUTLOMON

< V

OUT

OUT_FBOUT

B B

MODE =

DCM/HCM,

DIR = FWD

OUT

No Power

Flow

OUT

OUT_FBOUT

No Power

Transfer

MODE = DCM/

HCM, DIR = RVS

No Power Flow

Power Flows

from V

No Power Flow

OUT

to VIN

Note: Table 6(a) and Table 6(b) assume that the RVSOFF pin is not driven low by an external device.

• V

IN_FBIN

OUT_FBOUT

is the VIN voltage when FBIN is at 1.205V (typ)

is the V

voltage when FBOUT is at

OUT

1.207V (typ)

• V

IN_VINHIMON

is the VIN voltage when V

INHIMON

1.207V (typ)

• V

OUT_VOUTLOMON

is the V

voltage when V

OUT

OUTLOMON

is at 1.207V (typ)

If one or more of the FBIN, FBOUT, VINHIMON and VOUTLOMON pins are tied to their inactive states (see Table 5 and the VINHIMON, VOUTLOMON and RVSOFF section), the associated row(s) or column(s) will not apply to the application. For example, if FBIN is tied to LDO33 to deactivate that pin function, then the VIN < V

IN_FBIN

row of Table 6(a) is not applicable and no cells in that row should be circled.

Next, for each cell identified in Table 6(a), check that the operating condition described in Table 6(b) meets the application’s requirements.

See the Design Example section for a further example of using these tables.

OPERATING FREQUENCY SELECTION

The LT8708 uses a constant frequency architecture between 100kHz and 400kHz. The frequency can be set using the internal oscillator or can be synchronized to an external clock source. Selection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires more inductance and/or capacitance to maintain low output ripple voltage. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switching losses. The switching frequency can be set by placing an appropriate resistor from the RT pin to ground and tying the SYNC pin low. The frequency can also be synchronized to an external clock source driven into the SYNC pin. The following sections provide more details.

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OSC

APPLICATIONS INFORMATION

LT8708

INTERNAL OSCILLATOR

The operating frequency of the LT8708 can be set using the internal free-running oscillator. When the SYNC pin is driven low (< 0.5V), the operating frequency is set by the value of the resistor from the RT pin to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula:

⎛

⎜ ⎝

43,750

OSC

⎞

kHz

⎟

⎠

where:

is in kHz and RT is in kΩ.

OSC

Conversely, RT (in kΩ) can be calculated from the desired frequency (in kHz) using:

– 1

⎞ ⎟ ⎠

kΩ

⎛

43,750

RT=

⎜

⎝

SYNC PIN AND CLOCK SYNCHRONIZATION

The operating frequency of the LT8708 can be synchronized to an external clock source. To synchronize to the external source, simply provide a digital clock signal into the SYNC pin. The LT8708 will operate at the SYNC clock frequency.

CLKOUT PIN AND CLOCK SYNCHRONIZATION

The CLKOUT pin can drive up to 200pF and toggles at the LT8708’s internal clock frequency whether the internal clock is synchronized to the SYNC pin or is free-running based on the external RT resistor. The rising edge of CLKOUT is approximately 180° out of phase from the internal clock’s rising edge or the SYNC pin’s rising edge if it is toggling. CLKOUT starts toggling when the INITIALIZE state is entered (see Figure 2).

The CLKOUT pin can be used to synchronize other devices to the LT8708’s switching frequency. For example, the CLKOUT pin can be tied to the SYNC pin of another LT8708 regulator which will operate approximately 180°out of phase of the master LT8708. The frequency of the master LT8708 can be set by the external RT resistor or by toggling the SYNC pin. Note that the RT pin of the slave LT8708 must have a resistor tied to ground. In general, use the same value RT resistor for all of the synchronized LT8708s.

The duty cycle of CLKOUT is proportional to the die temperature and can be used to monitor the die for thermal issues. See the Junction Temperature Measurement section for more information.

INDUCTOR CURRENT SENSING AND SLOPE COMPENSATION

The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria:

1. SYNC may not toggle outside the frequency range of

100kHz to 400kHz unless it is stopped low to enable the free-running oscillator.

2. The SYNC pin frequency can always be higher than

the free-running oscillator set frequency, f should not be less than 25% below f

OSC

, but

After SYNC begins toggling, it is recommended that switching activity is stopped before the SYNC pin stops toggling. Excess inductor current can result when SYNC stops toggling as the LT8708 transitions from the external SYNC clock source to the internal free-running oscillator clock. Switching activity can be stopped by driving either the SWEN or SHDN pin low.

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The LT8708 operates using inductor current mode control. As described previously in the Power Switch Control section, the LT8708 measures the peak of the inductor current waveform in the boost region and the valley of the inductor current waveform in the buck region. The inductor current is sensed across the R

resistor with pins CSP and

SENSE

CSN. During any given cycle, the peak (boost region) or valley (buck region) of the inductor current is controlled by the VC pin voltage.

Slope compensation provides stability in constant-frequency current mode control architectures by preventing subharmonic oscillations at high duty cycles. This is accomplished internally by adding a compensating ramp to the inductor current signal in the boost region, or subtracting a ramp from the inductor current signal in the buck region. At higher duty cycles, this results in a reduction of maximum inductor current in the boost region, and an increase of the maximum

Rev 0

LT8708

⎝

⎠

⎝

⎠

≅ 68mV

∆I

≅

APPLICATIONS INFORMATION

inductor current in the buck region. For example, refer to the Maximum Inductor Current Sense Voltage vs Duty Cycle graph in the Typical Performance Characteristics section. The graph shows that, with VC at its maximum voltage, the maximum peak inductor sense voltage V

RSENSE

is between 47mV and 93mV depending on the duty cycle. It also shows that the maximum inductor valley current in the buck region is 82mV increasing to ~130mV at higher duty cycles.

The R

SELECTION AND MAXIMUM CURRENT

SENSE

resistance must be chosen properly to

SENSE

achieve the desired amount of output current (forward conduction) and input current (reverse conduction). Too much resistance can limit the input/output current below the application requirements. Start by determining the maximum allowed R and reverse boost regions (R and R

SENSE(MAX,BOOST,RVS)

maximum allowed R and reverse buck regions (R R

SENSE(MAX,BUCK,RVS)

resistances in the forward

SENSE

SENSE(MAX,BOOST,FWD)

). Follow this by finding the

resistances in the forward

SENSE

SENSE(MAX,BUCK,FWD)

). The selected R

SENSE

resistance

and

must be less than all four values.

Forward Conduction: In this section R

is calculated which is the maximum allowed R

Selection: Max R

SENSE

in the Boost Region

SENSE

SENSE(MAX,BOOST,FWD)

SENSE

resistance when operating in the boost region with forward conduction (VIN to V R

SENSE(MAX,BOOST,FWD)

). Skip this section and assume

OUT

= ∞ when this operating condition

does not apply to the application.

In the boost region, the maximum positive V

current

OUT

capability is the lowest when VIN is at its minimum and V

is at its maximum. Therefore, R

OUT

must be cho-

SENSE

sen to meet the output current requirements under these conditions.

Start by finding the maximum boost region duty cycle which occurs when VIN is minimum and V

is maximum using:

OUT

For example, an application with a VIN range of 12V to 48V and V

(MAX,M3,BOOST)

⎛ ⎜ ⎜

set to 36V will have:

OUT

≅

⎞

12V 36V

⎟ ⎟

•100% =67%

1–

Referring to the Maximum Inductor Current Sense Voltage graph in the Typical Performance Characteristics section, the maximum R

RSENSE(MAX,BOOST,MAXDC)

for VIN = 12V, V

voltage at 67% duty cycle is 68mV, or:

SENSE

= 36V.

OUT

Next, the inductor ripple current in the boost region must be determined. If the main inductor L is not known, the maximum ripple current ∆I by choosing ∆I

L(MAX,BOOST)

to be 30% to 50% of the maxi-

can be estimated

mum peak inductor current in the boost region as follows:

L(MAX,BOOST)

OUT(MAX,BOOST)•IOUT(MAX,FWD)



IN(MIN,BOOST)

100%

•





%Ripple

– 0.5

 



where:

OUT(MAX,FWD)

is the maximum V

load current

OUT

required in the boost region.

%Ripple is 30% to 50%

For example, using V I

OUT(MAX,FWD)

L(MAX,BOOST)

= 2A and %Ripple = 40% we can calculate:

36V • 2A



12V •

100%



40%



OUT(MAX)

– 0.5

 



=3A

= 36V, V

IN(MIN)

= 12V,

(MAX,M3,BOOST)

⎛

⎜ ⎜ ⎜

IN(MIN,BOOST)

1–

OUT(MAX,BOOST)

≅

⎞ ⎟

•100%

⎟ ⎟

Rev 0

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∆I

( )

APPLICATIONS INFORMATION

LT8708

Otherwise, if the inductance is already known then ∆I

L(MAX,BOOST,FWD)

can be more accurately calculated as

follows:

L(MAX,BOOST)

⎛

(MAX,M3,BOOST)

⎜ ⎜

⎜ ⎝

100%

ƒ •L

⎞ ⎟

• V

⎟

IN(MIN,BOOST)

⎟ ⎠

where:

(MAX,M3,BOOST)

is the maximum duty cycle percent-

age in the boost region as calculated previously

ƒ is the switching frequency

L is the inductance of the main inductor

After the maximum ripple current is known, the maximum allowed R duction (VIN to V

SENSE (MAX,BOOST,FWD)

2 •I

in the boost region while in forward con-

SENSE

) can be calculated as follows:

OUT

2 •V

OUT(M AX,FWD)

RSENS E(MAX ,BOOST,MAXDC)

• V

OUT(M AX,BOOST)

+ ∆I

L(MAX,BOOST)

• V

IN(MIN,BOOST)

• V

IN(MIN,BOOST)

Ω

where:

RSENSE(MAX,BOOST,MAXDC)

is the maximum inductor current sense voltage as discussed in the previous section.

Using values from the previous examples:

SENSE(MAX,BOOST,FWD)

duty cycle. See Switch Control: Boost Region (VIN << V

) section for the equation to calculate the minimum

OUT

duty cycle DC

(ABSMIN, M3, BOOST)

Before calculating the maximum R

resistance allowed

SENSE

during reverse operation, however, the inductor ripple current must be determined. If the main inductorL is not known, the ripple current ∆I by choosing ∆I

L(MIN,BOOST)

to be 10% of the minimum

can be estimated

peak inductor current in the boost region as follows:

∆I

L(MIN,BOOST)

IN(MAX,RVS)

≅



100%

 

10%

– 0.5

 



where:

IN(MAX,RVS)

is the maximum VIN load current required

in the boost region in the reverse direction

If the inductance is already known then ∆I

L(MIN,BOOST)

can

be calculated as follows:

∆I

L MIN,BOOST

( )

⎛

⎜ ⎜

⎜ ⎝

(ABSMIN,M3,BOOST)

100%

ƒ •L

⎞ ⎟

• V

⎟

IN(MIN,BOOST)

⎟ ⎠

where:

(ABSMIN,M3,BOOST)

is the minimum duty cycle percentage in the boost region (see Switch Control: Boost Region (VIN << V

) section)

OUT

2 • 2A • 36V

Reverse Conduction: In this section R is calculated which is the maximum allowed R sistance when operating in the boost region with reverse conduction (V R

SENSE(MAX,BOOST,RVS)

does not apply to the application.

In the boost region, the maximum reverse VIN current capability is the lowest when operating at the minimum

2 • 68mV •12V

to VIN). Skip this section and assume

OUT

+ 3A • 12V

= 9.1mΩ

SENSE(MAX,BOOST,RVS)

re-

SENSE

= ∞ when this operating condition

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ƒ is the switching frequency

L is the inductance of the main inductor

Now that the inductor ripple current is known, the maximum allowed R

in the boost region while in reverse

SENSE

conduction can be calculated as follows:

SENSE(MAX,BOOST,RVS)

2• | V

RSENSE(MIN,BOOST,MINDC)

2 •I

IN(MAX,RVS)

– ∆I

L(MIN,BOOST)

Ω

Rev 0

LT8708

( )

⎝

⎠

APPLICATIONS INFORMATION

where:

RSENSE(MIN,BOOST,MINDC)

is the minimum inductor current sense voltage in the boost region at the minimum duty cycle. Typical value is –93mV.

Negative result from the above equation indicates that any R

value can meet the requirement. Substitute the

SENSE

calculated result with ∞ and move onto the next section.

Forward Conduction: In this section R

is calculated which is the maximum allowed R

Selection: Max R

SENSE

in the Buck Region

SENSE

SENSE(MAX,BUCK,FWD)

SENSE

resistance when operating in the buck region with forward conduction (VIN to V

In the buck region, the maximum V

OUT

current capability

OUT

is the lowest when operating at the minimum duty cycle. See Switch Control: Boost Region (VIN << V

) section

OUT

for the equation to calculate the minimum duty cycle DC

(ABSMIN, M2,BUCK)

Before calculating the maximum R

resistance,

SENSE

however, the inductor ripple current must be determined. If the main inductor L is not known, the ripple current ∆I

L(MIN,BUCK)

can be estimated by choosing ∆I

L(MIN,BUCK)

to be 10% of the maximum peak inductor current in the buck region as follows:

∆I

L(MIN,BUCK)

OUT(MAX,FWD)



100%

 

– 0.5

10%

A≅

 



where:

OUT(MAX,FWD)

is the maximum V

load current

OUT

required in the buck region in the forward direction.

If the inductance is already known then ∆I

L(MIN,BUCK)

can be calculated as follows:

∆I

L MIN,BUCK

( )

⎛

⎜ ⎜

⎜ ⎝

(ABSMIN,M2,BUCK)

100%

ƒ •L

⎞ ⎟

• V

⎟

OUT(MIN,BUCK)

⎟ ⎠

where:

(ABSMIN,M2,BUCK)

is the minimum duty cycle per-

centage in the buck region as calculated previously

ƒ is the switching frequency

L is the inductance of the main inductor

After the inductor ripple current is known, the maximum allowed R

in the buck region while in forward con-

SENSE

duction can be calculated as follows:

SENSE(MAX,BUCK,FWD)

2 • V

RSENSE(MAX,BUCK,MINDC)

2 •I

OUT(MAX,FWD)

– ∆I

L(MIN,BUCK)

Ω

where:

RSENSE(MAX,BUCK,MINDC)

is the maximum inductor current sense voltage at the minimum duty cycle. Typical value is 82mV.

Negative result from the above equation indicates that any R

value can meet the requirement. Substitute the

SENSE

calculated result with ∞ and move onto the next section.

Reverse Conduction: In this section R

is calculated which is the maximum allowed R

RVS)

SENSE(MAX, BUCK,

SENSE

resistance when operating in the buck region with reverse conduction (V R

SENSE(MAX, BUCK, RVS)

to VIN). Skip this section and assume

OUT

= ∞ when this operating condition

does not apply to the application.

In the buck region, the maximum reverse VIN current capability is the least when VIN is at its maximum and V is at its minimum for buck operation. Therefore R

OUT

SENSE

must be chosen to meet the VIN current requirements under these conditions.

Start by finding the buck region duty cycle when VIN is minimum and V

(MAX,M2,BUCK)

⎛

⎜

1–

⎜ ⎜

is maximum using:

OUT

≅

OUT(MIN,BUCK)

IN(MAX,BUCK)

⎞ ⎟

•100%

⎟ ⎟

Rev 0

For more information www.analog.com

∆I

≅

APPLICATIONS INFORMATION

VIN/V

OUT

(V/V)

0.1110

0.20

0.40

0.60

0.80

1.00

NORMALIZED CURRENT

8708 F08

MAXIMUM

OUTPUT

INDUCTOR

CURRENT

MAXIMUM

CURRENT

LT8708

Next, the inductor ripple current in the buck region must be determined. If the main inductor L is not known, the maximum ripple current ∆I by choosing ∆I

L(MAX,BUCK)

to be 30% to 50% of the maxi-

can be estimated

mum peak inductor current in the buck region as follows:

L(MAX,BUCK)

IN(MAX,BUCK)•IIN(MAX,RVS)



OUT(MIN,BUCK)

•

 

%Ripple

100%

– 0.5

 



where:

IN(MAX,RVS)

is the maximum VIN load current in the

reverse direction required in the buck region.

%Ripple is 30% to 50%

Otherwise, if the inductance is already known then ∆I

L(MAX,BUCK)

∆I

L(MAX,BUCK)

can be more accurately calculated as follows:

≅

⎛

(MAX,M2,BUCK)

⎜ ⎜

⎜ ⎝

100%

⎞ ⎟ ⎟

⎟ ⎠

ƒ •L

• V

OUT(MIN,BUCK)

where:

(MAX,M2,BUCK)

is the maximum duty cycle percent-

age in the buck region as calculated previously

where:

RSENSE(MIN,BUCK,MAXDC)

is the minimum inductor current sense voltage at the maximum duty cycle. This value is determined in a similar manner to V

RSENSE(MAX,BOOST,MAXDC)

Selection: Max R

SENSE

discussed previously in the

in the Boost Region

SENSE

(Forward Conduction) section.

The final R maximum R R R

Selection: Final R

SENSE

value should be lower than all four

SENSE

values, R

SENSE

SENSE(MAX,BOOST,RVS)

SENSE(MAX,BUCK,RVS)

. A margin of 20% to 30% is rec-

Value

SENSE

SENSE(MAX,BOOST,FWD)

, R

SENSE(MAX,BUCK,FWD)

and

ommended.

Figure 8 shows approximately how the maximum positive I

and inductor currents would vary with VIN/V

OUT

while all other operating parameters remain constant (frequency = 120kHz, inductance = 10µH, R

SENSE

= 1mΩ). This graph is normalized and accounts for changes in maximum current due to the slope compensation ramps and the effects of changing ripple current. The curve is theoretical but can be used as a guide to predict relative changes in maximum currents over a range of VIN/V

OUT

voltages. Similarly, when in reverse conduction, Figure 9 shows approximately how the maximum negative IIN and inductor currents would vary with VIN/V

OUT

ƒ is the switching frequency

L is the inductance of the main inductor

After the maximum ripple current is known, the maximum allowed R tion can be calculated as follows:

SENSE(MAX,BUCK,RVS)

2• |I

( )

SENSE

2• | V

IN(MAX,RVS)

in the buck region while in reverse conduc-

RSENSE(MIN,BUCK,MAXDC)

| •V

IN(MAX,BUCK)

| •V

OUT(MIN,BUCK)

+ ∆I

( )

L(MAX,BUCK)

• V

OUT(MIN,BUCK)

For more information www.analog.com

Ω

Figure 8. Currents vs VIN/V

Ratio in Forward Conduction

OUT

Rev 0

LT8708

≅

VIN/V

OUT

(V/V)

0.1110

0.20

0.40

0.60

0.80

1.00

NORMALIZED CURRENT

8708 F09

MAXIMUM

INTPUT

INDUCTOR

CURRENT

MAXIMUM

CURRENT

10(b)

APPLICATIONS INFORMATION

Figure 9. Currents vs VIN/V

SENSE

FILTERING

Certain applications may require filtering of the inductor current sense signals due to excessive switching noise that can appear across R higher values of R

SENSE

will all contribute additional noise across R SW pins transition. The CSP/CSN sense signals can be filtered by adding one of the RC networks shown in Figure

10. Most PC board layouts can be drawn to accommodate either network on the same board. The network should be placed as close as possible to the IC. The network in Figure 10b can reduce common mode noise seen by the CSP/CSN pins of the LT8708 at the expense of some increased ground trace noise as current passes through the capacitors. A short direct path from the capacitor grounds to the IC ground should be used on the PC board. Resistors greater than 10Ω should be avoided as these can increase offset voltages at the CSP/CSN pins. The RC product should be kept to less than 30ns.

10Ω

SENSE

10Ω

SENSE

10Ω

1nF

Ratio in Reverse Conduction

OUT

. Higher operating voltages,

SENSE

, and more capacitive MOSFETs

when the

SENSE

CSP

LT8708

1nF

CSN

10(a)

CSP

LT8708

1nF

CSN

8708 F10

INDUCTOR (L) SELECTION

For high efficiency, choose an inductor with low core loss, such as ferrite. Also, the inductor should have low DC resistance to reduce the I2R losses, and must be able to handle the peak inductor current without saturating. To minimize radiated noise, use a toroid, pot core or shielded bobbin inductor.

The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. The following sections discuss several criteria to consider when choosing an inductor value. For optimal performance, choose an inductor that meets all of the following criteria.

L Selection: Load Current in Buck and Boost Regions

Small inductances result in increased ripple currents and thus, due to the positive and negative inductor current limits, decrease the maximum average forward I the boost region and the maximum average reverse I

OUT

in the buck region.

In order to provide adequate forward I

at low VIN volt-

OUT

ages in the boost region, L should be at least:

(MIN1,BOOST)



(MAX,M3,BOOST)

IN(MIN,BOOST)



RSENSE(MAX,BOOST,MAXDC)



2• ƒ•



SENSE



•



–

100%

OUT(MAX,FWD)

  

• V

OUT(MAX,BOOST)

IN(MIN,BOOST)

  

where:

(MAX,M3,BOOST)

age of the M3 switch (see R R

in the Boost Region section)

SENSE

is the maximum duty cycle percent-

Selection: Max

SENSE

ƒ is the switching frequency

RSENSE(MAX,BOOST,MAXDC)

is the maximum current sense voltage in the boost region at maximum duty cycle (see R

Selection: Max R

SENSE

in the Boost

SENSE

Region section)

OUT(MAX,FWD)

is the maximum forward V

OUT

current

in boost region

Figure 10. Inductor Current Sense Filter

Rev 0

For more information www.analog.com

≅

⎝

⎠

APPLICATIONS INFORMATION

LT8708

To provide adequate reverse IIN current at low V

OUT

volt-

ages in the buck region, L should be at least:

(MIN1,BUCK)

2• ƒ•

OUT(MIN,BUCK)



RSENSE(MIN,BUCK,MAXDC)

 

SENSE





•



–

(MAX,M2,BUCK)

100%

IN(MAX,RVS)

 



• V

IN(MAX,BUCK)

OUT(MIN,BUCK)

 



where:

(MAX,M2,BUCK)

of the M2 switch (see R

is the maximum duty cycle percentage

Selection: Max R

SENSE

in the Buck Region section)

ƒ is the switching frequency

RSENSE(MIN,BUCK,MAXDC)

is the minimum current sense voltage in the buck region at maximum duty cycle (see R

Selection: Max R

SENSE

in the Buck

Region section)

IN(MAX,RVS)

is the maximum reverse VIN current in

buck region

Negative values of L

(MIN1,BOOST)

or L

(MIN1,BUCK)

indicate that the load current can’t be delivered because the inductor current limit is too low. If L

(MIN1,BOOST)

is too large or is negative, consider reducing the R

or L

(MIN1,BUCK)

SENSE

resistor value to increase the inductor current limit.

In the boost region, if V calculate L

(MIN2,BOOST)

can be greater than twice VIN,

OUT

as follows:

(MIN2,BOOST)





OUT(MAX,BOOST)





IN(MIN,BOOST)



–



OUT(MAX,BOOST)

0.08 • f

• V

OUT(MAX,BOOST)

– V

IN(MIN,BOOST)



 

•R



SENSE





In the buck region, if VIN can be greater than twice V calculate L

(MIN2,BUCK)

as follows:

(MIN2,BUCK)

 



IN(MAX,BUCK)

 



 

• 1–

  

IN(MAX,BUCK)

OUT(MIN,BUCK)

– V

OUT(MIN,BUCK)









•R





SENSE



 





L Selection: Maximum Current Rating

The inductor must have a rating greater than its maximum operating current to prevent inductor saturation resulting in efficiency loss. The maximum forward inductor current in the boost region is:

L(MAX,BOOST,FWD)

≅ I

OUT(MAX,FWD)

OUT(MAX,BOOST)

• V

IN(MIN,BOOST)

OUT

L Selection: Subharmonic Oscillations

The LT8708’s internal slope compensation circuits will prevent subharmonic oscillations that can otherwise occur when VIN/V

is less than 0.5 or greater than 2.

OUT

The slope compensation circuits will prevent these oscillations provided that the inductance exceeds a minimum value (see the earlier section Inductor Current Sensing and Slope Compensation for more information). Choose an inductance greater than all of the relevant L

(MIN)

lim-

its discussed below. Negative calculation results can be

⎛ ⎜

⎜

IN(MIN,BOOST)

⎜ ⎜

⎜ ⎜ ⎜

⎜

⎛

⎜

•

⎜

⎜ ⎝

2 • L • ƒ

where:

(MAX,M3,BOOST)

is the maximum duty cycle percentage of the M3 switch (see R Maximum Current section).

(MAX,M3,BOOST)

100%

SENSE

⎞

⎟

⎠

⎟

⎟ ⎟ ⎟

⎟

Selection and

interpreted as zero.

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Rev 0

LT8708

⎝

⎠

OUT

⎝

⎠

⎝

⎠

⎝

⎠

⎝

⎠

APPLICATIONS INFORMATION

The maximum reverse inductor current in the boost region for applications in which V

L(MAX,BOOST,RVS)

⎛

IN(MAX,BOOST)

⎜

4 •L • ƒ

OUT(MAX)

≅

IN(MAX,RVS)

⎞ ⎟

⎟

For applications in which V

≥ 2•V

OUT(MAX)

IN(MAX)

< 2•V

is:

IN(MAX)

, the maximum reverse inductor current is smaller than the value given by the above equation. The following equation can be used to calculate the reverse inductor current for given combinations of VIN and V

L(MAX,BOOST,RVS)

⎛

⎜

•(V

2 •L • ƒ • V

≅ I

OUT

IN(MAX,RVS)

⎞

– VIN)

⎟ ⎟

⎟

OUT

where:

OUT

> V

The maximum positive inductor current in the buck region for applications in which V

L(MAX,BUCK,FWD)

⎛

OUT(MAX,BUCK)

⎜

For applications with V

≅

4 •L • ƒ

OUT(MAX,FWD)

IN(MAX)

⎞ ⎟ ⎟

⎟

≥ 2•V

< 2•V

OUT(MAX)

is:

, the maximum forward inductor current is smaller than the value given by the above equation. The following equation can be used to calculate the forward inductor current for given combinations of VIN and V

L(BUCK,FWD)

⎛ ⎜

⎜

OUT

≅ I

OUT(MAX,FWD)

•(VIN– V

•L • ƒ • V

OUT

⎞

)

⎟

The maximum reverse inductor current when operating in the buck region is:

L(MAX,BUCK,RVS)

⎛ ⎜

⎜

OUT(MIN,BUCK)

⎜

⎜ ⎜ ⎜

⎜

≅ I

IN(MAX,RVS)

(MAX,M2,BUCK)

•

2 • L • ƒ

100%

IN(MAX,BUCK)

• V

OUT(MIN,BUCK)

⎞ ⎟ ⎟ ⎟

⎟ ⎟ ⎟

⎟

where:

(MAX,M2,BUCK)

age of the M2 switch in the buck region (see R Selection: Max R

is the maximum duty cycle percent-

SENSE

in the Buck Region section).

SENSE

Note that the inductor current can be higher when there are load transients or the load current exceeds the expected maximum amount. It can also be higher during start-up if inadequate soft-start capacitance is used, or during output shorts. Consider using the IIN and/or I

OUT

current limiting to help prevent the inductor current from becoming excessive. IIN and I later in the IIN and I

current limiting are discussed

OUT

Current Monitoring and Limiting

OUT

section. Careful board evaluation of the maximum inductor current is recommended.

POWER MOSFET SELECTION

The LT8708 requires four external N-channel power MOSFETs, two for the top switches (switches M1 and M4, shown in Figure 3) and two for the bottom switches (switches M2 and M3, shown in Figure 3). Important parameters for the power MOSFETs are the breakdown voltage V R I

DS(MAX)

, output capacitance C

DS(ON)

. The gate drive voltage is set by the 6.3V GATEVCC

, threshold voltage V

BR,DSS

, on-resistance

GS,TH

, and maximum current

OSS

supply. Consequently, logic-level threshold MOSFETs must be used in LT8708 applications.

where:

VIN > V

OUT

Rev 0

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APPLICATIONS INFORMATION

or P

LT8708

It is very important to consider power dissipation when selecting power MOSFETs. The most efficient circuit will use MOSFETs that dissipate the least amount of power. Power dissipation must be limited to avoid overheating that might damage the devices. In forward conduction, the M1 and M3 switches will have the highest power dissipation, while M2 and M4 will have the highest power dissipation in reverse conduction. In some cases it can be helpful to use two or more MOSFETs in parallel to reduce power dissipation in each device. This is most helpful when power is dominated by I2R losses while the MOSFET is “on”. The additional capacitance of connecting MOSFETs in parallel can sometimes slow down switching edge rates and consequently increase total switching power losses.

SW2 node capacitance, which is dominated by the output capacitance of the external MOSFETs. Use Table 7 to determine which power components are applicable in the various regions of operation.

Table 7. NMOS Power in Various Operating Regions

OPERATING

REGION M1 M2 M3 M4

Pos.

Buck P

Boost P

Buck-Boost P

Neg.

Buck

Boost 0 P

Buck-Boost P

I2R

+ P

I2R

0 P

I2R

+ P

I2R

+ P

I2R

0 P

I2R

+ P

I2R

+ P

I2R

The following sections provide guidelines for calculating power consumption of the individual MOSFETs. From a known power dissipation, the MOSFET junction temperature can be obtained using the following formula:

TJ = TA + P • R

TH(JA)

where:

TJ is the junction temperature of the MOSFET

The MOSFET power components listed above can be approximated using the following equations. Note that IIN can be substituted for I

OUT

≅

• I

OUT

using:

OUT

where necessary.

I2R Component Equations:

TA is the ambient air temperature

P is the power dissipated in the MOSFET

is the MOSFET’s thermal resistance from the

TH(JA)

junction to the ambient air. Refer to the manufacturer’s data sheet.

TH(JA)

normally includes the R

for the device plus

TH(JC)

the thermal resistance from the case to the ambient temperature R

. Compare the calculated value of TJ to

TH(CA)

the manufacturer’s data sheets to help choose MOSFETs that will not overheat.

The power dissipation of the external N-channel MOSFETs comes from two primary components: (1) I2R power when the switch is fully “on” and inductor current is flowing between the drain and source connections and (2) power dissipated while the switch is turning “on” and “off”. The MOSFET switching power consists of (A) a combination of high current and high voltage as the switch turns “on” and “off” and (B) charging and discharging the SW1 or

I2R[M1,BUCK]

OUT

≅

I2R[M1,BOOST]

⎛

⎜

≅

⎜

⎜ ⎝

I2R[M2,BUCK]

≅

I2R[M3,BOOST]

OUT

≅

I2R[M4,BUCK]

≅ I

OUT

– V

• I

OUT

– V

• R

OUT

DS(ON)

I2R[M4,BOOST]

• R

DS(ON)

⎞ ⎟

• R

⎟

⎟ ⎠

• I

OUT

• V

OUT

• ρτW

DS(ON)

• R

DS(ON)

• I

OUT

• ρτW

• ρ

• R

• ρτW

DS(ON)

• ρτW

Rev 0

For more information www.analog.com

LT8708

or P

OSS

M3+M4

( )

OUT

NORMALIZED ON-RESISTANCE (Ω)

APPLICATIONS INFORMATION

Switching Component Equations for M1 and M2:

SW[M1,BUCK]

≅ P

≅ (VIN•|I

+(0.5 • C

Switching Component Equations for M3 and M4:

SW[M3,BOOST]

≅ P

⎛ ⎜

≅ V

⎜

⎜ ⎝

+(0.5 • C

where: t

is the average of the SW1 pin rise and fall times.

RF1

Typical values are 20 – 40ns depending on the MOSFET capacitance and VIN voltage.

is the average of the SW2 pin rise and fall times

RF2

and, similar to t on the MOSFET capacitance and V

DS(ON)

is a normalization factor (unity at 25°C) accounting

for the significant variation in MOSFET on-resistance with temperature, typically about 0.4%/°C, as shown in Figure 11. For a maximum junction temperature of 125°C, using a value = 1.5 is reasonable.

Figure 11. Normalized MOSFET RDS(ON) vs Temperature

SW[M2,BUCK ]

SWA+PSWB

| •ƒ • t

OUT

OSS

M1+M2

( )

or P

SWA+PSWB

•|I

OUT

RF1

OUT

)

RF1

• V

• ƒ) W

RF2

⎞ ⎟ ⎟

⎟ ⎠

]

• ƒ) W

SW[M4,BOOST

| •ƒ •

• V

, is typically 20ns – 40ns depending

voltage.

OUT

is the “on” resistance of the MOSFET at 25°C

2.0

1.5

1.0

0.5

–50

JUNCTION TEMPERATURE (°C)

100

150

8708 F11

Switch M1: For positive conduction, the maximum power dissipation in M1 occurs either in the buck region when VIN is highest, V

is highest, and switching power losses

OUT

are greatest, or in the boost region when VIN is smallest, V

is highest and M1 is always on.

OUT

In most cases of negative conduction, the M1 switching power dissipation is quite small and I2R power losses dominate. In negative conduction, M1 I2R power is greatest in the boost region due to the lower VIN and higher V

that cause the M1 switch to be “on” for the most

OUT

amount of time.

Switch M2: In most cases of positive conduction, the M2 switching power dissipation is quite small and I2R power losses dominate. In positive conduction, M2 I2R power is greatest in the buck region due to the higher VIN and lower V

that cause M2 to be “on” for the most amount of time.

OUT

For negative conduction, the maximum power dissipation in M2 occurs in the buck region when VIN is highest and V

is lowest.

OUT

Switch M3: If the inductor current is positive, the maximum power dissipation in M3 occurs when VIN is lowest and V

is highest.

OUT

In most cases of negative conduction, the M3 switching power dissipation is quite small and I2R power losses dominate. In negative conduction, M3 I2R power is greatest in the boost region due to the lower VIN and higher V

that cause the M3 switch to be “on” for the most

OUT

amount of time.

Switch M4: If the inductor current is positive, in most cases the switching power dissipation in the M4 switch is quite small and I2R power losses dominate. I2R power is greatest in the boost region due to the lower VIN and higher V

that cause M4 switch to be “on” for the most

OUT

amount of time.

If the inductor current is negative, the maximum power dissipation in the M4 switch occurs either in the boost region when VIN is highest, V power losses are greatest, or in the buck region when V is highest, V

is lowest and M4 is always on.

OUT

is highest, and switching

OUT

Rev 0

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APPLICATIONS INFORMATION

LT8708

Gate Resistors: In some cases it can be beneficial to add 1Ω to 10Ω of resistance between some of the NMOS gate pins and their respective gate driver pins on the LT8708 (i.e., TG1, BG1, TG2, BG2). Due to parasitic inductance and capacitance, ringing can occur on SW1 or SW2 when low capacitance MOSFETs are turned on/off too quickly. The ringing can be of greatest concern when operating the MOSFETs or the LT8708 near the rated voltage limits. Additional gate resistance slows the switching speed, minimizing the ringing.

Excessive gate resistance can have two negative side effects on performance:

1. Slowing the switch transition times can also increase power dissipation in the switch. This is described above.

2. Capacitive coupling from the SW1 or SW2 pin to the switch gate node can turn it on when it’s supposed to be off, thus increasing power dissipation. With too much gate resistance, this would happen to the M2 switch when SW1 is rising with positive inductor current and to the M3 switch when SW2 is rising with negative inductor current.

polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available.

Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. A ceramic capacitor, of at least 1μF at the maximum V V

operating voltage, should also be placed from

INCHIP

to GND as close to the LT8708 pins as possible.

INCHIP

Due to their excellent low ESR characteristics ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage.

VIN Capacitance: Discontinuous VIN current is highest in the buck region due to the M1 switch toggling on and off. Make sure that the CIN capacitor network has low enough ESR and is sized to handle the maximum RMS current. For buck operation, the VIN RMS current is given by:

Careful board evaluation should be performed when optimizing the gate resistance values. SW1 and SW2 pin ringing can be affected by the inductor current levels, therefore board evaluation should include measurements at a wide range of load currents, VIN and V

. When performing

OUT

PCB measurements of the SW1 and SW2 pins, be sure to use a very short ground post from the PCB ground to the scope probe ground sleeve in order to minimize false inductive voltage readings.

CIN AND C

and V

SELECTION

OUT

capacitance is necessary to suppress volt-

OUT

age ripple caused by discontinuous current moving in and out of the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low ESR (equivalent series resistance). Dry tantalum, special

OUT

• V

(IN,RMS)

≅ I

OUT

This formula has a maximum at VIN = 2•V I

(IN,RMS)

= I

/2. This simple worst-case condition is

OUT

• V

OUT

– 1 A

, where

OUT

commonly used for design because even significant deviations do not offer much relief.

CIN is necessary to reduce the VIN voltage ripple caused by discontinuities and ripple of IIN. The effects of ESR and the bulk capacitance must be considered when choosing the correct capacitor for a given VIN ripple.

The VIN ripple due to the voltage drop across the bulk cap ESR

, without having any ceramic capacitance in

BULK

parallel, is approximately:

∆V

(IN,BUCK,BULK)

≅ I

OUT

•ESR

BULK

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Rev 0

LT8708

∆V

⎝

⎠

⎝

⎠

⎝

⎠

⎝

⎠

∆V

APPLICATIONS INFORMATION

When low ESR ceramic capacitance is added in parallel with the bulk capacitor, the VIN ripple is approximately:

(IN,BUCK,CERAM)

⎛ ⎜ ⎜

⎜

OUT

1 – exp

•

≅

OUT

•ESR

⎛ ⎜ ⎜

⎜

VIN• ƒ •ESR

CERAM

•

– V

OUT

CERAM•CIN–CERAM

⎞

⎟

Add enough ceramic capacitance to make sure ∆V

(IN,BUCK,CERAM)

properly designed application, ∆V be much smaller than ∆V

Capacitance: Discontinuous V

OUT

is adequate for the application. In a

(IN,BUCK,CERAM)

(IN,BUCK,BULK)

OUT

current is highest

should

in the boost region due to the M4 switch toggling on and off. Make sure that the C

capacitor network has low

OUT

enough ESR and is sized to handle the maximum RMS current. For boost operation, the V

RMS current is

OUT

given by:

(OUT,RMS)

≅ I

OUT

• V

– 1 A

This formula has a maximum when VIN is minimum and V

is maximum.

OUT

With enough ceramic caps added in parallel, the steady state V ceramic C

ripple due to charging and discharging the

OUT

is given by the following equations:

OUT

∆V

(OUT,BOOST,CERAM)

•ESR

OUT

⎛ ⎜

1 – exp

⎜ ⎜

for V

OUT

(OUT,BUCK,CERAM)

8 •L • ƒ

CERAM

⎛ ⎜ ⎜

⎜

> VIN, and

OUT

for V

OUT

< V

Add enough ceramic caps to make sure ∆V and ∆V

(OUT,BUCK,CERAM)

In a properly designed application, ∆V and ∆V ∆V

(OUT,BUCK,CERAM)

(OUT,BOOST,BULK)

• ƒ •ESR

OUT

⎛ ⎜

• 1 –

⎜

⎜ ⎝

•C

OUT –CERAM

and ∆V

≅

•

⎞

– V

OUT

CERAM•COUT –CERAM

⎞

⎟

≅

⎞

OUT

⎟ ⎟

⎟

⎠

(OUT,BOOST,CERAM)

are adequate for the application.

(OUT,BOOST,CERAM)

should be much smaller than

(OUT,BUCK,BULK)

, respectively.

is necessary to reduce the V

OUT

discontinuities and ripple of I

OUT

ripple caused by

OUT

. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given V

The V

ripple due to the voltage drop across the bulk

OUT

ripple.

cap ESR without having any ceramic caps in parallel is approximately:

∆V

(OUT,BOOST,BULK)

∆V

(OUT,BUCK,BULK)

≅

≅ I

RIPPLE

OUT•IOUT

•ESR

BULK

SCHOTTKY DIODE (D1, D2, D3, D4) SELECTION

During forward conduction the Schottky diodes, D2 and D4, shown in Figure 1, conduct during the dead time between the conduction of the power MOSFET switches. They help to prevent the body diodes of synchronous switches M2 and M4 from turning on and storing charge. For example, D4 can significantly reduce reverse-recovery current when M3 turns on, which improves converter efficiency, reduces switch M3 power dissipation, and reduces noise in the inductor current sense resistor (R during reverse conduction, D1 and D3 conduct during the dead time between the conduction of the power MOSFET switches. In order for the diodes to be effective, the inductance between them and the synchronous switch must be as small as possible, mandating that these components be placed very close to the MOSFETs.

For more information www.analog.com

SENSE

). Similarly,

Rev 0

APPLICATIONS INFORMATION

LT8708

For applications with high input or output voltages (typically >40V) avoid Schottky diodes with excessive reverse-leakage currents, particularly at high temperatures. Some ultra-low VF diodes will trade-off increased high temperature leakage current for reduced forward voltage. Diodes D1 and D2 can have reverse voltages in excess of VIN and D3 and D4 can have reverse voltages in excess of V

. The combination of high reverse voltage

OUT

and current can lead to self-heating of the diode. Besides reducing efficiency, this can increase leakage current which increases temperatures even further. Choose packages with lower thermal resistance (θJA) to minimize self heating of the diodes.

TOPSIDE MOSFET DRIVER SUPPLY (CB1,DB1,CB2,DB2)

The top MOSFET drivers (TG1 and TG2) are driven digitally between their respective SW and BOOST pin voltages. The BOOST voltages are biased from floating booststrap capacitors CB1 and CB2, which are normally recharged through external silicon diodes DB1 and DB2 when the respective top MOSFET is turned off. The capacitors are charged to about 6.3V (about equal to GATEVCC) forcing the V

BOOST1-SW1

The boost capacitors CB1 and C

and V

BOOST2-SW2

voltages to be about 6.3V.

need to store about 100

times the gate charge required by the top switches M1 and M4. In most applications, a 0.1μF to 0.47μF, X5R or X7R dielectric capacitor is adequate. The bypass capacitance from GATEVCC to GND should be at least 10 times the CB1 or CB2 capacitance.

Top Driver: Boost Cap Charge Control Block

When the LT8708 operates exclusively in the boost or buck region, M1 or M4 respectively may be “on” continuously. This prevents the respective bootstrap capacitor, CB1 or CB2, from being recharged through the silicon diode, DB1 or DB2. The Boost Cap Charge Control block (see Figure 1) keeps the appropriate bootstrap capacitor charged in these cases. In the boost region, when M1 is always on, current is drawn, as needed, from the CSNOUT and/or BOOST2 pins to charge the CB1 capacitor. In the buck region, when M4 is always on, current is drawn, as needed, from the CSNIN and/or BOOST1 pins to charge the CB2 capacitor.

Because of this function, CSPIN and CSNIN should be connected across R

in series with the M1 drain.

SENSE1

Connect both pins to the M1 drain if they are not being used. Also, CSPOUT and CSNOUT should be connected across R

in series with the M4 drain or connect

SENSE2

both to the M4 drain if not being used.

Top Driver: Boost Diodes DB1 and D

Although Schottky diodes have the benefit of low forward voltage drops, they can exhibit high reverse current leakage and have the potential for thermal runaway under high voltage and temperature conditions. Silicon diodes are thus recommended for diodes DB1 and DB2. Make sure that DB1 and DB2 have reverse breakdown voltage ratings higher than V

IN(MAX)

and V

OUT(MAX)

and have less than 1mA of reverse-leakage current at the maximum operating junction temperature. Make sure that the reverse-leakage current at high operating temperatures and voltages won’t cause thermal runaway of the diode.

In some cases it is recommended that up to 5Ω of resistance is placed in series with DB1 and DB2. The resistors reduce surge currents in the diodes and can reduce ringing at the SW and BOOST pins of the IC. Since SW pin ringing is highly dependent on PCB layout, SW pin edge rates and the type of diodes used, careful measurements directly at the SW pins of the IC are recommended. If required, a single resistor can be placed between GATEVCC and the common anodes of DB1 and DB2 (as in the front page application) or by placing separate resistors between the cathodes of each diode and the respective BOOST pins. Excessive resistance in series with DB1 and DB2 can reduce the BOOST-SW capacitor voltage when the M2 or M3 ontimes are very short and should be avoided.

VINHIMON, VOUTLOMON AND RVSOFF

During reverse conduction, current and power are drawn from V draw V

and delivered to VIN. This has the potential to

OUT

lower than desired or drive VIN higher than

OUT

desired, depending on the supplies and loads. The VINHIMON and VOUTLOMON pins are used to detect either of these conditions and disable reverse conduction by pulling RVSOFF low.

For more information www.analog.com

Rev 0

LT8708

LOMON1+RLOMON2

⎝

⎠

HYSMON

⎝

⎠

APPLICATIONS INFORMATION

The purpose of the VINHIMON and VOUTLOMON functions becomes clearer when considering the priorities of the error amplifiers (see Table 3). A few important cases should be considered.

1. VIN and V

are both above regulation: In this case

OUT

FBIN is greater than 1.205V while FBOUT is greater than 1.207V. Normally this condition causes VC to fall due to FBOUT being above 1.207V. The LT8708 responds by increasing the reverse current and power being fed into VIN.

This can be an undesirable response, for example,

if VIN is connected to a battery being charged from V

. The solution is to use VINHIMON to detect the

OUT

maximum VIN and disable reverse conduction by pulling RVSOFF low.

2. VIN and V

are both below regulation: In this case

OUT

FBIN is below 1.205V while FBOUT is below 1.207V. Normally this condition causes VC to fall due to FBIN being below 1.205V. The LT8708 responds by increasing the reverse current and power being drawn fromV

OUT.

This can be an undesirable response, for example, if

is connected to a battery or supercapacitor sup-

OUT

plying power to VIN. The solution is to use VOUTLOMON to detect the minimum V

and disable reverse

OUT

conduction by pulling RVSOFF low.

If VINHIMON rises above its activation threshold or VOUTLOMON falls below its activation threshold (see Electrical Characteristics), the LT8708 will pull the RVSOFF pin low and not allow M4 switch to turn on if the inductor current is negative. In addition to the 24mV (typical) voltage hysteresis, the VINHIMON pin will source 1μA (typical) current and the VOUTLOMON pin will sink 1μA (typical) current as current hysteresis.

There are two ways to configure the VINHIMON and VOUTLOMON pins. Method (1) uses dedicated resistor dividers for VINHIMON and VOUTLOMON respectively, while method (2) uses common resistor dividers for VINHIMON and FBIN as well as for VOUTLOMON and FBOUT, allowing improved tracking with the FBOUT and FBIN regulation voltages, respectively.

1. Connect a resistor divider between VIN, VINHIMON

and GND to configure the VIN overvoltage threshold. Connect a resistor divider between V MON and GND to configure the V

OUT

, VOUTLO-

OUT

undervoltage threshold. (see Figure 12). Use the following equations to calculate the resistor values:

HIMON1

HIMON2

HIMON3

LOMON1

LOMON2

LOMON3

1.207

⎛ ⎜

⎜

⎜ ⎝

⎛ ⎜

–

⎜ ⎜

HYSMON

⎝

⎛

⎜

LOMON1•RLOMON2

–

⎜

OVIN

FBDIV

1.207 – V I

HYSMON

OVIN

•(R

UVOUT

FBDIV

1.207 I

FBDIV

⎛ ⎜ ⎜

⎜

HYSMON

⎝

– 1.207

⎞

HYSMON

–

•R

HIMON1+RHIMON2

– 1.207

–

UVOUT

•(R

⎟ ⎟

⎟ ⎠

HIMON2

•R

LOMON2

LOMON1+RLOMON2

⎛

⎞ ⎟

⎜

–

⎟

⎜

⎟

⎜

⎛

⎜

HIMON1•RHIMON2

–

⎜

HIMON1+RHIMON2

⎝

⎞ ⎟ ⎟

⎟

)

⎠

1.207 + V

HYSMON

⎞ ⎟ ⎟

⎟

)

⎠

⎞ ⎟ ⎟

⎟

where:

is the desired current through the resistor string.

FBDIV

50μA – 100μA is a good value.

OVIN

+ and V

– are the rising and falling VIN over-

OVIN

voltage thresholds.

UVOUT

+ and V

– are the rising and falling V

UVOUT

OUT

undervoltage thresholds.

HIMON1-3

HYSMON

and R

LOMON1-3

are shown in Figure 12.

is the VINHIMON and VOUTLOMON hyster-

esis voltage. Typical value is 24mV.

HYSMON

is the VINHIMON and VOUTLOMON hysteresis

current. Typical value is 1μA.

⎞ ⎟ ⎟

⎟ ⎠

Rev 0

For more information www.analog.com

⎝

⎠

APPLICATIONS INFORMATION

(b) Resistor Divider for VOUTLOMON

LT8708

HIMON1

HIMON2

HIMON3

LT8708

VINHIMON

2. Connect a resistor divider between VIN, FBIN, VINHIMON and GND to configure the VIN regulation and overvoltage thresholds (see Figure 13). Connect a resistor divider between V and GND to configure the V

VOUTLOMON, FBOUT

OUT,

regulation and under-

OUT

voltage thresholds (see Figure 14).

(a) Resistor Divider for VINHIMON

OUT

LOMON1

LOMON2

LOMON3

LT8708

VOUTLOMON

8708 F12

Figure 12.

where:

is the desired current through the resistor string.

FBDIV

50μA – 100μA is a good value.

VIN and V

are the desired regulation voltages.

OUT

Figure 13. Single Divider for VINHIMON and FBIN

IN1

FBIN

IN2

IN4

IN3

OUT

OUT1

OUT4

OUT2

OUT3

LT8708

VINHIMON

8708 F13

VOUTLOMON

LT8708

FBOUT

8708 F14

Use the following equations to calculate the resistor values:

IN3

IN1

IN2

IN4

OUT 3

OUT1

OUT 2

OUT 4

1.207 • V

OVIN

= V

OVIN

⎛

[(R

⎜

IN1+RIN2

⎜ ⎜

⎜ ⎝

⎛

⎜

HYSMON

–

⎜

HYSMON

⎝

1.207

FBDIV

= V

OUT •ROUT 3

⎛

⎜

OUT1•IHYSMON

⎜ ⎜

⎜ ⎝

⎛

⎜

HYSMON

–

⎜

HYSMON

⎝

OUT

•I

FBDIV

•R

IN3

– VIN)

– V

UVOUT

•

)•I

⎞ ⎟

–

⎟

⎟ ⎠

UVOUT

⎞ ⎟

–

⎟

⎟ ⎠

⎛

⎜ ⎜

⎜

1.207

⎝

•R

IN3

HYSMON

OVIN

⎛

⎜

OVIN

⎜ ⎜ ⎝

⎛ ⎜

•

⎜ ⎜

1.207

⎝

)

–

+ V

UVOUT

⎛

⎜

UVOUT

⎜ ⎜

–

+ V

•I

HYSMON

– 1.207) •R

OVIN

–

•R

OUT 3

•I

–

HYSMON

–

⎞

⎟ ⎟

⎟

⎠

– V

UVOUT

–

OVIN

⎞ ⎟ ⎟ ⎟ ⎠

OVIN

UVOUT

– V

– 1.207) •R

–

UVOUT

–

⎞ ⎟

IN3

⎟ ⎟ ⎠

)•1.207

–

OUT 3

]• 1.207

⎞ ⎟ ⎟ ⎟

⎟ ⎠

⎞ ⎟ ⎟ ⎟

⎟ ⎠

Figure 14. Single Divider for VOUTLOMON and FBOUT

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APPLICATIONS INFORMATION

OVIN

and V

– are the rising and falling VIN over-

OVIN

voltage thresholds.

UVOUT

and V

– are the rising and falling V

UVOUT

OUT

undervoltage thresholds.

and R

IN1-4

HYSMON

are shown in Figure 13 and Figure 14.

OUT1-4

is the VINHIMON and VOUTLOMON hyster-

esis voltage. Typical value is 24mV.

HYSMON

is the VINHIMON and VOUTLOMON hysteresis

current. Typical value is 1μA.

If unused, tie VINHIMON to GND and/or VOUTLOMON to LDO33.

Note: after the resistor values are selected, make sure to check that the FBIN and VOUTLOMON voltages are below their ABSMAX values when VIN and V

are at their

OUT

maximum, respectively.

IIN AND I

The LT8708 has independent IIN and I

CURRENT MONITORING AND LIMITING

OUT

current monitors

OUT

that can monitor and limit the respective currents in both positive and negative directions. Figure 15 and Figure 16 illustrate the operation of the current monitor circuits.

The remaining discussion refers to the IIN current monitor circuit of Figure 15. All discussion and equations are also applicable to the I

current monitor circuit, substituting

OUT

pin and device names as appropriate.

Current Monitoring: The IMON_INP and IMON_INN pins can be used to monitor IIN in the forward and reverse directions, respectively. When configured as shown in Figure 15, the IMON_INP and IMON_INN voltages are proportional to IIN. V

IMON_INP

is proportional to the positive IIN current, increasing as IIN becomes more positive. V

IMON_INN

is proportional to the negative IIN current,

increasing as IIN becomes more negative.

FROM

SYSTEM

LT8708

IMON_INN

FROM

CONTROLLER

OUT

LT8708

IMON_ON

20μA

SENSE1

CSPIN

gm = 1m

–

CSNIN

–

1.21V

EA1

TO CONTROLLER V

–

1.209V

20μA

EA5

–

IMON_INPIMON_INN

IMON_INN

IMON_INP

Figure 15. IIN Current Monitor and Limit

SENSE2

OUT

CSPOUT

CSNOUT

–

gm = 1m

–

1.21V

20μA

EA2

–

1.209V

20μA

EA6

–

IMON_OPIMON_ON

IMON_ON

IMON_OP

TO SYSTEM V

OUT

8708 F15

8708 F16

Figure 16. I

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Current Monitor and Limit

OUT

Rev 0

A V

⎝

⎠

APPLICATIONS INFORMATION

LT8708

Transconductance amplifier A3 performs this monitoring function. A3 converts the current sense voltage, V

, into two currents:

CSNIN

CSPIN-CSNIN

•1m

CSPIN-

and

– V

CSPIN-CSNIN

•1m

These currents are added to 20μA offsets and then forced into R

IMON_INP

Due to the 20μA offset currents, V

are not 0V when IIN is 0A. Instead, V

INN

20μA•R

IMON_INP

and R

IMON_INN

Volts and V

, respectively.

IMON_INP

IMON_INN(0)

and V

IMON_INP(0)

= 20μA•R

IMON_

IMON_INN

Volts (typical) when IIN = 0 Amps. As IIN becomes increasingly negative, V until V

IMON_INP

= 0V. Similarly, as IIN becomes increasingly positive, V until V

IMON_INN

= 0V. I

IMON_INP

IMON_INN

reduces below V

MON_INP

and I

MON_INN

IMON_INP(0)

IMON_INN(0)

will not be driven below ground as their output currents can only be positive or zero.

The complete transfer functions for IMON_INP and IMON_INN are given in the equations below:

⎛

IMON _ INP

IMON _ INN

⎜

= 1m

⎜ ⎝

⎛ ⎜

= –1m

⎜

•R

SENSE1

•R

SENSE1

The differential voltage V

•IIN + 20µA

CSPIN-CSNIN

⎞ ⎟

•R

IMON _ INP

⎟ ⎠

⎞ ⎟

•R

IMON _ INN

⎟

should remain between –100mV and 100mV due to the limited current that can be driven out of IMON_INP and IMON_INN. If the instantaneous V average V

CSPIN-CSNIN

exceeds these limits but the

is within the limits, consider includ-

ing the current sense filter described in the next section.

In addition, IMON_INP and IMON_INN should be filtered with capacitors C

IMON_INP

and C

IMON_INN

due to I

ripple

and discontinuities that can occur in various regions of operation. A few nF of capacitance is usually sufficient.

Current Limiting: As shown in Figure 15, IMON_INP voltage that exceeds 1.209V (typical) causes VC to reduce, thus limiting the forward IIN and inductor currents. IMON_INN voltage that exceeds 1.21V (typical) causes VC to increase, thus limiting the reverse IIN and inductor currents (see the Error Amplifiers section).

The forward IIN limit, I

(IN,FWD,LIMIT)

by choosing the appropriate R

, can be set as needed

and R

SENSE1

IMON_INP

resis-

tors using the following equation:

IMON _ INP

For example, if R

(IN,FWD,LIMIT)

SENSE1

•1m

1.209 A

•R

SENSE1

+ 20µA

Ω

is chosen to be 12.5mΩ and the

desired forward IIN current limit is 4A then:

IMON _ INP

4A •1m

1.209

•12.5mΩ + 20µA

= 17.3kΩ

Similarly, the reverse IIN limit, I needed by choosing the appropriate R

(IN,RVS,LIMIT)

SENSE1

, can be set as

and R

IMON_INN

resistors using the following equation:

IMON _ INN

IMON_INP

(IN,RVS,LIMIT)

and C

IMON_INN

•1m

1.21 A

•R

ESENSE1

+ 20µA

Ω

capacitors of at least a few nF are necessary to maintain loop stability when IMON_INP and IMON_INN, respectively, are used to operate the LT8708 at constant current limit.

Review the Electrical Characteristics and the IMON Output Currents graph in the Typical Performance Characteristics section to understand the operational limits of the IMON_OP, IMON_ON, IMON_INP and IMON_INN currents.

External currents can be summed to the IMON pins to adjust IIN and/or I

limit in both directions while switch-

OUT

ing. When the IMON_OP and IMON_ON pins are used in

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LT8708

APPLICATIONS INFORMATION

this way, ICP and ICN can be used to monitor the I

OUT

current in the forward and reverse directions respectively (see the Current Monitoring, Regulation and Limiting: ICP and ICN Pins section).

Current Sense Filter: The + and – outputs of current sense amplifiers A1 and A3 are rated to provide a range of –20μA to +100μA. For example, IMON_INP, which primarily reports forward IIN current, may not provide the expected output current when V

CSPIN-CSNIN

exceeds 100mV. In addition, the IMON_INP pin will not provide the expected output current when V

CSPIN-CSNIN

is below –20mV.

Currents that flow through the current sense resistors (R

SENSE1

, R

in Figure 17) are often discontinu-

SENSE2

ous and can contain significant AC content during each switching cycle. One example is the forward IIN in the buck region. If the IIN current presents an average differential (V

CSPIN-CSNIN

) less than 100mV, but contains AC peaks exceeding 100mV, the IMON_INP current may clip. To prevent clipping, the current sense filter shown in Figure 17, can be added. The filter will reduce the peak differential (V

CSPIN-CSNIN

) to <100mV while keeping the same average, thus allowing the correct result to be presented on IMON_INP. As another example, consider the reverse I

measured by IMON_ON. If the current presents an

OUT

average differential (V

CSNOUT-CSPOUT

) less than 100mV, but contains AC peaks exceeding 100mV, the current sense filter can be used to reduce the peaks below 100mV while keeping the same average.

The –20μA output current limits for amplifiers A1 and A3 are often most important when using the HCM mode (see the Unidirectional Conduction: HCM section). The current

SENSE1

FILTER1

CSPIN CSNIN

LT8708

SENSE2

FILTER2

CSPOUT CSNOUT

LT8708

sense amplifier outputs may clip at the –20μA limits when the average sensed current is low but contains high AC content. Clipping may distort the ICN or IMON_INP voltages that are used to select between heavy and light load HCM operation. Once again, the current sense filter can be used to reduce the AC content appearing at the amplifier inputs.

Current sense filter(s) should be connected as shown in Figure 16. Note that resistance in series with CSNIN and CSNOUT is not recommended. As described in the Topside MOSFET Driver Supply (CB1,DB1,CB2,DB2) section, the CSNIN and CSNOUT pins are also connected to the Boost Cap Charge Control block (also see Figure 1) and can draw current under certain conditions. In addition, the same CSNIN and CSNOUT current sense pins can draw bias current under normal operating conditions, while CSPIN and CSPOUT draw zero (typical) bias current. A time constant lower than 10μs is recommended for the filter(s).

Also, because of their use with the Boost Cap Charge Control block, tie the CSPIN and CSNIN pins to VIN and tie the IMON_INP and IMON_INN pins to ground when the input current sensing is not in use. Similarly, the CSPOUT and CSNOUT pins should be tied to V

, the IMON_OP,

OUT

IMON_ON pins should be grounded when not in use.

LOOP COMPENSATION

The loop stability is affected by a number of factors including the inductor value, output capacitance, load current, VIN, V

and the VC resistor and capacitors. The LT8708

OUT

uses internal transconductance error amplifiers driving VC to help compensate the control loop. For most applications a 3.3nF series capacitor at VC is a good value. The parallel capacitor (from VC to GND) is typically 1/10th the value of the series capacitor to filter high frequency noise. A larger VC series capacitor value may be necessary if the output capacitance is reduced. A good starting value for the VC series resistor is 20k. Lower resistance will improve stability but will slow the loop response. Use a trim pot instead of a fixed resistor for initial bench evaluation to determine the optimum value.

Figure 17. CSPIN/CSNIN and CSPOUT/CSNOUT Current Sense Filter

8708 F17

Also note that C least a few nF are necessary to maintain loop stability

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IMON_INP

and C

IMON_INN

capacitors of at

Rev 0

APPLICATIONS INFORMATION

LT8708

when IMON_INP and IMON_INN, respectively, are used to operate the LT8708 at constant current limit.

INTVCC REGULATORS AND EXTVCC CONNECTION

The LT8708 features two PNP LDOs (low dropout regulators) that regulate the 6.35V (typical) INTVCC pin from either the V

or EXTVCC supply pin. INTVCC powers

INCHIP

the MOSFET gate drivers via the required GATEVCC connection and also powers the LDO33 pin regulator and much of the LT8708’s internal control circuitry. The INTVCC LDO selection is determined automatically by the EXTV

pin voltage. When EXTVCC is lower than 6.2V (typical), INTVCC is regulated from the V above 6.4V (typical), INTVCC is regulated by the EXTV

pin LDO. After EXTVCC rises

INCHIP

pin LDO instead.

Overcurrent protection circuitry typically limits the maximum current draw from either LDO to 127mA. When GATEVCC and INTVCC are below 4.65V, during start-up or during an overload condition, the typical current limit is reduced to 42mA. The INTVCC pin must be bypassed to ground with a minimum 4.7μF ceramic capacitor placed as close as possible to the INTVCC and GND pins. An additional ceramic capacitor should be placed as close as possible to the GATEVCC and GND pins to provide good bypassing to supply the high transient current required by the MOSFET gate drivers. 1μF to 4.7μF is recommended.

Power dissipated in the INTVCC LDOs must be minimized to improve efficiency and prevent overheating of the LT8708. Since LDO power dissipation is proportional to the supply voltage and V

can be as high as 80V in some applica-

INCHIP

tions, the EXTVCC pin is available to regulate INTVCC from a lower supply voltage. The EXTVCC pin is connected to V

in many applications since V

OUT

a much lower voltage than the maximum V

is often regulated to

OUT

. During

INCHIP

start-up, power for the MOSFET drivers, control circuits and the LDO33 pin is usually derived from V V

/EXTVCC rises above 6.4V, after which the power is

OUT

derived from V in a case where V V

voltage is 40V. EXTVCC can be floated or grounded

INCHIP

/EXTVCC. This works well, for example,

OUT

is regulated to 12V and the maximum

OUT

INCHIP

until

when not in use or can also be connected to an external power supply if available.

The following list summarizes the three possible connections for EXTVCC:

1. EXTVCC left open (or grounded). This will cause INTV to be powered from V

through the internal 6.3V

INCHIP

regulator at the cost of a small efficiency penalty.

2. EXTVCC connected directly to V

OUT

> 6.4V). This is the normal connection for the regulator and usually provides the highest efficiency.

3. EXTVCC connected to an external supply. If an external supply is available greater than 6.4V (typical) it may be used to power EXTVCC.

Powering INTVCC from EXTVCC can also provide enough gate drive when V the part to operate with a reduced V V

gets into regulation.

OUT

drops as low as 2.8V. This allows

INCHIP

voltage after

INCHIP

The maximum current drawn through the INTVCC LDO occurs under the following conditions:

1. Large (capacitive) MOSFETs are being driven at high frequencies.

2. VIN and/or V

is high, thus requiring more charge

OUT

to turn the MOSFET gates on and off.

3. The LDO33 pin output current is high.

4. In some applications, LDO current draw is maximum when the part is operating in the buck-boost region where VIN is close to V

since all four MOSFETs are

OUT

switching.

To check for overheating find the operating conditions that consume the most power in the LT8708 (P

LT8708

). This will often be under the same conditions just listed that maximize LDO current. Under these conditions monitor the CLKOUT pin duty cycle to measure the approximate die temperature. See the Junction Temperature Measurement section for more information.

LDO33 REGULATOR

The LT8708 includes a low dropout regulator (LDO) to regulate the LDO33 pin to 3.3V. This pin can be used to power external circuitry such as a microcontroller or other desired peripherals. The input supply for the LDO33 pin

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LT8708

1.181

– 34.4%

0.325%

APPLICATIONS INFORMATION

regulator is INTVCC. Therefore INTVCC must have sufficient voltage, typically > 4.0V, to properly regulate LDO33. The LDO33 and INTVCC regulators are enabled by the SHDN pin and are not affected by SWEN. The LDO33 pin regulator has overcurrent protection circuitry that typically limits the output current to 17.25mA. An undervoltage lockout monitors LDO33 and disables switching activity when LDO33 falls below 3.04V (typical). LDO33 should be bypassed locally with 0.1μF or more.

VOLTAGE LOCKOUTS

The LT8708 contains several voltage detectors to make sure the chip is under proper operating conditions. Table 8 summarizes the pins that are monitored and also indicates the state that the LT8708 will enter if an under or over voltage condition is detected.

Table 8. Voltage Lockout Conditions

APPROXIMATE

VOLTAGE

PIN(S)

INCHIP

SHDN <1.18V

INTVCC and

GATEV

LDO33 <3.04V

VINHIMON >1.207V

VOUTLOMON <1.207V

RVSOFF <1.209V

FBIN <1.205V Voltage Lockouts

CONDITION

<2.5V

<4.65V

CHIP STATE

(Figure 2) READ SECTION

CHIP OFF

SWITCHER

OFF 1SWEN <1.18V

–

Operation: Start-Up

Applications

Information:

VINHIMON,

VOUTLOMON and

RVSOFF

The conditions are listed in order of priority from top to bottom. If multiple over/undervoltage conditions are detected, the chip will enter the state listed highest on the table.

Due to their accurate thresholds, configurable undervoltage lockouts (UVLOs) can be implemented using the SHDN and SWEN and in some cases, FBIN pin. The UVLO function sets the turn on/off of the LT8708 at a desired minimum voltage. For example, a resistor divider can be connected between VIN, SHDN and GND as shown in Figure 1. From the Electrical Characteristics, SHDN has typical rising and

falling thresholds of 1.221V and 1.181V, respectively. The falling threshold for turning-off switching activity can be chosen using:

SHDN1

For example, choosing R

SHDN2

•(V

(IN,CHIPOFF,FALLING)

1.181

SHDN2

– 1.181)

Ω

= 20k and a falling V

threshold of 5.42V results in:

SHDN1

20k • (5.42 –1.181)

1.181

≅ 71.5kΩ

The rising threshold for enabling switching activity wouldbe:

(IN,CHIPOFF,RISING)

= V

(IN,CHIPOFF,FALLING)

1.221

•

or 5.6V in this example.

Similar calculations can be used to select a resistor divider connected to SWEN that would stop switching activity during an undervoltage condition. Make sure that the divider doesn’t cause SWEN to exceed 7V (ABSMAX rating) under maximum supply voltage conditions. See the Start-Up: SWEN Pin section for additional information.

The same technique described in the VIN: Regulation section can be used to create an undervoltage lockout if the LT8708 is in forward non-CCM mode, where forcing VC low will stop all switching activity. Note that this does not reset the soft-start function, therefore resumption of switching activity will not be accompanied by a soft-start.

JUNCTION TEMPERATURE MEASUREMENT

The duty cycle of the CLKOUT signal is linearly proportional to the die junction temperature, TJ. Measure the duty cycle of the CLKOUT signal and use the following equation to approximate the junction temperature:

TJ≅

CLKOUT

°C

Rev 0

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APPLICATIONS INFORMATION

LT8708

where DC is the die junction temperature in °C. The actual die temperature can deviate from the above equation by ±10°C.

THERMAL SHUTDOWN

If the die junction temperature reaches approximately 165°C, the part will go into thermal shutdown. The power switches will be turned off and the INTVCC and LDO33 regulators will be turned off (see Figure 2). The part will be re-enabled when the die temperature has dropped by ~5°C (nominal). After re-enabling, the part will start in the SWITCHER OFF 1 state as shown in Figure 2. The part will then INITIALIZE, perform a SOFT-START, then enter NORMAL OPERATION as long as the die temperature remains below approximately 165°C.

EFFICIENCY CONSIDERATIONS

The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, three main sources account for most of the losses in LT8708 circuits. These and a few additional loss components are listed below:

is the CLKOUT duty cycle in % and T

CLKOUT

from a high efficiency source, such as the output or alternate supply if available. Also, lower capacitance MOSFETs can reduce INTVCC current and power loss.

4. CIN and C

of filtering the large RMS input current to the regulator in buck mode. The C job of filtering the large RMS output current in boost mode. Both CIN and C ESR to minimize the AC I2R loss and have sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries.

5. Other losses. Schottky diodes D1, D2, D3 and D4 are

responsible for conduction losses during dead time and light load conduction periods. Inductor core loss occurs predominately at light loads.

Hybrid conduction mode (HCM) can be used to improve the efficiency when large inductor current ripples are present in DCM. See the Unidirectional Conduction: HCM section for details.

When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If one makes a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency.

loss. The CIN capacitor has the difficult job

OUT

capacitor has the more difficult

OUT

are required to have low

OUT

1. Switching losses. These losses arise from the brief amount of time the switches (M1 – M4) spend in the saturated region during switch node transitions. Power loss depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. See the Power MOSFET Selection section for more details.

2. DC I2R losses. These arise from the resistances of the MOSFETs (M1 – M4), sensing resistors, inductor and PC board traces and cause the efficiency to drop at high currents.

3. INTVCC current. This is the sum of the MOSFET driver current, LDO33 pin current and control currents. The INTVCC regulator’s input voltage times the current represents lost power. This loss can be reduced by supplying INTVCC current through the EXTVCC pin

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CIRCUIT BOARD LAYOUT CHECKLIST

The basic circuit board layout requires a dedicated ground plane layer. Also, for high current, a multilayer board provides heat sinking for power components.

• The ground plane layer should not have any traces and should be as close as possible to the layer with the power MOSFETs.

• The high di/dt path formed by switch M1, switch M2, D1, R with short leads and PC trace lengths. The high di/ dt path formed by switch M3, switch M4, D2 and the C

OUT

leads and PC trace lengths. Two layout examples are shown in Figure 18 (a) and (b).

and the CIN capacitor should be compact

SENSE

capacitor also should be compact with short

Rev 0

LT8708

APPLICATIONS INFORMATION

M1 M2

SW1 SW2

SENSE

LT8708

CKT

18(a)

D4D2D1 D3

M3 M4

OUT

GND

OUT

Figure 18. Switches Layout

• Avoid running signal traces parallel to the traces that carry high di/dt current because they can receive inductively coupled voltage noise. This includes the SW1, SW2, TG1 and TG2 traces to the controller.

• Use immediate vias to connect the components (including the LT8708’s GND pins) to the ground plane. Use several vias for each power component.

• Minimize parasitic SW pin capacitance by removing GND, VIN and V

copper from underneath the SW1

OUT

and SW2 regions.

• Except under the SW pin regions, flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to a DC net (i.e., quiet GND) with many vias. The more vias the board has, the better heat conduction it has.

• Partition the power ground from the signal ground. The small-signal component grounds should not return to the IC GND through the power ground path.

• Place switch M2 and switch M3 as close to the controller as possible, keeping the GND, BG and SW tracesshort.

OUT

GND

8708 F18

SW1 SW2

M3M2

SENSE

LT8708

CKT

18(b)

• Minimize inductance from the sources of M2 and M3 to R

by making the trace short and wide.

SENSE

• Keep the high dv/dt nodes SW1, SW2, BOOST1, BOOST2, TG1 and TG2 away from sensitive smallsignal nodes.

• The output capacitor (–) terminals should be connected as closely as possible to the (–) terminals of the input capacitor.

• Connect the top driver boost capacitor CB1 closely to the BOOST1 and SW1 pins. Connect the top driver boost capacitor CB2 closely to the BOOST2 and SW2pins.

• Connect the CIN and C

capacitors closely to the

OUT

power MOSFETs. These capacitors carry the MOSFET AC current in the boost and buck regions.

• Connect the FBOUT, FBIN, VINHIMON and VOUTLOMON pin resistor dividers to the (+) terminals of C

OUT

and CIN, respectively. Small FBOUT/FBIN/VINHIMON/ VOUTLOMON bypass capacitors may be connected closely to the LT8708’s GND pin if needed. The resistor connections should not be along the high current or noise paths.

• Route current sense traces (CSP/CSN, CSPIN/CSNIN, CSPOUT/CSNOUT) together with minimum PC trace

Rev 0

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LT8708

spacing. Avoid having sense lines pass through noisy areas, such as switch nodes. The optional filter network capacitor between CSP and CSN should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the R

SENSE

resistors.

• Connect the VC pin compensation network closely to the IC, between VC and the signal ground pins. The capacitor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensationloop.

• Connect the INTVCC and GATEVCC bypass capacitors close to the IC. The capacitors carry the MOSFET drivers’ current peaks.

• Run the trace from the LT8708’s SW1/SW2 pin to the drain of M2/M3 in parallel with the trace from the GATEVCC capacitor’s GND to the CIN GND. Route the traces (as much as possible) directly above/below one another on adjacent layers and in such a way that they carry currents in opposite directions.

• Attention is required when making the PCB layout for R

SENSE1

and R

, especially for sense resistor

SENSE2

values smaller than 5mΩ. Improper PCB layout can yield significant errors in the sense voltage.

HOT PLUGGING CONSIDERATIONS

When connecting a battery to an LT8708 application, there can be significant inrush current due to charge equalization between the partially charged battery stack and the charger output capacitors. To a lesser extent a similar effect can occur when connecting a powered DC supply to the input or output. The magnitude of the inrush current depends on (1) the battery or supply voltage, (2) ESR of the input or output capacitors, (3) initial voltage of the capacitors, and (4) cable impedance. Excessive inrush current can lead to sparking that can compromise connector integrity and/ or voltage overshoot that can cause electrical overstress on LT8708 pins.

Excessive inrush current can be mitigated by first connecting the battery or supply to the charger through a resistive path, followed quickly by a short circuit. This can be accomplished using staggered length pins in a

multi-pin connector. Alternatively, consider the use of a Hot Swap controller such as the LT1641, LT4256, etc. to make a current limited connection.

DESIGN EXAMPLE

VIN = 8V to 25V

OUT(MAX,FWD)

IN(MAX,RVS)

= 12V (VIN regulation voltage set by FBIN loop)

IN_FBIN

OUT_FBOUT

= 12V (V

regulation voltage set by FBOUT loop)

OUT

= 5A

= 3A

ƒ = 150kHz

This design operates in CCM.

Maximum ambient temperature = 60°C

Power Flow Verification: Determine which conditions in Table 6(a) apply to this application. In this design example, the VINHIMON and VOUTLOMON are disabled, therefore the conditions highlighted in blue in the copy of Table 6(a) apply to this application.

Table 9. A Copy of Table 6(a)

OUT

OUT_VOUTLOMON

< V

OUT

OUT_FBOUT

B B

OUT

OUT_FBOUT

No Power

Transfer

VIN < V

VIN > V

VIN <

IN_VINHIMON

VIN >

IN_VINHIMON

IN_FBIN

OUT_VOUTLOMON

OUT

No Power

Transfer

A D C

A D

Next, check each of these highlighted cells using Table 6(b) with MODE = CCM. A copy of Table 6(b) is shown below:

9(b). A Copy of Table 6(b)

MODE =

BURST MODE = CCM

A Power Flows from VIN to V

No Power

Flow

D Power Flows from VIN to V

Power Flows

from V

OUT

to V

DCM/HCM, DIR = FWD

OUT

No Power

Flow

OUT

MODE = DCM/

HCM, DIR = RVS

No Power Flow

Power Flows

from V

No Power Flow

OUT

to VIN

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Rev 0

LT8708

OSC

⎝

⎠

⎝

⎠

= 200ns • 150kHz • 100% = 3%

∆I

≅

APPLICATIONS INFORMATION

Verify expected operation by combining Table 6(a) and Table 6(b):

• When VIN < V

B – power is transferred from V

• When VIN < V

B – power is transferred from V

• When VIN > V

C – power is transferred from V

• When VIN > V

D – power is transferred from VIN to V

(12V) and V

IN_FBIN

(12V) and V

IN_FBIN

(12V) and V

IN_FBIN

(12V) and VOUT < V

IN_FBIN

OUT

> V

OUT_FBOUT

OUT

< V

OUT_FBOUT

OUT

> V

OUT_FBOUT

OUT

OUT_FBOUT

to V

OUT

(12V)

The results above are as expected for this design example.

RT Selection: Choose the RT resistor for the free-running oscillator frequency using:

⎛

43,750

⎜

RT=

⎜

– 1

⎞ ⎟ ⎟

⎟

kΩ =

⎛

43,750

⎜ ⎜

150

⎞ ⎟

– 1

= 290.7kΩ

⎟

We will choose 294k for RT resistor.

Selection: Start by calculating the maximum and

SENSE

minimum duty cycle in the boost region:

RSENSE(MIN,BOOST,MINDC)

≅ 93mV

Next, estimate the inductor current ripples at maximum and minimum boost duty cycles:

L(MAX,BOOST)

OUT(MAX,BOOST)•IOUT(MAX,FWD)



IN(MIN,BOOST)

∆I

L(MIN,BOOST)

100%

•

 

%Ripple

8V •

IN(MAX,RVS)

≅

100%





10%



100%

 



12V • 5A

100%

 



10%

40%

– 0.5

 



– 0.5

 



 



=3.75A

 



=0.32A

Now calculate the maximum R

values in the boost

SENSE

region:

(MAX,M3,BOOST)

⎛

⎜

1–

⎜ ⎜

OUT(MAX,BOOST)

⎝

⎛ ⎜

= 1–

⎜

12V

⎝

(ABSMIN,M3,BOOST)

≅

IN(MIN,BOOST)

⎞

⎟

•100% = 33%

⎟ ⎠

≅ t

⎞ ⎟

•100%

⎟ ⎟ ⎠

ON(M3,MIN)

• ƒ • 100%

Next, from the Maximum Inductor Current Sense Voltage vs Duty Cycle graph in the Typical Performance Characteristics section:

RSENSE(MAX,BOOST,MAXDC)

≅ 83mV

Rev 0

For more information www.analog.com

∆I

≅

APPLICATIONS INFORMATION

LT8708

SENSE(MAX,BOOST,FWD)

2 • V

RSEN SE(M AX,BOOST,MAXDC)

2 •I

( )

OUT(MAX,FWD)

2 • 5A •12V

( )

SENSE(MAX,BOOST,RVS)

2• | V

2• |I

( )

2 • 3A

( )

• V

OUT(MAX,BOOST)

2 • 83m V • 8V

+ 3.75A • 8V

( )

RSENSE(MIN,BOOST,MINDC)

IN(MAX,RVS)

2 • 93m V

– 0.32A

– ∆I

= 32.7mΩ

L(MIN,BOOST)

• V

IN(MIN ,BOOST)

+ ∆I

( )

L(MAX,BOOST)

= 8.85mΩ

Ω

• V

IN(MIN ,BOOST)

Ω

Next, calculate the maximum and minimum duty cycle in the buck region:

(ABSMIN,M2,BUCK )

= 200ns • 150kHz •100% = 3%

(MAX,M2,BUCK)

⎛

⎜

OUT(MIN,BUCK)

1–

⎜ ⎜

⎝

= 1–

IN(MAX,BUCK)

⎛

12V

⎜ ⎜

25V

⎝

≅ t

ON(M2,MIN)

≅

⎞ ⎟ ⎟ ⎟ ⎠

⎞ ⎟

•100% = 52%

⎟ ⎠

• ƒ • 100%

•100%

Next, from the Maximum Inductor Current Sense Voltage vs Duty Cycle graph in the Typical Performance Characteristics section:

RSENSE(MAX,BUCK,MINDC)

RSENSE(MIN,BUCK,MAXDC)

Next, estimate the inductor current ripples at maximum and minimum buck duty cycles:

≅ 82mV

≅ 65mV

L(MIN,BUCK)

OUT(MAX,FWD)



100%

 

– 0.5

10%

A =

 





100%



10%



= 0.526A

∆I

L(MAX,BUCK)

OUT(MIN,BUCK)

12V •

Now calculate the maximum R

≅

IN(MAX,BUCK)•IIN(MAX,RVS)



100%

•



%Ripple



25V • 3A



100%



40%



– 0.5

= 3.125A

 



SENSE

region:

SENSE(MAX,BUCK,FWD)

2 • V

RSENSE(MAX,BUCK,MINDC)

2 •I

( )

OUT(MAX,FWD)

2 • 82mV

SENSE(MAX,BUCK,RVS)

2• |I

( )

2 • 3A • 25V

( )

– 0.53A

2 • 5A

( )

2• | V

IN(MAX,RVS)

2 • 65mV • 12V

– ∆I

L(MIN,BUCK)

= 17.3mΩ

RSEN SE(M IN,BUCK,MAXDC)

| •V

IN(MAX,BUCK)

+ 3.125A • 12V

( )

Choose the smallest calculated R ditional 30% margin, choose R

Ω

| •V

+ ∆I

( )

L(MAX,BUCK)

= 8.3mΩ

SENSE

6.3mΩ



– 0.5

 



– 0.5

 

values in the boost

OUT(MIN,BUCK)

• V

OUT(MIN,BUCK)

and add an ad-

to be 8.3mΩ/1.3 =

Ω

Rev 0

For more information www.analog.com

LT8708

(MIN2,BOOST)

OUT(MAX,BOOST)

–

IN(MIN,BOOST)

• V

OUT(MAX,BOOST)

– V

IN(MIN,BOOST)





 







 







  





  

•R

SENS

0.08 • ƒ

12V –

8V • 12V

12V – 8V





 





 





 







 



• 6.3mΩ

0.08 •150kHz

= –6.3µH

(MIN1,BUCK)

IN(MAX,BUCK)

1–

OUT(MAX,BUCK)

IN(MAX,BUCK)

– V

OUT(MIN,BUCK)





  





  





  







  



•R

SENSE

0.08 • ƒ

= 25V • 1–

12V

25V – 12V





 





 





 







 



• 6.3mΩ

0.08 •150kHz

= 1.01µH

– T

PM1=P

13W

APPLICATIONS INFORMATION

Inductor Selection: With R

known, we can now

SENSE

determine the minimum inductor value that will provide adequate load current in the boost region using:

(MIN1,BOOST)

2 • ƒ •

≅

IN(MIN,BOOST)



RSEN SE(M AX,BOOST,MAXDC)

 

 

2 •150kHz •

SENSE

8V •

  

100%





83mV

 

6.3mΩ







•



 

OUT(MAX,BOOST)

–



33%

 



–

(MAX,M3,BOOST)

100%

IN(MIN ,BOOST)

   

5A • 12V

  

 

• V

OUT(MAX,BOOST)

= 1.55µH

  

 

To avoid subharmonic oscillations in the inductor current, choose the minimum inductance according to:

Select M1 and M2: With 25V maximum input voltage, MOSFETs with a rating of at least 30V are used. As we do not yet know the actual thermal resistance (circuit board design and airflow have a major impact) we assume that the MOSFET thermal resistance from junction to ambient is 50°C/W.

If we design for a maximum junction temperature, T

J(MAX)

= 125°C, the maximum allowable power dissipation can be calculated. First, calculate the maximum power dissipation:

(MAX )

J(MAX)

125°C –60°C

TH(JA)

°C

A(MAX)

= 1.3W

Since maximum I2R power in the boost region with positive inductor current happens when VIN is minimum, we can determine the maximum allowable R

for the boost

DS(ON)

region using (see Table 7):

≅

I2R

⎡

⎛

⎢

OUT

⎜

⎢

⎜

⎢

⎝

⎢

⎣

• I

OUT(MAX,FWD)

⎞ ⎟

• R

⎟

DS(ON)

⎟ ⎠

• ρ

⎤ ⎥ ⎥

⎥ ⎥

⎦

The inductance must be higher than all of the minimum values calculated above. We will choose a 10μH standard value inductor for improved margin.

MOSFET Selection: The MOSFETs are selected based on voltage rating, C ensure that the part is specified for operation with the available gate voltage amplitude. In this case, the amplitude is 6.3V and MOSFETs with an R VGS = 4.5V can be used.

OSS

and R

DS(ON)

value. It is important to

DS(ON)

value specified at

For more information www.analog.com

and therefore

DS(ON)





12V









•5

 

•1.5



=15.4mΩ

 



The Fairchild FDMS7672 meets the specifications with a maximum R

of ~6.9mΩ at V

DS(ON)

= 4.5V (~10mΩ at

125°C).

The maximum dissipation in M2 occurs at maximum V

voltage when the circuit is operating in the buck region in the reverse direction. Using the 6.9mΩ Fairchild FDMS7672, the dissipation is (see Table 7):

Rev 0

= 0.13W + 0.225W + 0.064W = 0.419W

= 0.06W + 0.38W + 0.064W = 0.504W

+ P

(

)

(

)

APPLICATIONS INFORMATION

LT8708

PM2≅ P

≅

+ V

+ 0.5 • C

(M2,MAX)

⎛ ⎜ ⎜ ⎝

+ 25V • 3A • 150kHz • 20ns

+ (0.5 • (685P + 685P) • 25V • 25V • 150k)

+ P

I2R

SWITCHING

⎛

– V

⎜ ⎜

⎜ ⎝

( )

(

OUT

• I

OUT(MAX,RVS)

• I

OSS(M1+M2)

OUT(MAX,RVS)

• ƒ • t

RF1

• V

• ƒ

• R

DS(ON)

)

• ρ

≅

25V – 12V

25V

• 3A

( )

• 6.9mΩ • 1.5

⎞ ⎟ ⎟ ⎠

( )

[ ]

⎞ ⎟

⎟

⎟ ⎠

To check the power dissipation in the buck region with VIN maximum and V

minimum, choose the equation

OUT

from Table 7 with positive inductor current in buck mode which yields:

PM1≅ P

≅

+ V

+ 0.5 • C

(M1,MAX)

⎡ ⎢ ⎢ ⎢ ⎣

+ 25V • 5A • 150k • 20ns

+ P

I2R

SWITCHING

⎡

⎛

⎢

OUT

⎜

⎢

⎜

⎢

⎝

⎢

⎣

( )

(

• I

OUT(MAX,FWD)

• I

OUT(MAX,FWD)

OSS(M1+M2)

• V

• ƒ • t

⎞ ⎟ ⎟

⎟ ⎠

RF1

• ƒ

• R

)

≅

⎛ ⎜ ⎜ ⎝

12V 25V

• 5A

⎞ ⎟

• 6.9mΩ • 1.5

⎟ ⎠

⎤ ⎥ ⎥ ⎥ ⎦

( )

DS(ON)

• ρ

⎤ ⎥ ⎥

⎥ ⎥

⎦

Select M3 and M4: With 12V output voltage we need MOSFETs with 20V or higher rating.

The highest dissipation of M3 and M4 occurs in the boost region. For switch M3, the max dissipation occurs when the I

is highest in the forward direction and VIN is at

OUT

the minimum 8V (see Table 7):

≅

I2R

SWITCHING

⎛

OUT

OSS(M3+M4)

– VIN) • V

• I

OUT(MAX,FWD)

OUT

• I

OUT(MAX,FWD)

• ƒ •

• V

OUT

• ƒ

RF2

• R

DS(ON)

⎞ ⎟ ⎟

⎟ ⎠

⎜

≅

⎜ ⎜

⎝

⎛ ⎜

+ V

⎜

⎜ ⎝

+ 0.5 • C

For switch M4, the max dissipation occurs when the I

• ρ

⎞ ⎟ ⎟

⎟ ⎠

highest in the reverse direction and VIN is highest in the boost region (see Table 7):

PM4≅ P

≅

+ V

+ 0.5 • C

+ P

I2R

SWITCHING

⎛

⎜

OUT

• I

IN(MAX,RVS)

OSS(M3+M4)

⎜

⎜ ⎝

( )

• ƒ • t

• V

OUT

• R

DS(ON)

RF2

• ƒ

• ρ

⎞ ⎟ ⎟

⎟ ⎠

and

IN(MAX,BOOST)

OUT(MAX,BOOST )

= 1– DC

(ABSMIN,M3,BOOST)

therefore,

+ (0.5 • (685P + 685P) • 25V • 25V • 150k)

[ ]

The maximum switching power of 0.38W can be reduced by choosing a slower switching frequency. Since this calculation is approximate, measure the actual rise and fall times on the PCB to obtain a better power estimate.

Rev 0

For more information www.analog.com

LT8708

1.207V

⎝

⎠

1.207V

⎝

⎠

∆V

= 12.5mV

∆V

= 25mV

APPLICATIONS INFORMATION

≅ P

⎡

= (1– DC

⎢ ⎣

+ V

( )

+ 0.5 • C

(

+ P

I2R

(ABSMIN,M3,BOOST)

• I

OUT

IN(MAX,RVS)

OSS(M3+M4)

SWITCHING

• ƒ • t

• V

OUT

) • I

IN(MAX,RVS)

RF2

• ƒ

• R

DS(ON)

)

• ρ

⎤ ⎥

⎦

The Fairchild FDMS7672 can also be used for M3 and M4. Assuming 20ns rise and fall times, the calculated power loss is then 0.48W for M3 and 0.21W for M4.

Select R

= 5A and I

, R

SENSE2

IN(MAX,RVS)

IMON_OP

and R

IMON_ON

: The I

= 3A, with a 20%margin, the I

OUT(MAX,FWD)

OUT

current limit is set to 6A in the forward and the IIN current limit is set to 3.6A in the reverse directions, respectively.

Choose R

IMON_OP

limit becomes 50mV, and the R

SENSE2

Using the equation given in the IIN and I toring and Limiting section, R

IMON _ ON

3.6A •1m

Voltage: V

OUT

20k. R

FBOUT1

to be 17.4k, so that the V

50mV

≅ 8mΩ

(OUT,RVS,LIMIT)

1.21

• 8mΩ + 20µA

voltage is 12V. Select R

OUT

is:

⎛

OUT

⎜

– 1

⎞ ⎟

•R

⎟

SENSE2

IMON_ON

1.21 A

•1m V

FBOUT2

CSPOUT-CSNOUT

is calculated to be:

Current Moni-

OUT

is calculated to be:

•R

SENSE2

= 24.9kΩ

+ 20µA

FBOUT2

Ω

Select R

as 178k. Both R

FBOUT1

and R

FBOUT2

should

have a tolerance of no more than 1%.

VIN Voltage: Input voltage is 12V. Select R R

is:

FBIN1

⎛

⎜

– 1

⎞ ⎟

•R

⎟

FBIN2

as 20k.

Select R

as 178k. Both R

FBIN1

and R

should have

FBIN2

a tolerance of no more than 1%.

Capacitors: A low ESR (5mΩ) capacitor network with 30μF ceramic capacitors for CIN is selected. In this mode, the maximum ripple is:

(BUCK,CAP)

OUT(MAX,FWD)

⎛ ⎜

1– exp

⎜ ⎜

⎝

≅ 5A •

⎛ ⎜

• 1– exp

⎜

⎜ ⎝

≅

OUT

⎛ ⎜ ⎜

⎜

VIN• ƒ •ESR

⎝

12V

• 5mΩ

•

•ESR

CERAM

– V

OUT

CERAM•CIN–CERAM

24V

⎛ ⎜ ⎜

⎜

24V • 150kHz • 5mΩ • 30µF

⎝

– 12V

•

⎞ ⎟ ⎟

⎟ ⎠

⎞

⎟

⎠

Having 5mΩ of ESR with 66μF ceramic capacitor for the C

network sets the maximum output voltage ripple at:

OUT

1– exp

⎛ ⎜ ⎜

⎜ ⎝

≅

•ESR

⎛ ⎜ ⎜

⎜

• ƒ •ESR

OUT

⎝

⎛ ⎜ ⎜

⎜

12V • 150kHz •5mΩ • 66µF

⎝

•

CERAM

– V

OUT

CERAM•COUT –CERAM

8V – 12V

⎞

⎟

⎠

⎞

⎟

⎠

(Boost,CAP)

OUT(MAX,FWD)

⎛ ⎜ ⎜

⎜ ⎝

≅ 5A • 5mΩ

• 1– exp

⎞ ⎟ ⎟

⎟ ⎠

Rev 0

For more information www.analog.com

TYPICAL APPLICATIONS

RVS (0V)

M5–M6: T2N7002AK, TOSHIBA

M1–M4: INFINEON BSC010N04LS

TO 16V

POWER FLOW

TO 16V

POWER FLOW

RVS (0V)

–

OUT3

OUT2

×2

OUT1

10V

TO DIODE

TO 16V

BATTERY

1Ω

0.22μF

1Ω2mΩ

100nF

100Ω

681k

154k

100k

133k

100k

20k

47nF

CSPOUT

CSNOUT

EXTV

VOUTLOMON

OUT

BAT2

2mΩ

4.7μF

FBOUT

INTV

12.1k

GATEV

3.3Ω

4.7μF

IMON_OP

23.7k

22nF

ICP

ICN

IMON_ON

17.4k

4.7nF

17.4k

4.7nF

CLKOUTSYNC

IMON_INP

IMON_INN

BOOST2

BOOST1

4.7nF

17.4k

4.7nF

17.4k

23.7k

22nF

8708 TA03a

120kHz

LT8708

BAT2

10V

–

154k

2mΩ

BAT1

2mΩ

CHARGING

LIMIT V

CURRENT TO 15A

Reverse Operation (DIR = 0V)Forward Operation (DIR = 3V)

93.1k

FBIN

27.4k

–

BAT1

10V

*SEE UNI AND BIDIRECTIONAL CONDUCTION SECTION FOR MORE DETAILS.D

TO 16V

LD033

100k

VOUTLOMON

PREVENT

BAT1

14.6V

CHARGE

100k

8708 TA03c

20k

10.5V

BELOW

BAT2

DISCHARGING

12.1k

GND BG2SW2 BOOST2 TG2

10Ω

3.3μH

1nF

10Ω

M2 M3

1Ω

LT8708

0.22μF

12V Bidirectional Dual Battery System with FHCM & RHCM

2mΩ

BAT1

TO DIODE

1Ω

IN2

IN1

1μF

IN3

×2

–

10V

TO 16V

BATTERY

TG1 BOOST1 SW1 BG1 CSP CSN

100nF

100Ω

665k

INCHIP

CSNIN

CSPIN

47nF

100k

DECISION LOGIC

POWER TRANFER

SHDN

93.1k

FBIN

VINHIMON

DIR

LD033

FWD (3V)

SWEN

LD033

27.4k

LDO33

100k

12.1k

100k

SSRT

CMODE

RVSOFF

365k 1μF

680pF 10nF

10k

54.9k

4.7μF

127k

XOR

68.1k

220pF

: 220μF, 50V

: 22µF, 50V, X7R

: 10µF, 50V, X7R

OUT3

OUT2

OUT1

, C

IN3

IN1

IN2

: CENTRAL SEMI CMMR1U-02-LTE

, D

L1: 3.3μH, WURTH 701014330

XOR: DIODES INC. 74AHC1G86SE-7

BAT2

10V

–

133k

8708 TA03b

12.1k

FBOUT

BAT2

CHARGING

LIMIT V

CURRENT TO 15A

BAT2

CHARGE

14.5V

BELOW 10.5V

BAT1

PREVENT

DISCHARGING

2mΩ 2mΩ

FBIN

93.1k

–

BAT1

10V

12.1k

Rev 0

For more information www.analog.com

LT8708

BAT2

OUT

CHARGING TIME (HOURS)

0510

1011121314

0361013

(V)

OUT

(A)

BAT2

8708 TA03g

BAT1

IINCHARGING TIME (HOURS)

0510151011121314

0361013

BAT1

(V)

(A)

BAT1

8708 TA03h

200ms/DIV

8708 TA03d

DIR

5V/DIV

25A/DIV

OUT

25A/DIV

200ms/DIV

8708 TA03e

DIR

5V/DIV

25A/DIV

OUT

25A/DIV

200ms/DIV

8708 TA03f

DIR

5V/DIV

25A/DIV

OUT

25A/DIV

APPLICATIONS INFORMATION

12V Bidirectional Dual Battery System with FHCM & RHCM Details

Charge Voltage = 14.6V (FBIN in RHCM) V

BAT1

Charge Voltage = 14.5V (FBOUT in FHCM) V

BAT2

BAT1_DEAD

BAT2_DEAD

BAT1_UV

= 9V (Falling) or 9.4V (Rising) V

= 9.25V (Falling) or 9.4V (Rising) Frequency = 120kHz

to Stop Discharging = 10.5V (FBIN in FHCM)

Table of Operation Modes and Power Flow Directions

CONDITIONS RESULTS

BAT1

BAT1_DEAD

– <V

BAT1_UV

BAT1_DEAD

>14.6V >V

BAT1_DEAD

and <14.6V >V

*For use with LT8708-1(s)

BAT2_DEAD

>14.5V

BAT2_DEAD

BAT2

–

and <14.5V

and <V

BAT2_UV

to Stop Discharging = 10.5V (VOUTLOMON Falling) or 11.7V (VOUTLOMON Rising)

BAT2_UV

Charging Current Limit = 15A (IMON_INN)

BAT1

Charging Current Limit = 15A (IMON_OP)

BAT2

DIR POWER FLOW CHIP OPERATES IN RVSOFF*

–

No Power Flow

Hi FHCM

Power Flows from V

BAT2

No Power Flow

Power Flows from V

BAT1

Charging)

BAT2

Charging)

to V

BAT2

BAT1

Shutdown

No Switching

–

RHCM

Direction Change with V

= 13.5V and V

BAT1

BAT2

Charging Lead Acid Battery V

BAT1

= 13.5V

Direction Change with V

= 13.5V and V

BAT1

BAT2

For more information www.analog.com

BAT2

= 16V

Direction Change with V

= 16V and V

BAT1

Charging Lead Acid Battery V

BAT2

BAT1

= 13.5V

Rev 0

APPLICATIONS INFORMATION

RVS (0V)

M5–M7: T2N7002AK, TOSHIBA

TO 16V

POWER FLOW

TO 16V

POWER FLOW

RVS (0V)

–

OUT3

OUT2

OUT1

10V

TO 16V

TO DIODE

(MAX

LOAD

DUMP

681k

93.1k

178k

133k

100k

12.1k

CSPOUT

CSNOUT

36V FOR

BATTERY

1μF

1Ω

0.22μF

1Ω

4.7μF

FBOUT

EXTV

VOUTLOMON

12.1k

INTV

GATEV

3.3Ω

4.7μF

ICN

IMON_OP

IMON_ON

23.7k

4.7nF

17.4k

ICP

IMON_INP

10nF

OUT

BAT2

2mΩ

BOOST2

BOOST1

4.7nF

13.3k

10nF

17.4k

4.7nF

30.1k

10nF

8708 TA04a

CLKOUTSYNC

IMON_INN

120kHz

LT8708

BAT2

10V

–

93.1k

2mΩ

BAT1

5mΩ

CHARGING

LIMIT V

CURRENT TO 4A

CHARGE

Reverse Operation (DIR = 0V)Forward Operation (DIR = 3V)

340k

FBIN

16.9k

–

BAT1

24V

*SEE UNI AND BIDIRECTIONAL CONDUCTION SECTION FOR MORE DETAILS.D

TO 55V

LD033

17.8k

VOUTLOMON

PREVENT

TO 48V

BAT1

100k

8708 TA04c

12.1k

10.5V

BELOW

BAT2

DISCHARGING

18.2k

1.5mΩ

GND BG2SW2 BOOST2 TG2

10Ω

1nF

10μH

10Ω

M2 M3

3.3nF

1Ω

LT8708

0.22μF

TO DIODE

48V to 12V Bidirectional Dual Battery System with FHCM & RHCM

1Ω

IN2

TG1 BOOST1 SW1 BG1 CSP CSN

CSNIN

CSPIN

INCHIP

SHDN

FBIN

VINHIMON

DIR

SWEN

5mΩ

IN1

1μF

340k

20k

340k

IN3

BAT1

24V

TO 55V

BATTERY

–

DECISION LOGIC

POWER TRANFER

LD033

FWD (3V)

LDO33

LD033

16.9k

100k

RVSOFF

18.2k

SSRT

CMODE

127k

12.1k

365k 1μF

5.6nF

220pF

54.9k

4.7μF

XOR

220pF

68.1k

: 10µF, 100V, X7R

OUT1

, C

IN2

, C

OUT2

: 330μF, 40V

: 220μF, 100V

, C

IN3

OUT3

IN1

M3–M4: INFINEON BSC010N04LS

: CENTRAL SEMI CMMR1U-02-LTE

, D

L1: 10μH, SER2918H-103KL

XOR: DIODES INC. 74AHC1G86SE-7

M1–M2: INFINEON BSC026N08NS5

BAT2

10V

–

133k

8708 TA04b

12.1k

FBOUT

BAT2

CHARGING

LIMIT V

CURRENT TO 15A

BAT2

CHARGE

14.5V

BELOW 24V

BAT1

PREVENT

DISCHARGING

5mΩ 2mΩ

FBIN

340k

–

BAT1

24V

18.2k

Rev 0

For more information www.analog.com

LT8708

30ms/DIV

8708 TA04d

20A/DIV

10A/DIV

20A/DIV

30ms/DIV

8708 TA04e

20A/DIV

10A/DIV

20A/DIV

30ms/DIV

8708 TA04f

CHARGIN V

BAT2

CHARGING V

BAT1

VBAT1 (V)

VBAT2 (V)

1020304050

8588919497

100

EFFICIENCY (%)

EFFICIENCY

8708 TA04g

BAT2

OUT

CHARGING TIME (HOURS)

0510151011121314

0361013

BAT2

(V)

OUT

(A)

BAT2

8708 TA04h

APPLICATIONS INFORMATION

48V to 14V Bidirectional Dual Battery System with FHCM & RHCM Details

Charge Voltage = 48V (FBIN in RHCM) V

BAT1

Charge Voltage = 14.5V (FBOUT in FHCM) V

BAT2

BAT1_DEAD

BAT2_DEAD

= 21.3V (Falling) or 22.2V (Rising) V

= 9.25V (Falling) or 9.4V (Rising) Frequency = 120kHz

Table of Operation Modes and Power Flow Directions

CONDITIONS RESULTS

BAT1

BAT1_DEAD

– <V

BAT1_UV

BAT1_DEAD

>48V >V

BAT1_DEAD

and <48V >V

*For use with LT8708-1(s)

BAT2_DEAD

> V

BAT2_DEAD

>14.5V

BAT2_DEAD

BAT2_UV

BAT2

–

and <14.5V

and <V

BAT2_UV

to Stop Discharging = 10.5V (VOUTLOMON Falling) or 12.3V (VOUTLOMON Rising)

BAT2_UV

Charging Current Limit = 4A (IMON_INN)

BAT1

Charging Current Limit = 15A (IMON_OP)

BAT2

DIR POWER FLOW CHIP OPERATES IN RVSOFF*

–

No Power Flow

Hi FHCM

Power Flows from V

Charging)

BAT2

BAT1

to V

No Power Flow

Power Flows from V

Charging)

BAT1

BAT2

to V

BAT2

BAT1

Shutdown

No Switching

–

RHCM

Direction Change with V

= 47.5V and V

BAT1

DIR

5V/DIV

OUT

Direction Change with

BAT2

= 14V

DIR

5V/DIV

OUT

= 55V and V

BAT1

BAT2

= 14V

Efficiency V

Direction Change with V

= 47.5V and V

BAT1

DIR

5V/DIV

20A/DIV

5A/DIV

OUT

20A/DIV

Charging Lead Acid Battery V

BAT1

BAT2

= 36V

Rev 0

For more information www.analog.com

APPLICATIONS INFORMATION

VOLTAGE:

OUT3

52V

TO LOADS

TO 52.1V

52V

52V LOADS

TO 52.1V

47.4V LOADS

BAT

CHARGE

52.1V

–

OUT3

OUT2

1μF

10mΩ

OUT1

TO DIODE

2Ω

0.22μF

2Ω5mΩ

294k

422k

10k

CSPOUT

CSNOUT

INCHIP

SHDN

4.7μF

FBOUT

INTV

10k

GATEV

4Ω

4.7μF

IMON_OP

IMON_ON

17.4k

ICN

22nF

17.4k

6.8nF

ICP

IMON_INP

BOOST2

BOOST1

6.8nF

17.4k

6.8nF

26.7k

22nF

8708 TA05a

CLKOUTSYNC

IMON_INN

150kHz

: 4.7µF, 100V, X7R

OUT2

C ,

OUT1

, C

IN3h

, C

IN2

M5: TOSHIBA T2N7002AK

BAT

POWER FLOW

Is Regulated to 47.4V

LOAD

Drops Below 36V

BAT

Until V

Is Not Applied, V

10mΩ 10mΩ

When V

36V

CURRENT

LOAD

TO 5A WHEN

LIMIT V

LT8708

–

294k

SHDN

PREVENT

BAT

TO 47.4V

LOAD

REGULATE

464k

0.73k

8708 TA05c

10k

BELOW 35V

DISCHARGING

BAT

11.3k

GND BG2SW2 BOOST2 TG2

10μH

10Ω

M2 M3

52V Battery Backup Supply Using FHCM and RHCM

IN3

1nF

TO DIODE

10Ω

1nF

2Ω

0.22μF

CSNIN

CSPIN

FBIN

EXTV

VINHIMON

2Ω

TG1 BOOST1 SW1 BG1 CSP CSN

5mΩ

IN BACKUP)

47.4V WHEN

(REGULATE TO

IN2

0.73k

464k

IN1

LOAD

84.5k

11.3k

LT8708

DIR

100k

SWEN

VOUTLOMON

LDO33

127kM554.9k

4.7μF

100k

MODE

100k

SSRT

RVSOFF

24.9k

294k 1μF

6.8nF

220pF

: 220μF, 100V

: 1200μF, 100V

IN1

L1: 10μH, WURTH 701014101

M1–M4: INFINEON BSC039N06NS

Is Charged to 52.1V

BAT

Is Applied, V

BAT

37.5V

–

422k

BAT

LIMIT V

CHARGING

CURRENT TO 5A

BAT

CHARGE

8708 TA05b

10k

52.1V

10mΩ 10mΩ

When V

: CENTRAL SEMI CMMR1U-02-LTE

, D

: APPROPRIATE 8A SCHOTTKY DIODE OR IDEAL DIODE

SUCH AS LTC4357.

POWER FLOW

Rev 0

For more information www.analog.com

LT8708

3ms/DIV

8708 TA05d

3ms/DIV

8708 TA05e

3ms/DIV

8708 TA05f

APPLICATIONS INFORMATION

52V Battery Backup Supply Using FHCM and RHCM Detail

Charge Voltage = 52.1V (FBOUT in FHCM) V

BAT

Regulation Voltage = 47.4V (FBIN in RHCM) V

LOAD

BAT_DEAD

= 36V (Falling) or 37.5V (Rising) V

Frequency = 150kHz V

Table of Operation Modes and Power Flow Directions

CONDITIONS RESULTS

LOAD

– <V

>50.2V*

Fell Into (47.4V to 50.2V) Range*

Fell Into (45.9V to 47.4V) Range*

Rose Into (47.4V to 50.2V) Range*

<45.9V

is powered from VIN.

LOAD

BAT_DEAD

BAT

BAT_DEAD

>52.1V

to 52.1V

>52.1V

BAT_DEAD

LOAD

Charging Current Limit = 5A (IMON_OP)

BAT

LOAD

Power Flows from V

Rising to Activate V

Charging = 50.2V (VINHIMON Rising Activating FHCM)

BAT

Falling to Activate Backup Operation = 45.9V (VINHIMON Falling Activating RHCM)

Current Limit = 5A (IMON_INN)

POWER FLOW CHIP OPERATES IN RVSOFF DIR

No Power Flow Shutdown – –

Power Flows from VIN to V

Charging)

BAT

FHCM Lo Hi

No Power Flow

BAT

to V

LOAD

RHCM Hi LoRose Into (45.9V to 47.4V) Range

(Backup Operation)

DIR 5V/DIV

5V/DIV

LOAD

5V/DIV

5A/DIV

Transient Behavior Upon VIN Dropout, V

BAT

= 52V

DIR 5V/DIV

LOAD

Transient Behavior Upon VIN

5V/DIV

10A/DIV

Dropout, V

BAT

= 53V

Transient Behavior Upon VIN Dropout, V

DIR 5V/DIV

5V/DIV

LOAD

5V/DIV

5A/DIV

BAT

= 38V

Rev 0

For more information www.analog.com

8708 TA06b

12V

12V LOADS

OUT

TO LOADS

SUCH AS LTC4358, LTC4412, LTC4352, ETC.

L1: 2.2

8708 TA06c

LOADS

APPLICATIONS INFORMATION

15V

1.2k

×6

OUT2

25mΩ

OUT1

TO DIODE

2Ω5mΩ

M3M2

2.2μH

1nF

10Ω

Supercapacitor Backup Supply Using CCM

TO DIODE

2Ω

IN2

1µF

IN1

11V WHEN

(REGULATE TO

IN BACKUP)

25mΩ

12V

1nF

71.5k162k

115k

1µF

47nF

100Ω

TG2

CSPOUT

CSNOUT

0.22µF

10Ω

0.22µF

BOOST1 SW1 BG1 CSP CSN GND BG2 SW2 BOOST2

TG1

CSPIN

CSNIN

4.7µF

100Ω

20k20k

EXTV

INCHIP

FBOUT

SHDN

200k

4.7µF

FBIN

INTV

LT8708

150k

10k

4Ω

4.7µF

GATEV

IMON_OP

VINHIMON

VOUTLOMON

20k

50k

ICN

SWEN

6.8nF

ICP

IMON_INP

LDO33

50k

LD033

26.7k

22nF

17.4k

IMON_ON

RVSOFF

BOOST2

BOOST1

22nF

8708 TA06a

CLKOUTSYNC

IMON_INN

SSRT

15k

MODE

DIR

6.8nF

17.4k

1µF

350kHz

124k

5.6nF

220pF

Is Regulated to 11VWhen V

LOAD

Is Not Applied, V

When V

: 220μF, 35V 35HVP220M

: 22µF, 25V, TDK C4532X741E226M

OUT2

OUT1

, C

: 60F, 2.5V COOPER BUSSMAN HB1840-2R5606-R

IN1

IN2

M1–M4: INFINEON BSC050NE2LS

Is Charged to 15V

OUT

Is Applied, V

: CENTRAL SEMI CMMR1U-02-LTE

μH, VISHAY IHLP-5050CE-01-2R2-M-01

, D

: APPROPRIATE 2A SCHOTTKY DIODE OR IDEAL DIODE

OUT

POWER FLOW

25mΩ 25mΩ

BACKUP

OUT

25mΩ 25mΩ

BACKUP

POWER FLOW

1.2k

×6

REGULATE

162k

1.2k

×6

CHARGING

CURRENT TO 1A

LIMIT CAPACITOR

INPUT CURRENT

IN EXCESS OF 2A

WILL DRAW FROM

SUPERCAPACITORS

162k

LOADS TO 11V

29k

115k

10k

REGULATE

CAPACITOR TO 15V

29k

LT8708

PREVENT CHARGING

LOADS > 13.3V

200k

29k

Rev 0

For more information www.analog.com

LT8708

20s/DIV

8708 TA06d

5V/DIV

5A/DIV

3s/DIV

8708 TA06e

APPLICATIONS INFORMATION

Supercapacitor Backup Supply Using CCM Detail

Charge Voltage = 15V (FBOUT) V

OUT

Regulation Voltage = 11V (FBIN) V

BACKUP

= 5.42V (Falling) or 5.65V (Rising) V

IN_MIN

Frequency = 350kHz VIN Current Limit = 2A (IMON_INP)

Table of Operation Modes and Power Flow Directions

BACKUP

IN_MIN

>13.3V

Fell Into (12.9V to 13.3V)

Range

Rose Into (12.9V to 13.3V)

Range

>11V and <12.9V >15V

<11V and >V

IN_MIN

*For use with LT8708-1(s)

OUT

–

>15V

<15V Power Flows from VIN to V

>15V

<15V

–

Overvoltage Rising Threshold in Backup Operation = 13.3V (VINHIMON Rising)

BACKUP

Overvoltage Falling Threshold in Backup Operation = 12.9V (VINHIMON Falling)

BACKUP

Charging Current Limit = 1A (IMON_OP)

OUT

POWER FLOW CHIP OPERATES IN RVSOFF*

NO POWER FLOW

Charging)

OUT

No Power Flow

Power Flows from V

to LOADS

OUT

(Backup Operation)

Power Flows from VIN to V

Charging)

OUT

Power Flows from V

to LOADS

OUT

(Backup Operation)

OUT

Shutdown –

CCM

Charging V

OUT

to 15V with 1A Current

OUT

Transient Behavior Upon VIN

OUT

5V/DIV

BACKUP

5V/DIV

5A/DIV

Dropout (I

LOAD

= 4A)

Rev 0

For more information www.analog.com

PACKAGE DESCRIPTION

LT8708

5.50 ±0.05

4.10 ±0.05

PIN 1 TOP MARK

3.50 REF

5.00 ±0.10

40-Lead Plastic QFN (5mm × 8mm)

UHG Package

(Reference LTC DWG # 05-08-1528 Rev Ø)

5.85 ±0.10

3.10 ±0.10

6.50 REF

7.10 ±0.05

8.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.00 TYP

0.70 ±0.05

PACKAGE OUTLINE

C 0.35

4034

0.40 ±0.05

133

8.00 ±0.10

DETAIL A

0.75 ±0.05

2115

NOTE:

1. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES IN DEGREES.

2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08MM.

3. WARPAGE SHALL NOT EXCEED 0.10MM.

0.20 REF

0.00 – 0.05

0.75 TYP

× 4

5.85 ±0.10

3.10 ±0.10

0.675

2222

REF

0.55 REF

DETAIL A

0.203 ±0.008

0.00 – 0.05

4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S).

5. REFER JEDEC M0-220.

0.203 +0.058, –0.008 TERMINAL THICKNESS

1.00 TYP

BOTTOM VIEW—EXPOSED PAD

R = 0.125 TYP

0.25 ±0.05

0.50 BSC

DETAIL B

(UHG) QFN 0116 REV Ø

DETAIL B

0.08 REF

0.31 REF

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

Rev 0

LT8708

12V

OUT

TO LOADS

D SUCH AS LTC4358, LTC4412, LTC4352, ETC. D L1: 2.2

TYPICAL APPLICATION

(REGULATE TO

11V WHEN

100Ω

LD033

25mΩ

IN BACKUP)

4.7µF

50k

IN2

TO DIODE

2Ω

BOOST1 SW1 BG1 CSP CSN GND BG2SW2 BOOST2

TG1

CSNIN

CSPIN V

INCHIP

SHDN

FBIN

VINHIMON VOUTLOMON SWEN LDO33

RVSOFF

DIR

MODE

IN1

1µF

71.5k162k

20k20k

200k

150k

20k

Supercapacitor Backup Supply Using CCM

2.2μH

M3M2

5.6nF

10Ω

1nF

10Ω

LT8708

124k

2Ω5mΩ

SSRT

1µF

0.22µF

15k

220pF

TO DIODE

DB2

0.22µF

IMON_INP

IMON_INN

TG2

CSPOUT

CSNOUT

EXTV

FBOUT

INTV

GATEV

IMON_OP

ICN ICP

IMON_ON

CLKOUTSYNC

8708 TA02

350kHz

25mΩ

OUT1

100Ω

4.7µF

6.8nF

17.4k

22nF

17.4k

1µF

4.7µF

22nF

OUT2

6.8nF

4.7µF

26.7k TO

BOOST1TOBOOST2

4Ω

DB1D

×6

115k

10k

1.2k ×6

V 15V

: APPROPRIATE 2A SCHOTTKY DIODE OR IDEAL DIODE

, DB2: CENTRAL SEMI CMMR1U-02-LTE

μH, VISHAY IHLP-5050CE-01-2R2-M-01

M1–M4: INFINEON BSC050NE2LS C

, C

: 220μF, 35V 35HVP220M

IN1

OUT2

, C

: 22µF, 25V, TDK C4532X741E226M

IN2

OUT1

: 60F, 2.5V COOPER BUSSMAN HB1840-2R5606-R

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT8708-1 80V Synchronous 4-Switch Buck-Boost DC/DC

LT8705A 80V VIN and V

LT C®3779 150V VIN and V

LTC7813 60V Low IQ Synchronous Boost+Buck Controller

LTC3899 60V, Triple Output, Buck/Buck/Boost Synchronous

LT M®8056 58VIN, Buck-Boost µModule Regulator, Adjustable

LTC3895/ LTC7801

LTC3871 Bidirectional Multiphase DC/DC Synchronous Buck

LTC7103 105V, 2.3A, Low EMI Synchronous

Slave Controller for LT8708 Multiphase System

Synchronous 4-Switch Buck-

OUT

Boost DC/DC Controller

Synchronous 4-Switch Buck-

OUT

Boost Controller

Low EMI and Low Input/Output Ripple

Controller with 29µA Burst Mode I

Input and Output Current Limiting

150V Low IQ, Synchronous Step-Down DC/DC Controller with 100% Duty Cycle

or Boost On-Demand Controller

Step-Down Regulator

2.8V (Need EXTVCC > 6.4V) ≤ VIN ≤ 80V,1.3V ≤ V

2.8V ≤ VIN ≤ 80V, Input and Output Current Monitor, 5mm × 7mm QFN-38 and TSSOP-38 Packages

4.5V ≤ VIN ≤ 150V, 1.2V ≤ V or STD Threshold MOSFETs, TSSOP-38 Package

4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, Boost V

0.8V ≤ Buck V

4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, V Buck V

OUT

5V ≤ VIN ≤ 58V, 1.2V ≤ V

4V ≤ VIN ≤ 140V, 150V ABS Max, PLL Fixed Frequency 50kHz to 900kHz,

0.8V ≤ V

OUT

4mm × 5mm QFN-24, TSSOP-24, TSSOP-38(31) Packages

VIN/V

Up to 100V, Ideal for High Power 48V/12V Automotive Battery

OUT

Applications

4.4V ≤ VIN ≤105V, 1V ≤ V 5mm × 6mm QFN Package

SEE MORE DETAILS OF THIS APPLICATION ON PAGE 61.

≤ 80V, 5mm × 8mm QFN-40

OUT

≤ 150V, Up to 99% Efficiency Drives Logic-Level

OUT

≤ 60V, IQ = 29µA, 5mm × 5mm QFN-32 Package

OUT

Up to 60V,

Range: 0.8V to 60V, Boost V

≤ 48V, 15mm × 15mm × 4.92mm BGA Package

OUT

Up to 60V

≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40μA,

≤ VIN, IQ = 2µA, Fixed Frequency 200kHz,

OUT

Up to 60V,

Rev 0

D16897-0-6/18(0)

www.analog.com

For more information www.analog.com

Linear Technology Analog Devices LT8708 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

APPLICATIONS

TYPICAL APPLICATION

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS

PIN FUNCTIONS

BLOCK DIAGRAM

OPERATION

TYPOGRAPHICAL CONVENTIONS

START-UP

Start-Up: SHDN Pin

Start-Up: SWEN Pin

Start-Up: Soft-Start of Switching Regulator

CONTROL OVERVIEW

POWER SWITCH CONTROL

Switch Control: Soft-Start

UNI AND BIDIRECTIONAL CONDUCTION

Bidirectional Conduction: CCM

Unidirectional Conduction: DCM

Unidirectional Conduction: HCM

Unidirectional Conduction: Burst Mode

ERROR AMPLIFIERS

VIN REGULATION AND SENSING

VIN: Regulation

VIN: Above Regulation and Overvoltage

VIN: Below Regulation

CURRENT MONITORING AND LIMITING

Monitoring and Limiting: IMON Pins

Monitoring: ICP and ICN Pins

INTVCC/EXTVCC/GATEVCC/LDO33 POWER

CLKOUT AND TEMPERATURE SENSING

APPLICATIONS INFORMATION

VERIFY THE POWER FLOW CONDITIONS

OPERATING FREQUENCY SELECTION

INTERNAL OSCILLATOR

SYNC PIN AND CLOCK SYNCHRONIZATION

CLKOUT PIN AND CLOCK SYNCHRONIZATION

INDUCTOR CURRENT SENSING AND SLOPE COMPENSATION

INDUCTOR (L) SELECTION

L Selection: Load Current in Buck and Boost Regions

L Selection: Maximum Current Rating

L Selection: Subharmonic Oscillations

POWER MOSFET SELECTION

SCHOTTKY DIODE (D1, D2, D3, D4) SELECTION

Top Driver: Boost Cap Charge Control Block

VINHIMON, VOUTLOMON AND RVSOFF

LOOP COMPENSATION

INTVCC REGULATORS AND EXTVCC CONNECTION

LDO33 REGULATOR

VOLTAGE LOCKOUTS

JUNCTION TEMPERATURE MEASUREMENT

THERMAL SHUTDOWN

EFFICIENCY CONSIDERATIONS

CIRCUIT BOARD LAYOUT CHECKLIST

HOT PLUGGING CONSIDERATIONS

DESIGN EXAMPLE

TYPICAL APPLICATIONS

PACKAGE DESCRIPTION

TYPICAL APPLICATION

RELATED PARTS