Linear LTM4641EY, LTM4641IY, LTM4641MPY Schematics

38V, 10A DC/DC µModule

MSP: (OPTIONAL) SERIES-PASS OVERVOLTAGE POWER INTERRUPT MOSFET, NXP PSMN014-60LS MCB: (OPTIONAL) OUTPUT OVERVOLTAGE CROWBAR MOSFET, NXP PH2625L

4.5V START-UP

OUT

(200mV/DIV)

4µs/DIV

TESTED AT WORST-CASE CONDITION: NO LOAD

4641 TA01b

SHORT-CIRCUIT APPLIED

1.1V

OUT

PEAK

CROWBAR (5V/DIV)

321

INL

, V

INH

(25V/DIV)

Regulator with Advanced

Input and Load Protection

FeaTures DescripTion

Wide Operating Input Voltage Range: 4.5V to 38V

10A DC Typical, 12A Peak Output Current

Output Range: 0.6V to 6V

±1.5% Maximum Total Output DC Voltage Error

Differential Remote Sense Amplifier for POL Regulation

Internal Temperature, Analog Indicator Output

Overcurrent Foldback and Overtemperature

Protection

Current Mode Control/Fast Transient Response

Parallelable for Higher Output Current

Selectable Pulse-Skipping Operation

Soft-Start/Voltage Tracking/Pre-Bias Start-Up

15mm × 15mm × 5.01mm BGA Package

SnPb or RoHS Compliant Finish

Input Protection

UVLO, Overvoltage Shutdown and Latchoff Thresholds

N-Channel Overvoltage Power-Interrupt MOSFET Driver

Surge Stopper Capable with Few External Components

Load Protection

Robust, Resettable Latchoff Overvoltage Protection

N-Channel Overvoltage Crowbar Power MOSFET Driver

applicaTions

Ruggedized Electronics

Avionics and Industrial Equipment

The LT M®4641 is a switch mode step-down DC/DC

µModule

(micromodule) regulator with advanced input and load protection features. Trip detection thresholds for the following faults are customizable: input undervoltage, overtemperature, input overvoltage and output overvolt age. Select fault conditions can be set for latchoff or hysteretic restart response—or disabled. package are the switching controller and housekeeping ICs, power MOSFETs, inductor, overvoltage drivers, biasing circuitry and supporting components. Operating from input voltages of 4V to 38V (4.5V start-up), the device supports output voltages from 0.6V to 6V, set by an external resis tor network remote sensing the point-of-load’s voltage.

The LTM4641’s high efficiency 10A continuous current with a few input and output ca pacitors. The regulator’s constant on-time current mode control architecture enables high step-down ratios and fast response to transient line and load changes. The LTM4641 is offered in a 15mm × 15mm × 5.01mm with SnPb or RoHS compliant terminal finish.

L, LT, LTC, LTM , µModule, Burst Mode, Linear Technology and the Linear logo are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5847554, 6100678, 6304066, 6580258, 6677210, 8163643.

Click to view associated TechClip Videos.

LTM4641

Included in the

design can deliver up to

Typical applicaTion

µModule Regulator with Input Disconnect and Fast Crowbar Output Overvoltage Protection

4V TO 38V

100µF 50V

10nF

750k

MSP*

10µF 50V ×2

INGVINGPVINH

INL

SET

UVLO INTV

DRV

RUN

TRACK/SS

IOVRETRY

SGND CONNECTS TO GND INTERNAL TO µMODULE REGULATOR

TOP

CROWBAR

BOT

LTM4641

OVLO FCB LATCH SGND

OSNS

GND

OUT

PGM

For more information www.linear.com/LTM4641

1V Load Protected from M

Short-Circuit at 38V

MCB**

5.49k

–

5.6M

LOAD

4641 TA01a

100µF ×3

V 1V 10A

OUT

TOP

4641fe

LTM4641

Features ..................................................... 1

Applications ................................................ 1

Typical Application ........................................ 1

Description.................................................. 1

Absolute Maximum Ratings .............................. 3

Order Information .......................................... 3

Pin Configuration .......................................... 3

Electrical Characteristics ................................. 4

Typical Performance Characteristics ................... 8

Pin Functions .............................................. 10

Simplified Block Diagram ............................... 15

Decoupling Requirements ............................... 15

Operation................................................... 16

Introduction ............................................................ 16

Motivation ............................................................... 16

Power µModule Regulator Reliability ...................... 16

Overview ................................................................. 16

Applications Information—Power Supply Features . 17

Power (V Switching Frequency (On Time) Selection and Voltage Dropout Criteria (Achievable V

Step-Down Ratios).................................................. 18

Setting the Output Voltage; the Differential

Remote Sense Amplifier .........................................21

Input Capacitors .....................................................23

Output Capacitors and

Loop Stability/Loop Compensation ......................... 23

Pulse-Skipping Mode vs Forced Continuous Mode Soft-Start, Rail-Tracking and Start-Up Into Pre-Bias INTV

REF ......................................................................................... 28

TEMP, OTBH and Overtemperature Protection ........28

Input Monitoring Pins: UVLO, IOVRETRY, OVLO ....29

Applications Information—Input Protection

Features .................................................... 29

Start-Up/Shutdown and Run Enable; Power-On Reset and Timeout Delay Time

) and Bias (V

INH

.................................................................. 24

and DRV

CC ............................................................... 27

) Input Pins ................. 17

INL

-to-V

....................................... 24

OUT

...............31

Applications Information—Load Protection Features

Applications Information—EMI Performance ........ 35

Applications Information—Multimodule Parallel Operation Applications Information—Thermal Considerations

and Output Current Derating ............................ 38

Applications Information—Output Capacitance Table Applications Information—Safety and Layout

Guidance ................................................... 46

Typical Applications ...................................... 48

Appendices ................................................ 56

Package Description ..................................... 63

Package Photo ............................................ 63

Package Description ..................................... 64

Revision History .......................................... 65

Typical Application ....................................... 66

Related Parts .............................................. 66

.................................................... 32

Overcurrent Foldback Protection ............................32

Power Good Indicator and Latching Output

Overvoltage Protection ........................................... 32

Power-Interrupt MOSFET (MSP), CROWBAR Pin and Output CROWBAR MOSFET (MCB)

Fast Output Overvoltage Comparator Threshold ..... 34

The Switching Node: SW Pin .................................. 35

........................................ 36

Thermal Considerations and Output Current Derating

........................................................ 45

Safety Considerations ............................................. 46

Layout Checklist/Example ......................................46

Appendix A. Functional Block Diagram and Features Quick Reference Guide

Appendix B. Start-Up/Shutdown State Diagram .....57

Appendix C. Switching Frequency Considerations and Usage of R Appendix D. Remote Sensing in Harsh Environments Appendix E. Inspiration For Pulse-Skipping Mode Operation Appendix F. Adjusting the Fast Output Overvoltage

Comparator Threshold ............................................ 60

................................................. 58

fSET

............................................... 59

...................................................... 60

.........................................38

.............................56

.................. 33

4641fe

For more information www.linear.com/LTM4641

(Note 1)

144-LEAD (15mm × 15mm × 5.01mm)

TOP VIEW

REF

TRACK/SS

Terminal Voltages V

INL

OUT

ING

INTV

, SW, f

INH

...................................................... –0.3V to 9.2V

............................................ –0.3V to V

, DRVCC, RUN, TRACK/SS, PGOOD,

............................... –0.3V to 40V

SET

INH

+ 20V

, V

CROWBAR, HYST .................................... –0.3V to 6V

FCB, TMR................................-0.3V to INTV

+ 0.3V

COMP ................................................... –0.3V to 2.7V

V V

OSNS OSNS

+ –

, V , V

...................................... –0.6V to 9.7V

ORB ORB

–

..........V

OSNS

– 2.7V to V

OSNS

+ 0.3V

OTBH, UVLO, IOVRETRY, OVLO,

....................................................–0.3V to 7. 5V

LATCH

TEMP, OV

....................................... –0.3V to 1.5V

PGM

Terminal Currents INTV INTV

(Continuous)....................................... –30mA

(Continuous; CROWBAR

Sourcing 15mA) ............................................... –15mA

CROWBAR (Continuous) ..................................–15mA

V 1V

(Continuous) ........................... –50mA to 15mA

INGP

(Continuous) ................................–1mA to 1mA

REF

Internal Operating Temperature Range (Note 2)

E- and I-Grades .................................. –40°C to 125°C

MP-Grade .......................................... –55°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Peak Package Body Temperature (SMT Reflow) ... 245°C

pin conFiguraTionabsoluTe MaxiMuM raTings

PGOOD

OSNS

SGND

COMP

SET

INL

OSNS

ORB

INTV

FCB

–

1 2 3 4 5 6 7 8 109 11 12

DRV

GND

RUNTMROTBH

LATCH

SGND

GND

UVLO

HYST

= 125°C, θ

JMAX

θ VALUES DETERMINED PER JESD51-12

OVLO

BGA PACKAGE

= 11°C/W, θ

JCtop

= 3°C/W, θJA = 10.4°C/W

WEIGHT = 2.9 GRAMS

CROWBARTEMP IOVRETRY

JCbottom

LTM4641

INGP

INGSGND

GND

PGM

= 2.5°C/W

INH

OUT

orDer inForMaTion

PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE

TYPE

LTM4641EY#PBF

DEVICE FINISH CODE

SAC305 (RoHS) LTM4641Y e1 BGA 4 –40°C to 125°C LTM4641IY#PBF SAC305 (RoHS) LTM4641Y e1 BGA 4 –40°C to 125°C LTM4641IY SnPb (63/37) LTM4641Y e0 BGA 4 –40°C to 125°C LTM4641MPY#PBF SAC305 (RoHS) LTM4641Y e1 BGA 4 –55°C to 125°C LTM4641MPY SnPb (63/37) LTM4641Y e0 BGA 4 –55°C to 125°C

Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping

container. Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Pb-free and Non-Pb-free Part Markings:

www.linear.com/leadfree

For more information www.linear.com/LTM4641

• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures:

www.linear.com/umodule/pcbassembly

• LGA and BGA Package and Tray Drawings:

www.linear.com/packaging

MSL

RATING

TEMPERATURE RANGE (Note 2)

4641fe

LTM4641

elecTrical characTerisTics

The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V shown in Figure 45, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

OUT

OUT(DC)

Input Specifications

RUN(ON,OFF)

RUN(ON)

RUN(OFF)

INL(UVLO)

INRUSH(VINH)

Q(VINH)

Q(VINL)

S(VINH)

Output Specifications

OUT(DC)

∆V

OUT(LINE)/VOUT

∆V

OUT(LOAD)/VOUT

OUT(AC)

OUT(START)

START

RUN(ON-DELAY)

∆V

OUT(LS)

SETTLE(LS)

Input DC Voltage

Output Voltage Range Use R

SET1A

= R

SET1B

≤ 8.2kΩ. R

Recommended in Table 1

Output Voltage, Total Variation with Line and Load, and Prior to UVLO

4.5V ≤ VIN ≤ 38V, 0A ≤ I V

= 4V (Ramped Down from 4.5V), I

RUN On/Off Threshold Run Rising, Turn On

Run Falling, Turn Off

RUN Pull-Up Current V

RUN Pull-Down Current, Switching

= 0V

RUN

= 3.3V

RUN

= 3.3V, UVLO = 0V (M

RUN

Inhibited

Undervoltage Lockout V

INL

Rising Falling

Hysteresis

Input Inrush Current Through V

CSS = Open 230 mA

INH

at Start-Up

Power Stage Bias Current (I No Load

VINH

) at

= 0A and:

OUT

FCB ≥ 0.84V (Pulse-Skipping Mode) FCB ≤ 0.76V (Forced Continuous Mode) Shutdown, RUN = 0

Control Bias Current (I

Power Stage Input Current (I Full Load

) INTVCC Connected to DRVCC and:

VINL

VINH

) at

= 28V, I

= 28V, Shutdown, RUN = 0

= 10A and:

OUT

= 4.5V

= 28V

= 38V

OUT OUT

= 0A = 10A

Output Continuous Current Range (Note 3)

Line Regulation Accuracy VIN from 4.5V to 38V, I

Load Regulation Accuracy I

Output Voltage Ripple Amplitude I

Output Voltage Ripple Frequency I

Turn-On Overshoot I

VIN-to-V

RUN-to-V

Start-Up Time RUN Electrically Open Circuit, Time Between

OUT

Turn-On Response

OUT

Time

from 0A to 10A (Note 3)

OUT

= 0A 16 mV

OUT

= 0A

OUT

= 10A

OUT

= 0A 10 mV

OUT

Application of V OV

= 1.5V, C

PGM

to V

= CSS = Open

TMR

VIN Established, (TMR-Set POR Time Expired) Time Between RUN Releasing from GND to PGOOD Going Logic High, C OV

= 1.5V

PGM

Peak Deviation for Dynamic Load Step

Settling Time for Dynamic Load Step I

from 0A to 5A at 5A/µs

OUT

from 5A to 0A at 5A/µs

OUT

from 0A to 5A at 5A/µs

OUT

from 5A to 0A at 5A/µs

OUT

fSET

≤ 10A

OUT

On) 1 nA

HYST

= 0A

OUT

Becoming Regulated,

OUT

= Open,

INH

Values

= 0A

OUT

= V

= 28V, per the typical application

INL

4.5 38 V

0.6 6 V

l l

l l l

1.773

–580 –220

0.8

3.5

300

1.800

1.25

1.15

–520 –165

4.2

3.8

400

0.2

14.5

15.5 5

4.65

790 590

0 10 A

0.02 0.15 %

0.04 0.15 %

290 330

3 ms

175 400 μs

40 40

20 20

1.827

2 V

–460 –110

4.5 4

µA µA

mA mA mA

mA mA

P-P

kHz kHz

mV mV

V V

μs µs

4641fe

For more information www.linear.com/LTM4641

LTM4641

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

OUT(PK)

VINH(IOUT_SHORT)

Control Section

TRACK/SS

FCB

ON(MIN)

OFF(MIN)

OSNS(DM)

OSNS(CM)

IN(VOSNS+)

, DRVCC, 1V

INTV

INTVCC

∆V

INTVCC(LOAD)

INTVCC

INTVCC(LOWLINE)

DRV

CC(UVLO)

DRVCC

1VREF(DC)

PGOOD Output

PGOOD(TH)

PGOOD(HYST)

PGOOD(VOL)

PGOOD(DELAY)

Output Current Limit 5.1kΩ Pull-Up from PGOOD to 5V Source, I

Ramped Up Until V

Below PGOOD Lower

OUT

Threshold, PGOOD Pulls Logic Low

Power Stage Input Current During

Electrically Shorted to GND 45 mA

OUT

Output Short Circuit

Differential Feedback Voltage from V

OSNS

to V

OSNS

–

TRACK/SS Pull-Up Current V

= 0A

OUT

TRACK/SS

= 0V –0.45 –1 μA

FCB Threshold 0.76 0.8 0.84 V

FCB Pin Current V

= 0.8V 0 ±1 μA

FCB

Minimum On-Time (Note 4) 43 75 ns

Minimum Off-Time (Note 4) 220 300 ns

Remote Sense Pin-Pair Differential Mode Input Range

Remote Sense Pin-Pair Common Mode Input Range

Input Resistance V

REF

Valid Differential V (Use R

Valid V Valid V (Use R

OSNS

= R

SET1A

–

Common Mode Range

OSNS

Common Mode Range

OSNS

= R

SET1A

to GND 16318 16400 16482 Ω

OSNS

SET1B

-to- V

≤ 8.2k)

OSNS

Internal VCC Voltage 6V ≤ VIN ≤ 38V, INTVCC Not Connected to DRVCC,

DRV

= 5.3V

INTVCC Load Regulation RUN = 0V, INTVCC Not Connected to DRVCC,

DRV

= 5.3V and:

Varied from 0mA to –20mA

INTVCC

Varied from 0mA to –30mA

INTVCC

INTVCC Voltage at Low Line VIN = 4.5V, R

Value Recommended in Table 1)

fSET

SET1A

= R

= 0Ω (~0.6V

SET1B

DRVCC Undervoltage Lockout DRVCC Rising

DRV

Falling

DRVCC Current INTVCC Not Connected to DRVCC, DRVCC = 5.3V,

, R

DC Voltage Regulation I

REF

Power Good Window, Logic State Transition Thresholds

OUT OUT

SET1A

SET1B

, R

fSET

, R

fSET

= R

and R

SET1B

= Open, 0A ≤ I

SET1A

1.8V

6.0V (Use R

1VREF

= 0mA = ±1mA

Ramping Differential V Up, PGOOD Goes Logic Low → High

Setting V

SET2

= 2MΩ, 0A ≤ I

≤ 8.2k)

– V

OSNS

OUT OUT

OSNS

Up, PGOOD Goes Logic High → Low Down, PGOOD Goes Logic Low → High Down, PGOOD Goes Logic High → Low

Hysteresis Differential V

Logic-Low Output Voltage I

PGOOD

= 5mA

OSNS

PGOOD Logic-Low Blanking Time Delay Between Differential V

– V

–

Voltage Returning 8 16 24 mV

OSNS

Voltage Exiting PGOOD Valid Window to PGOOD Going Logic Low (Note 4)

INH

–

Range

to:

OUT

≤ 10A ≤ 10A

–

Voltage:

– V

OSNS

= V

= 28V, per the typical application

INL

OUT

591 600 609 mV

–0.3

5.1 5.3 5.4 V

24 A

0 2.7 V

–0.7

–1

OUT

4.2 4.3 V

3.9

3.2

4.05

3.35

11 20

0.985

0.980

–

533 645 621 525

1.000

556 660 644 540

75 400 mV

12 μs

±2 ±3

4.2

3.5

18 27

1.015

1.020

579 675 667 555

mA mA

mV mV mV mV

V V

% %

V V

For more information www.linear.com/LTM4641

4641fe

LTM4641

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power-Interrupt MOSFET Drive

VING

Gate Drive Voltage for PowerInterrupt MOSFET, MSP

VING(UP)

VING_DOWN(CROWBAR ACTIVE,CROWBAR INACTIVE)

VING(OVP_DELAY)

VINGP(LEAK)

INGP(CLAMP)

Zener Diode Leakage Current V

Zener Diode Breakdown Voltage V

Fault Pins and Functions

OVPGM

Default Output Overvoltage Program Setting

OVPGM(UP)

OVPGM(DOWN)

OVP

Output Overvoltage Protection Inception Threshold

OVP

ERR

Output Overvoltage Protection Inception Error

CROWBAR(OVP_DELAY)

CROWBAR(OH)

CROWBAR Response Time OVPGM Driven from 650mV to 550mV

CROWBAR Output, Active High Voltage

CROWBAR(OL)

CROWBAR Output, Passive Low Voltage

CROWBAR(OVERSHOOT)

CROWBAR Peak Voltage Overshoot at V

CROWBAR(TH)

TEMP

TH(INCEPTION)

CROWBAR Latchoff Threshold CROWBAR Ramped Up Until HYST Goes Logic

TEMP Voltage RUN = 0V, TA = 25°C

TEMP Overtemperature Inception Threshold

TH(RECOVER)

TEMP Overtemperature Recovery Threshold

UVOV

UVLO/OVLO/IOVRETRY Undervoltage/Overvoltage Inception Thresholds

Pull-Up Current V

ING

Pull-Down Current V

ING

OVP Pull-Down Delay OV

ING

Pull-Up Current OV

PGM

Pull-Down Current OV

PGM

Start-Up and Shutdown

INL

VIN = 4.5V, 0A ≤ I V

= 28V, 0A ≤ I

= 38V, 0A ≤ I

= 4V (Ramped Down from 4.5V), I

Sourcing 1µA

ING

Tied to V

ING

= 4.5V, V

= 28V, V

Tied to V

ING

≤ 10A, V

OUT

≤ 10A, V

OUT

≤ 10A, V

OUT

, and:

INGP

Pulled to 6.5V

ING

Pulled to 30V

ING

, Pulled to 33V, and:

INGP

ING

Sourcing 1µA

ING

Sourcing 1µA

ING

RUN Pulled to 0V (CROWBAR Inactive) OV

Pulled to 0V (CROWBAR Active)

PGM

Driven from 650mV to 550mV, V

PGM

Discharge Response Time

Driven to (V

INGP

-to-V

INGP

INH

Electrically Open Circuit

PGM

= 0V

PGM

= 1V

PGM

Ramping Up Differential V

+ 10V) 1 nA

INH

Differential Voltage; I

-to-V

OSNS

Voltage Until CROWBAR Outputs Logic High

Difference Between OVPTH and V (OVP

TH-VOVPGM

)

OVPGM

OVPGM Pulled to 0V and: I

CROWBAR

INL

= –100μA, I = –4mA, I

INTVCC

= –20mA

= 1μA

Ramped Up from/Down to 0V

Low

RUN = 0V, T

= 125°C

(See Figure 10 for Reference)

Ramping TEMP Downward Until HYST Outputs Logic Low

Ramping TEMP Upward Until HYST Outputs Logic High

Ramping UVLO, OVLO or IOVRETRY Positive Until HYST Toggles Its State

= V

INH

Sourcing 1µA

OUT

ING

VINGP

OSNS

= 28V, per the typical application

INL

= 0A,

l l l

l l

11.5

10.5

35 45

350 425

13.3

38.4

48.4

11.5

475 550

20 27

1.3 2.6 µs

= 5mA 15 V

650 666 680 mV

–2.07 –2 –1.91 μA

0.945 1 1.06 μA

–

647 666 683 mV

–12 0 12 mV

4.3

4.2

1.4 1.5 1.6 V

400 500 ns

4.65

4.55

260 500 mV

550 900 mV

950 980

585

428 438 448 mV

501 514 527 mV

488 500 512 mV

15.5 41

51.5

14.2

600 675

µA µA

30 30

mA mA

4.9

1010 mV

V V V V

V V

4641fe

For more information www.linear.com/LTM4641

LTM4641

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

UVOVD

UVOV

HOUSEKEEPING(UVLO)

HYST(SWITCHING ON)

HYST(SWITCHING OFF,

RUN)

HYST(SWITCHING OFF,

FAULT)

TMR

UOTO

LATCH(IH)

LATCH(IL)

LATCH

TMR(UP)

TMR(DOWN)

TMR(DIS)

OTBH

VIL

OTBH

OTBH(MAX)

UVLO/OVLO/IOVRETRY/ TEMP Response Time

Input Current of UVLO, OVLO and IOVRETRY

Housekeeping Circuitry UVLO Voltage on INTVCC, INTVCC Rising (Note 4)

HYST Voltage (M

HYST

Off, RUN

Logic High)

HYST Voltage (M

HYST

Off, RUN

Logic Low)

HYST Voltage, Switching Action Inhibited (M

HYST

On)

Timeout and Power-On Reset Period C

LATCH Clear Threshold Input High LATCH Clear Threshold Input Low LATCH Input Current V

TMR Pull-Up Current V

TMR Pull-Down Current V

Timer Disable Voltage Referenced to INTV

OTBH Low Level Input Voltage

OTBH Pin Voltage When Left Electrically Open Circuit

Maximum OTBH Current OTBH Electrically Shorted to SGND

±50mV Overdrive (All Pins) ±5mV Overdrive, UVLO/OVLO/IOVRETRY Pins Only (Note 4)

UVLO = 0.55V or OVLO = 0.45V or IOVRETRY = 0.45V

Hysteresis, INTV

Returning (Note 4)

RUN Electrically Open Circuit RUN = 1.8V

RUN = 0V

UVLO < UVOV IOVRETRY > UVOV or CROWBAR > V DRV

< DRVCC

or OVLO > UVOVTH or

or TEMP < OT

CROWBAR(TH)

UVLO(FALLING)

(See Figures 62, 63)

= 1nF, Time from Fault Clearing to HYST

TMR

Being Released by Internal Circuitry

= 7.5V

LATCH

= 0V

TMR

= 1.6V

TMR

–10μA ≤ I

OTBH

≤ 10μA

= V

INH

TH(INCEPTION)

= 28V, per the typical application

INL

125

1.9 5

4.9

1.85

170 350 480 mV

5.1

2.1

100 500

±30 nA

2.1 50

5.25

2.35

30 65 mV

5 9 14 ms

1.2 V

–1.2 –2.1 –2.8 μA

1.2 2.1 2.8 μA

–180 –270 mV

0.6 0.9 1.2 V

0.8 V

±1 μA

0.4 V

30 μA

µs µs

V V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

The LTM4641 SW absolute maximum rating of 40V is verified in ATE by regulating V

while at 40VIN, in a controlled manner guaranteed to not

OUT

affect device reliability or lifetime. Static testing of SW leakage current at 40V

is performed at control IC wafer level only.

Note 2: The LTM4641 is tested under pulsed load conditions such that T

≈ TA. The LTM4641E is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the

For more information www.linear.com/LTM4641

–40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4641I is guaranteed over the –40°C to 125°C operating junction temperature range. The LTM4641MP is tested and guaranteed over the full –55°C to 125°C operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors.

Note 3:

See output current derating curves for different V

, V

and TA.

OUT

Note 4: 100% tested at wafer level only.

4641fe

LTM4641

4641 G05

Typical perForMance characTerisTics

(Figure 45 circuit with R

per Table 1 and R

fSET

SET1A

, R

SET1B

and R

per Table 2, unless otherwise noted)

SET2

Efficiency vs Load Current at 36V

EFFICIENCY (%)

OUTPUT CURRENT (A)

6.0V

OUT

5.0V

OUT

3.3V

OUT

2.5V

OUT

1.8V

OUT

6 8

Efficiency vs Load Current at 6V

EFFICIENCY (%)

OUTPUT CURRENT (A)

3.3V

OUT

2.5V

OUT

1.8V

OUT

1.5V

OUT

6 8

1.5V

OUT

1.2V

OUT

1.0V

OUT

0.9V

OUT

4641 G01

Efficiency vs Load Current at 24V

EFFICIENCY (%)

6.0V

OUT

5.0V

OUT

3.3V

OUT

2.5V

OUT

1.8V

OUT

OUTPUT CURRENT (A)

6 8

1.5V

OUT

1.2V

OUT

1.0V

OUT

0.9V

OUT

4641 G02

Efficiency vs Load Current at 12V

EFFICIENCY (%)

6.0V

OUT

5.0V

OUT

3.3V

OUT

2.5V

OUT

1.8V

OUT

OUTPUT CURRENT (A)

6 8

1.5V

OUT

1.2V

OUT

1.0V

OUT

0.9V

OUT

4641 G03

Pulse-Skipping vs Forced Continuous Mode Efficiency,

1.2V

OUT

1.0V

OUT

0.9V

OUT

4641 G04

28VIN to 3.3V

(PULSE-SKIPPING)

EFFICIENCY (%)

0.001

OUT

FCB = INTV

0.01 OUTPUT CURRENT (A)

0.1

FCB = SGND FORCED CONTINUOUS

50mV/DIV

AC-COUPLED

1V Transient Response, 38V

OUT

2.5A/DIV

0A TO 5A LOAD STEPS AT 5A/µs FRONT PAGE CIRCUIT WITH

= OPEN CIRCUIT

PGM

20µs/DIV

4641 G06

OUT

50mV/DIV

AC-COUPLED

OUT

2.5A/DIV

1V Transient Response, 4.5V

0A TO 5A LOAD STEPS AT 5A/µs FRONT PAGE CIRCUIT WITH

= OPEN CIRCUIT

PGM

20µs/DIV

4641 G07

3.3V Transient Response, 28VIN to 3.3V

OUT

50mV/DIV

AC-COUPLED

OUT

2.5A/DIV

0A TO 5A LOAD STEPS AT 5A/µs FIGURE 46 CIRCUIT

For more information www.linear.com/LTM4641

OUT

20µs/DIV

4641 G08

OUT

1V/DIV

200mA/DIV

RUN

5V/DIV

Output Start-Up, No Load

VIN = 24V C

IN(MLCC)

800µs/DIV

= 2 × 10µF X7R

4641 G09

4641fe

Typical perForMance characTerisTics

4641 G18

(Figure 45 circuit with R

per Table 1 and R

fSET

SET1A

, R

SET1B

and R

per Table 2, unless otherwise noted)

SET2

LTM4641

Output Start-Up, 10A Load

OUT

1V/DIV

1A/DIV

RUN

5V/DIV

VIN = 24V C

IN(MLCC)

800µs/DIV

= 2 × 10µF X7R

Output Short-Circuit, 10A Initial Load

OUT

1V/DIV

1A/DIV

VIN = 24V C

IN(MLCC)

20µs/DIV

= 2 × 10µF X7R

4641 G10

4641 G13

OUT

1V/DIV

LOAD

1mA/DIV

200mA/DIV

RUN

5V/DIV

20V/DIV

INH

2V/DIV

OUT

200mV/DIV

CROWBAR

5V/DIV

Output Start-Up, Pre-Bias Condition

VIN = 24V C

IN(MLCC)

Start-Up with V Node, 1V

FRONT PAGE CIRCUIT WITH V CIRCUITED TO SW PRIOR TO POWER-UP. APPLYING UP TO 38V

800µs/DIV

= 2 × 10µF X7R

INH

OUT(NOM)

400µs/DIV

. NO LOAD

Shorted to SW

INH

SHORT

4641 G11

4641 G14

OUT

1V/DIV

1A/DIV

10V/DIV

INH

5V/DIV

OUT

1V/DIV

CROWBAR

5V/DIV

Output Short-Circuit, No Initial Load

VIN = 24V C

IN(MLCC)

Start-Up with V Node, 3.3V

FIGURE 46 CIRCUIT WITH V CIRCUITED TO SW PRIOR TO POWER-UP. APPLYING UP TO 38V

20µs/DIV

= 2 × 10µF X7R

INH

OUT(NOM)

800µs/DIV

Shorted to SW

SHORT

INH

. NO LOAD

4641 G12

4641 G15

10V/DIV

INH

10V/DIV

OUT

1V/DIV

CROWBAR

5V/DIV

Autonomous Restart with V Shorted to SW Node, 3.3V

FIGURE 46 CIRCUIT, SHORT CIRCUITING V TO SW IN SITU, OPERATING AT 38VIN AND NO LOAD. LATCH CONNECTED TO INTV

= 47nF

TMR

100ms/DIV

INH

OUT(NOM)

4641 G16

INH

AND

Paralleled Modules, CurrentSharing Performance. cf. Figure 66 Circuit. 28V

MODULE OUTPUT CURRENT (A)

–2

For more information www.linear.com/LTM4641

U1 I

4 8 12 20 TOTAL OUTPUT CURRENT (A)

OUT

U2 I

OUT

BANDGAP VOLTAGE (V)

4641 G17

Control IC Bandgap and 1V Voltages vs Temperature. 28V

0.606

0.604

0.602

0.600

0.598

0.596

0.594 –50 0

–75

JUNCTION TEMPERATURE (°C)

–25

1VREF(DC)

50 150

REF

1.006

1.004

REF

1.002 VOLTAGE (V)

1.000

0.998

0.996

125

0.994

4641fe

100

LTM4641

pin FuncTions

SGND (A1-A3; B1-B3; C1-C4; K1, K3; L3; M1-M3): Signal Ground Pins. This is the return ground path for all analog control and low power circuitry. SGND is tied to GND in

ternal to the µModule regulator in a manner that promotes the best internal signal integrity—therefore, SGND should not be connected to GND in the user’s PCB layout. See the Layout Checklist/Example section of the Applications Information section for more information pertaining to SGND and layout. All SGND pins are electrically connected to each other, internally.

HYST (A4): Input Undervoltage Hysteresis Programming Pin. Normally used as an output, but can be used as an input. If the LTM4641’s inherent, default undervoltage lockout (UVLO) settings are satisfactory, 4.5V

MAX)

and 4V

IN(FALLING, MAX)

, HYST can be left electrically

IN(RISING,

open circuit. See the Applications Information section to customize the LTM4641’s UVLO thresholds.

HYST is a logic-high output with moderate pull-up strength that commands LTM4641’s internal control IC to regulate the module’s output voltage when conditions on the RUN, UVLO, OVLO, IOVRETRY, TEMP, CROWBAR, INTV and DRV

pins permit it (any recent latchoff events

notwithstanding, otherwise OTBH and LATCH can also play a role). When a fault condition is detected, internal circuitry (M

; see Figure 1) drives HYST logic low and

HYST

the LTM4641’s output is turned off. HYST can be used as a fault-indicator. See the Applications Information section.

may be deasserted when TEMP subsequently exceeds 514mV (nominally corresponding to a cool-off hysteresis of ~10°C), depending on the OTBH setting. (See

OTBH and

the Applications Information section.)

To disable the µModule regulator shutdown feature, connect the TEMP and 1V

’s overtemperature

pins. The

REF

thermal shutdown inception threshold can also be modified, see the Applications Information section.

IOVRETR

Y (A6): Nonlatching Input Over

voltage Threshold Programming Pin. The LTM4641 pulls HYST low to inhibit regulation of its output voltage when IOVRETRY exceeds

0.5V. The LTM4641 can resume switching action when IOVRETRY is below 0.5V. If no nonlatching input over voltage shutdown behavior is desired, connect this pin to SGND. Do not leave this pin open circuit.

GND (A7-A12; B6-B8, B11-B12; C7-C8; D6-D8; E1-E8; F1-F12; G1-G12; H3-H9, H11-H12; J5-J12; K5-K6, K11K12; L4-L6; M4-M6): Power ground pins for input and

output returns. See the Layout Checklist/Example section of the Applications Information section. All GND pins are electrically connected to each other, internally.

UVLO (B4): Input Undervoltage Lockout Programming Pin. The LTM4641 pulls HYST low to inhibit regulation of its output voltage whenever UVLO is less than 0.5V. The LTM4641 can resume switching action when UVLO exceeds 0.5V. Do not leave this pin open circuit.

HYST is pulled low when the RUN pin is pulled low, via an internal Schottky diode. HYST can be driven low by external open-collector/open-drain circuitry directly—as an alternate to the RUN pin interface. However, external circuitry should never drive HYST high, since doing so (indiscriminately) could cause thermal overstress to M

HYST

, when M

HYST

is on.

TEMP (A5): Power Stage Temperature Indicator and Overtemperature Detection Pin. When left electrically open circuit, TEMP’s voltage varies according to an internal NTC (negative temperature coefficient) thermistor, residing in close proximity to LTM4641’s power stage. When TEMP falls below 438mV (corresponding to a thermistor and power stage temperature of ~145°C), the LTM4641 pulls HYST low to inhibit regulation of its output voltage. HYST

For more information www.linear.com/LTM4641

the LTM4641’s default UVLO settings are

4.5V

IN(RISING, MAX)

and 4V

IN(FALLING, MAX)

pin should be electrically connected to 1V

, then the UVLO

REF

used,

or INTVCC. Otherwise, see HYST and the Applications Information section for using a resistor-divider network to implement personalized UVLO rising and UVLO falling settings.

OVLO (B5): Input Overvoltage Latchoff Programming Pin. LTM4641 pulls HYST low to inhibit regulation of its output voltage when OVLO exceeds 0.5V. If OVLO subsequently falls below 0.5V, the module’s output remains latched off; the LTM4641 cannot resume regulation of the output voltage until either the LATCH pin is toggled high or V

INL

is power cycled. If input overvoltage latchoff behavior is not desired, electrically short this pin to SGND. Do not leave this pin open circuit.

4641fe

pin FuncTions

LTM4641

CROWBAR (B9): Crowbar Output Pin. Normally logic low, with moderate pull-down strength to SGND.

When an output overvoltage (OOV) condition is detected, the LTM4641’s fast OOV comparator pulls CROWBAR logic high through a series-connected internal diode. If utilizing LTM4641’s OOV feature, CROWBAR should connect to the gate of a logic-level N-channel MOSFET configured to crowbar the module’s output voltage (MCB, in Figure 1).

Furthermore, the LTM4641 latches off its output when CROWBAR nominally exceeds 1.5V and latches HYST logic low (see HYST).

If not using the OOV protection features of the LTM4641, leave CROWBAR electrically open circuit.

(B10): Output Overvoltage Threshold Programming

PGM

Pin. The voltage on this pin sets the trip threshold for the inverting input pin of LTM4641’s fast OOV comparator. When left electrically open circuit, resistors internal to the LTM4641 nominally bias OV above the nominal V

feedback voltage (600mV) that the

to 666mV (OV

PGM

)—11%

PTH

control loop strives to present to the noninverting input pin of LTM4641’s fast OOV comparator. The aforementioned voltages correspond proportionally to the module’s OOV inception threshold and V tion, respectively. Altering the OV

’s nominal voltage of regula-

OUT

voltage provides a

PGM

means to adjust the OOV threshold; its DC-bias setpoint can be tightened with simple connections to external components (see the Applications Information section). Trace route lengths and widths to this sensitive analog node should be minimized. Minimize stray capacitance to this node unless altering the OOV threshold as described in the Applications Information section and Appendix F.

LATCH (C5): Latchoff Reset Pin. When a latchoff fault oc curs, the LTM4641 turns off its output and latches M

HYST

on to indicate a fault condition has occurred (see HYST). To configure the LTM4641 for latched off response to latchoff faults, connect LATCH to SGND. As long as LATCH is logic

;

low, the LTM4641 will not unlatch. Regulation can be re sumed by

cycling V

or by toggling LATCH from logic low

INL

to high. It is also permissible to connect LATCH to INTV this configures the LTM4641 for autonomous restart with a timeout delay (programmed by C

—see TMR).

TMR

If no latchoff faults are present when LATCH transitions from logic low to logic high, the LTM4641 immediately unlatches. If any latchoff fault is present when LATCH is high, a timeout delay timing requirement is imposed: the LTM4641 will not unlatch

until all latchoff fault-monitoring

pins meet operationally valid states for the full duration of the timeout delay. If LATCH becomes logic low before that timeout delay has expired, the LTM4641 remains latched off and the timeout delay is reset. Unlatching the LTM4641 can be reattempted by pulling LATCH logic high at a later time.

The following are latchoff fault conditions:

• CROWBAR activates (see CROWBAR)

• Input latchoff overvoltage fault (see OVLO)

• Latchoff overtemperature fault (when OTBH is logic

low; see TEMP and OTBH) LATCH is a high impedance input and must not be left elec-

trically open

circuit. LATCH can

be driven by a μController

in intelligent systems: a reasonable implementation for unlatching the LTM4641 is to pull LATCH logic high for the maximum anticipated timeout delay time—after which, HYST can be observed to indicate whether the LTM4641 has become unlatched.

(C6): Buffered 1V Reference Output Pin. Minimize

REF

capacitance on this pin, to assure the OV

and TEMP

PGM

pins are operational in a timely manner at power-up. 1V should never be externally loaded except as explained in the Applications Information section.

(C9-C12; D9-D12; E9-E12): Power Output Pins of

OUT

the LTM4641 DC/DC Converter Power Stage. All V pins are electrically connected to each other, internally. Apply output load between these pins and the GND pins. It is recommended to place output decoupling capacitance directly between these pins and the GND pins. Review Table 9. See the Layout Checklist/Example section of the Applications Information section.

(D1): V

ORB

internal to the µModule regulator. It is recom-

OSNS

mended to route this pin (differentially with V

Readback Pin. This pin connects to

OSNS

ORB

–

) to a test

point so as to allow the user a way to confirm the integrity

logic

REF

OUT

For more information www.linear.com/LTM4641

4641fe

LTM4641

pin FuncTions

of the remote-sense connections prior to powering up the

LTM4641. V feedback connection to V

–

(D2): V

ORB

–

internal to the µModule regulator. It is recom-

OSNS

mended to route this pin (differentially with V

can also be connected as a redundant

ORB

OSNS

–

Readback Pin. This pin connects to

on the user’s motherboard.

OSNS

ORB

) to a test point so as to allow the user a way to confirm the integrity of the remote-sense connections prior to powering up the

–

LTM4641. V feedback connection to V

can also be connected as a redundant

ORB

–

on the user’s motherboard.

OSNS

OTBH (D3): Overtemperature Behavior Programming Pin. When an overtemperature condition is detected (see TEMP), HYST pulls logic low to inhibit switching. If OTBH is connected to SGND, the LTM4641 latches HYST low. If OTBH is left floating, output voltage regulation can resume when the overtemperature event clears.

TMR (D4): Timeout Delay Timer and Power-On Reset (POR) Programming Pin. Connect a capacitor (C

) from TMR

TMR

to SGND to program the POR and timeout delay time of the LTM4641; 9ms delay time per nanofarad of capacitance. The minimum delay time

is ~90μs, when TMR is left electrically open circuit. Even though they use the same capacitor, the power-on reset and timeout delay timers operate independently of each other. Any nonlatching fault or latching fault will reset the respective timer to the full delay time without impacting the other timer.

The timeout delay time programmed by a C can be negated by pulling TMR to INTV

TMR

capacitor

RUN (D5): Run (On/Off) Control Pin. A RUN pin voltage below 0.8V will turn off the module. A voltage above 2V will command the module to turn on, if HYST is not as serted low by M (10k) pull-up resistor from HYST to INTV

. The LTM4641 contains a moderate

HYST

, and a pull-up

Schottky diode from RUN to HYST (see Figure 1). When RUN is pulled logic low, HYST is pulled logic low via the internal Schottky diode. RUN is compatible with directdrive (totem-pole output drive) as well as open-collector/ open-drain interfaces.

(H1): Positive Input to the Remote Sense Differ-

OSNS

ential Amplifier. This pin connects to the positive side of the output voltage remote sense point (V a resistor (R

). When regulating the output voltage,

SET1A

potential) via

OUT

the LTM4641 control loop drives the differential voltage between V SS and 0.6V. V

OSNS

the module (see V V

OSNS

to V

OSNS

–

and V

is connected to V

ORB

for some output voltage settings. (See

–

to the lesser of TRACK/

OSNS

internal to

ORB

). A resistor may be needed from

the Applications Information section: Setting the Output Voltage.) Minimize stray capacitance to this pin to protect the integrity of the output voltage feedback signal.

–

(H2): Negative Input to the Remote Sense Dif-

OSNS

ferential Amplifier. This pin connects to the negative side of the output voltage remote sense point (GND potential) via a resistor (R

). When switching action is on,

SET1B

the LTM4641 control loop drives the differential voltage between V SS and 0.6V. V

OSNS

the module (see V V

OSNS

to V

OSNS

–

and V

–

is connected to V

–

ORB

for some output voltage settings. (See

–

to the lesser of TRACK/

OSNS

–

internal to

ORB

). A resistor may be needed from

the Applications Information section.) Minimize stray capacitance to this pin to protect the integrity of the output voltage feedback signal.

SW (H10): Switching Node of the Power Stage. Mainly used for testing purposes, however, one may optionally connect a snubber (series-configured capacitor C resistor R

) from SW to GND to reduce radiated EMI—in

and

exchange for a minor compromise to power conversion efficiency. (See the Applications Information section.)

COMP (J1): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold of LTM4641’s valley current mode control loop—and correspondingly, the commanded trough of

the power inductor current—increases as this control voltage increases. It can be useful to make COMP available for observation on a PCB via or test pad with an oscilloscope probe. However, stray capacitance and trace lengths to this sensitive analog node should be minimized.

(J2): Switching Frequency Setting and Adjustment Pin.

SET

This pin interfaces directly to the ION pin of LTM4641’s internal control IC. Current flow into the ION pin programs the on-time of the control loop’s one-shot timer and power control MOSFET, M

. Minimize stray capacitance and

TOP

any tracelengths to this pin.

For applications requiring regulated output voltages of 3V or less at any time including during voltage rail tracking,

4641fe

For more information www.linear.com/LTM4641

pin FuncTions

LTM4641

an on-time adjustment with a resistor to f Otherwise, f

can be left open circuit. See the Applica-

SET

is required.

SET

tions Information section for details.

(J3): Input Voltage Pin, Low Current for Power

INL

Control and Logic Bias. Feeds LTM4641’s internal 5.3V LDO (see INTV

). Apply input voltage bias between this

pin and GND. Decouple to GND with a capacitor (0.1µF to 1µF). This pin powers the heart of LTM4641’s DC/DC controller and internal housekeeping ICs. V rent is within ~5mA of the sum of INTV

bias cur-

INL

and CROWBAR

loading currents.

If using the advanced output overvoltage (OOV) protection features of the LTM4641, connect V

to either the drain of

INL

the external power-interrupt power MOSFET, identified on the front page schematic as MSP, or a separate input bias supply. If not making use of the advanced OOV protection features, V

INL

and V

can connect directly to the same

INH

input power source.

LDO losses can be eliminated by connecting V and DRV

if a low power auxiliary ~5V rail is available to

, INTVCC,

INL

power the resulting node. (See the Applications Information section, Figure 47 and Figure 49.)

RVCC (J4): Power MOSFET Driver Input Power Pin. DRVCC

is normally connected to INTV diode drops (2 • V

or ~1.2V at 25°C) of INTVCC. DRVCC

. It must be kept within two

powers the internal MOSFET driver that interfaces to the switching MOSFETs (M

TOP

and M

power stage. It is pinned out separately from INTV

) within LTM4641’s

BOT

to allow gate-driver current to be observed, and to allow an auxiliary ~5V to 6V bias supply to optionally provide the MOSFET driver bias current. The INTV

/DRVCC pin pair

can be biased from up to 6V (absolute maximum) from an external supply with 50mA peak sourcing capability, to reduce the LTM4641’s INTV tions Information section and Figure connected directly to INTV

LDO losses (see Applica-

51). When DRVCC is

, no bypass capacitance is

needed except in rare applications where very fast output voltage ramp up is required (e.g., no soft-start capacitor on TRACK/SS, or rail-tracking rails with sub-60µs turn-on rise-time). Otherwise, ~2.2µF to 4.7μF X7R MLCC local bypassing to GND is recommended. Higher impedance sources may require higher bypass capacitance, to mitigate DRV

sag during V

start-up.

OUT

An undervoltage lockout detector monitors DRV pulled low and switching action is inhibited if DRV

. HYST is

is less

than 4.2V rising (maximum) and 3.5V falling (maximum).

FCB (K2): Forced Continuous/Pulse-Skipping Mode Opera

tion Programming Pin. Connect this pin to SGND to force continuous mode operation of the synchronous power MOSFETs (M

TOP

and M

Connect this pin to INTV

) at all output load conditions.

BOT

to enable pulse-skipping mode

operation: the freewheeling power switching MOSFET

) is turned off of to prevent reverse flow of output

BOT

current (I

) at light loads. See Appendix E for more

OUT

details. This is a high impedance input and must not be left electrically open circuit.

INTV

of V housekeeping circuitry. INTV DRV

(K4): Internal 5.3V LDO Output. LDO operates off

. The INTVCC rail biases low power control and

INL

is usually connected to

to power the MOSFET drivers interfacing to the

switching power MOSFETs. No decoupling capacitance is needed on this pin unless it is being used to bias external circuitry (not common); do not apply more than 4.7µF (±20% tolerance) of external decoupling capacitance. The INTV

/DRVCC pin pair can be overdriven by an external

supply, from up to 6V (absolute maximum) with 50mA peak sourcing capability, to eliminate power losses otherwise incurred by the LTM4641’s V

-to-INTVCC linear regulator

INL

(see the Applications Information section and Figure 51).

(K7-10; L7-12; M7-8, 11-12): Input Voltage Pin, High

INH

Current to the Power Converter Stage of the LTM4641. All V ternally. Devote a large copper of the V

pins are electrically connected to each other in-

INH

plane to connect as many

pins to each other as is feasible. This will help

INH

form a low impedance electrical connection between the input source and the LTM4641’s power stage. It will also provide a thermal path for removing heat from the BGA package and minimize junction temperature rise of the LTM4641 for a given application.

If utilizing the advanced output overvoltage (OOV) protec tion features of the LTM4641, connect V

to the source

INH

pin(s) of the external power-interrupt MOSFET, identified on the front page schematic as MSP, with a short wide trace, or preferably a small copper plane capable of adequately

4641fe

For more information www.linear.com/LTM4641

LTM4641

pin FuncTions

handling the input current to LTM4641’s power stage. Do not decouple the V

pins with any bypass capacitance

INH

in this case. Instead, place all decoupling capacitance directly between the drain of MSP to GND.

If not utilizing the advanced OOV protection features of the LTM4641, do decouple the V

pins to GND with

INH

local ceramic and bulk decoupling capacitance (see the Applications Information section).

PGOOD (L1): Output Voltage Power Good Indicator. This is an open-drain logic output pin that is pulled to ground when the output voltage (and accordingly, the divided-down representation of the output voltage, V

, as presented to

the control loop) is outside ±10% of the nominal target for regulation.

TRACK/SS (L2): Output Voltage Tracking and Soft-Start Programming Pin. This pin has a 1.0μA pull-up current source, typical. A capacitor can be placed from this pin to

SGND to obtain an output voltage soft-start ramp-up rate whose turn-on time is 0.6ms per nanofarad of capacitance. Alternatively, when a voltage is applied to TRACK/SS through a resistor-divider network from another rail, the LTM4641 output is able to track the external voltage to satisfy requirements.

coincident and ratiometric rail-voltage sequencing

See the Applications Information section.

(M9): Gate Drive Output Pin. If utilizing the advanced

ING

output overvoltage (OOV) protection features of the LTM4641, connect V

ING

to V

external power-interrupt N-channel MOSFET feeding V

and to the gate of the

INGP

INH

identified on the front page schematic as MSP; otherwise, leave this pin electrically open circuit.

(M10): Gate Drive Protection Pin. If utilizing the ad-

INGP

vanced OOV protection features of the LTM4641, connect

to V

INGP

N-channel MOSFET feeding V

and to the gate of the external power-interrupt

ING

, MSP; otherwise, leave

INH

this pin electrically open circuit.

4641fe

For more information www.linear.com/LTM4641

siMpliFieD block DiagraM

LTM4641

BOVPGM

HYST

TUV

BUV

TOV

MOV

BOV

TMR

TOVPGM

OVPGM

HYST

UVLO

IOVRETRY

OVLO

TEMP

OTBH TMR

LATCH

FCB COMP

DRV

INTV

PGOOD

TRACK/SS 1V

REF

PGM

RUN

DASHED BOXES INDICATE OPTIONAL COMPONENTS *R

REQUIRED FOR CERTAIN VIN/V

fSET

SEE APPLICATIONS INFORMATION SECTION SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND ROUTES/PLANES SEPARATE FROM GND, ON MOTHERBOARD

REF

3.48k

NTC

PROTECTION

COMPARATORS

FAULT LATCHES

OSC

REF

499k

AND

INTERNAL

4µF

COMP

COMBINATIONS

OUT

HYST

INTV

10k

ENABLE SWITCHING ACTION

VALLEY MODE

SYNCHRONOUS

CONTROLLER

TO E/A

FAST OUTPUT

OVERVOLTAGE

COMPARATOR

POWER

CONTROL

CONSTANT

ON-TIME

BUCK

ENABLE

8.2k

0.1µF

15V

ZENER

TOP

0.8µH

BOT

–

8.2k

R C

8.2k

1.3M f

SET

ING

INGP

INH

2.2µF

OUT

10µF

GND

SGND

CROWBAR

ORB

OSNS

ORB

4641 F01

INL

MSP

OUT(BULK)

SET1B

SET1A

  

= R

SET1A

8.2kΩ

SET1B

IN(MLCC)

fSET

MCB

–

SET2

= 0.6 1+

OUT

USE R

SET1A

REQUIRED FOR V

SET2

NOT NECESSARY FOR V

SET2

OUT

0.6V TO 6V UP TO 10A

OUT(MLCC)

2 •R

SET2

≤8.2k

OUT

4V TO 38V (4.5V START-UP)

IN(BULK)



SET1A

 

> 1.2V

≤ 1.2V

OUT

Figure 1. Simplified Block Diagram. cf. Functional Block Diagram in Appendix A, Figure 62

Decoupling requireMenTs

SYMBOL PARAMETER CONDITIONS

IN(MLCC)

IN(BULK)

OUT(MLCC)

OUT(BULK)

External Input Capacitor Requirement I

External Output Capacitor Requirement I

For more information www.linear.com/LTM4641

= 10A, 2 × 10μF or 4 × 4.7μF

OUT

= 10A, 3 × 100μF or 6 × 47μF

OUT

MIN TYP MAX

300

UNITS

μF

4641fe

LTM4641

operaTion

Introduction

The LTM4641 contains a buck-topology regulator employ-

constant on-time current mode control scheme,

ing a including built-in power

MOSFET devices with fast switching speed and a power inductor. In its most basic configuration (see Figure 45), the module operates as a standalone nonisolated switching mode DC/DC step-down power supply. It can provide up to 10A of output current with a few external input and output capacitors and output feedback resistors. The supported output voltage range is from 0.6V DC to 6V DC. The supported input voltage range is 4V to 38V, with a maximum start-up voltage of 4.5V (over temperature). Power conversion from lower input voltages can be realized if an auxiliary bias supply is avail

able to power LTM4641’s control and housekeeping bias input pin, V

. The LTM4641 Simplified Block Diagram is

INL

found in Figure 1. For a more detailed look, the Functional Block Diagram is found in Appendix A, Figure 62.

Motivation

Pulsed loading conditions and abnormal disturbances within the electrical systems found in industrial, vehicle, aeronautic, and military applications can induce wildly varying voltage transients (surges) on what is nominally a 24V DC to 28V DC distributed bus (28V DC duration of such disturbances

can extend for periods of

bus). The

time between a millisecond to a minute in length, with excursions sometimes reaching (or exceeding) 40V and falling below 6V.

While switching buck regulators are of universal interest due to their compact size and ability to deliver DC/ DC power conversion at

high efficiency, FMEA (failure modes and effects analysis) leads one to believe that there is no way to reduce the severity rating and effects of an electrical short from the input source to the output load—however improbable. The LTM4641 challenges this notion by protecting the load from seeing excessive voltage stress, even when its high side switching MOSFET is short circuited.

Power µModule Regulator Reliability

First and foremost, Linear Technology μModule products adhere to rigorous testing and high reliability control, fabrication, and manufacturing processes—as is required of all its products. Furthermore, as part of its commit ment to program periodically updates its

excellence, the Linear Technology Quality Control

Reliability Data report

for LTM4600 series products to include cumulative data obtained from ongoing and routine in-house testing relating to operational life, highly accelerated stress, power and temperature cycling, thermal and mechanical shock, and

more. To view the latest report visit http://www.

much linear.com/docs/13557.

The LTM4641 easily supports high step-down ratios with few external components. The additional protection features when implemented provide an extra degree of insurance beyond other μModule regulators.

Overview

When configured as shown in Figure 46, the LTM4641 can regulate an output voltage between 0.6V and 6V from an input voltage between 4V and 38V (4.5V

start-up,

maximum).

If an optional N-channel power MOSFET, MSP, is placed between the input power source (V stage input pins (V

), MSP’s role becomes that of a

INH

) and the power

resettable electronic power-interrupt switch. The gate of MSP is operated by V

, and its gate-to-source voltage

ING

is assured to be clamped by a built-in 15V Zener diode accessed via V

charges the gate of MSP to nominally 10V above

ING

potential—suitable for driving a standard-logic MOS-

INH

FET—and MSP becomes enhanced to

. When switching action is engaged,

INGP

pull V

up to the

INH

input source supply’s electrical potential. The switching regulator steps down V

potential to V

INH

when MSP is

OUT

on. When switching action is inhibited by pulling the RUN pin low or when

a fault condition is detected by LTM4641’s internal circuitry—such as an output overvoltage (OOV) condition—the gate of MSP is discharged and MSP turns off. The input source supply is thus disconnected from LTM4641’s power stage input (V

INH

4641fe

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applicaTions inForMaTion—power supply FeaTures

LTM4641

The operation of MSP as a power interrupter provides a critical element of robust OOV protection: it removes a means for input power to flow through a damaged power stage to any precious loads on the output voltage rail, even when input power is cycled.

For even greater resilience to a short-circuit between V

INH

and the SW switching node of the power stage, an external logic-level N-channel power MOSFET, MCB, is optionally placed—in a crowbar configuration—on the output of the power module. When an OOV condition is detected, CROWBAR turns on MCB (within 500ns, maximum) to discharge the output capacitors and transform any residual energy in LTM4641’s power stage into a trivial amount of heat—energy which would otherwise have only served to inject charge into (further pump up the voltage on) the output capacitors, where precious loads reside.

The control and monitoring circuitry within the LTM4641 power module provide the following:

• Fast, accurate, latching output overvoltage detector (<500ns response time, <±12mv threshold error)

• N-channel output overvoltage crowbar power MOSFET drive

• Accurate (<±2.4%) nonlatching and resettable latching input overvoltage shutdown thresholds

• N-channel overvoltage power-interrupt MOSFET

Accurate (<±2.4%) Input UVLO rising and UVLO falling

•

drive

thresholds

• Built-in and adjustable overtemperature shutdown protection, programmable for resettable latching or nonlatching (hysteretic restart) response

• Analog temperature indicator output pin

• Adjustable power-on reset and timeout delay time

• Latchoff behavior that can be altered to instead provide

autonomous restart after timeout delay time expires

• Parallelable for higher output power

• Differential remote sensing of POL voltage

• Internal loop compensation

• Output current foldback protection

• Selectable pulse-skipping mode operation

• Output voltage soft-start and rail tracking

• Power-up into pre-biased conditions without sinking

current from the output capacitors

• Adjustable switching frequency

• Power good indicator

• RUN enable pin

Novel and simple circuit implementations with LTM4641 and a few external components enable surge ride-through protection and overtemperature detection of a powerinterrupt MOSFET. (See Figure 47, for example.) The aforementioned features enabled by LTM4641 are grouped by function and described in the remainder of the Applica tions Information section.

Power (V

) and Bias (V

INH

LTM4641’s power stage (V

) Input Pins

INL

) and control bias (V

INH

input pins are brought out separately to allow freedom for implementing more sophisticated system configura tions, such as: fully utilizing LTM4641’s advanced output overvoltage (OOV) protection features to protect (e.g., front page schematic or Figure 46); providing rudimentary input

surge ride-through protection

(Figure47); performing DC/DC down conversion from a power rail below LTM4641’s inherent UVLO thresholds (from a 3.3V bus in Figure 49).

If V recommended to power up V with V

3.5V within 2ms of V dation to sequence V

INH

and V

. V

INH

are powered from separate rails, it is

INL

prior to or concurrently

INL

should have a final value of at minimum

INL

exceeding 3.5V. The recommen-

INH

ahead of or closely with V

INL

not related at all to module device reliability but stems rather from a desire to assure that the control section of LTM4641 drives the MOSFETs in LTM4641’s power stage deterministically whenever any appreciable V is present. It is always permissible for V present—regardless of the state of V that there is no UVLO detection on V

—however, realize

INH

voltage to be

INL

To prevent the control section from trying to regulate through a dropout condition or commencing switching activity in the absence of V

potential, it is recommended

INH

)

INL

the load

INH

voltage

4641fe

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LTM4641

0.7V • 10pF

ION

1.3MΩ

2ms/DIV

4641 F02

500mV/DIV

applicaTions inForMaTion—power supply FeaTures

to implement a custom UVLO falling setting above the dropout curve in Figure 4 (see also Figure 11).

LT3010-5 is shown in Figure 47 to provide bias for V to enable ride-through of 80V transients on V detection of V a discharge path for V

and V

INH

ing requirement, only that V whenever V

and V

INL

is realized in this example by D2 creating

in the event of loss of VIN.

INL

have no specific power-down sequenc-

INL

should stay above 3.5V

INL

is above 3.5V.

INH

sequencing is inherently addressed by the

INH

INL

. UVLO

LTM4641 in the Figure 45 and Figure 46 circuits.

The V

and V

start-up and shutdown waveforms of the

INL

Figure 47 circuit—but with 1Ω output load and TMR tied to INTV ing capacitor, C

—are shown in Figure 2. The effect of the tim-

, that normally generates a power-on

TMR

reset (POR) delay at start-up is negated by tying TMR to INTV

. The ~3ms VIN-to-V

start-up delay time seen in

OUT

Figure 2 is due to POR of the LTM4641’s fault-monitoring circuitry and soft-start ramp (C

5V/DIV

INL

5V/DIV

OUT

scheme. During a load transient step-up, the control loop will command a compensate fo

r a defi

higher inductor trough current to

ciency in output voltage; the effective switching frequency will increase until the output voltage returns to normal (an overcurrent event, notwithstanding). During a load transient step-down, the control loop will command a lower inductor trough current to compensate for an excess of output voltage; the effective switching frequency will decrease until the output voltage returns to normal. The control loop perceives inductor current-sense information via the voltage signal that appears across the synchronous power MOSFET, M

, when M

BOT

(this is commonly referred to in the industry as R

BOT

is on

DS(ON)

current sensing).

The on-time of the one-shot timer—and hence the power control MOSFET, M

tON=

where I

is in units of amperes. For output voltages

ION

,—is given, in units of seconds, by:

TOP

(1)

greater than 3V, and for non-rail-tracking applications, no external R

resistor is needed, and the I

fSET

(units: amperes) is set solely by the V volts) and the internal 1.3MΩ V

ION

INL

-to-f

voltage (units:

INL

SET

current

ION

resistor:

(2)

Figure 2. Start-Up and Shutdown Waveforms of Figure 47 Circuit. TMR Tied to INTVCC to Highlight VIN and V Sequencing without POR Delay. 1Ω Load

INL

Switching Frequency (On Time) Selection and Voltage Dropout Criteria (Achievable V

-to-V

Step-Down

OUT

Ratios)

The LTM4641 controller employs a current mode constant on-time architecture, in which the COMP voltage corre sponds to the trough inductor current at which the internal high side power MOSFET

) is commanded on by

TOP

the control loop—for a duration of time proportional to controller’s I

pin current (Refer to Figure 1). Regulation

is maintained by a pulsed frequency modulation (PFM)

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The switching frequency of operation of the LTM4641’s buck converter power stage at full load in this scenario is given, in Hz, by:

fSW=

where V

0.7V • 1.3MΩ • 10pF

is the desired nominal output voltage, in units

OUT

(3)

of volts.

An external R greater than 3V, if desired, to obtain increased switching

resistor can be applied when setting V

fSET

OUT

frequency. Usually, increasing switching frequency comes from a desire to reduce output voltage ripple and/or output capacitance requirement—but at a moderate penalty to DC/DC conversion efficiency. There are some limitations to how low an R

value can be applied in practice due

fSET

4641fe

applicaTions inForMaTion—power supply FeaTures

fSET

( )

• I

LTM4641

to non-zero minimum off-time, dropout voltage, and maximum achievable switching frequency of operation.

When an R nected between V on-time setting, the total I

resistor external to the LTM4641 is con-

fSET

INL

and f

to decrease the default

SET

current (units: amperes) is

given by:

ION

where V R

fSET

equal to 3V

INL

1.3MΩ

is in units of volts and R

INL

is needed for output voltage settings less than or

OUT

INL

1.3MΩ ||R

fSET

is in units of ohms.

, and for rail-tracking applications.

(4)

The minimum on-time the LTM4641 supports is 43ns, typical, but Therefore, for a conser than 75ns, typical. From Equation 1, it follows that I

guard banded conservatively to 75ns, maximum.

vative design, t

should be larger

ION

should be designed to be less than 93.3μA.

When an external R

fSET

(and V

INL

and R

resistor is applied between V

fSET

and V

are operating from the same

INH

INL

rail—Figure 45 and Figure 46), the switching frequency of operation of the power stage at full load, in Hz, is given by:

fSW=

where R

0.7V • 1.3MΩ|| R

is in ohms, and V

fSET

OUT

• 10pF

fSET

OUT

is the desired nominal

(5)

output voltage, in units of volts.

In the general case, the switching frequency of the buck converter power stage at full load is given, in Hz, by:

fSW=

INH

OUT

• t

OUT

• 0.7V • 10pF

INH

ION

(6)

• When V

INL

and V

are operated from separate

INH

supplies…

… why should R

source rather than V

…when is it okay for R

ordinarily connect to the VIN power

fSET

(Figure 49)?

INH

to connect to V

fSET

INH

(Figure 47)?

For application circuits

of the form found in Figure 45, Figure 46, Figure 47 and Figure 51: see Figure 3 for the maximum recommended value of R

as a function

fSET

of nominal target output voltage, and resulting full-load switching frequency corresponding to those R

fSET

values.

Figure 3 can also be interpreted to provide the lowest recommended switching frequency for a given target output voltage. Table 1 summarizes nominal values of

endorsed for some popular output voltages; use

fSET

of commonly available ±5% tolerance resistors or better with ±100ppm/°C temperature coefficient or better is recommended.

fSET

4641 F03

700

TYPICAL f

600

500

AT FULL LOAD (kHz)

400

300

200

100

vs V

fSET

VALUE (MΩ)

fSET

0.5

MAXIMUM RECOMMENDED R

0.1 0 0.5 1 1.5

OUT

REGION

TO AVOID

MAX RECOMMENDED R SWITCHING FREQUENCY

2 2.5 3 3.5 4 4.5 5 5.5 6

NOMINAL OUTPUT VOLTAGE (V)

NOT

fSET

NEEDED FOR

> 3V

OUT

See Appendix C for a detailed discussion on the following topics:

Figure 3. Maximum Recommended R Non-Tracking Applications, and Resulting Full-Load Operating Switching Frequency vs Nominal Output Voltage

(Nominal Values) for

fSET

• Why should the switching controller be operated at a higher switching frequency (i.e., programmed for a shorter on-time with R internal 1.3MΩ V

INL

-to-f

) than that yielded by the

fSET

resistor alone…

SET

…for nominal output voltages of 3V and less?

…in rail-tracking applications?

4641fe

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LTM4641





applicaTions inForMaTion—power supply FeaTures

Table 1. Endorsed R Non-Tracking Applications—and Resulting Full-Load Switching Frequency (cf. Figure 45, Figure 46, Figure 47, and Figure 51 Circuits)

Greater Than 3.0 ∞ (Not Used) See Figure 2

(V)

OUT(NOM)

0.6 0.787 175

0.7 0.825 200

0.8 0.887 215

0.9 0.931 235

1.0 1.00 255

1.2 1.13 285

1.5 1.43 315

1.8 2.00 325

2.0 2.55 330

2.5 5.76 335

3.3 ∞ (Not Used) 360

5.0 ∞ (Not Used) 550

6.0 ∞ (Not Used) 660

Resistor Value vs Output Voltage for

fSET

(MΩ) (Nearest

fSET

EIA-Standard Values) f

(kHz)

In rail-tracking applications, it is recommended to use the

value corresponding to the lowest voltage needed

fSET

to be regulated during output voltage ramp down. For example: to ramp V

down to 0.5V requires R

OUT

fSET

to be

not more than 750kΩ (nominal) per Figure 3.

It is often permissible to use lower R

values than those

fSET

indicated in Figure 3 and Table 1 if, for example, lower output ripple voltage and/or a lower output capacitance is desired. However, be aware of three guiding principles:

I. Minimum On-Time. Ensure I

< 93.3µA. See Equa-

ION

tions1 and 4.

Minimum Off-Time and Dropout Operation. The mini-

II.

mum off

-time, t

OFF(MIN)

, is the shortest time required for the LTM4641 to perform the following tasks: turn on its power synchronous

MOSFET (M control loop’s current comparator, and turn off M The minimum input voltage on V

, in volts, that one

INH

), trip the

BOT

can regulate the output at and still avoid dropout is given by:

IN(DROPOUT)

= V

OUT

• 1+

 

OFF(MIN)

 

+ R

PS•IOUT

(7)

where:

• V

• t

is nominal output voltage in volts.

OUT

OFF(MIN)

be on, after M

is the minimum length of time M

turns off. For a conservative de-

TOP

sign, use a value of 300ns, taken from the Electrical Characteristics Table.

is the on-time of the power control MOSFET,

•

, as programmed by the current flowing into

TOP

the I

• R stage, from V

pin of LTM4641’s internal control IC.

is the series resistance of the module’s power

INH

to V

. For VIN ≥ 6V, this is less

OUT

than 50mΩ, even at extreme temperatures (T 125°C). For V increases due to drop in INTV

< 6V, the effective series resistance

voltage and cor-

responding decreased gate-drive enhancement of

. Printed circuit board (PCB) and/or cable

TOP

resistance present in the copper planes and/or wires that physically connect the output of the module to the load adds to R

• I

is the load current on V

OUT

’s effective value.

in amperes.

OUT

For applications of the form shown in Figure 45, Figure46 and

Figure 47: the minimum allowable V voltage of operation to avoid dropout for 3V < V ≤ 6V is shown in Figure 4. The curves are a result of realizing that V

IN(DROPOUT)

equals V

(neglecting

INH

MSP voltage drop) when dropout actually occurs, and that Equations 1 and 2 yield an expression for t

. M

a function of V

INH

during its on-time if DRV value of 5.3V (for example, when V DRV R

bias is provided by INTVCC). DRVCC’s effect on

at low line is illustrated in Figure 4.

III. Maximum Attainable f

will be less fully enhanced

TOP

is less than its nominal

< 6V and when

INL

. The maximum attainable

switching frequency of operation (in units of Hz) for a given on-time (t

MAX

tON+ t

, in seconds) is governed simply by:

OFF(MIN)

where a conservative value of 300ns can be used for

OFF(MIN)

BOT

can

INH

OUT

≈

(8)

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applicaTions inForMaTion—power supply FeaTures

OUT

SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP MODULE SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

, C

: FEEDFORWARD CAPACITORS YEILD IMPROVED TRANSIENT

LTM4641

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

LINE DROPOUT VOLTAGE (V)

4.0

3.5

3.0

3.5

OUTPUT VOLTAGE SETTING (V)

10A OUTPUT, DRVCC BIASED FROM INTVCC (5.3V 10A OUTPUT, DRV NO LOAD, DRV

(UVLO FALLING)

4.5

BIASED TO 5.3V BY EXTERNAL SUPPLY

≥ 4.2V(UVLO RISING) AND 3.5V

5.5

4641 F04

NOM

)

Figure 4. Line Dropout Voltage vs Output Voltage at No Load and Full Load. Figure 45, Figure 46 and Figure 47 Circuit Applications. R Setting V

OUT

= Open and R

fSET

SET1A

, R

SET1B

for Regulation at or Above 3V

, R

SET2

Values

Given that the PFM control scheme increases switching

frequency (to as high as f

) to maintain regulation

MAX

during a transient load step-up, the design guidance is: set the steady-state operating frequency f less than f

. Furthermore, when the LTM4641 is

MAX

to be

in dropout operation, the switching frequency of the converter is f

MAX

It is best to avoid operation in dropout scenarios, because the control loop will rail COMP high to command M

TOP

at highest possible duty cycle. If input voltage “snaps upwards” at a sufficiently high slew rate when COMP has railed, the control loop may be unable provide satisfactory line rejection.

See Figure 11 to set the UVLO falling response of LTM4641 above the computed V switching action for V

IN(DROPOUT)

< V

IN(DROPOUT)

voltage; this will inhibit

. Input voltage ripple,

and any line sag between the input source supply and the

pins—and voltage drop across the power interrupt

INH

MOSFET, MSP, if used—must be taken into account by the system designer.

Setting the Output Voltage; the Differential Remote Sense Amplifier

A built-in differential remote-sense amplifier enables preci

sion regulation at the point-of-load (POL), compensating for any voltage drops in the system’s output distribution path: the total variation of LTM4641’s output DC voltage over line, load, and temperature is better than ±1.5%.

The basic feedback connection between the POL and the module’s feedback sense pins is shown in Figure 5.

TO ERROR

AMPLIFIER

TRUE DIFFERENTIAL REMOTE

Figure 5. Basic Feedback Remote Sense Connections and Techniques; Setting the Output Voltage

FFA

RESPONSE WHEN FILTERING V (C

OUT(MLCC)

OUT

LTM4641

ICT TEST

ORB

8.2k V

8.2k

OSNS

SGND

ORB

GND

SENSE AMPLIFIER

–

8.2k

POINT

–

ICT TEST POINT

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FFB

)

SET2

PLACE ALL

FEEDBACK COMPONENTS LOCAL TO THE

LTM4641

FFA

SET1A

SET1B

FFB

WITH ONLY MLCC OUTPUT CAPACITORS

OUT

OUT(BULK)

ROUTE FEEDBACK SIGNAL AS

A DIFFERENTIAL PAIR (OR

TWISTED PAIR IF USING WIRES).

SANDWICH BETWEEN GROUND

PLANES TO FORM A PROTECTIVE SHIELD

GUARDING AGAINST STRAY NOISE

OUT(MLCC)

LOAD

4641 F05

4641fe

LTM4641





2 • R

0.6

8.2kΩ





applicaTions inForMaTion—power supply FeaTures

The output voltage at the POL is differentially sensed via a symmetrical impedance-divider network. In Figure 1 and Figure 5, it is seen that the control loop regulates the output voltage such that the differential V

OSNS

-to-V

OSNS

–

feedback signal voltage is the lesser of the TRACK/SS pin voltage or the regulator’s nominal bandgap voltage of 600mV. The arrangement and values of the resistors in the symmetrical impedance-divider network set the output voltage.

The remote sense pins (V

OSNS

, V

–

) have redundant

OSNS

connections internal to the module to readback pins (V

ORB

, V

–

). The readback pins provide a means to

ORB

verify the integrity of the feedback signal connection during motherboard

ICT (in

circuit test). The importance of verifying the integrity of the connection of the feedback signal to the output voltage prior to powering up the input voltage cannot be understated. If one or both feedback pins are left electrically floating due to manufacturing as sembly defect

, for example, or

if the remote-sense pins

are short circuited to each other, the control loop and overvoltage-detector circuitry have no awareness of the actual output voltage condition. A compromised

feedback connection presents a very real danger of (1) the control loop commanding on M

at the highest possible duty

TOP

cycle—due to the lack of negative feedback—and (2) the LTM4641’s protection circuitry being unaware of any issue. In a production environment, modern day ICT can easily catch any such stuffing or assembly errors; in a lab or prototyping environment, an ohmmeter can do the job.

For many applications that use a mixture of MLCC and bulk (low ESR tantalum or polymer) output capacitors, the symmetrical impedance-divider network that feeds back the POL’s voltage to the module need only be constructed with resistors R

1.2V

and lower. R

OUT

SET1A

and R

SET2

voltages in excess of 1.2V

OUT

, for output voltages of

SET1B

must be present for output

. R

SET1A

and R

SET1B

should always have the same nominal value. Applications with MLCC-only output capacitors (see Output Capacitors and Loop Stability in following pages) will demonstrate improved transient response when feedforward capaci

FFA

and C

tors C electrically in parallel with R

, nominally equal in value, are installed

FFB

SET1A

and R

, respectively.

SET1B

Use of 0.1% tolerance resistors (or better) for R R

SET1B

, and R

are recommended—with temperature

SET2

SET1A

coefficients of resistance suitable for one’s operating range of PCB temperature—to assure that output voltage error introduced by resistor value variation is acceptable for the application. SMT resistors with T.C.R.s of ±25ppm/°C and better are readily available in the marketplace.

For output voltage settings less than or equal to 1.2V

is not needed, and R

SET2

SET1A

= R

SET1B

OUT

 

0.6V

For output voltages above 1.2V

SET1A

– 1

and R

• 8.2kΩ

 

, R

OUT

SET1B

SET1A

(and R

are given by:

OUT

(9)

SET1B

) should be set equal to 8.2kΩ (or less, if 8.2kΩ is not a convenient value for the user), and

–

SET1A

− 1

SET2

OUT

It is always permissible to select a value for R R calculate a valid value for R long as R

) less than that given by Equation 9—and then

SET1B

from Equation 10—as

SET2

SET1A

and R

are designed to withstand the

SET1B

is then given by:

RSET2

SET1A

(10)

(and

higher resulting power dissipation.

When V

–

OSNS

VOSNS

is in regulation, the voltages at V

OUT

are given by:



8.2kΩ ||R

( )



• R

( )

SET1A

0.6V

SET1A

||16.4kΩ

||R

SET2

∆V

OSNS

GND

SET1A

and



(11)

 

and

–

VOSNS

= V

respectively. ∆V

VOSNS

– 0.6V (12)

is the voltage drop between ground at

GND

the POL and LTM4641’s SGND pins in volts. This voltage drop is usually entirely a result of I • R drop in the output distribution path—largest when maximum load current is being drawn:

∆V

GND

= V

GND(POL)

– V

SGND(LTM4641)

(13)

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applicaTions inForMaTion—power supply FeaTures





LTM4641

With R

SET1A

, R

SET1B

, and R

determined, double-check

SET2

the output voltage setting with:

= 0.6V • 1+

OUT

 

SET1A

8.2kΩ

Some recommended values for R

2 • R

SET1A

SET2

, R

 

SET1B

, and R

(14)

SET2

for popular output voltages are shown in Table 2.

Table 2. Recommended R for Some Popular Output Voltages, cf. Figure 5 Feedback Connections.

OUT

0.6V 0Ω ∞ (Not Used)

0.7V 1.37kΩ ∞ (Not Used)

0.8V 2.74kΩ ∞ (Not Used)

0.9V 4.12kΩ ∞ (Not Used)

1.0V 5.49kΩ ∞ (Not Used)

1.2V 8.2kΩ ∞ (Not Used)

1.5V 8.2kΩ 33.2kΩ

1.8V 8.2kΩ 16.5kΩ

2.0V 8.2kΩ 12.4kΩ

2.5V 8.2kΩ 7.5kΩ

3.3V 8.2kΩ 4.7kΩ

5.0V 8.2kΩ 2.61kΩ

6.0V 8.2kΩ 2.05kΩ

SET1A

, R

SET1B

and R

SET2

Values

SET2

See Appendix D for a detailed discussion on the following topics:

• What is the rationale for using a symmetrical resistor network?

• What should I do if I cannot shield the differential sense feedback lines with GND? (I anticipate differential mode noise in the feedback signal?)

• What should I do if the module and the load(s) are separated by a significant distance (~50cm or more), or if the load current flows through a cable assembly

or power connector? (I anticipate common mode noise in the feedback signal?)

Input Capacitors

The LTM4641 module should be connected to a low AC impedance, nominally DC output voltage source. MLCC input bypass capacitors must be provided externally, as

in proximity to the module

as possible (see Figure43). If external MOSFET MSP is not used (Figure 45), two 10μF or four 4.7μF ceramic capacitors should be electrically connected directly between the V

and GND pins. If MSP

INH

is used (Figure46, Figure47 and Figure 49), then MSP must be placed as close to the LTM4641’s V

pins as

INH

possible, and two 10μF or four 4.7μF ceramic capacitors should be electrically connected directly between the drain of MSP and GND (see Figure 44). A 47μF to 100μF surface mount bulk capacitor can be used to supplement input power bypassing, and can share the burden of any local ceramic capacitors in filtering the power stage’s ripple current. If low impedance power planes are used to bring V

to the vicinity of the module, input source

impedance will be low enough that bulk capacitors will not be needed. A localized bulk input capacitor is needed when an underdamped LC-resonant tank is formed by routing long input leads or traces (low ESR inductance) bypassed only with MLCCs (ultralow ESR capacitance).

Neglecting the inductor peak-to-peak current ripple, the RMS current of the input capacitor can be estimated as:

CIN(RMS)

OUT(MAX)

• D• 1– D

( )

(15)

where η is the power conversion efficiency of the LTM4641 module and D is the duty cycle on-time of M

. The bulk

TOP

capacitor can be a switcher-rated electrolytic aluminum capacitor or a polymer capacitor.

For a buck converter, the switching duty cycle of M

TOP

can be estimated as:

OUT

D =

(16)

Output Capacitors and Loop Stability/Loop Compensation

The current mode constant on-time architecture enables very high step-down input-to-output ratios with compelling transient

response. It also

enables cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. The LTM4641 is internally compensated to yield stability over all operating conditions.

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LTM4641

applicaTions inForMaTion—power supply FeaTures

The output capacitors C

OUT(BULK)

and C

OUT(MLCC)

must be chosen with low enough effective series resistance (ESR) to meet the output voltage ripple requirements and provide localized bypassing for the load. Although the LTM4641 provides fast transient response, the output voltage at the POL is reliant on nearby charge stored in a reservoir of ceramic capacitors C

OUT(MLCC)

to minimize sag and overshoot in the initial microseconds of a high dI/dt transient If used, C

OUT(BULK)

load step-up and

can be comprised of low ESR tantalum

step-down, respectively.

or low ESR polymer capacitor(s); these capacitors then serve as a local reservoir to replenish the MLCCs during transient load events. It is also possible to use C

OUT(MLCC)

only, however, the use of feedforward capacitors, CFF, should then be installed in the remote-sense feedback path, to obtain an optimized transient response (see Figure5 feedback connections).

The C

OUT(MLCC)

ceramic capacitors should be at least X5R-type material. X5R-type and X7R-type MLCCs are recommended when operating PCB temperatures are not more than 85°C and 125°C, respectively. Both materials

renown in the industry for having a relatively low ca-

are pacitance change over

their respective

temperature range of operation (±15%). However, X5R and X7R MLCCs do exhibit significant loss of capacitance with applied DC voltage and are subject to aging effects, and this must be taken into account in any system design. Refer to the capacitor manufacturer’s specifications for details.

The typical output capacitance range is between 200μF to 800μF. The system designer should use discretion in determining whether additional output filtering may be needed, if further reduction of output ripple—or output voltage deviation during dynamic load or line transient events—is required.

In Table 9, guidelines are provided for output capacitor selection, for various operating conditions. The table optimizes total equivalent ESR and total bulk capacitance for the transient load step performance. Stability criteria is considered. The Linear Technology LTpowerCAD™ de sign tool

is available for transient simulation and stability

analysis, if desired.

Pulse-Skipping Mode vs Forced Continuous Mode

In applications where high

DC/DC conversion efficiency at light-load currents is highly desired—when the input voltage source is a battery, for example—pulse-skipping mode operation should be employed. Pulse-skipping mode operation prevents to the input sour sulting asynchronous operation at light

power flow from the output capacitors

ce. Be aware, however, due to M

BOT

load, applications

’s re-

employing pulse-skipping mode may necessitate more output capacitance and/or a higher OV

setting than

PGM

operation in forced continuous mode would.

Pulse-skipping mode is activated by connecting FCB to INTV

. Forced continuous operation is activated by con-

necting FCB to SGND.

Be aware that in (say, less than 20mA out), the V

pulse-skipping mode and ultralight loads

voltage may appear as

ING

a sawtooth waveform as a result of being charge-pumped at a slower rate, to conserve energy.

See Appendix E for more information on how pulse-skipping mode works.

Soft-Start, Rail-Tracking and Start-Up Into Pre-Bias

The TRACK/SS pin can be used to either soft-start the output of the LTM4641 regulator, or make LTM4641’s output voltage track another rail coincidentally or ratio

metrically. When RUN or HYST is low, the TRACK/SS pin is discharged. When RUN and HYST are released, TRACK/SS sources a microamp of current.

When a soft-start capacitor, CSS, is applied to the pin, the current source is responsible for gene

rating an output voltage turn-on time of 0.6ms per nanofarad of capacitance. The power stage is

high impedance (M

TOP

and M

are off) until the TRACK/SS pin voltage exceeds V

BOT

, the remote-sense differential amplifier’s output voltage. This allows power-up into pre-biased output voltage conditions without sinking of current from the output capacitors. When TRACK/SS exceeds the control IC’s 600mV bandgap voltage, V

is regulated at 600mV and V

reaches its

OUT

nominal output voltage.

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applicaTions inForMaTion—power supply FeaTures









TIME

MASTER

OUTPUT VOLTAGE

4641 F06a

TIME

MASTER

OUTPUT VOLTAGE

4641 F06b

LTM4641

Figure 6 shows idealized output voltage waveforms for applications in which LTM4641’s output (V a master rail (V respectively.

To configure LTM4641 for coincident or ratiometric tracking, begin the design (initially) the same way as for nontracking applications:

(1) Determine the R

(2)

) tracks

OUT

MASTER

Figure 6. Tw o Different Modes of Output Voltage Tracking

) coincidently and ratiometrically,

OUT

(6a) Coincident Tracking

OUT

(6b) Ratiometric Tracking

SET1A

, R

SET1B

, and R

SET2

values ap-

propriate for the final, “full-scale” (FS) output voltage.

Determine the R

resistor needed to guarantee

fSET

ramp down of the output voltage to the desired value. For example, if it is necessary for V to 0.8V while tracking the master rail, then R

to ramp down

OUT

fSET

recommended from Table 1 to be ~887kΩ. If rampdown tracking is not needed, then R

can be chosen

fSET

according to Table 1 (or Figure 3) and the FS output voltage of the LTM4641 generated rail.

(3) Choose output capacitors and input capacitors for the

design in the same manner as is done for nontracking applications.

To fulfill a coincident rail-tracking requirement, recognize that when the output voltage of the master rail reaches the tracking rail’s nominal FS voltage, the TRACK/SS pin of the LTM4641 (tracking slave) needs to be 600mV. This can be satisfied by forming a resistor-divider network composed of R

TAC

and R

, interfacing V

TBC

OUT_MASTER

TRACK/SS of the LTM4641 tracking slave, and terminating to SGND of the LTM4641 tracking slave. In Figure 7 and Figure 8, U1 generates a master rail while U2 generates a coincident-tracking rail that follows U1’s output. Values of R

TAC

and R

are selected such that:

TBC

OUT_SLAVE_C (FS OUTPUT)

 

0.6V

– 1

•R

 

In the example circuit of Figure 7, the master rail generated by U1 ramps up its output to 1.8V. The coincident-tracking rail is generated by U2 and has a nominal FS output voltage of 1V. Values of R

TAC

and R

are determined

TBC

such that when U1’s output reaches 1V, the TRACK/SS pin of U2 reaches ~600mV; choosing R yields R

= (1V/0.6V – 1) • 10kΩ, or ~6.65kΩ. It is

TAC

TBC

common to choose resistor values of 10k or less for this task, so that voltage offset errors introduced by the 1µA current source on TRACK/SS working into the R

TAC/RTBC

network are sufficiently small.

To fulfill a ratiometric rail-tracking requirement, recognize that when the output voltage of the master rail reaches its final FS value, the TRACK/SS pin of the LTM4641 (tracking slave) needs to reach 600mV. This can be satisfied by forming a resistor-divider network composed of R and R

, interfacing V

TBR

OUT_MASTER

to TRACK/SS of the LTM4641 tracking slave, and terminating to SGND of the LTM4641 tracking slave. In Figure 7 and Figure 8, U3 generates a ratiometric-tracking rail that follows output. Values of R

TAR

and R

TAR

OUT_MASTER (FS_OUTPUT)

 

0.6V

are selected such that:

TBR

•R

– 1

 

(17)

TBC

to be 10kΩ

TAR

U1’s

(18)

TBR

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LTM4641

applicaTions inForMaTion—power supply FeaTures

4V TO 38V

(4.5V START-UP)

U1 V

OUT

SOFTSTART

IN nF)

INM(BULK)

50V

RAMP TIME

= 0.6ms/nF • CSS

INSC(BULK)

50V

OUT_MASTER

6.65k

R 10k

INSR(BULK)

50V

OUT_MASTER

R 20k

R 10k

Figure 7. Examples of LTM4641 Performing Coincident and Ratiometric Rail-Tracking. cf. Figure 8 Waveforms

INM(MLCC)

10µF

R 2M

MfSET

50V ×2

UVLO

HYST FCB

INTV DRV

IOVRETRY

OVLO

RUNRUN

INL

SET

TRACK/SS

INGVINGP

4.7nF

INH

LTM4641

SWV

OUT

CROWBAR

LATCH

ORB

OSNS

ORB

TEMP

OVPGM

OTBH

PGOOD

OUTM(MLCC)

100µF

6.3V ×3

SETM2

16.4k

FFMA

220pF

SETM1A

8.2k

SETM1B

8.2k

FFMB

220pF

LOAD

–

REF

GNDSGNDCOMPTMR

TAC

TBC

R 680k

CfSET

RUN

INSC(MLCC)

10µF 50V ×2

INL

SET

UVLO

HYST FCB

INTV

DRV

IOVRETRY

OVLO

RUN

INGVINGPVINH

LTM4641

OUT

CROWBAR

LATCH

ORB

OSNS

ORB

TEMP

OVPGM

OTBH

PGOOD

–

REF

COINCEDENT TRACKING

OF THE 1.8V RAIL

OUTSC(MLCC)

100µF

6.3V ×4

SETC1A

5.49k

SETC1B

5.49k

LOAD

GNDSGNDCOMPTMRTRACK/SS

TAR

TBR

R 1M

RfSET

RUN

INSR(MLCC)

10µF 50V ×2

INL

SET

UVLO

HYST FCB

INTV

DRV

IOVRETRY

OVLO

RUN

INGVINGPVINH

LTM4641

OUT

CROWBAR

LATCH

ORB

OSNS

ORB

TEMP

OVPGM

OTBH

PGOOD

GNDSGNDCOMPTMRTRACK/SS

33.2k

–

REF

4641 F07

SETR2

OUTSR(MLCC)

100µF

6.3V ×4

220pF

SETR1A

SETR1B

220pF

RATIOMETRIC TRACKING

OF THE 1.8V RAIL

FFRA

8.2k

LOAD

8.2k

FFRB

U1, U2 AND U3 SGND ( ) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP SGND ROUTES/PLANES OF MODULES SEPARATE FROM EACH OTHER AND FROM GND ON MOTHERBOARD

2,3

OUT_MASTER

1.8V UP TO 10A

OUT_SLAVE_C

1V UP TO 10A

OUT_SLAVE_R

1.5V UP TO 10A

LOCAL HIGH FREQUENCY DECOUPLING

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applicaTions inForMaTion—power supply FeaTures

LTM4641

In the example circuit of Figure 7, the master rail generated by U1 ramps up its output to 1.8V. The ratiometric-tracking rail is generated by U3 and has a nominal FS output volt age of 1.5V. Values of R

TAR

and R

are determined such

TBR

that when U1’s output reaches its final value, 1.8V, the TRACK/SS pin of U3 reaches ~600mV: choosing R be 10kΩ yields R

= (1.8V/0.6V – 1) • 10kΩ, or ~20kΩ.

TAR

TBR

It is common to choose resistor values of 10k or less for this task, so that errors introduced by the 1µA current source on TRACK/SS are sufficiently small.

Figure 8 shows an oscilloscope snapshot of the output voltage waveforms of the modules configured per the Figure 7 circuit, with 6Ω load on V on the V

OUT_SLAVE_C

U1 V

OUT

1V/DIV

U2 V

OUT

1V/DIV

U3 V

OUT

1V/DIV

RUN

5V/DIV

Figure 8. Output Voltage Waveforms of U1, U2 and U3. cf. Figure 7 Circuit.

and V

OUT_MASTER

OUT_SLAVE_R

2ms/DIV

and no load

outputs.

4641 F08

For applications that do not require tracking or sequencing, applying at least 100pF on the TRACK/SS pin is recommended, corresponding

to ~60μs

output voltage start-up ramp time. The resulting soft-start period will limit start-up input surge current and output voltage overshoot.

INTV

and DRV

The LTM4641 module has an internal 5.3V low dropout regulator whose input is fed from the low current input voltage bias pin, V put, INTV

, is used to power control and housekeeping

, through a Schottky diode. The out-

INL

circuitry and the MOSFET drivers, and is up-and-running whenever bias on V

is present. DRVCC is the power input

INL

pin to the MOSFET driver circuitry. In most cases, connect INTV 30mA, continuous, which is sufficient for powering DRV

to DRVCC. The INTVCC regulator can source up to

, even at the LTM4641’s highest recommended switching frequency (6V

condition).

OUT

The power loss in the LDO can be considerable at high input voltage, given by:

LOSS(INTVCC_LDO)

= (V

– 5.3V) • (5mA + I

INL

DRVCC

) (19)

This power loss can be virtually eliminated when a ~5V to 6V rail is available to overdrive the INTV

/DRVCC pins

through a Schottky diode, as shown in the Figure 51 circuit. This is because the LDO can only pull INTV

’s voltage

in an upward direction—that is to say, the series-pass element turns off when INTV

exceeds the LDO control

loop’s regulation setpoint. Infrared thermal images in Figures 52 to 55 illustrate operating conditions in which up to ~5°C reduction in package surface temperature is obtained by employing this technique. Note the importance to provide a diode-ORed path from V INTV

/DRVCC to V

by an auxiliary rail (or V

when INTVCC/DRVCC is overdriven

INL

). This assures proper MOSFET

OUT

to V

and from

INL

driver behavior regardless of disappearance/appearance of V

versus V

INL

, in any combination or sequence of

AUX

rail ramp-up/ramp-down events. The series-connected Schottky diode internal to the LTM4641 that feeds the LDO from V

assures proper MOSFET driver and internal

INL

logic behavior, even in the event of rapid discharging and restoration of V

A housekeeping circuit that monitors DRV hibits switching action until DRV switching action commences, DRV to 3.35V before switching action is inhibited. The DRV

INL

voltage in-

exceeds 4.05V. Once

is allowed to fall

voltage monitor has glitch immunity characteristics as shown in Figure 12.

DRV

current is proportional to switching frequency. For

applications with extremely fast output voltage start-up (e.g., C

< 100pF on TRACK/SS, or rail tracking very fast

rails with sub 60μs turn-on time), switching frequency may

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LTM4641

20µs/DIV

4641 F09

applicaTions inForMaTion—power supply FeaTures

conceivably approach f (see Equation 8). When biasing DRV such applications, INTV

at start-up, however briefly

MAX

from INTVCC in

may require additional bypass

capacitance to ride through the resulting current surge on

. INTVCC can by bypassed with up to 4.7μF (±20%

DRV

tolerance) of external decoupling capacitance.

REF

A housekeeping IC internal to the LTM4641 generates a 1V ±1.5% reference voltage. This voltage reference is generated independent of the control IC’s 600mV bandgap voltage. The 1V

should only be used to alter the OV

REF

PGM

threshold programming voltage for the fast OOV comparator (see Fast section) or to implement

Output Overvoltage Comparator Threshold

an auxiliary overtemperature detector with an NTC having ultrahigh resistance (470k at 25°C, B-value < 5000K)—in the manner shown in Figure47. Loading 1V

must become established quickly at start-up to

REF

properly bias OV

beyond ±100μA is not recommended.

REF

, and therefore no external capacitance

PGM

should be applied to this pin. To minimize disturbance to the OV

voltage, dynamic step-loading of the 1V

PGM

REF

not recommended. Figure 9 shows the step response of

to a 0μA to 100μA step load with 100A/s slew rates,

REF

and the resulting impact to OV

REF

100mV/DIV

AC-COUPLED

1VREF

50µA/DIV

PGM

10mV/DIV

AC-COUPLED

Figure 9. Response of 1V Applied at 100A/s—and Resulting Disturbance and Recovery of OV

. Figure 45 Circuit at 28VIN. Do Not Load 1V

PGM

to 0μA ⇔ 100μA Load Steps

REF

’s voltage waveform.

PGM

Arbitrarily

REF

TEMP, OTBH and Overtemperature Protection

As seen in Figure 1, a resistor-NTC-divider network formed between 1V

and SGND generates TEMP, an analog

REF

temperature indicator pin. The pin nominally measures ~0.98V at 25°C and colder, and ~585mV at 125°C. A graph of the relationship between junction temperature, NTC resistance, and TEMP voltage is found in Figure 10.

The TEMP pin also connects indirectly to a comparator input whose output can pull HYST low to inhibit switch

ing action. If TEMP falls below 438mV, corresponding to a junction temperature

of ~147°C, switching action is inhibited. If OTBH is logic low when TEMP falls below 438mV, a latchoff overtemperature event is registered. Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section. If OTBH is open circuit when TEMP falls below 438mV, a nonlatching overtemperature event is registered: switch ing action TEMP pin rises above

can resume when the units cools off and the

514mV, corresponding to a junction

temperature of ~136°C.

The LTM4641’s overtemperature protection feature is intended to protect the device during momentary overload conditions. Recognize that the

LTM4641 is rated for 125°

C junction, absolute maximum, and that junction temperature exceeds 125°C when overtemperature protection is active. Continuous operation above the specified maximum op erating junction temperature may impair

device reliability.

The overtemperature protection circuit can be disabled by connecting TEMP to 1V

. With moderate linear cir-

REF

cuit analysis, the information in Figure 10 and Figure 62 (Appendix A)

can be used

to alter the overtemperature inception and recovery thresholds. If desired, the thresholds can 1V

be increased by applying a resistor from TEMP to

, or decreased by applying a resistor from TEMP to

REF

SGND. The overtemperature comparator contains built-in filtering, yielding glitch immunity characteristics shown in Figure 12.

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LTM4641

NTC RESISTANCE (Ω)

TEMP PIN VOLTAGE (V)

1000000

4641 F10

4641 F11

ON MOTHERBOARD

applicaTions inForMaTion—inpuT proTecTion FeaTures

Input Monitoring Pins: UVLO, IOVRETRY, OVLO

The UVLO pin feeds directly into the inverting input of a comparator whose trip threshold is 0.5V. The behavior of the UVLO pin is an example of a nonlatching fault: when the UVLO pin falls below 0.5V, HYST is pulled low and switching action is inhibited; when the UVLO pin exceeds 0.5V, HYST goes logic high and switching action can resume. The IOVRETRY and OVLO pins each feed directly into noninverting inputs of comparators whose trip thresholds are 0.5V. The behavior of the IOVRETRY pin is also an example of a nonlatching fault pin: when the IOVRETRY pin exceeds 0.5V, HYST is pulled low and switching action is inhibited; when IOVRETRY falls below

0.5V, switching action can resume. The behavior of the OVLO pin is an example of a latchoff fault pin: when the OVLO pin exceeds 0.5V, HYST is pulled low and switching action is inhibited; when OVLO subsequently falls below

0.5V, HYST remains latched low, and switching action cannot occur until the latch has been reset. Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section.

These three pins haviors of the LTM4641. The UVLO pin input is primarily used to set customized thresholds, utilizing a high impedance connection to the HYST pin to obtain hysteresis. There are times when the LTM4641’s default UVLO rising and UVLO falling thresholds of 4.5V

0.95

0.85

100000

10000

1000

–15 25 65 105 145 185

–55

JUNCTION TEMPERATURE (°C)

0.75

0.65

0.55

0.45

0.35

0.25

Figure 10. Relationship of NTC Resistance to Junction Temperature and Resulting TEMP Voltage. Curves for Nominal Values and Calculated Extreme Values Shown

give added flexibility to tailor some be-

UVLO rising and UVLO falling

rising (maximum) and 4VIN falling (maximum)

are not suitable. For example, it can be convenient to apply customized UVLO settings to

inhibit switching prior to entering a region of possible dropout operation (Figure 51). It may be desirable to set a very large UVLO hysteresis, if line sag is problematic. UVLO is highly recommended to be customized to monitor the source supply feeding V

INH

when V

is biased from an auxiliary rail (Figure 49).

INL

The UVLO pin input may also be used to provide novel circuit solutions such as one found in Figure 47: to detect an overtemperature event in MSP—sensed via an external NTC in close proximity to the power interrupt MOSFET, MSP; and to respond to MSP overtemperature by inhibiting switching action and turning off MSP until the MOSFET returns to normal temperatures.

IOVRETRY is primarily used to set the input

voltage (V

) threshold above which switching action is inhibited, but not latch off. OVLO is primarily used to set the input volt

age (VIN) threshold above which switching action latches off. Just as the UVLO pin can be used in versatile ways, so can IOVRETRY and OVLO.

Consult Appendix A to see the UVLO/IOVRETRY/OVLO pins’ functions in greater detail.

The most common arrangement of components connect

ing VIN to UVLO, HYST, IOVRETRY and OVLO is shown in Figure 11.

IN(BULK)

TOV

MOV

BOV

SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND ROUTES/PLANES SEPARATE FROM GND

Figure 11. Setting the LTM4641 Custom UVLO Rising and UVLO Falling Thresholds, Nonlatching Input Overvoltage Threshold, and Latching Input Overvoltage Threshold

IN(MLCC)

10µF ×2

TUV

UVLO < 0.5V = OFF

BUV

HYST PULLS UP WHEN

ON, HYST PULLS DOWN

IOVRETRY > 0.5V = OFF

OVLO > 0.5V = LATCHOFF

WHEN OFF

HYST

INH

INL

UVLO

LTM4641

HYST

IOVRETRY

OVLO

SGND GND

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LTM4641

VSU− V

HYST

UVOV

TUV

HYST





HYST

DIV

•UVOV





applicaTions inForMaTion—inpuT proTecTion FeaTures

Variables to define up-front are as follows:

: VIN start-up voltage, in volts. This is the custom-

• V

ized UVLO rising voltage.

: VIN shutdown voltage, in volts. This is the custom-

•

ized UVLO falling voltage.

•

: The value of the voltage on the HYST pin (in

HYST

volts) when switching action is on and just prior to the input voltage (V

• R

: The hysteresis-setting resistor. If used, R

HYST

) falling below VSD.

HYST

recommended to take on a value of 1MΩ or higher, so

and it is inferred (in that scenario) that V closer to 4.1V, when RUN is floating.

It is the moderately weak pull-up strength of HYST (10kΩ pull-up to INTV

), and the desire for any loading of

the HYST signal to negligibly alter the HYST logic-high output voltage level (

less than ~50mV), that motivates a high impedance (~1MΩ) hysteresis-setting resistor to interface between HYST and UVLO, when custom UVLO settings are desired.

The customized UVLO start-up and shutdown input voltage settings can be double-checked with:

would be

HYST

that the HYST voltage is negligibly affected by external loading.

: The input voltage above which a latchoff input

• V

VSU= UVOVTH•

BUV

TUV

||R

 

HYST

+ 1

 

(22)

overvoltage event occurs.

: The input voltage above which a nonlatching input

• V

overvoltage event occurs.

Then, R

TUV

and R

are given by:

BUV

•R

HYST

(20)

VSD= VSU–

To set the input overvoltage (latching and nonlatching) thresholds, choose first how much current, I ally have drawn by the R string for this function, at ultrahigh line. 10μA to 20µA is

HYST

•R

TUV

TOV/RMOV/RBOV

(23)

, to continu-

DIV

resistor-divider

a normal amount to allocate.

and

The total resistance of the divider string is then given by:

BUV

UVOV

VSU− UVOV

is nominally 0.5V, from the Electrical Characteristics

Table. The value of V requires more careful consideration. Review Figure 1 and assess system details of the specific application in which the LTM4641 is being placed. It is known from the Electrical Characteristics table that when V INTV

= 5.3V; and we see the voltage on the HYST pin,

when switching action is on, is V

5.1V—nominally. Observe that if the RUN pin were driven high by 3.3V logic, however, that V diode forward-voltage drop above 3.3V—and V that instance would be 3.6V. If V it is necessary to consider that V INTV

4.5V input, INTV

, is decreasing with V

is nominally 4.3V (V

UVOV

–

used in the above equations

HYST

INL

≥ 6V that

INL

HYST(SWITCHING_ON)

would be a Schottky

HYST

is targeted below 6VIN,

’s pull-up voltage,

HYST

. For example, at V

INTVCC(LOWLINE)

HYST

INL

(21)

TOT

Then, the resistors in the input overvoltage divider are given by:

BOV

MOV

TOV

TOT

= UVOVTH•R

= R

– RM – RB (27)

TOT

•





–





It may be tempting to try rearranging these equations so that R R

BOV

ratio (usually) of ultrahigh line input voltage down to these

’s value is fixed, first, and to compute R

TOV

subsequently. However, due to large divide-down

pins with ~0.5V thresholds, the rounding off of R

to nearest EIA standard values after fixing R

BOV

MOV

(24)

(25)

(26)

and

TOV

4641fe

’s

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LTM4641













COMPARATOR OVERDRIVE PAST THRESHOLD (%)

TYPICAL TRANSIENT DURATION (µs)

700

4641 F12

applicaTions inForMaTion—inpuT proTecTion FeaTures

value in place often significantly alters one or both VIN referred overvoltage thresholds. It is more efficient to work through Equations 24 to 27 in the sequence shown and iterate (if necessary) towards finding convenient (EIA standard) resistor values.

The latchoff input overvoltage threshold can be doublechecked with:

VOV= UVOVTH•

The nonlatching overvoltage threshold can be doublechecked with:

VRT= UVOVTH•

The UVLO, IOVRETRY and OVLO pins do not require any filter capacitance due to built-in filtering in the LTM4641’s housekeeping IC. This results in glitch immunity with characteristics shown in Figure 12.

600

500

400

300

200

100

GLITCH

IGNORED

0.1

Figure 12. Transient Duration vs Comparator Overdrive Glitch Immunity Characteristics. Monitored Signals: UVLO, IOVRETRY, OVLO, TEMP, CROWBAR and DRVCC

Start-Up/Shutdown and Run Enable; Power-On Reset and Timeout Delay Time

The LTM4641 is a feature-rich and versatile self-contained DC/DC converter system, and includes multiple on-board supply monitors. The inputs to several monitors are avail

the user for system customization (UVLO, OVLO,

able to IOVRETRY and TEMP).

+ R

TOV

 



( )



MOV

1 10 100

MOV

BOV

TOV

+ R

RESPECTIVE

FAULT CONDITION

BECOMES DETECTED

+ 1

BOV

The LTM4641 powers up its output when the following conditions are met:

• RUN exceeds 1.25V (nominal; 2V, overtemperature);

power-on reset (POR) and timeout delay times do not apply to RUN.

• All nonlatching fault-monitor pins have been in their

operationally valid states for the full duration of the POR delay time, set optionally by C

 

(28)

on the TMR pin). Explicit pins and operationally valid thresholds follow:

a. DRV

+ 1

(29)

b. UVLO > 500mV

c. IOVRETRY < 500mV

d. TEMP > 514mV (when OTBH is electrically open

• No latchoff fault conditions are present, and the

LTM4641 is not in a “latched off” state from any pre viously detected latchoff fault condition. If a latchoff fault condition occurs/occurred, the LTM4641 must be unlatched by a logic high LATCH signal: if all la tchoff fault-monitoring pins are in operationally valid states when LATCH transitions from logic low to high, the LTM4641 becomes immediately unlatched; if, in stead, any latchoff fault-monitoring pin is outside its operationally valid state when LATCH is logic high, the LTM4641 becomes unlatched if LATCH remains logic high after all latchoff fault-monitoring pins have been in their operationally valid states for the full duration of the timeout delay time (set optionally by C pins and operationally valid thresholds follow:

a. OVLO < 500mV

b. TEMP > 514mV (when OTBH is logic low)

c. CROWBAR < 1.5V

The POR and timeout delay time is 9ms per nanofarad of C

timeout delay time is ~90μs.

For more information www.linear.com/LTM4641

(the capacitor

TMR

> 4.05V. In the circuits of Figures 45 and

46, this is guaranteed for V

≥ 4.5V, minimum. In

INL

Figure49, this requirement is met when the auxiliary bias supply exceeds 4.05V.

circuit)

). Explicit

TMR

capacitance. If C

TMR

is not used, the POR and

TMR

4641fe

LTM4641

applicaTions inForMaTion—loaD proTecTion FeaTures

If any nonlatching fault conditions occur, internal circuitry pulls HYST low and switching action is inhibited. The power stage will be high impedance until the aforementioned startup conditions are met. If any latchoff fault condition occurs, HYST is latched low and switching action is inhibited until the LTM4641 is unlatched (by pulling LATCH logic high) or V

power is recycled (with INTVCC falling below 2V).

INL

The LTM4641 can be configured to restart autonomously after an adjustable timeout delay time—instead of exhibit

ing latchoff behavior—by leaving LATCH logic high (con- nected to INTV timeout delay time with C that use of C

, for example) and setting the hiccup retry

(see Figure 47). Be reminded

TMR

also introduces POR behavior, yet the POR

TMR

and timeout delay timers operate independently. The effect of C

can be negated by pulling the TMR pin to INTVCC.

TMR

Switching action will be inhibited if any of the following occur:

• RUN is less than 1.15V (nominal; 0.8V, overtem perature). Not a fault; no

POR or timeout delay time is

imposed.

• Any nonlatching faults occur:

a. DRV

falls below 3.35V. In the Figure 45 and

Figure 46 circuits, this happens at V

< 4V, maximum.

INL

b. UVLO falls below 0.5V.

c. IOVRETRY exceeds 0.5V.

d. TEMP falls below 438mV when OTBH is electrically

open circuit.

• Any latchoff faults occur:

a. OVLO exceeds 0.5V.

b. CROWBAR exceeds 1.5V.

c. TEMP falls below 438mV when OTBH is logic low.

The LTM4641’s state diagram is provided in AppendixB.

pins

Start-up and shutdown mechanisms for any given op erating scenario TEMP and DRV

are identified in

pins have built-in hysteresis. The UVLO,

the state diagram. The

IOVRETRY, OVLO, TEMP, CROWBAR and DRV connect to comparators with built-in glitch immunity, with characteristics indicated in Figure 12.

Overcurrent Foldback Protection

The LTM4641 has overcurrent protection (OCP). In a short circuit from V

to GND, the internal current comparator

OUT

threshold folds back during a short to reduce the output current, progressively down to about one-third of its nor

mal value (down from 24A to 8A, typical). To recover from foldback current limit, the excessive load or low impedance short

needs to be removed.

Foldback current limiting

action is disabled during soft-start and tracking start-up.

Power Good Indicator and Latching Output Overvoltage Protection

Internal overvoltage and undervoltage

open-drain PGOOD output logic low if the output voltage

the

comparators assert

is outside ±10% of nominal, after a 12μs “blanking time”. The blanking time allows the output voltage to experience brief excursions (due to large load-step transients, for example) without nuisance-tripping PGOOD. The PGOOD output is deasserted without any deliberate blanking time when the output voltage returns to (or enters) the power good window, with ~2% to 3% of hysteresis. If the feed

back voltage exceeds the upper PGOOD valid limit, the synchronous power MOSFET, M

, turns on (with no

BOT

blanking time)—to try sinking current from the output to GND, through LTM4641’s power inductor—until the output voltage returns to the PGOOD valid region. If the output voltage exceeds an adjustable threshold set by OV

, whose default value corresponds to 11% above

PGM

nominal, the LTM4641 pulls its CROWBAR output logic high immediately (500ns response time, maximum) and latches off its output voltage: the power stage becomes high impedance, with both M

TOP

and M

turning off and

BOT

staying latched off; furthermore, MSP’s gate is pulled to

potential rapidly (<2.6μs response time, maximum),

INH

to disconnect the input source voltage from the module’s power stage

. Restarting regulation after a

latchoff event has occurred is explained in detail in the Start-Up/Shutdown section

The behavior of turning ing detection

on the synchronous MOSFET dur-

of an output

overvoltage is a rudimentary and popular kind of output overvoltage protection scheme commonly found in the power supply and semiconductor control IC industry. It can provide mediocre overvoltage

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LTM4641

applicaTions inForMaTion—loaD proTecTion FeaTures

protection during severe load current step-down events, but is not very effective at protecting loads from genuine fault conditions such as a short circuited high side power switching MOSFET. Furthermore, such schemes tend to be implemented with the overvoltage detector’s threshold dependent on the same bandgap voltage that the output is being regulated to. Applications needing superior output overvoltage and load protection require the performance achieved with the output crowbar MOSFET, MCB and power interrupt switch, MSP, and LTM4641’s use of an independent reference voltage(1V

) to generate an OOV

REF

threshold.

Power-Interrupt MOSFET (MSP), CROWBAR Pin and Output CROWBAR MOSFET (MCB)

Within 500ns (maximum) of the control-loop-referred feedback signal, V (plus-or-minus OVP

, exceeding the voltage on OV

), an OOV event is detected, and

ERR

PGM

the CROWBAR output swings high enough to turn on an optional crowbaring device (MCB) residing on V more than 2.6µs after OOV detection, V

is discharged

ING

OUT

. No

and an optional power interrupt switch, MSP, disconnects the LTM4641’s power stage from the input source supply.

When MCB and MSP are used in conjunction as shown in the Figure 46 circuit, the best-in-class output overvoltage ably the

most despised failure mode high step-down buck

converters can theoretically suffer:

LTM4641 is able to provide

protection against argu-

an electrical short between the input source to the output, via the switching node. Turning on MCB upon detection of OOV helps dis

charge the output capacitors and prevent any further positive excursion of

output voltage

by transforming residual energy in LTM4641’s power stage into heat; meanwhile, turning off MSP removes a path for current flow between the input power source and the output—preventing haz

ardous (input) voltage from reaching the precious load.

It should be noted

that when an OOV event is detected, CROWBAR is not held high (equivalently, MCB is not left turned on) indefinitely. The act of pulling CROWBAR high (above 1.5V nominal), whether due to internal or external circuitry, invokes a latchoff response and strong discharge

; HYST is latched low and switching action is inhibited

of V

ING

after CROWBAR overcomes the glitch immunity requirement (see Figure

12). The fast OOV

comparator’s output

is fed through a blocking PN diode into a 10nF capacitor on the CROWBAR output; internal circuitry interfacing to CROWBAR presents in Appendix A). The tor creates

a way for the CROWBAR output to stay logic

high, even if the

itself as a ~10kΩ load (see Figure 62

use of the PN diode and 10nF capaci-

duration of OOV is very brief, and assures the glitch immunity of the latchoff detection circuitry is overcome. The 10kΩ load and 10nF capacitor provide an upper bound for the duration of time MCB might be on after CROWBAR activates: 400μs, or four time constants. Parasitic capacitance on the gate of MCB may increase this time, slightly.

Observe that when HYST is low, the noninverting input to the fast OOV comparator (see Appendix A) is clamped by a Schottky diode. (When RUN is low, the noninvert ing input series Schottky diodes.) This

to the fast OOV comparator is clamped by two

differs from when switching

action is engaged, where the noninverting input to the fast OOV comparator is normally the V

signal. Therefore, be

aware that the CROWBAR output is nominally inhibited when switching action is inhibited.

Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section.

MCB should be placed close to the majority of the load bulk an

d MLCC local bypass capacitors. CROWBAR should

(s)’s

be connected to the gate of MCB with a generous signal trace width (20mils, or 0.5mm), to support driving the peak current needed to turn on MCB upon OOV detection. At the instant that MCB turns on, it typically draws hundreds of amps from the output capacitors which are mainly located near the load. When MCB turns off, the B-field that may have been built up in the parasitic inductance in the cop

per plane between the output capacitors and MCB cannot vanish instantaneously, and the

collapsing of that B-field can induce a negative voltage across the output capacitors and load. Closer proximity of MCB to the majority of the output capacitors minimizes this parasitic inductance and hence the resulting magnitude of the negative voltage spike.

MCB must be selected according to the following criteria:

• MCB must be a logic-level N-channel MOSFET

• The drain-to-source rating of MCB must be greater than

the maximum output voltage, V

OUT(PEAK,OOV_DETECTED)

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• When CROWBAR goes logic high, the peak drain current in MCB will be given by V R

. The peak drain current, and its duration, must

DS(ON)

OUT(PEAK,OOV_DETECTED)

not exceed the maximum safe operating area of the MOSFET; consult the MOSFET vendor’s data sheet. An upper bound for MCB’s on-time is 400μs. However, this worst-case conduction time can only happen if the output capacitance on V

is extraordinarily large. The length

OUT

of time that MCB can possibly conduct ultrahigh drain current is also bounded by 4 • R

DS(ON)

• C

OUT(TOTAL)

. In a majority of applications, output capacitance is low enough that MCB does not conduct ultrahigh drain current for longer than a few microseconds, as seen on the front page.

• MCB’s junction temperature must not exceed its specified maximum at any time. Consult the MOSFET vendor’s data sheet for device thermal characteristics for “single shot” thermal transients or “single pulse” power-handling capability. The peak power sustained by MCB is V

OUT(PEAK,OOV_DETECTED)

DS(ON)

If MCB is used and it is expected that LATCH will be toggled high (to unlatch continuously (for automatic

the LTM4641) or held logic high

LTM4641 restart after faultoff), recognize that peak power sustained by MCB during CROWBAR activity may not be single pulse anymore. Therefore, to prevent MCB thermal overstress in such applications, it is recommended to use C

to set a rea-

TMR

sonable cool-down period for the MOSFET. Additionally, one may opt to

implement a circuit that shuts down the LTM4641 when MCB temperature is detected to be too high: a minor modification to Figure 47, RT1 would be located as close in proximity to MCB as possible (instead of MSP), and R1, R2, and R3 would be experimentally determined. Consult the MOSFET vendor’s data sheet for maximum rated junction temperature and device thermal characteristics for repeated pulsed-power transients.

When using MSP, connect V

ING

to V

and to the gate of

INGP

MSP. See the Input Capacitors section (earlier) for information on

MSP must be selected

the input bypassing technique when MSP is used.

according to the following criteria:

• MSP can be either a standard logic or a logic-level

N-channel MOSFET.

• The drain-to-source breakdown voltage of MSP must be greater than the maximum input source voltage. Consult

the MOSFET vendor’s data sheet and consider

temperature effects.

• In order to support very fast turn-on of output volt age (e.g., sub 1ms ramp up), on quickly to bring up V input capacitance (C

) below 4.7nF is preferred (less

ISS

MSP should be turned

quickly. Therefore, a gate

INH

is better).

• MSP must be able to conduct the maximum input current to the LTM4641’s power stage without getting too hot. Choose a suitable MOSFET package size and R temperature rise. Be mindful that I

that results in reasonable MOSFET junction

DS(ON)

Q(VINH)

is highest

during low line operation.

Blowing a series-pass input fuse with a crowbaring SCR can be an effective overvoltage protection scheme for higher output voltages, e.g., 5V, but a crowbaring MOSFET on the output of the converter is more effective at clamping the output voltage. For the same current, the power MOSFET will have much less voltage drop than the PN-junction voltage drop of an SCR. SCR-based circuits involving the LTM4641 are not presented here. Evaluation of induced or simulated overvoltage events on a demo board (such as DC1543) is recommended

to ensure the end result meets

the user’s expectations.

Fast Output Overvoltage Comparator Threshold

is nominally biased by internal circuitry to

PGM

666mV, according to a 499kΩ and 1MΩ resistor-divider network internal to the LTM4641 driven from the 1V This pin connects directly to the inverting input of the fast OOV comparator—setting the trip threshold that the control-loop-referred feedback voltage, V

have to exceed to result in CROWBAR becoming logic high. Recall that the control-loop pulse frequency modu lates M TRACK/SS pin or the bandgap

such that VFB is driven to the lesser of the

TOP

reference voltage of 600mV. When TRACK/SS (and hence, the output voltage) has been fully ramped up, the 666mV on OV

represents

PGM

an OOV setting 11% above nominal output voltage. To increase the OOV threshold, a resistor can be connected externally from 1V

REF

to OV

; to decrease the OOV

PGM

threshold, a resistor can be connected externally from

REF

, would

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applicaTions inForMaTion—eMi perForMance

4641 F13

LTM4641

OVPGM to SGND. Furthermore, the OV

trip voltage

PGM

can be made more accurate than its default setting by paralleling the existing (internal) OV

resistor-divider

PGM

with an external resistor divider comprised of low T.C.R. ±0.1%-tolerance resistors, for example. See Appendix F for details on how to adjust or tighten the fast OOV comparator trip threshold.

The Switching Node: SW Pin

The SW pin provides access to the midpoint of the power MOSFETs in LTM4641’s power stage.

Connecting an optional series RC network from SW to GND can dampen high frequency (~30MHz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. The RC network is called a snubber circuit because it dampens (or “snubs”) the resonance of the parasitics, at the expense of higher power loss.

To use a snubber, choose first how much power to allocate to the task and how much PCB real estate is available to implement the snubber. For example, if PCB space al

lows a low inductance 1W resistor to be used—derated

)—then the capacitor in

SNUB

) is computed by:

618.6 814.8

IN(BULK)

1010

= 2 × 100μF,

(30)

EN55022 CLASS B LIMIT

SNUB

226.2

mW (P

• f

422.4

FREQUENCY (MHz)

conservatively to 600 the snubber network (C

CSW=

Figure 13. Radiated Emissions Scan of LTM4641 Producing 5V

OUT

Network Installed. fSW = 550kHz. C C

IN(MLCC)

10 Meter Chamber. Quasi-Peak Detect Method

INH(MAX)

SIGNAL AMPLITUDE (dB µV/m)

–10

at 10A, from 12VIN. DC1543 Hardware with No Snubber

= 4 × 10μF X7R + 2 × 4.7μF X7R. Measured in a

where V

INH(MAX)

to the power stage (V

is the DC/DC converter’s full load switching frequency

of operation. C better) material.

The snubber resistor (R

RSW=

is the maximum input voltage that the input

) will see in the application, and

INH

should be NPO, C0G or X7R-type (or

) value is then given by:

5nH

The snubber resistor should be low ESL and capable of withstanding the pulsed currents present in snubber circuits. A value between 0.7Ω and 4.2Ω is normal.

EMI performance of

snubber is compared and contrasted in Figures13 to

out a

16. In the examples

LTM4641 (on DC1543) with and with-

shown, the snubber networks reduce

EMI signal amplitude by as much as ~5dB.

Access to SW is also provided to make it possible to deliberately induce a short circuit between the input of LTM4641’s power stage (V

) and its switch node—to

INH

evaluate, in hardware, the performance of the LTM4641 when a high side MOSFET fault condition is simulated.

SIGNAL AMPLITUDE (dB µV/m)

–10

226.2 FREQUENCY (MHz)

Figure 14. Radiated Emissions Scan of LTM4641 Producing 5V

at 10A, from 12VIN. DC1543 Hardware with Ad Hoc

OUT

Snubber Network Installed Directly Between SW Probe Point and GND, CSW = 10nF, RSW = 1Ω (1W-Rated). fSW = 550kHz. C X7R. Measured in a 10 Meter Chamber. Quasi-Peak Detect Method

IN(BULK)

= 2 × 100μF, C

IN(MLCC)

618.6 814.8

422.4

= 4 × 10μF X7R + 2 × 4.7μF

EN55022 CLASS B LIMIT

1010

4641 F13

(31)

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4641 F15

4641 F16

applicaTions inForMaTion—eMi perForMance

SIGNAL AMPLITUDE (dB µV/m)

–10

226.2 FREQUENCY (MHz)

Figure 15. Radiated Emissions Scan of LTM4641 Producing

2.5V Network Installed. f C Meter Chamber. Quasi-Peak Detect Method

at 10A, from 24VIN. DC1543 Hardware with No Snubber

OUT

= 4 × 10μF X7R + 2 × 4.7μF X7R. Measured in a 10

IN(MLCC)

= 335kHz. C

422.4

618.6 814.8

IN(BULK)

1010

= 2 × 100μF,

Figure 16. Radiated Emissions Scan of LTM4641 Producing

2.5V

OUT

Snubber Network Installed Directly Between SW Probe Point and GND, CSW = 2.2nF, RSW = 2.2Ω (1W Rated). fSW = 335kHz. C

IN(BULK)

Measured in a 10 Meter Chamber. Quasi-Peak Detect Method

SIGNAL AMPLITUDE (dB µV/m)

–10

226.2 FREQUENCY (MHz)

at 10A, from 24VIN. DC1543 Hardware with Ad Hoc

= 2 × 100μF, C

IN(MLCC)

618.6 814.8

422.4

= 4 × 10μF X7R + 2 × 4.7μF X7R.

1010

applicaTions inForMaTion—MulTiMoDule parallel operaTion

For loads that demand more than 10A of load current, multiple LTM4641 devices can be paralleled to provide more output current. See Figures 56 and 66 for examples of four or two LTM4641 operating in parallel to deliver 40A or 20A load current, respectively, while providing robust output overvoltage protection.

The LTM4641 does not support phase interleaving or clock synchronization, and therefore no ripple-current cancelation effect and no multiplication effect on the output voltage ripple frequency occurs when modules are paral leled. Therefore, it should be

anticipated that paralleled

applications contain beat frequencies in the output voltage waveform and are contained in the reflected input current. For example, if one module operates freely at 400kHz while its paralleled sibling operates freely at 410kHz, the conducted EMI content will include not only the switching fundamental frequencies—400kHz and 410kHz—but also a beat frequency at the difference of those frequencies, 10kHz. The system designer may be motivated to apply an external LC (or “pi”) filter on the input to each LTM4641 if attenuation of the reflected input currents is desired.

The LTM4641 device is a current mode controlled device, so paralleled modules demonstrate good current This helps equilibrate power

losses and reduce thermal

sharing.

differences between paralleled modules.

The following pins should be connected to all correspond

ing LTM4641s’ pin(s) when paralleling LTM4641 outputs:

•

OUT

• GND

• V

INH

• V

INL

• HYST (to synchronize start-up and shutdown)

• TRACK/SS

• COMP (to accomplish current sharing)

• CROWBAR (to synchronize output overvoltage

response)

LATCH (to reset all modules after a latchoff event)

•

• V

, if MSP is used

ING

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LTM4641





8.2kΩ





8.2kΩ

2 • R

0.6

8.2kΩ









applicaTions inForMaTion—MulTiMoDe parallel operaTion

• V

, differentially bussed with V

OSNS

–

; use GND

shielding

• V

–

, differentially bussed with V

OSNS

; use GND

shielding

• PGOOD, if used

Pulling any one module’s RUN pin low will pull all mod

ule’s HYST pins low, to cease switching and output voltage regulation. When paralleling each module should have its own R (if needed) to set the on time (I

LTM4641 outputs,

resistor locally

fSET

) consistent with the

ION

output voltage setting (cf. Table1 and Figure 3). Customized UVLO settings, latching and nonlatching input overvolt age thresholds, and output over only be configured on one LTM4641. INTV

voltage thresholds need

and DRVCC

should be connected to each other, separately on each module (see Figures 56 and 66)—or, if powering DRV

from an auxiliary bias rail, then by applying the technique of Figure 51 to each module.

If MSP is used, only one V

need be connected to

INGP

the gate of MSP. The routing of MSP’s source pins to the V

of all modules may be difficult to accomplish in

INH

layout without introducing significant loop area; it may be necessary then to use one MSP MOSFET on the input to each LTM4641 connections of V

power stage for practical routing. Also, the

OSNS

and V

–

to multiple modules

OSNS

can be difficult to shield, in practice, so leaving provision for differential-mode filtering of the remote sense signal

, C

DM1

) local to each modules’ remote-sense input

DM2

pins is advisable.

Be aware that the loading of the paralleled remote sense amplifiers on the bussed feedback signal alters the equa

tions for setting output voltage as follows.

When paralleling n modules,

for V

≤1.2V, select R

OUT

not larger than that given by:

SET1A

= R

SET1B

For V

> 1.2V, select R

OUT

SET1A

= R

SET1B

Then, determine R

SET2

OUT

– n •

SET2

OUT

 

0.6V

SET1A

by:

SET1A

– 1

•









 

not larger than that given by:

– 1

The output voltage setting can be double-checked by:

= 0.6V 1+ n•

OUT

The voltage on the V

 

8.2kΩ

OSNS

SET1A

2 • R

SET1A

SET2

 

pins of the modules during

regulation become:

VOSNS+

 

8.2kΩ

 



• R

 

SET1A

0.6V

||R

SET1A

16.4kΩ

In multimodule parallel scenarios, V

SET2

 



OSNS

∆V

GND

SET1A

– and ∆V

still given by Equations 12 and 13, respectively.

Lastly, be aware that the total charge current on the TRACK/SS net will be n • 1μA.

SET1A

  



GND

(32)

(33)

(34)

(35)

(36)

are

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LTM4641

applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing

Thermal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board de fined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”).

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and thermal per

The cients explicitly defined are quoted or paraphrased below:

1 θ

Configuration

, the thermal resistance from junction to ambient, is

the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo sure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition.

JESD51-12

formance to one’s own application.

section gives four thermal coeffi-

are intended for use with

and

The motivation

can be

adapted to correlate

51-12; these coefficients

JESD

2 θ

JCbottom

bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the pack age, but environment. As a result, may be useful for comparing packages but the test conditions don’t generally match the user’s application.

3 θ

JCtop

the product case, is determined with nearly all of component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ for comparing packages but the test conditions don’t generally match the user’s application.

4 θ

circuit board, is the junction-to-board thermal resistance where bottom of the µ and is really the sum of the θ resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9.

A graphical representation of the aforementioned thermal resistances is given in Figure 17; blue resistances are contained within the µModule regulator, whereas green resistances are external to

As a

practical

no individual or sub-group of the four thermal resistance

, the thermal resistance from junction to the

there is always heat flow out into the ambient

this thermal resistance value

, the thermal resistance from junction to top of

the

JCbottom

, the thermal resistance from junction to the printed

almost all of the heat flows through the

Module regulator and into the board,

matter,

it should be clear to the reader that

, this value may be useful

JCbottom

the µModule package.

and the thermal

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LTM4641

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parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bot

tom of the µModule package—as the standard defines for θ

JCtop

and θ

JCbottom

, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board.

Within the LTM4641, be aware there are multiple power devices and components dissipating power, with a con

sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reason

ably define and correlate the thermal resistance values supplied in this data

sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4641 and the specified

PCB with all of the correct

material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED 51-9 and JESD 51-12 to predict

power

loss

heat

and temperature

flow readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4641 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled envi ronment chamber while

operating

device at the same

the

power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated JESD51-12-defined θ values provided in the Pin Configuration section of this data sheet.

The 6V, 3.3V and 1.5V power loss curves in Figures 18, 19 and 20 respectively can be used in coordination with the load current derating curves in Figures 21 to 42 calculating an approximate θ

thermal resistance for the

for

LTM4641 with various heat sinking and air flow conditions. These thermal resistances represent demonstrated

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION AMBIENT

µMODULE DEVICE

Figure 17. Graphical Representation of JESD51-12 Thermal Coefficients

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

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CASE (BOTTOM)-TO-BOARD

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4641 F17

4641fe

LTM4641

applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing

performance of the LTM4641 on DC1543 hardware; a 4-layer FR4 PCB measuring 96mm × 87mm × 1.6 mm using outer and inner copper weights of 2oz and 1oz, respectively. The power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. These approximate factors are listed in Table 3. (Compute the factor by interpolation, for intermediate temperatures.) The derating curves are plotted with the output current starting at 10 A and the ambient temperature at 40°C. The output voltages are 6V, 3.3V and 1. 5V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal

alys

modeling an monitored while ambie

is. The junction temperatures are

nt temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. The BGA heat sinks evaluated in Table 7 (and attached to the LTM4641 with thermally conductive adhesive tape listed in Table8) yield very comparable performance in laminar airflow despite being visibly different in construction and form factor. The power loss

increase with ambie

nt temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 12 0° C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 38, the load current is derated to ~8A at ~81°C ambient with no air or heat sink and the power loss for this 36V

to 1.5V

OUT

condition is ~3.1W. The 3.74W loss is calculated

OUT

with the ~3.1W room temperature loss from the 36V

1.5V

power loss curve at 8A (Figure 20), and the 1.205

OUT

multiplying factor at 81°C ambient (interpolating from Table 3). If the 81°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 39°C divided by 3.74W yields a thermal resistance, θ of 10.4°C/W—in good agreement with Table 6. Tables 4, 5 and 6 provide equivalent thermal resistances for 6V,

3.3V and 1.5V outputs with and without air flow and heat sinking. The derived thermal resistances in Tables 4, 5 and 6 for the various conditions can calc

ulated power loss as a function of ambient temperature

to derive temperature rise above ambient, thus maximum

be multiplied by the

junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors.

Table 3. Power Loss Multiplicative Factors vs Ambient Temperature

AMBIENT TEMPERATURE

Up to 40°C 1.00

50°C 1.05

60°C 1.10

70°C 1.15

80°C 1.20

90°C 1.25

100°C 1.30

110°C 1.35

120°C 1.40

POWER LOSS MULTIPLICATIVE

FACTOR

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LTM4641

POWER LOSS (W)

4641 F18

POWER LOSS (W)

4146 F19

POWER LOSS (W)

4.5

4641 F20

MAXIMUM LOAD CURRENT (A)

4146 F21

120

MAXIMUM LOAD CURRENT (A)

4146 F22

120

MAXIMUM LOAD CURRENT (A)

4146 F23

120

MAXIMUM LOAD CURRENT (A)

4146 F24

120

MAXIMUM LOAD CURRENT (A)

4146 F25

120

MAXIMUM LOAD CURRENT (A)

4146 F26

120

applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing

Figure 18. 6V

OUTPUT CURRENT (A)

OUT

Power Loss, fSW = 660kHz at Full Load, FCB Tied to SGND

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

100

36V 24V 12V

8 9

110

36V

24V

IN IN IN

10 3 5 7 9

2 4 6 8

OUTPUT CURRENT (A)

Figure 19. 3.3V

OUT

Power Loss,

12V 6V

IN IN

fSW = 360kHz at Full Load, FCB Tied to SGND

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

110

100

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

1 2 3 4 5 10

OUTPUT CURRENT (A)

Figure 20. 1.5V

OUT

fSW = 315kHz at Full Load, FCB Tied to SGND

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

36V

24V

12V

6 7 8 9

Power Loss,

110

100

Figure 21. 12VIN to 6V Sink, fSW = 660kHz at Full Load

50 70

Figure 24. 12VIN to 6V Sink, fSW = 660kHz at Full Load

, No Heat

OUT

400LFM 200LFM 0LFM

OUT

100

with Heat

AMBIENT TEMPERATURE (°C)

110

Figure 22. 24VIN to 6V

, No Heat

OUT

Sink, fSW = 660kHz at Full Load

Figure 25. 24VIN to 6V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

110

100

with Heat

OUT

Sink, fSW = 660kHz at Full Load

For more information www.linear.com/LTM4641

Figure 23. 36VIN to 6V

, No Heat

OUT

Sink, fSW = 660kHz at Full Load

Figure 26. 36VIN to 6V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

100

with Heat

OUT

Sink, fSW = 660kHz at Full Load

110

4641fe

LTM4641

MAXIMUM LOAD CURRENT (A)

4146 F27

120

MAXIMUM LOAD CURRENT (A)

4146 F28

120

MAXIMUM LOAD CURRENT (A)

4146 F29

120

MAXIMUM LOAD CURRENT (A)

4146 F30

120

MAXIMUM LOAD CURRENT (A)

4146 F31

120

MAXIMUM LOAD CURRENT (A)

4146 F32

120

MAXIMUM LOAD CURRENT (A)

4146 F33

120

MAXIMUM LOAD CURRENT (A)

4146 F34

120

4146 F35

applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing

Figure 27. 6VIN to 3.3V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

OUT

100

No Heat

Sink, fSW = 360kHz at Full Load

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

100

110

Figure 28. 12VIN to 3.3V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

100

No Heat

OUT

Sink, fSW = 360kHz at Full Load

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

100

110

Figure 29. 24VIN to 3.3V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

OUT

100

No Heat

Sink, fSW = 360kHz at Full Load

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

100

110

Figure 30. 36VIN to 3.3V Sink, fSW = 360kHz at Full Load

50 70

Figure 33. 24VIN to 3.3V Sink, fSW = 360kHz at Full Load

, No Heat

OUT

400LFM 200LFM 0LFM

100

with Heat

OUT

AMBIENT TEMPERATURE (°C)

110

Figure 31. 6VIN to 3.3V

, with Heat

OUT

Sink, fSW = 360kHz at Full Load

Figure 34. 36VIN to 3.3V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

100

OUT

110

with Heat

Sink, fSW = 360kHz at Full Load

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Figure 32. 12VIN to 3.3V

OUT

Sink, fSW = 360kHz at Full Load

MAXIMUM LOAD CURRENT (A)

Figure 35. 6VIN to 1.5V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

OUT

Sink, fSW = 315kHz at Full Load

, with Heat

110

100

120

No Heat

4641fe

LTM4641

MAXIMUM LOAD CURRENT (A)

4146 F36

120

MAXIMUM LOAD CURRENT (A)

4146 F37

120

MAXIMUM LOAD CURRENT (A)

4146 F38

120

MAXIMUM LOAD CURRENT (A)

4146 F39

120

MAXIMUM LOAD CURRENT (A)

4146 F40

120

MAXIMUM LOAD CURRENT (A)

4146 F41

120

MAXIMUM LOAD CURRENT (A)

4146 F42

120

applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing

Figure 36. 12V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

to 1.5V

100

No Heat

OUT

Sink, fSW = 315kHz at Full Load

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

110

Figure 37. 24VIN to 1.5V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

OUT

100

No Heat

110

Sink, fSW = 315kHz at Full Load

110

100

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

Figure 38. 36VIN to 1.5V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

OUT

100

No Heat

Sink, fSW = 315kHz at Full Load

110

100

110

Figure 39. 6VIN to 1.5V

, with Heat

OUT

Sink, fSW = 315kHz at Full Load

Figure 41. 24V

400LFM 200LFM 0LFM

to 1.5V

OUT

50 70

AMBIENT TEMPERATURE (°C)

100

, with Heat

Sink, fSW = 315kHz at Full Load

For more information www.linear.com/LTM4641

110

Figure 40. 12V

to 1.5V

OUT

, with

Heat Sink, fSW = 315kHz at Full Load

Figure 42. 36VIN to 1.5V

400LFM 200LFM 0LFM

50 70

AMBIENT TEMPERATURE (°C)

110

100

OUT

with Heat

Sink, fSW = 315kHz at Full Load

4641fe

LTM4641

applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing

Table 4. 6V Output, Switching Frequency Nominally 660kHz at Full Load

DERATING CURVE V

Figure 21 to Figure 23 12V, 24V, 36V Figure 18 0 None 10.1

Figure 21 to Figure 23 12V, 24V, 36V Figure 18 200 None 8.2

Figure 21 to Figure 23 12V, 24V, 36V Figure 18 400 None 6.8

Figure 24 to Figure 26 12V, 24V, 36V Figure 18 0 BGA Heat Sink 8.1

Figure 24 to Figure 26 12V, 24V, 36V Figure 18 200 BGA Heat Sink 6.5

Figure 24 to Figure 26 12V, 24V, 36V Figure 18 400 BGA Heat Sink 5.5

Table 5. 3.3V Output, Switching Frequency Nominally 360kHz at Full Load

DERATING CURVE V

Figure 27 to Figure 30 6V, 12V, 24V, 36V Figure 19 0 None 10.4

Figure 27 to Figure 30 6V, 12V, 24V, 36V Figure 19 200 None 8.4

Figure 27 to Figure 30 6V, 12V, 24V, 36V Figure 19 400 None 7.1

Figure 31 to Figure 34 6V, 12V, 24V, 36V Figure 19 0 BGA Heat Sink 8.6

Figure 31 to Figure 34 6V, 12V, 24V, 36V Figure 19 200 BGA Heat Sink 6.8

Figure 31 to Figure 34 6V, 12V, 24V, 36V Figure 19 400 BGA Heat Sink 5.8

POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)

Table 6. 1.5V Output, Switching Frequency Nominally 315kHz at Full Load

DERATING CURVE V

Figure 35 to Figure 38 6V, 12V, 24V, 36V Figure 20 0 None 10.3

Figure 35 to Figure 38 6V, 12V, 24V, 36V Figure 20 200 None 8.4

Figure 35 to Figure 38 6V, 12V, 24V, 36V Figure 20 400 None 7.2

Figure 39 to Figure 42 6V, 12V, 24V, 36V

Figure 39 to Figure 42 6V, 12V, 24V, 36V Figure 20 200 BGA Heat Sink 7.0

Figure 39 to Figure 42 6V, 12V, 24V, 36V Figure 20 400 BGA Heat Sink 5.8

POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)

Figure 20 0 BGA Heat Sink 9.0

Table 7. Heat Sink Vendors (with Thermally Conductive Adhesive Tape Pre-Attached)

HEAT SINK MANUFACTURER PART NUMBER WEBSITE

Wakefield Engineering LT N20069 www.wakefield.com

Aavid Thermalloy 375424B00034G www.aavid.com

Table 8. Thermally Conductive Adhesive Tape Vendor

TH ERMALLY CONDUCTIVE ADHESIVE TAPE MANUFACTURER PART NUMBER WEBSITE

Chomerics T411 www.chomerics.com

4641fe

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Table 9. Transient Performance (Typical Values) vs Recommended Output Capacitance. Figure 45 and Figure 46 Circuits

OUT(MLCC)

≤ 3.3V AVX 12106D107MAT2A (100µF, 6.3V, 1210 Case Size)

> 3.3V AVX 1206YD226MAT2A (22µF, 16V, 1206 Case Size)

*Bulk Capacitance is optional if V

VENDOR PART NUMBER VENDOR PART NUMBER

OUT

12066D226MAT2A (22µF, 6.3V, 1206 Case Size)

Taiyo Yuden JMK325BJ107MM-T (100µF, 6.3V, 1210 Case Size)

TDK C3225X5R0J107MT (100µF, 6.3V, 1210 Case Size)

Taiyo Yuden LMK316BJ476ML-T (47µF, 10V, 1206 Case Size)

TDK C3216X5R1A476M (47µF, 10V, 1206 Case Size)

OUT

(V) V

0.9 5, 12, 24, 36 0.931 4.12 – 2 × 10µF 100µF 3 × 22µF 680µF – 5 60 130 25

0.9 5, 12, 24, 36 0.931 4.12 – 2 × 10µF 100µF 4 × 100µF – – 5 60 140 25 1 5, 12, 24, 36 1.00 5.49 – 2 × 10µF 100µF 3 × 22µF 680µF – 5 65 135 25 1 5, 12, 24, 36 1.00 5.49 – 2 × 10µF 100µF 4 × 100µF – – 5 70 150 25

1.2 5, 12, 24, 36 1.13 8.2 – 2 × 10µF 100µF 3 × 22µF 680µF – 5 70 140 25

1.2 5, 12, 24, 36 1.13 8.2 – 2 × 10µF 100µF 4 × 100µF – – 5 80 170 30

1.5 5, 12, 24, 36 1.43 8.2 33.2 2 × 10µF 100µF 3 × 22µF 680µF – 5 75 155 30

1.5 5, 12, 24, 36 1.43 8.2 33.2 2 × 10µF 100µF 4 × 100µF – 220pF 5 90 190 30

1.8 5, 12, 24, 36 2.00 8.2 16.5 2 × 10µF 100µF 3 × 22µF 680µF – 5 80 170 40

1.8 5, 12, 24, 36 2.00 8.2 16.5 2 × 10µF 100µF 3 × 100µF – 220pF 5 100 215 30

2.5 5, 12, 24, 36 5.76 8.2 7.5 2 × 10µF 100µF 3 × 22µF 680µF – 5 100 230 50

2.5 5, 12, 24, 36 5.76 8.2 7.5 2 × 10µF 100µF 3 × 100µF – 220pF 5 140 290 30

3.3 5, 12, 24, 36 – 8.2 4.7 2 × 10µF 100µ

3.3 5, 12, 24, 36 – 8.2 4.7 2 × 10µF 100µF 3 × 100µF – 100pF 5 200 420 30 5 12, 24, 36 – 8.2 2.61 2 × 10µF 100µF 2 × 22µF 150µF 220pF 5 220 450 50 5 12, 24, 36 – 8.2 2.61 2 × 10µF 100µF 3 × 47µF – 100pF 5 250 570 30 6 12, 24, 36 – 8.2 2.05 2 × 10µF 100µF 2 × 22µF 150µF 220pF 5 240 500 55 6 12, 24, 36 – 8.2 2.05 2 × 10µF 100µF 3 × 47µF – 100pF 5 300 660 30

(V)

JMK316BJ226ML-T (22µF, 6.3V, 1206 Case Size)

C3216X5R0J226MT (22µF, 6.3V, 1206 Case Size)

EMK316BJ226ML-T (22µF, 16V, 1206 Case Size)

C3216X5R1C226M (22µF, 16V, 1206 Case Size)

SET1A

fSET

(MΩ)

SET1B

(kΩ)

has very low input impedance.

Sanyo POSCAP 6TPE680MI (680µF, 6.3V, 18mΩ ESR, D4 Case Size)

Sanyo POSCAP 10TPF150ML (150µF, 10V, 15mΩ ESR, D3L Case Size)

SET2

(kΩ)

CIN

(CERAMIC)

CIN*

(BULK)

OUT2

(CERAMIC)

F 3 × 22µF 680µF –

OUT1

(BULK)

FFA

FFB

OUT(BULK)

LOAD

STEP

TRANSIENT

SLEW

(A/µs)

DROOP, 0A

RATE

TO 5A LOAD

STEP (mV)

5 140 275 60

TRANSIENT, PEAK-TO-PEAK, 0A TO 5A TO 0A STEP (mV

PK-PK

RECOVERY

)

TIME (µs)

For more information www.linear.com/LTM4641

4641fe

LTM4641

applicaTions inForMaTion—saFeTy anD layouT guiDance

Safety Considerations

The LTM4641 modules do not provide galvanic isolation from V

to V

. There is no internal fuse. If fusing is

OUT

required, a slow blow fuse with a rating twice the maximum input current needs to be provided. The LTM4641 sup

ports overcurrent protection and two kinds of overvoltage protection (see the Power Good Indicator and Latching Output Overvoltage Protection section).

Layout Checklist/Example

The high integration of LTM4641 makes the PCB board layout very straightforward. To optimize its electrical and thermal performance, some layout considerations are necessary. Figure 43 and Figure 44 show recommended layouts for the circuits shown in Figure 45 and Figure 46, respectively.

• Refer to the following document for device land pattern

and stencil design: http://www.linear.com/docs/40146.

• The gerber file for demo board DC1543 can be down

loaded at http://www.linear.com/demo

Use a solid copper GND plane directly underneath the

•

module. This will help form the return path electrical connections to the input source and output load. It will also provide a thermal path for removing heat from the BGA package and minimize junction temperature rise of the LTM4641 for a given application. For consistent ripple and noise from application

to application, connect the output GND plane (the one that conducts load side return current back to the module) and the input GND plane (the one that conducts module return current back to the input source) underneath the module, only.

• Use large PCB copper areas for high current paths, including V

INH

and V

OUT

• Place high frequency ceramic input and output capaci-

tors next to the V high frequency noise. V (1) place MSP as close to the V

, GND and V

INH

pins to minimize

OUT

exception: If MSP is used,

pins of the LTM4641

INH

as possible and (2) bypass the drain of MSP—and not

—to GND pins of the LTM4641. Only one or two

INH

high frequency MLCCs (C directly next to the V

and GND pins of the LTM4641,

OUT

OUT(MLCC)

) need be placed

to minimize high frequency noise close to the source.

The majority of C

OUT(MLCC)

should be located close to

the load to provide high quality bypassing.

• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.

• Do not put vias

directly under any pads, unless they

are capped or plated over.

• Use a separated SGND ground copper area for compo nents connecting to signal pins. Components connecting to SGND should be placed as close to the module as possible and routed with minimum trace lengths and trace widths, for best noise immunity.

• Note that there are two clusters of SGND pins on the module: one, formed by Pins A1-A3, B1-B3, C1-C4 (A1-quadrant); and a second formed by Pins K1, K3, L3, and M1-M3 (M1-quadrant). It is good PCB design practice to provide a copper plane connecting all A1-quadrant SGND pins together and another plane connecting all M1-quadrant SGND pins together. It is not necessary to connect these two clusters of SGND copper planes to each other in the PCB layout, because all SGND pins are electrically connected to each other internal to the module.

• Do not connect the any SGND pins or SGND plane(s) to the GND plane; the electrical star connection is made internal to the module.

• For parallel module operation, see the Multimodule Parallel Operation section for a list of interconnecting pins across paralleled modules. 66 show

four and two LTM4641 devices operating in

Circuit Figures56 and

parallel, respectively. Route signal-level (non-power) nets on an internal layer, with GND planes overlapping signal routes to shield them from noise. It is even more effective to surround module-to-module signal connections on the internal layer containing the signal routes with adjacent GND planes or routes, and periodi cally “punching-through” GND

via connections to plane shields on adjacent layers. This practice forms the equivalent of a “coaxial cable” structure within the PCB, and is highly effective at shielding sensitive signals from noise sources. Maintain differential routing of the V

OSNS

–

pin pair.

GND

4641fe

For more information www.linear.com/LTM4641

LTM4641

applicaTions inForMaTion—saFeTy anD layouT guiDance

• Place all feedback components as close to the module as possible, giving layout priority first to capacitors

, C

FFA

FFB

next by R

, C

SET1A

CMA

, R

, C

CMB

SET1B

and CDM (if used)—followed

and R

(if used). See Figure5

SET2

in the Applications Information section and Figure 64 in Appendix D for more details. Maintain differential routing of the remote-sense lines between the load and the module. Form a “coaxial cable” structure that surrounds the remote-sense lines with GND potential within the PCB, to the extent that layout permits. See

an example of routing the VOUT/GND remote-sense pin pair in Layer 3 of DC1543.

• To facilitate stuffing verification, and test and debug ac tivities, consider routing control signals of the LTM4641 with short traces to localized test points, test pads or test vias—as PCB layout space permits. Both in-house and contract manufacturers enjoy gaining electrical access to all non low impedance (≥10Ω) pins of an IC or μModule regulator to improve in-circuit test (ICT) coverage.

Figure 43. Recommended PCB Layout, Figure 45 Circuit. View of the LTM4641 from Top of Package

Figure 44. Recommended PCB Layout, Figure 46 Circuit. View of the LTM4641 from Top of Package

For more information www.linear.com/LTM4641

4641fe

LTM4641

(4.5V START-UP)

DECOUPLING

4.5V START-UP

DECOUPLING

Typical applicaTions

4V TO 38V

IN(BULK)

50V

fSET

IN(MLCC)

10µF 50V ×2

SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

INL

SET

UVLO HYST FCB

INTV

DRV

IOVRETRY OVLO

RUN

TRACK/SS

INGVINGP

4.7nF

INH

LTM4641

TMR

N/U

SWV

CROWBAR

LATCH

OSNS

TEMP

OVPGM

OTBH

PGOOD

GNDSGNDCOMPTMR

OUT

ORB

REF

4641 F45

OUT

LOAD

1.8V 10A

LOCAL HIGH FREQUENCY

OUT(MLCC)

47µF 10V ×6

SET2

16.4k

SET1A

8.2k

SET1B

8.2k

–

OPERATION

UP TO 38V

Figure 45. 4VIN to 38VIN, LTM4641 Basic Configuration, 1.8V Output at 10A

MSP

IN(BULK)

100µF 50V

IN(MLCC)

10µF 50V ×2

SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

INL

SET

UVLO HYST FCB

INTV

DRV

IOVRETRY OVLO

RUN

TRACK/SS

INGVINGP

22nF

INH

LTM4641

SWV

CROWBAR

LATCH

OSNS

TEMP 1V

OVPGM

PGOOD

GNDSGNDCOMPTMR

OUT

ORB

REF

OTBH

4641 F46

FFA

100pF

MCB

SET2

4.7k

–

SET1A

8.2k

SET1B

LOAD

8.2k

FFB

100pF

MCB: NXP PSMN5R0-30YL MSP: NXP PSMN7R0-60YS

Figure 46. LTM4641 Delivering 3.3V Output at 10A, and Providing Robust Output Overvoltage Protection from up to 38VIN. Dropout Operation May Occur Below 4.8VIN. See Figure 11 to Implement Custom UVLO Rising/Falling Settings to Avoid Dropout Operation

100µF

6.3V ×3

LOCAL HIGH FREQUENCY

OUT

3.3V 10A

4641fe

For more information www.linear.com/LTM4641

Typical applicaTions

4.5V START-UP OPERATION UP TO 28V CONTINUOUS, TRANSIENT PROTECTED TO 80V

is Turned On to Protect the Load Upon OOV Detection.

IN(BULK)

100µF 100V

D2 Enables Detection

UVLO Falling

of V

LT®3010-5

SHDN

ROV

4.7M

BOV

Switching Action Is

29.4k

Temporarily Latched Off if V Restart Attemps Occur in 9 Second Intervals When Input Voltage Returns Below 80V. Note LT3010-5 is Rated for 80V, Absolute Maximum. See Note 1.

D2: CENTRAL SEMI CMMSH1-100G MCB: NXP PSMN5R0-30YL MSP: NXP PSMN028-100YS RT1: MURATA NCP15WM474J03RC

SENSE

GND

Exceeds 80V; Autonomous

IN(MLCC)

10µF 100V ×2

OUTV

LTM4641

20k

Exceeds ~36V, D1 Ensures MSP Is Operated

RT1 NTC

MSP

INGP

36V 2%

LTM4641

TMR

1µF

INH

8.25k

fSET

2.7M

SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

INL

SET

UVLO

HYST FCB

INTV

DRV

IOVRETRY

OVLO

RUN

TRACK/SS

ING

1nF

When V

in Its Linear Region and Provides Rudimentary Surge Ride-Through Protection for LTM4641.

Optional: RT1, R1, R2, R3.To Enable RT1’s Detection of Thermal Overstress in MSP During Sustained Input Voltage

Surge Events, Place RT1 in Extremely Close Proximity to MSP in PCB Layout. Experimentally Determine the Vaules of R1, R2 and R3 That Yield Desired Overtemperature Shutdown Inception and Restart Recovery Thresholds Consistent with MSP’s Rated Operating Junction Temperature and Safe Operating Area

SWV

OUT

CROWBAR

LATCH

ORB

OSNS

ORB

TEMP 1V

REF

OVPGM

OTBH

PGOOD

GNDSGNDCOMPTMR

4641 F47

MCB

–

SET1A

5.49k

SET1B

LOAD

5.49k

MSP and Switching Action Are Temporarily Latched Off When a Module Overtemperature or Output Overvoltage (OOV) Condition is Detected--Additionally, the Crowbar MOSFET MCB

Autonomous Restart Attempts Occur in 9 Second Intervals When Conditions Return to Normal

TechClip Available (Click to View)

100µF

6.3V ×4

LOCAL HIGH FREQUENCY DECOUPLING

V 1V 10A

OUT

Figure 47. LTM4641 Generating 1V Output at 10A, Surge Protected up to 80VIN Transients. Start-Up and Shutdown Waveforms with TMR = INTVCC Shown In Figure 2

20V/DIV

INH

20V/DIV

20mV/DIV

OUT

INL

AC-COUPLED

/INTVCC/DRVCC/LATCH

5V/DIV

2ms/DIV

4641 F48

Figure 48. Oscilloscope Snap-Shot of Figure 47 Circuit Riding Through 80V Transient While Delivering 1V

For more information www.linear.com/LTM4641

at 10A to the Load

OUT

4641fe

LTM4641

Typical applicaTions

3.3VIN NOMINAL

RISING START-UP

FALLING SHUTDOWN

2.3V

LOW POWER BIAS

Figure 49. LTM4641 Producing 0.9V V

MSP

IN(BULK)

<50mA PEAK

, INTVCC, and DRVCC Biased from a Low Power Auxiliary 5V Rail

INL

TUV

150k

BUV

30.9k

100k

SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

IN(MLCC)

47µF

6.3V ×2

fSET

360k

HYST

at 10A, from 3.3VIN, and Providing Advanced Output Overvoltage Protection.

OUT

INL

SET

UVLO

HYST FCB

INTV

DRV

IOVRETRY OVLO

RUN

TRACK/SS

INGVINGP

4.7nF

INH

LTM4641

SWV

OUT

CROWBAR

LATCH

ORB

OSNS

ORB

TEMP 1V

REF

OVPGM

OTBH

PGOOD

GNDSGNDCOMPTMR

MCB

–

4641 F49

SET1A

4.12k

SET1B

LOAD

4.12k

MCB: NXP PH2625L MSP: NXP PSMN013-30LL

100µF

6.3V ×4

LOCAL HIGH FREQUENCY DECOUPLING

OUT

0.9V 10A

1V/DIV

OUT

1V/DIV

HYST

5V/DIV

PGOOD

5V/DIV

4ms/DIV

Figure 50. Oscilloscope Snap-Shot of Figure 49 Circuit, 2Ω Load on V

4641 F50

OUT

3.3VIN Applied Briefly to Highlight UVLO Rising and Falling Thresholds

4641fe

For more information www.linear.com/LTM4641

Typical applicaTions

LTM4641

8.5V TO 38V

(10V START-UP)

LDO Losses in the LTM4641 Can Be Greatly Reduced When an Auxilliary ~5V to 6V Source (V

AUX

IN(BULK)

TUV

294k

BUV

15.8k

D1, D2: CENTRAL SEMI CMKSH2-4LR SOT-363 PACKAGE

IN(MLCC)

DRVCC

2.2µF

Through a Schottky Diode as Shown (D1c). When LTM4641 Is Conﬁgured to Produce ~5V

Drive DRV

its Output Can Be V with V

AUX

10µF

50V

×2

VINL

0.1µF 50V

AUX

–Accomplished Here with D1a and D1b

INL

SET

UVLO

HYST

HYST FCB

INTV DRV IOVRETRY OVLO

RUN

Figure 51. Over-Driving INTVCC/DRVCC to Reduce V

) Is Available to

AUX

. Provide a Current Path to V

INGVINGP

LTM4641

TRACK/SS

47nF

SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

-to-INTVCC Linear Regulator Losses (cf. Figures 52 to 54)

INL

from VIN and INTVCC/DRVCC Whenever Overdriving INTVCC/DRV

INL

SWV

INH

OUT

CROWBAR

LATCH

ORB

OSNS

ORB

TEMP

OVPGM

OTBH

PGOOD

GNDSGNDCOMPTMR

REF

–

4641 F51

OUT(BULK)

150µF 10V

SET2

~2.05k TO 2.61k

OUT

to 6V

OUT(MLCC)

47µF 10V ×2

SET1A

8.2k

SET1B

8.2k

OUT

LOAD

~5V TO 6V UP TO 10A

OUT

Figure 52. Thermal Image of U1 from Figure 51 Circuit. Delivering 5V

at 10A from 36VIN, with INTVCC Connected

OUT

to DRVCC and D1c = Open and D2 = Open. TA = 25°C, Bench Testing, No Airflow

Figure 53. Thermal Image of U1 from Figure 51 Circuit. Delivering 6V

at 10A from 36VIN, with INTVCC Connected

OUT

to DRVCC and D1c = Open and D2 = Open. TA = 25°C, Bench Testing, No Airflow

For more information www.linear.com/LTM4641

Figure 54. Thermal Image of U1 from Figure 51 Circuit. Delivering 5V

at 10A from 36VIN, with 5V

OUT

Feeding INTVCC/

OUT

DRVCC Through D1c Diode. TA = 25°C, Bench Testing, No Airflow

Figure 55. Thermal Image of U1 from Figure 51 Circuit. Delivering 6V

at 10A from 36VIN, with 6V

OUT

Feeding INTVCC/

OUT

DRVCC Through D1c Diode. TA = 25°C, Bench Testing, No Airflow

4641fe

LTM4641

Typical applicaTions

4.5V

START-UP

OPERATION UP TO 38V AND DOWN TO 4V

IN(BULK)

100µF 50V ×2

RUN ENABLE

(OPTIONAL)

AND INSTALL C

, C

TMR3

FAULT INDICATOR

LATCHOFF RESET

AND C

TMR4

TMR1

TO SET

TO SYSTEM µP

PULL LATCH NORMALLY LOW FOR LATCHOFF RESPONSE TO OUTPUT OVERVOLTAGE AND OVERTEMPERATURE EVENTS. PULL LATCH HIGH TO RESTART 1V OUTPUT

ALTERNATIVELY, CONNECT LATCH TO INTV

TMR2

1V OUTPUT FOR TIMED AUTONOMOUS RESTART AFTER FAULT SHUTDOWN EVENTS

MCB: NXP PSMN5R0-30YL MSP: NXP PSMN3R0-60BS

IN(MLCC)

10µF 50V ×4

R 750k

fSET1

fSET2

INL

SET

UVLO HYST FCB

INTV

DRV

IOVRETRY OVLO

RUN

22nF

INL

SET

UVLO HYST FCB

INTV

DRV

IOVRETRY OVLO

RUN

MSP

INGVINGP

TMR1

N/U

INGVINGPVINH

TMR2

N/U

INH

LTM4641

OUT

CROWBAR

LATCH

ORB

OSNS

DM1

10pF

–

OSNS

–

ORB

TEMP

REF

OVPGM

OTBH

PGOOD

LATCH

ORB

OSNS

ORB

TEMP

OTBH

PGOOD

OUT

DM2

10pF

–

REF

GNDSGNDCOMPTMRTRACK/SS

CROWBAR

OVPGM

GNDSGNDCOMPTMRTRACK/SS

MCB

100pF

SET1A

1.37k

SET1B

1.37k

100pF

FF1

LOAD

FF2

MLCC(OUT)

100µF

6.3V ×12

LOCAL HIGH FREQUENCY DECOUPLING

OUT

1V 40A

INGVINGPVINH

INL

fSET3

750k

SET

UVLO HYST FCB

INTV

DRV

IOVRETRY OVLO

RUN

TMR3

N/U

INGVINGPVINH

INL

fSET4

750k

SET

UVLO HYST FCB

INTV

DRV

IOVRETRY OVLO

RUN

TMR4

N/U

U1, U2, U3 AND U4 SGND ( 1, 2, 3, 4) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP MODULE SGND ROUTES/PLANES SEPARATE FROM OTHER MODULES AND FROM GND ON MOTHERBOARD

LTM4641

OUT

CROWBAR

LATCH

ORB

OSNS

DM3

10pF

–

OSNS

–

ORB

TEMP

REF

OVPGM

OTBH

PGOOD

LATCH

ORB

OSNS

ORB

TEMP

OTBH

PGOOD

OUT

DM4

10pF

–

REF

4641 F56

GNDSGNDCOMPTMRTRACK/SS

CROWBAR

OVPGM

GNDSGNDCOMPTMRTRACK/SS

Figure 56: 1V, 40A Fault-Protected Load Powered by Four Parallel LTM4641—from Up to 38VIN. cf. Figure 57

4641fe

For more information www.linear.com/LTM4641

Typical applicaTions

LTM4641

MODULE OUTPUT CURRENT (A)

–2

8 16 24 40

TOTAL OUTPUT CURRENT (A)

U1 OUTPUT CURRENT U2 OUTPUT CURRENT U3 OUTPUT CURRENT U4 OUTPUT CURRENT

4641 F57

Figure 57: Current-Sharing Performance of Four Paralleled LTM4641. Figure 56 Circuit, Operating at 28V

OPERATION

UP TO 32.8V

4.5V START-UP

IN(BULK)

50V

IN(MLCC)

10µF 50V ×4

100k

D1: CENTRAL SEMI CMPSH1-4LE SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND

INL

SET

UVLO HYST FCB

INTV

DRV

IOVRETRY OVLO

RUN

INGVINGPVINH

LTM4641

10nF

ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

FOR MORE INFORMATION ABOUT CONFIGURING STEP-DOWN BUCK CONVERTERS AS BUCK-BOOST CONVERTERS, FOR GENERATING NEGATIVE V

CROWBAR

, SEE http://www.linear.com/docs/39881

OUT

LATCH

ORB

OSNS

ORB

TEMP

OVPGM

OTBH

PGOOD

GNDSGNDCOMPTMRTRACK/SS

+ +

–

REF

SET2

2.46k

SET1A

8.2k

SET1B

8.2k

OUT(MLCC)

47µF 10V ×4

LOAD

LOCAL HIGH FREQUENCY DECOUPLING

OUT

–5.2V AT UP TO 10A

4641 F58

Figure 58. Negative Output Application. Delivering –5.2V

OUT

For more information www.linear.com/LTM4641

at Up to 10A, from Up to 32.8VIN. cf. Figure 59

4641fe

LTM4641

Typical applicaTions

VIN 10V/DIV

HYST 2V/DIV

PGOOD 2V/DIV

OUT

2V/DIV

4.5V < VIN < 15V

ADDITIONAL

FAULT INDICATOR

3.3V

TO UPSTREAM

SYSTEM ENABLE

PMBus

INTERFACE

WRITE PROTECT

TO/FROM

OTHER

LTC2978s

†

PWR

DD33

IN_EN

SDA SCL

ALERT

CONTROL0 WP

FAULTOO

SHARE_CLK

20ms/DIV

4641 F59

Figure 59. Pulsed Application of VIN. Figure 58 Circuit with 500Ω Load.

*Ultralow VF of D1 Minimizes V

fSET

1.13M

C 22µF 25V ×2

IN(MLCC)

INL

SET

UVLO HYST FCB

INTV DRV

IOVRETRY OVLO

RUN

TO µP RESET INPUT

IN(BULK)

100µF 25V

IN_SNS

OUT_EN0

LTC2978**

DACPO

SENSEPO

SENSEMO

DACMO

PWRGD

WDI/RESET WATCHDOG TIMER INTERRUPT

ASEL1GND ASELO

INGVINGP

4.7nF

MSP

Overshoot Upon Energization

OUT

INH

LTM4641*

OUT

CROWBAR

LATCH

ORB

OSNS

–

OSNS

–

ORB

TEMP

REF

OVPGM

OTBH

PGOOD

GNDSGNDCOMPTMRTRACK/SS

LTM4641 SGND CONNECTS TO GND INTERNAL TO MODULE.

KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

ONLY ONE OF EIGHT LTC2978 CHANNELS SHOWN. LTC2978 PULL-UPS,

BYPASSING COMPONENTS, AND SOME PINS NOT SHOWN. FOR DETAILS OF LTC2978 IMPLEMENTATION, SEE LTC2978 DATA SHEET

†

LTC2978 MAY BE POWERED FROM EITHER AN EXTERNAL 3.3V SUPPLY OR THE SYSTEM BUS

LATCHOFF RESET

R30

35.7k

SET1A

8.2k

SET1B

8.2k

MCB

LOAD

MSP: NXP PSMN017-30LL MCB: NXP PSMN5R0-30YL

1.2V NOMINAL UP TO 10A OUTPUT

100µF

6.3V ×4

LOCAL HIGH FREQUENCY DECOUPLING

OUT

Figure 60. Fault-Protected Load with Power Supply Management. LTM4641’s Fast Output Overvoltage Latchoff Trip Threshold Remains Consistently 11% Above LTC2978-Commanded Target V

For more information www.linear.com/LTM4641

, Even as V

OUT

is Margined Via I2C

OUT

4641fe

Typical applicaTions

LTM4641

200mV/DIV

500mV/DIV

SDA, SCL

2V/DIV

OUT

DACPO

20ms/DIV

4641 F61a

20ms/DIV

4641 F61b

OUT

200mV/DIV

DACPO

500mV/DIV SDA, SCL

2V/DIV

(61a) PMBus OPERATION (Reg. 0x01): 0x80 → 0xA8 (Margin High) (61b) PMBus OPERATION (Reg. 0x01): 0xA8 → 0x80 (Margin Off)

4641 F61d

OUT

200mV/DIV

DACPO

500mV/DIV SDA, SCL

2V/DIV

200mV/DIV

500mV/DIV

SDA, SCL

2V/DIV

OUT

DACPO

20ms/DIV

4641 F61c

20ms/DIV

(61c) PMBus OPERATION (Reg. 0x01): 0x80 → 0x98 (Margin Low) (61d) PMBus OPERATION (Reg. 0x01): 0x98 → 0x80 (Margin Off)

Figure 61. LTM4641’s V

Margined High/Low by LTC2978 Via I2C Commands. Figure 60 Circuit. 12VIN.

OUT

VOUT_COMMAND (0x21) = 1.20V, VOUT_MARGIN_HIGH (0x25) = 1.32V, VOUT_MARGIN_LOW (0x26) = 1.08V

For more information www.linear.com/LTM4641

4641fe

LTM4641

Undervoltage Lockout and Hystersis

Optional Programmable

Low Current Path: Power

(4.5V START-UP)

for example of n = 4.)

appenDices

Appendix A. Functional Block Diagram and Features Quick Reference Guide

VIN4V TO 38V

≤ 3V,

OUT

IN(BULK)

INH

IN(MLCC)

≠ V

INL

Rail Tracking Applications and When

On-Time and Switching Frequency

Adjustment REQUIRED for V

fSET

INL

0.1µF C

INTV

1.3M

10k

POR/Timeout

Circuit Output

ENABLE

SWITCHING

Control and Logic Bias Input

) Charge Pump and

Optional Series Pass

Electronic “Circuit Breaker”

N-Ch Protection MOSFET

Discharge Path for Optional

External Series Pass N-Ch FET

10V Bias (V

MSP

ING

Turn-on Charge Pump

ING

And Fault/Shutdown Discharge

Circuitry

POWER

CONTROL

ACTION

HYST

Optional Power RC

Snubber for Reduced

High Current Path:

Input to SMPS DC/DC Converter Stage

INH

CONSTANT

ON-TIME

SET Q

2.2µF

TOP

VALLEY MODE

SYNCHRONOUS

BUCK CONTROLLER

RST

SET

INGP

15V

ZENER

RST

EMI

OUT

0.6V TO 6V

OUT

0.8µH

UP TO 10A

OUT(MLCC)

OUT(BULK) C

OUT

10µF



4641 F62

SET1A

SET2

2• R

≤ 1.2V

OUT

> 1.2V

SET1A

OUT

8.2kΩ

≤ 8.2k

SET1



SET1A

ORB

8.2k

Remote Sense

= R

SET1A

= 0.6V 1+n

Required for V

Not Necessary for V

SET2

OUT

n = number of modules operaing in parallel

(See Figure 66 for example of n = 2 and Figure 56

Use R

Readback Pins

Ampliﬁer

Differential Sense Feedback Path with Redundant

Differential

Optional Output

Protection

Crowbar N-Ch

Logic-Level

MOSFET

SET1B

SET2

–

ORB

10nF

8.2k

100pF

47pF

–

OSNS

8.2k

–

MCB

GND

SGND

CROWBAR

1.5M

10k

Pull-Down

TO E/A

REF

)

600mV

ING

To V

OOV

–

Comparator

Fast Output Overvoltage

RST

SET

BOT

Figure 62. Functional Block Diagram

IUV

–

0.5V

HYST

UVLO

HYST

BUV

TUV

Optional Programming of Input

IOV

IOVR

–

499k

OVLO

IOVRETRY

TOVRMOVRBOV

Thresholds

of Nonlatching

Overvoltage (OV)

and Latching Input

Optional Programming

REF

–OT+

12.1k

3.48k

TEMP

Analog Temperature Output

REF

PGOOD

SS/TRACK

INL

LDO Off of V

5.3V Internal V

INTERNAL

REF*

Output Voltage

DRUV

–

66.5k

NTC

(OT) Protection

Programmable OT Shutdown

Indicator and Overtemperature

Behavior: Latchoff vs Hysteretic

10k

OTBH

Restart

Input and Output

OV and OT Latch Reset

Timeout Delay Time

Power-On Reset and

POR/Timeout

TMR

Delay Timer Circuit

OSC*

FCB

COMP

DRVCCINTV

LATCH

Efﬁciency

FET Driver Bias Input

Optional Pulse-Skipping

Operation for Light Load

TMR

Internal Control

Loop Compensation

For more information www.linear.com/LTM4641

COMP

4µF

NOM

499k

666mV

PGM

TOVPGM

Recommended

Soft-Start or Rail Tracking

Power Good Indicator

OVPGM

BOVPGM

Optional Adjustment of Output

Overvoltage Threshold (Default

/SGND RAILS

RUN

Nominal)

Internal Setting: 11% Above

*OSC, REF, COMPARATORS, OP AMPS AND DIGITAL GATES SHOWN

OPERATE FROM INTV

<0.8V = Off

Output Enable Pin

>2V or Floating = On

SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND ROUTES/PLANES

SEPARATE FROM GND ON MOTHERBOARD

4641fe

)

TEMP

TH(INCEPTION)

LATCHOFF IS CLEARED WHEN INTV

> 2V, NOM AND LATCH = HIGH

appenDices

Appendix B. Start-Up/Shutdown State Diagram

)

, ~0.5V

)

, ~514mV

)

TH(RECOVER)

> OT

, ~1.5V

TEMP

, ~0.5V<)

CROWBAR(TH)

< UVOV

< V

OVLO

CROWBAR

3. TEMPERATURE O.K. (OTBH = LOW AND V

AND ALL LATCHOFF FAULT-MONITOR OUTPUTS REMAIN OPERATIONALLY

VALID FOR THE FULL DURATION OF THE TIMEOUT PERIOD:

1. INPUT VOLTAGE O.K. (V

2. CROWBAR O.K. (V

LTM4641 TIMEOUT DELAY IMPOSED DURING LATCHOFF:

, ~514mV

, ~0.5V

> UVOV

, ~3.9V

TH(RECOVER)

< UVOV

IOVRETRY

< OT

ULVO

CC(UVLO_RISING)

TEMP

< DRV

DRVCC

TOO LOW (V

> 2V, NOM;

4. NONLATCHING OVERTEMPERATURE

(OTBH = OPEN CIRCUIT AND V

2. NONLATCHING INPUT OVERVOLTAGE (V

INTV

AND ANY OF THE FOLLOWING NONLATCHING CONDITONS APPEAR:

1. CUSTOM UVLO INPUT TOO LOW (V

3. DRV

IS ON)

HYST

)

TMR

> 2V, NOM AND

LATCH = LOW

< 2V, NOM INTV

INTV

UNTIL AND UNLESS ALL LATCHOFF FAULT-MONITOR OUTPUTS

REMAIN CLEAR FOR THE FULL DURATION OF THE TIMEOUT

PERIOD, AS SET BY TMR PIN (C

HOUSEKEEPING CIRCUITRY HOLDS HYST LOW (M

)

, ~1.5V

, ~514mV

, ~0.5V

CROWBAR(TH)

TH(RECOVER)

> V

> UVOV

< OT

OVLO

CROWBAR

TEMP

> 2V, NOM AND LATCH = HIGH

2. CROWBAR ACTIVE (V

AND ANY LATCHOFF FAULT IS PRESENT:

1. INPUT OVERVOLTAGE (V

3. LATCHOFF OVERTEMPERATURE

INTV

(OTBH = LOW AND V

LTM4641 SHUT DOWN:

)

, ~1.5V

, ~514mV

, ~0.5V

CROWBAR(TH)

TH(RECOVER)

< UVOV

< V

> OT

OVLO

TEMP

CROWBAR

AND NO LATCHOFF FAULTS ARE PRESENT:

1. INPUT VOLTAGE O.K. (V

2. CROWBAR O.K. (V

3. TEMPERATURE O.K.

(OTBH = LOW AND V

IS ON); POWER

HYST

SWITCHING ACTION:

HYST IS PULLED LOW

ALIVE AND INHIBITING

LTM4641 HOUSEKEEPING

< 2V, NOM

INTV

TIMEOUT PERIOD

BECOMES RESET

> 2V, NOM

INTV

ING

DISCHARGED

CONTROL SECTIONS

HOUSEKEEPING AND

STAGE IS OFF; V

ARE UNBIASED; POWER

> 2V, NOM;

INTV

ING

DISCHARGED

STAGE IS OFF; V

LTM4641 LATCHOFF

> 2V, NOM

INTV

AND LATCH = LOW

< 2V, NOM

INTV

)

, ~0.5V

> UVOV

UVLO

AND ALL OF THE FOLLOWING FAULT FREE CONDITIONS

ARE PRESENT (OR RECENTLY APPEARED, EXITING LATCHOFF):

1. CUSTOM UVLO INPUT O.K. (V

2. NO INPUT OVERVOLTAGE(S)

> 2V, NOM

LATCHOFF IS CLEARED WHEN INTV

IS ON); POWER

HYST

HYST IS LATCHED LOW

CONDITION DETECTED:

< 2V, NOM

INTV

)

, ~1.5V

, ~514mV

, ~0.5V

)

CROWBAR(TH)

< UVOV

TH(RECOVER)

< V

, ~4.05V

OVLO

> OT

CROWBAR

TEMP

AND V

< UVOV

IOVRETRY

3. CROWBAR INACTIVE (V

4. TEMPERATURE O.K. (V

)

, ~1.5V

, ~0.5V

< UVOV

< V

OVLO

AND LATCH TOGGLES FROM LOGIC LOW

TO HIGH AND NO LATCHOFF FAULTS ARE PRESENT:

1. INPUT VOLTAGE O.K. (V

2. CROWBAR O.K. (V

ING

OF TIMEOUT PERIOD

LTM4641 VERIFICATION

CC(UVLO_RISING)

> DRV

ABOVE ITS UVLO

DRVCC

5. DRV

)

, ~514mV

CROWBAR(TH)

TH(RECOVER)

> OT

TEMP

CROWBAR

3. TEMPERATURE O.K.

(OTBH = LOW AND V

DISCHARGED

STAGE IS OFF; V

)

, ~0.5V

, ~1.5V

, ~438mV

> UVOV

OVLO

CROWBAR(TH)

TH(INCEPTION)

> V

< OT

CROWBAR

TEMP

> 3.9V, NOM

INTV

> 2V, NOM

INTV

AND ANY OF THE FOLLOWING LATCHOFF FAULTS ARE PRESENT:

1. LATCHOFF INPUT OVERVOLTAGE (V

3. LATCHOFF OVERTEMPERATURE

(OTBH = LOW AND V

2. CROWBAR ACTIVE (V

SWITCHING ACTION

LTM4641 POWER STAGE

IS ON) UNTIL AND

HYST

MONITOR OUTPUTS REMAIN

EXPIRATION: HOUSEKEEPING

CIRCUITRY HOLDS HYST LOW

UNLESS THE UVLO/IOVRETRY/

OVLO/CROWBAR/TEMP/DRV

CLEAR FOR THE FULL DURATION

OF THE TIMEOUT PERIOD, AS SET

< 2V, NOM

INTV

)

, ~0.5V

, ~1.5V

, ~514mV

> UVOV

OVLO

CROWBAR(TH)

TH(RECOVER)

> V

< OT

CROWBAR

TEMP

> 2V, NOM

INTV

AND ANY LATCHOFF FAULTS ARE PRESENT:

1. LATCHOFF INPUT OVERVOLTAGE (V

3. LATCHOFF OVERTEMPERATURE

(OTBH = LOW AND V

2. CROWBAR ACTIVE (V

)

, ~1.5V

, ~0.5V

, ~514mV

, ~0.5V

CROWBAR(TH)

> UVOV

< UVOV

TH(RECOVER)

< V

UVLO

OVLO

> OT

CROWBAR

TEMP

AND V

< UVOV

IOVRETRY

3. CROWBAR INACTIVE (V

2. NO INPUT OVERVOLTAGE(S)

AND ALL OF THE FOLLOWING

FAULT FREE CONDITIONS ARE PRESENT:

IS OFF;

HYST

IS CHARGE PUMPED

IS ON: M

ING

4. TEMPERATURE O.K. (V

1. CUSTOM UVLO INPUT O.K. (V

OUT

; CONTROL

INH

ABOVE V

LOOP REGULATES V

MONITOR

); POWER

IS DISCHARGED

TMR

ING

BY TMR PIN (C

STAGE IS OFF; V

OUTPUTS HAVE REMAINED CLEAR FOR THE FULL DURATION

OF THE TIMEOUT PERIOD

UVLO/IOVRETRY/OVLO/CROWBAR/TEMP/DRV

< 2V, NOM

INTV

)

, ~4.05V

, MAX)

(2V

CC(UVLO_RISING)

RUN(ON)

> DRV

ABOVE ITS UVLO

DRVCC

5. DRV

6. RUN > V

)

4641 F63

, ~0.5V

< UVOV

> 2V, NOM;

INTV

AND ANY OF THE FOLLOWING NONLATCHING CONDITONS APPEAR:

1. CUSTOM UVLO INPUT TOO LOW (V

;

NOM

TO EXCEED 3.6V

REGULATE: WAITING

LTM4641 PRIMED TO

ONLY FOR RUN PIN TO

TRANSISTION HIGH AND

SWITCHING ACTION NOT

INTV

)

, MIN)—

, ~0.5V

> UVOV

< UVOV

UVLO

AND V

< 3.2V, NOM— AND ADDITIONALLY,

> 3.2V NOM AND RUN = LOW (0.8V

OR 2V < INTV

EITHER INTV

< UVOV

IN EITHER CASE, ALL OF THE FOLLOWING FAULT FREE

CONDITIONS EXIST:

1. CUSTOM UVLO INPUT O.K. (V

2. NO INPUT OVERVOLTAGE(S)

)

, ~0.5V

> UVOV

UVLO

> 3.2V, NOM

INTV

AND ALL OF THE FOLLOWING

FAULT FREE CONDITIONS ARE PRESENT:

1. CUSTOM UVLO INPUT O.K. (V

2. NO INPUT OVERVOLTAGE(S)

LTM4641

)

, ~0.5V

, ~438mV

)

, ~3.35V

> UVOV

IOVRETRY

UVLO

CC(UVLO_FALLING)

< DRV

DRVCC

TOO LOW (V

2. NONLATCHING INPUT OVERVOLTAGE (V

3. DRV

IS OFF);

HYST

CIRCUITRY (M

INHIBITED BY HOUSEKEEPING

)

, ~1.5V

, ~514mV

CROWBAR(TH)

TH(RECOVER)

< V

OVLO

> OT

CROWBAR

TEMP

IOVRETRY

3. CROWBAR INACTIVE (V

4. TEMPERATURE O.K. (V

)

, ~1.5V

, ~438mV

, ~0.5V

CROWBAR(TH)

< UVOV

TH(INCEPTION)

< V

OVLO

> OT

CROWBAR

TEMP

AND V

< UVOV

IOVRETRY

3. CROWBAR INACTIVE (V

4. TEMPERATURE O.K. (V

)

, ~1.5V

TH(INCEPTION)

, ~0.5V

< OT

CROWBAR(TH)

TEMP

< UVOV

< V

OVLO

CROWBAR

4. NONLATCHING OVERTEMPERATURE

(OTBH = OPEN CIRCUIT AND V

2. CROWBAR O.K. (V

3. TEMPERATURE O.K.

AND NO LATCHOFF FAULTS ARE PRESENT:

1. INPUT VOLTAGE O.K. (V

IS DISCHARGED

ING

POWER STAGE IS OFF;

)

, ~3.35V

CC(UVLO_FALLING)

> DRV

ABOVE ITS UVLO

DRVCC

5. DRV

)

, ~3.35V

, MAX)

(2V

CC(UVLO_FALLING)

RUN(ON)

> DRV

ABOVE ITS UVLO

DRVCC

6. RUN > V

5. DRV

)

, ~438mV

> OT

(OTBH = LOW AND V

Figure 63. Start-Up/Shutdown State Diagram

4641fe

For more information www.linear.com/LTM4641

LTM4641

appenDices

Appendix C. Switching Frequency Considerations and Usage of R

There exist many scenarios in which a resistor, R should be connected externally to LTM4641’s f decrease the on-time of M

fSET

pin—to

SET

: most commonly, when the

TOP

fSET

output voltage setting is less than or equal to 3V, and in rail-tracking applications; and less commonly, when V and V the former cases, R

are operating from different source supplies. In

INH

is usually applied from f

fSET

SET

to V

INL

(Figure 45 and front page application circuit); in the latter,

is usually applied from f

fSET

to the voltage source

SET

feeding LTM4641’s power stage—upstream of MSP, if a power-interrupt input MOSFET is used (Figure49). There are several motivations and considerations behind this guidance:

(1) Inherent to LTM4641’s constant on-time architec

ture, the switching frequency of LTM4641 decreases as output voltage decreases. In order to maintain a reasonable output capacitor value solution size and output voltage ripple—even at lower output voltages (≤3V ler’s I

)—R

OUT

pin current and the resulting nominal switching

should be applied, so that the control-

fSET

frequency is higher than the on-time dictated by the internal V

INL

-to-f

-connected 1.3MΩ resistor.

SET

(2) The PFM control scheme employed by LTM4641 yields

a switching frequency at zero load current (“no-load operation”) that is typically 20% to 25% lower than

DS(ON)

what it is at full load. As a result, inductor ripple cur

proportionally higher at no

rent is

load than what it is at heavy load. Recall that LTM4641 employs R current sensing; furthermore, realize that it is essential for the controller’s current-sense amplifier to be able to perceive and command sufficiently negative inductor trough current, enough to maintain a maximum average inductor current of 0A, so that output voltage can be properly regulated down to no load. A value of R

fSET

should be used to assure that switching frequency is high enough (or on-time is small enough) at no load so that the current-sense information representing the trough of choke current is never too large in ampli tude. Figure maximum value of R

current) that assures proper no-load operation.

3 provides conservative

(or equivalently, the minimum

fSET

guidance on the

(3) In rail-tracking applications, LTM4641’s output voltage

must track a reference voltage not only during V ramp up but also during V

ramp down; fulfilling

OUT

the latter requires LTM4641 to sink current from the output capacitors. A value of R

should be used

fSET

that assures the output voltage can be ramped down to one’s minimum desired output voltage of regula

tion—not just the intended nominal output voltage. Figure 3 provides this guidance.

(4) In order to maintain a relatively constant switching

frequency for a given output voltage (across the full line voltage), the on-time of M proportional to the voltage source feeding the V

should be inversely

TOP

INH

power stage—upstream of MSP, if a power-interrupt MOSFET is used (Figure 46). When V

INL

and V

INH

are operated from different rails, this goal can be accomplished satisfactorily and the power V connection is to V

input source (see Figure 49: the

and not V

by placing R

, and usually not V

INL

between f

fSET

SET

INH

but see a counterexample in Figure47 and explana-

item number 5 of this list). A minor error term

tion in to the on-time is

-to-f

INL

SET

calculation of I cases (power, V

introduced by the internal 1.3MΩ

-connected resistor in such scenarios, so at all operating input voltage corner

ION

and control bias, V

INH

extremes)

INL

and the resulting switching frequency range of operation, given by Equation 6, should be considered.

When MSP is used, and when V

(5)

and V

INL

INH

are operated from different rails—here is the reason it is recommended to connect R drain of MSP rather than V is off, and V

would set the on-time at the instant switching

INH

is discharged. Connecting R

INH

from f

fSET

: prior to start-up, MSP

SET

to the

fSET

activity commenced to be much lower than intended. The on-time would not reach its final settling value until V V

INH

circuitry had turned on MSP enough for

ING

to become pulled up to VIN potential. It should become apparent that a mechanism may exist for dynamic interaction between how rapidly the output voltage ramps up (depending on TRACK/SS pin usage) versus how rapidly MSP might turn on. We know from item number

2 of this list that on-time should not be

arbitrarily large. In general, to avoid any undesirable

4641fe

For more information www.linear.com/LTM4641

appenDices

OUT

, C

: If Appreciable Cable Length Connects the LTM4641’s Output

To Attenuate Differential Mode Noise if Necessary

SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD

LTM4641

interactions—which might at worst result in excessive output voltage ripple or non-monotonic output voltage ramp-up, a sufficiently ramp-up time can eliminate the danger of V

slow output voltage

and

INH

on-time settling interactions influencing output voltage ripple and hardware evaluation on Figure47 shows an example where R between f supply. Because MSP limits the V the input voltage surge, the correct I

—but properly, this requires investigation

a case-by-case basis.

connects

fSET

SET

and V

—rather than the input source

INH

voltage during

INH

programming

current can only be made with a resistor interface to

, in that example.

INH

Appendix D. Remote Sensing in Harsh Environments

The rationale for using the symmetrical resistor network is to provide a consistent feedback structure that enables fully differential remote-sense of output voltages between 0.6V and 6V with the flexibility to filter differential and common mode noise in harsh environments. See Figure64. The use of not greater than 8.2kΩ nominal resistors for R (and R

) assures that the remote-sense signal is not

SET1B

SET1A

attenuated at frequencies of interest by the pole formed by the feedback resistors and parasitic capacitances.

Furthermore, using an R for 1.2V

and larger assures that the common mode

OUT

SET1A

(and R

) value of 8.2kΩ

SET1B

range of the remote-sense pins is within their valid range of –0.3V, minimum, to 3V, maximum—even if voltage drop between the module’s ground deviates from the POL’s ground by as much as ±0.6V.

The differential remote-sense feedback signal is routed from the load as a differential pair on PCB traces (or twisted pair, if wires are used) to R back components. It is ver R

and all other components forming the feedback

SET1B

y important to place R

SET1A/RSET1B

impedance-divider network as close to LTM4641 as is possible. Ground shielding of the differential remote-sense signal is strongly recommended, to prevent stray noise from contaminating the feedback information.

If good shielding of the feedback signals cannot be pro vided, it is proactive to leave space in one’s layout for a small filter capacitor, C

–

and V

, as close to the pins of the module as pos-

OSNS

sible—in anticipation of the possible

, placed directly between V

need to attenuate

differential mode noise.

Finally, if the POL the output power connection

is very far from the LTM4641, such as:

and GND) is made

OUT

feed-

SET1A

OSNS

CMA

CMB

to the Load (e.g., Through Several Feet of Wire), Leave Provision

for High Frequency Decoupling of Common Mode Ground Noise with

These Capacitors. These Are Not Needed in Purely PCB-Based Designs,

TO ERROR

AMPLIFIER

LTM4641

–

8.2k

TRUE DIFFERENTIAL REMOTE

SENSE AMPLIFIER

Where the LTM4641 Is Close to the Load

OUT

ICT TEST

8.2k

OSNS

SGND

ORB

GND

POINT

–

ICT TEST POINT

CMA

SET2

CMB

Place All Feedback

Components Local

To The LTM4641

If Effective Ground Shielding of the Feedback Signals Cannot Be Implemented, Leave Provision for a Small Capacitor (C

, C

: Feedforward Capacitors

FFA

FFB

Yeild Improved Transient Response When Filtering V Output Capacitors (C

FFA

SET1A

SET1B

FFB

Route Feedback Signals as

Twisted Pair if Using Wires).

Sandwich Between Ground

Planes to Form a Protective Shield,

Guarding Against Stray Noise

with Only MLCC

OUT

OUT(MLCC)

OUT(BULK)

a Differential Pair (or

)

OUT(MLCC)

)

LOAD

4641 F064

Figure 64. Feedback Remote Sense Connections and Techniques for Harshest Operating Environments

4641fe

For more information www.linear.com/LTM4641

LTM4641

BOVPGM

appenDices

through a board-to-board connector; an inductive length of cable (say, 50cm in length, or more); or, if the load is highly inductive—then it is proactive to leave provision in one’s layout for a pair of small filter capacitors, C

. C

and C V

OSNS

CMA

and C

CMB

to SGND and V

should be placed directly from

CMB

–

to SGND, respectively—as

OSNS

CMA

close to the pins of the module as possible. Configured in this manner, C

CMA

and C

can be used to attenuate

CMB

common mode noise in the remote-sense signal pin pair.

Appendix E. Inspiration For Pulse-Skipping Mode Operation

When M tional to I

is turned on—for a duration of time propor-

TOP

current—inductor current is ramped upwards,

ION

and energy is built up in the inductor’s B-field. Ultimately, a “packet” of energy is transferred from the input capaci

tors to the output capacitors. In forced continuous mode operation (FCB logic low), M

TOP

and M

a purely synchronous fashion, meaning: when M

is off—and vice versa. Observe that when M

BOT

are operated in

BOT

TOP

is on,

TOP

turned off, the B-field in the inductor cannot instantaneously vanish: the collapsing B-field flow through M

’s on-die Schottky diode—resulting in

BOT

unwanted freewheeling diode power loss; M on for lower power loss, instead. With M

forces inductor current to

is turned

BOT

on, inductor

BOT

current ramps downward as energy in its B-field wanes.

In steady-state forced continuous mode operation, the inductor ripple current appears as a triangle waveform whose average value equates to the load’s current. Forced continuous mode operation (forcing synchronous opera tion of M

TOP

and M

) provides a mechanism for consis-

BOT

tent output voltage ripple, regardless of the load current. However, in this mode

of operation, at light load currents (say, less than 2A out), observe that the inductor current is periodically negative—which means some packets of energy that are transferred from the input capacitors to the output are recirculated and transferred back to the input capacitors. This is a source of inefficiency that brings about the motivation for pulse-skipping mode operation, to turn off M

when the inductor current ramps down

BOT

to 0A. This concept is also described in the industry as “diode emulation”, because M

is made to mimic the

BOT

behavior of a Schottky rectifier. In pulse-skipping mode

operation

(FCB logic high), the inductor ripple current at light loads appears as an asymmetrical truncated triangle waveform; inductor current does not go below 0A.

Appendix F. Adjusting the Fast Output Overvoltage Comparator Threshold

The output overvoltage inception threshold (OV

PGM

voltage) can be adjusted or tightened from its default value. The following guidelines must be followed, however:

It is not recommended to change the OV

•

PGM

voltage dynamically because the fast OOV comparator has no glitch immunity beyond what is provided by OV internal 47pF capacitor, and routing of OV

can make

PGM

’s

it vulnerable to electrostatic noise.

• The 15.6μs time constant filter formed by OV ternal 47pF capacitor and default 499kΩ||1

MΩ resistor-

PGM

’s in-

divider network should be maintained for practical values of OV filtering of OV The OV 1V

REF

voltage: 0.6V < V

PGM

must not be applied indiscriminately.

PGM

voltage must come up very rapidly with the

PGM

at start-up, to prevent a race condition that would

< 0.9V. Capacitive

OVPGM

otherwise result in nuisance OOV detection and a faulty latchoff event—so any externally applied capacitance cannot be arbitrarily high. On the other hand, OV

PGM

must have some filtering from switching noise sources and should be sufficiently insulated from any possible dynamic activity on 1V

• External resistor(s) applied between OV

. (See Figure 9.)

REF

PGM

and 1V

REF

/ SGND should be relatively high impedance, to minimize loading on the 1V C

achieve a consistent time constant as OVPGM’s

OVPGM

output. Then, small values of

REF

resistance-divider network is altered.

Figure 65 shows the optional network one can apply to alter or tighten the OV

LTM4641

SGND

Figure 65. Optional OV

setpoint.

PGM

REF

TOVPGM

PGM

OVPGM

4641 F65

Network to Alter or Tighten V

PGM

OVPGM

4641fe

For more information www.linear.com/LTM4641

appenDices

1V • 1MΩ || R

( )

1V • 1MΩ

15.6µs

( )

1V • 1MΩ || R

( )

LTM4641

To nudge the OV inception threshold voltage at OV R

BOVPGM

The new OV

resistor, only—calculate:

BOVPGM

PGM

PGM(NEW)

When lowering the OV R

BOVPGM

only, it is not necessary to apply a C

setpoint downward, to a new OOV

PGM

—using an

(37)

1V – OV

PGM(NEW)

• 499kΩ

PGM(NEW)

–

1MΩ

threshold can then be double-checked by

499kΩ + 1MΩ || R

( )

PGM

BOVPGM

(38)

setpoint with application of

OVPGM

capacitor, because: for an extreme OVPGM(NEW) setting of 600mV, which is not practical since that is the voltage

during normal regulation, the time-constant of the

of V

network would have changed by less than 2μs

PGM

from its default value.

To nudge the OV OOV inception threshold voltage at OV an R

TOVPGM

resistor only—calculate:

trip threshold upward to set a new

PGM

PGM(NEW)

—using

100kΩ, low T.C.R. resistor. Using tolerances of ±0.1% and a T.C.R. of ±25ppm/°C can provide a considerable improvement in accuracy over the default divider network, over temperature. Next, decide the new value of V desired—OV OV

The new OV

PGM(NEW)

TOVPGM

1V – OVP

PGM(NEW)

< 0.9V. Then, compute R

GM(NEW )

PGM

—within a practical window of 0.6V <

according to:

–

499kΩ

PGM(NEW)

• 1MΩ ||R

( )

BOVPGM

TOVPGM

setting can be double-checked by:

BOVPGM

499kΩ ||R

( )

TOVPGM

+ 1MΩ ||R

BOVPGM

Then, use the next smallest standard value of C available, computed by:

OVPGM(NEW)

499kΩ ||1MΩ ||R

( )

15.6µs

TOVPGM

||R

BOVPGM

– 47pF

OVPGM

(42)

(43)

OVPGM

(44)

TOVPGM

The new OV

If R

TOVPGM

10kΩ, connect OV C

OVPGM

PGM

PGM(NEW)

1V – OV

PGM(NEW)

• 1MΩ

–

499kΩ

setting can then be double-checked by:

499kΩ ||R

( )

TOVPGM

+ 1MΩ

is computed in Equation 39 to be smaller than

PGM

to 1V

and do not apply any

REF

capacitor; this will yield an OOV setting of 167%

(39)

(40)

of nominal. Otherwise, use the next smallest standard value of C

OVPGM

The default V temperature. To tighten the OV choosing R

available, computed by:

OVPGM

499kΩ ||1MΩ ||R

( )

setpoint is 665mV ±2.26%, over

OVPGM

BOVPGM

to be a commonly available precision

TOVPGM

– 47pF

setpoint, begin by

PGM

(41)

For example, the OV

PGM(NEW)

setpoint can be kept at its nominal value of 666mV—but with better accuracy—by using ±0.1% precision resistors with ±25ppm/°C T.C.R. for R

BOVPGM

ing OV V

OVPGM

= 100k and R

to SGND with C

PGM

TOVPGM

OVPGM

OOV setpoint threshold becomes better than

= 49.9k, and bypass-

= 470pF. The resulting

±1.8%, over temperature. The vast majority of the remaining variation the 1V

in the threshold setting comes variation of

—a ±1.5% reference, over temperature.

REF

The extreme values of the OOV setpoint voltage, plus the OVP

term—which is the offset voltage of the fast

ERR

comparator (±12mV maximum, over temperature)—gives guidance on what the minimum and maximum voltage V

can be at which the CROWBAR output would swing logic high and invoke latchoff overvoltage protection.

One must take care to set the OV level and not too aggressively. If OV

voltage to a practical

PGM

is set too low,

PGM

the system will demonstrate nuisance output overvoltage latchoff behavior. The output voltage of any switching

For more information www.linear.com/LTM4641

4641fe

LTM4641

appenDices

regulator can witnesses transient excursions above its ideal DC voltage operating point routinely, owing to:

• Control IC bandgap reference accuracy

• Output voltage ripple and noise

• Load current step-down transient events—including

recovery from a short-circuit condition

• Steep line voltage step-up

• Start-up overshoot (little or no soft-starting of V

or rail-tracking a fast master rail

The Linear Technology LTpowerCAD design tool can help quantify some of these dynamic values; LTM4641’s total DC error (including bandgap reference variation) is better than ±1.5%, over temperature.

If OV and output voltage overshoot during high side MOSFET

has been decreased to its lowest practical level

PGM

OUT

short-circuit testing (shorting V hardware such as DC1543, for example) does not clamp the output voltage to one’s satisfaction, be aware that increasing output capacitance can reduce the maximum output voltage excursion. The reason follows: the larger the output capacitance, the longer it takes for the output voltage to be ramped up, even in the extreme case of deliberately short circuiting V on V shooting up to V

Multimodule parallel applications also have better output voltage overshoot during high side MOSFET short-circuit testing, owing to the fact that the sibling modules whose high side MOSFETs are not short circuited are able to help pull the output voltage down by turning on their low side power MOSFETs. Examples of paralleled LTM4641 power ing and protecting loads are shown in Figures 56 and 66.

is mainly what prevents the output voltage from

OUT

—until CROWBAR turns on MCB.

INH

to SW on evaluation

INH

to SW. The capacitance

INH

4641fe

For more information www.linear.com/LTM4641

LTM4641

package DescripTion

Table 10. LTM4641 Component BGA Pinout

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

A1 SGND B1 SGND C1 SGND D1 V A2 SGND B2 SGND C2 SGND D2 V

ORB

–

A3 SGND B3 SGND C3 SGND D3 OTBH E3 GND F3 GND A4 HYST B4 UVLO C4 SGND D4 TMR E4 GND F4 GND

A5 TEMP B5 OVLO C5 LATCH D5 RUN E5 GND F5 GND A6 IOVRETRY B6 GND C6 1V

REF

D6 GND E6 GND F6 GND A7 GND B7 GND C7 GND D7 GND E7 GND F7 GND A8 GND B8 GND C8 GND D8 GND E8 GND F8 GND

A9 GND B9 CROWBAR C9 V

A10 GND B10 OV

PGM

C10 V A11 GND B11 GND C11 V A12 GND B12 GND C12 V

OUT

D9 V D10 V D11 V D12 V

OUT

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

G1 GND H1 V G2 GND H2 V

OSNS

–

G3 GND H3 GND J3 V G4 GND H4 GND J4 DRV

J1 COMP K1 SGND L1 PGOOD M1 SGND J2 f

SET

INL

K2 FCB L2 TRACK/SS M2 SGND

K3 SGND L3 SGND M3 SGND

K4 INTV

G5 GND H5 GND J5 GND K5 GND L5 GND M5 GND G6 GND H6 GND J6 GND K6 GND L6 GND G7 GND H7 GND J7 GND K7 V G8 GND H8 GND J8 GND K8 V G9 GND H9 GND J9 GND K9 V

G10 GND H10 SW J10 GND K10 V

INH

G11 GND H11 GND J11 GND K11 GND L11 V G12 GND H12 GND J12 GND K12 GND L12 V

E1 GND F1 GND E2 GND F2 GND

E9 V E10 V E11 V E12 V

OUT

F9 GND F10 GND F11 GND F12 GND

L4 GND M4 GND

M6 GND L7 V L8 V L9 V

L10 V

INH

M7 V

M8 V

M9 V

M10 V M11 V M12 V

INH

ING

INGP

INH

package phoTo

For more information www.linear.com/LTM4641

4641fe

LTM4641

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

SEE NOTES

LJK

PIN 1

2 14 356712 891011

DETAIL A

aaa Z

ccc Z

MOLD

BGA Package

(Reference LTC DWG # 05-08-1914 Rev A)

144-Lead (15mm × 15mm × 5.01mm)

BGA 144 1112 REV A

PACKAGE BOTTOM VIEW

µModule

LTMXXXXXX

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR

MARKED FEATURE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS

BALL DESIGNATION PER JESD MS-028 AND JEP95

SEE NOTES

5. PRIMARY DATUM -Z- IS SEATING PLANE

LAYOUT CAREFULLY

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu

COMPONENT

PIN “A1”

PACKAGE IN TRAY LOADING ORIENTATION

BEVEL

TRAY PIN 1

NOTES

DETAIL B

PACKAGE SIDE VIEW

SUBSTRATE

CAP

DETAIL B

// bbb Z

X YZddd

Zeee

Øb (144 PLACES)

DETAIL A

PACKAGE TOP VIEW

aaa Z

0.0

CORNER

PIN “A1”

DIMENSIONS

6.9850

5.7150

4.4450

3.1750

1.9050

0.6350

0.0000

0.6350

1.9050

3.1750

4.4450

5.7150

6.9850

5.21

MAX

5.01

NOM

MIN

4.81

SYMBOL

5.7150

6.9850

0.630 ±0.025 Ø 144x

0.70

0.60

0.50

4.51

4.41

4.31

4.4450

0.90

0.75

0.60

3.1750

0.66

0.63

0.60

15.00

1.9050

15.00

0.6350

1.27

0.0000

13.97

0.6350

13.97

1.9050

0.46

0.41

0.36

4.05

4.00

3.95

3.1750

0.15

aaa

4.4450

0.10

bbb

0.20

0.30

0.15

TOTAL NUMBER OF BALLS: 144

ccc

eee

ddd

5.7150

6.9850

TOP VIEW

SUGGESTED PCB LAYOUT

4641fe

For more information www.linear.com/LTM4641

LTM4641

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

B 02/13 Updated Figure 1. 15

C 05/13 Updated video play buttons. 1, 49

D 10/13 Added patent number 8163643.

Changed Figure 9 title from "Figure 43 Circuit” to "Figure 45 Circuit at 28V

E 02/14 Added SnPb BGA package option 1, 3

(Revision history begins at Rev B)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTM4641

4641fe

LTM4641

4.5V

START-UP

DECOUPLING

TO SYSTEM µP

SGND ROUTES/PLANES SEPARATE FROM OTHER MODULES AND FROM GND ON MOTHERBOARD

Typical applicaTion

OPERATION UP TO 38V AND DOWN TO 4V

IN(MLCC)

10µF 50V ×4

INL

fSET1

750k

SET

UVLO HYST FCB

INTV DRV

IOVRETRY OVLO

RUN

22nF

INL

fSET2

750k

SET

UVLO HYST FCB

INTV DRV

IOVRETRY OVLO

RUN

U1 AND U2 SGND ( ) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP MODULE

(OPTIONAL)

PULL LATCH NORMALLY LOW FOR LATCHOFF RESPONSE TO OUTPUT OVERVOLTAGE AND OVERTEMPERATURE EVENTS. PULL LATCH HIGH TO RESTART 1V OUTPUT

ALTERNATIVELY, CONNECT LATCH TO INTV

TO SET 1V OUTPUT FOR TIMED

TMR2

AUTONOMOUS RESTART AFTER FAULT SHUTDOWN EVENTS

MCB: NXP PSMN5R0-30YL MSP: NXP PSMN7R0-60YS

RUN ENABLE

FAULT INDICATOR

LATCHOFF RESET

AND INSTALL C

IN(BULK)

100µF 50V ×2

TMR1

AND

Figure 66. 1V, 20A Fault-Protected Load Powered by Paralleled LTM4641—from Up to 38VIN. cf. Typical Performance Characteristics

MSP

INGVINGP

LTM4641

TMR1

N/U

INGVINGPVINH

LTM4641

TMR2

N/U

INH

CROWBAR

LATCH

OVPGM

PGOOD

GNDSGNDCOMPTMRTRACK/SS

CROWBAR

LATCH

OVPGM

PGOOD

GNDSGNDCOMPTMRTRACK/SS

ORB

OSNS

ORB

TEMP

OTBH

ORB

OSNS

ORB

TEMP

OTBH

OUT

FF1

100pF

MCB

DM1

22pF

–

REF

DM2

22pF

–

REF

4641 F66

SET1A

2.74k

SET1B

2.74k

FF2

100pF

LOAD

MLCC(OUT)

100µF

6.3V ×6

LOCAL HIGH FREQUENCY

V 1V 20A

OUT

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LTM4620 Dual 13A, Single 26A µModule

Regulator

LTM4613 EN55022B Certified 36V, 8A

Step-Down µModule Regulator

LTM4627 20V, 15A Step-Down µModule

Regulator

LTM8027 60V, 4A Step-Down µModule

Regulator

LTM4609 36V, 4A Buck-Boost µModule

Regulator

LT4356 High Voltage Surge Stopper 100V

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

Up to 100A with Four Devices; 4.5V ≤ V Higher V

OUT

≤ 36V; 3.3V ≤ V

5V ≤ V

15mm × 15mm × 4.32mm LGA

4.5V ≤ V

≤ 20V; 0.6V ≤ V

Remote Sensing, 15mm × 15mm × 4.32mm LGA or 15mm × 15mm × 4.92mm BGA

4.5V ≤ V

≤ 60V; 2.5V ≤ V

15mm × 15mm × 4.32mm LGA

4.5V ≤ V

≤ 36V; 0.8V ≤ V

and 10A in Buck Mode, 15mm × 15mm × 2.82mm LGA or 15mm × 15mm × 3.42mm BGA

Overvoltage and Overcurrent Protection, Latchoff and Auto-Retry Options

For more information www.linear.com/LTM4641

www.linear.com/LTM4641

≤ 16V; 0.6V ≤ V

; 15mm × 15mm × 4.41mm LGA

≤ 15V; Synchronizable, Parallelable,

OUT

≤ 5V; Synchronizable, Parallelable,

OUT

≤ 24V; Synchronizable,

OUT

≤ 34V; Synchronizable, Parallelable, Up to 4A in Boost Mode

OUT

≤ 2.5V. See LTM4620A for

OUT

4641fe

LT 0214 REV E • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2012

Linear LTM4641EY, LTM4641IY, LTM4641MPY Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual

FeaTures DescripTion

applicaTions

Typical applicaTion

Table oF conTenTs

pin conFiguraTionabsoluTe MaxiMuM raTings

orDer inForMaTion

elecTrical characTerisTics

Typical perForMance characTerisTics

pin FuncTions

siMpliFieD block DiagraM

Decoupling requireMenTs

operaTion

applicaTions inForMaTion—power supply FeaTures

applicaTions inForMaTion—inpuT proTecTion FeaTures

applicaTions inForMaTion—loaD proTecTion FeaTures

applicaTions inForMaTion—eMi perForMance

applicaTions inForMaTion—MulTiMoDule parallel operaTion

applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing

applicaTions inForMaTion—ouTpuT capaciTance Table

applicaTions inForMaTion—saFeTy anD layouT guiDance

Typical applicaTions

appenDices

package DescripTion

package phoTo

package DescripTion

revision hisTory

Typical applicaTion

relaTeD parTs