Linear LTM4641EY, LTM4641IY, LTM4641MPY Schematics

38V, 10A DC/DC µModule

MSP: (OPTIONAL) SERIES-PASS OVERVOLTAGE POWER INTERRUPT MOSFET, NXP PSMN014-60LS
MCB: (OPTIONAL) OUTPUT OVERVOLTAGE CROWBAR MOSFET, NXP PH2625L

4.5V START-UP

V

OUT

(200mV/DIV)

4µs/DIV

TESTED AT WORST-CASE CONDITION: NO LOAD

4641 TA01b

SHORT-CIRCUIT APPLIED

1.1V

OUT

PEAK

CROWBAR (5V/DIV)

4

321

V

INL

, V

INH

(25V/DIV)

Regulator with Advanced

Input and Load Protection

FeaTures DescripTion

n

Wide Operating Input Voltage Range: 4.5V to 38V

n

10A DC Typical, 12A Peak Output Current

n

Output Range: 0.6V to 6V

n

±1.5% Maximum Total Output DC Voltage Error

n

Differential Remote Sense Amplifier for POL Regulation

n

Internal Temperature, Analog Indicator Output

n

Overcurrent Foldback and Overtemperature

Protection

n

Current Mode Control/Fast Transient Response

n

Parallelable for Higher Output Current

n

Selectable Pulse-Skipping Operation

n

Soft-Start/Voltage Tracking/Pre-Bias Start-Up

n

15mm × 15mm × 5.01mm BGA Package

n

SnPb or RoHS Compliant Finish

Input Protection

n

UVLO, Overvoltage Shutdown and Latchoff Thresholds

n

N-Channel Overvoltage Power-Interrupt MOSFET Driver

n

Surge Stopper Capable with Few External Components

Load Protection

n

Robust, Resettable Latchoff Overvoltage Protection

n

N-Channel Overvoltage Crowbar Power MOSFET Driver

applicaTions

n

Ruggedized Electronics

n

Avionics and Industrial Equipment

The LT M®4641 is a switch mode step-down DC/DC

®

µModule

(micromodule) regulator with advanced input
and load protection features. Trip detection thresholds for
the following faults are customizable: input undervoltage,
overtemperature, input overvoltage and output overvolt
age. Select fault conditions can be set for latchoff or
hysteretic restart response—or disabled.
package are the switching controller and housekeeping ICs,
power MOSFETs, inductor, overvoltage drivers, biasing
circuitry and supporting components. Operating from input
voltages of 4V to 38V (4.5V start-up), the device supports
output voltages from 0.6V to 6V, set by an external resis
tor network remote sensing the point-of-load’s voltage.

The LTM4641’s high efficiency
10A continuous current with a few input and output ca
pacitors. The regulator’s constant on-time current mode
control architecture enables high step-down ratios and
fast response to transient line and load changes. The
LTM4641 is offered in a 15mm × 15mm × 5.01mm with
SnPb or RoHS compliant terminal finish.

L, LT, LTC, LTM , µModule, Burst Mode, Linear Technology and the Linear logo are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 5847554, 6100678, 6304066, 6580258, 6677210, 8163643.

Click to view associated TechClip Videos.

LTM4641

-

Included in the

-

design can deliver up to

-

Typical applicaTion

µModule Regulator with Input Disconnect and Fast Crowbar Output Overvoltage Protection

V

IN

4V TO 38V

+

100µF
50V

10nF

4

750k

*

**

MSP*

10µF
50V
×2

V

INGVINGPVINH

V

INL

f

SET

UVLO
INTV

CC

DRV

CC

RUN

TRACK/SS

IOVRETRY

SGND CONNECTS TO GND INTERNAL TO µMODULE REGULATOR

3

SW

M

TOP

CROWBAR

M

BOT

V

LTM4641

OVLO FCB LATCH SGND

OSNS

V

OSNS

OV

V

GND

OUT

PGM

For more information www.linear.com/LTM4641

1V Load Protected from M

Short-Circuit at 38V

1

2

MCB**

5.49k

+

5.49k

–

5.6M

LOAD

4641 TA01a

100µF
×3

V
1V
10A

OUT

TOP

IN

4641fe

1

LTM4641

Table oF conTenTs

Features ..................................................... 1

Applications ................................................ 1

Typical Application ........................................ 1

Description.................................................. 1

Absolute Maximum Ratings .............................. 3

Order Information .......................................... 3

Pin Configuration .......................................... 3

Electrical Characteristics ................................. 4

Typical Performance Characteristics ................... 8

Pin Functions .............................................. 10

Simplified Block Diagram ............................... 15

Decoupling Requirements ............................... 15

Operation................................................... 16

Introduction ............................................................ 16

Motivation ............................................................... 16

Power µModule Regulator Reliability ...................... 16

Overview ................................................................. 16

Applications Information—Power Supply Features . 17

Power (V
Switching Frequency (On Time) Selection and
Voltage Dropout Criteria (Achievable V

Step-Down Ratios).................................................. 18

Setting the Output Voltage; the Differential

Remote Sense Amplifier .........................................21

Input Capacitors .....................................................23

Output Capacitors and

Loop Stability/Loop Compensation ......................... 23

Pulse-Skipping Mode vs
Forced Continuous Mode
Soft-Start, Rail-Tracking and Start-Up Into
Pre-Bias
INTV

CC

1V

REF ......................................................................................... 28

TEMP, OTBH and Overtemperature Protection ........28

Input Monitoring Pins: UVLO, IOVRETRY, OVLO ....29

Applications Information—Input Protection

Features .................................................... 29

Start-Up/Shutdown and Run Enable;
Power-On Reset and Timeout Delay Time

) and Bias (V

INH

.................................................................. 24

and DRV

CC ............................................................... 27

) Input Pins ................. 17

INL

-to-V

IN

....................................... 24

OUT

...............31

Applications Information—Load Protection
Features

Applications Information—EMI Performance ........ 35

Applications Information—Multimodule
Parallel Operation
Applications Information—Thermal Considerations

and Output Current Derating ............................ 38

Applications Information—Output Capacitance
Table
Applications Information—Safety and Layout

Guidance ................................................... 46

Typical Applications ...................................... 48

Appendices ................................................ 56

Package Description ..................................... 63

Package Photo ............................................ 63

Package Description ..................................... 64

Revision History .......................................... 65

Typical Application ....................................... 66

Related Parts .............................................. 66

.................................................... 32

Overcurrent Foldback Protection ............................32

Power Good Indicator and Latching Output

Overvoltage Protection ........................................... 32

Power-Interrupt MOSFET (MSP), CROWBAR Pin
and Output CROWBAR MOSFET (MCB)

Fast Output Overvoltage Comparator Threshold ..... 34

The Switching Node: SW Pin .................................. 35

........................................ 36

Thermal Considerations and
Output Current Derating

........................................................ 45

Safety Considerations ............................................. 46

Layout Checklist/Example ......................................46

Appendix A. Functional Block Diagram and
Features Quick Reference Guide

Appendix B. Start-Up/Shutdown State Diagram .....57

Appendix C. Switching Frequency Considerations
and Usage of R
Appendix D. Remote Sensing in
Harsh Environments
Appendix E. Inspiration For Pulse-Skipping
Mode Operation
Appendix F. Adjusting the Fast Output Overvoltage

Comparator Threshold ............................................ 60

................................................. 58

fSET

............................................... 59

...................................................... 60

.........................................38

.............................56

.................. 33

2

4641fe

For more information www.linear.com/LTM4641

(Note 1)

144-LEAD (15mm × 15mm × 5.01mm)

TOP VIEW

REF

TRACK/SS

Terminal Voltages
V

INL

V

OUT

V

ING

INTV

, SW, f

INH

...................................................... –0.3V to 9.2V

............................................ –0.3V to V

, DRVCC, RUN, TRACK/SS, PGOOD,

CC

............................... –0.3V to 40V

SET

INH

+ 20V

, V

CROWBAR, HYST .................................... –0.3V to 6V

FCB, TMR................................-0.3V to INTV

+ 0.3V

CC

COMP ................................................... –0.3V to 2.7V

V
V

OSNS
OSNS

+
–

, V
, V

+

...................................... –0.6V to 9.7V

ORB
ORB

–

..........V

OSNS

+

– 2.7V to V

OSNS

+

+ 0.3V

OTBH, UVLO, IOVRETRY, OVLO,

....................................................–0.3V to 7. 5V

LATCH

TEMP, OV

....................................... –0.3V to 1.5V

PGM

Terminal Currents
INTV
INTV

(Continuous)....................................... –30mA

CC

(Continuous; CROWBAR

CC

Sourcing 15mA) ............................................... –15mA

CROWBAR (Continuous) ..................................–15mA

V
1V

(Continuous) ........................... –50mA to 15mA

INGP

(Continuous) ................................–1mA to 1mA

REF

Internal Operating Temperature Range (Note 2)

E- and I-Grades .................................. –40°C to 125°C

MP-Grade .......................................... –55°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Peak Package Body Temperature (SMT Reflow) ... 245°C

pin conFiguraTionabsoluTe MaxiMuM raTings

PGOOD

V

V

OSNS

SGND

COMP

f

SET

V

INL

OSNS

V

ORB

V

ORB

INTV

CC

M

L

FCB

K

J

H

+

–

G

F

E

+

D

–

C

B

A

1 2 3 4 5 6 7 8 109 11 12

DRV

CC

GND

GND

RUNTMROTBH

LATCH

SGND

GND

UVLO

HYST

= 125°C, θ

T

JMAX

θ

JB

θ VALUES DETERMINED PER JESD51-12

OVLO

BGA PACKAGE

= 11°C/W, θ

JCtop

= 3°C/W, θJA = 10.4°C/W

WEIGHT = 2.9 GRAMS

CROWBARTEMP IOVRETRY

JCbottom

LTM4641

V

V

INGP

INGSGND

GND

OV

PGM

= 2.5°C/W

V

INH

SW

V

OUT

1V

orDer inForMaTion

PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE

TYPE

LTM4641EY#PBF

DEVICE FINISH CODE

SAC305 (RoHS) LTM4641Y e1 BGA 4 –40°C to 125°C
LTM4641IY#PBF SAC305 (RoHS) LTM4641Y e1 BGA 4 –40°C to 125°C
LTM4641IY SnPb (63/37) LTM4641Y e0 BGA 4 –40°C to 125°C
LTM4641MPY#PBF SAC305 (RoHS) LTM4641Y e1 BGA 4 –55°C to 125°C
LTM4641MPY SnPb (63/37) LTM4641Y e0 BGA 4 –55°C to 125°C

Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping

container. Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Pb-free and Non-Pb-free Part Markings:

www.linear.com/leadfree

For more information www.linear.com/LTM4641

• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:

www.linear.com/umodule/pcbassembly

• LGA and BGA Package and Tray Drawings:

www.linear.com/packaging

MSL

RATING

TEMPERATURE RANGE
(Note 2)

4641fe

3

LTM4641

elecTrical characTerisTics

The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V
shown in Figure 45, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

V

OUT

V

OUT(DC)

Input Specifications

V

RUN(ON,OFF)

I

RUN(ON)

I

RUN(OFF)

V

INL(UVLO)

I

INRUSH(VINH)

I

Q(VINH)

I

Q(VINL)

I

S(VINH)

Output Specifications

I

OUT(DC)

∆V

OUT(LINE)/VOUT

∆V

OUT(LOAD)/VOUT

V

OUT(AC)

f

S

V

OUT(START)

t

START

t

RUN(ON-DELAY)

∆V

OUT(LS)

t

SETTLE(LS)

Input DC Voltage

Output Voltage Range Use R

SET1A

= R

SET1B

≤ 8.2kΩ. R

Recommended in Table 1

Output Voltage, Total Variation with
Line and Load, and Prior to UVLO

4.5V ≤ VIN ≤ 38V, 0A ≤ I
V

= 4V (Ramped Down from 4.5V), I

IN

RUN On/Off Threshold Run Rising, Turn On

Run Falling, Turn Off

RUN Pull-Up Current V

RUN Pull-Down Current, Switching

= 0V

RUN

V

= 3.3V

RUN

V

= 3.3V, UVLO = 0V (M

RUN

Inhibited

V

Undervoltage Lockout V

INL

INL

V

INL

Rising
Falling

Hysteresis

Input Inrush Current Through V

,

CSS = Open 230 mA

INH

at Start-Up

Power Stage Bias Current (I
No Load

VINH

) at

I

= 0A and:

OUT

FCB ≥ 0.84V (Pulse-Skipping Mode)
FCB ≤ 0.76V (Forced Continuous Mode)
Shutdown, RUN = 0

Control Bias Current (I

Power Stage Input Current (I
Full Load

) INTVCC Connected to DRVCC and:

VINL

VINH

) at

V

= 28V, I

IN

V

= 28V, I

IN

V

= 28V, Shutdown, RUN = 0

IN

I

= 10A and:

OUT

V

= 4.5V

IN

V

= 28V

IN

V

= 38V

IN

OUT
OUT

= 0A
= 10A

Output Continuous Current Range (Note 3)

Line Regulation Accuracy VIN from 4.5V to 38V, I

Load Regulation Accuracy I

Output Voltage Ripple Amplitude I

Output Voltage Ripple Frequency I

Turn-On Overshoot I

VIN-to-V

RUN-to-V

Start-Up Time RUN Electrically Open Circuit, Time Between

OUT

Turn-On Response

OUT

Time

from 0A to 10A (Note 3)

OUT

= 0A 16 mV

OUT

= 0A

OUT

I

= 10A

OUT

= 0A 10 mV

OUT

Application of V
OV

= 1.5V, C

PGM

to V

IN

= CSS = Open

TMR

VIN Established, (TMR-Set POR Time Expired)
Time Between RUN Releasing from GND to
PGOOD Going Logic High, C
OV

= 1.5V

PGM

Peak Deviation for Dynamic Load
Step

Settling Time for Dynamic Load Step I

I

from 0A to 5A at 5A/µs

OUT

I

from 5A to 0A at 5A/µs

OUT

from 0A to 5A at 5A/µs

OUT

I

from 5A to 0A at 5A/µs

OUT

fSET

≤ 10A

OUT

On) 1 nA

HYST

= 0A

OUT

Becoming Regulated,

OUT

= Open,

SS

INH

Values

= 0A

OUT

= V

= 28V, per the typical application

INL

l

4.5 38 V

l

0.6 6 V

l
l

l
l

l
l

l
l
l

1.773

1.773

–580
–220

0.8

3.5

300

1.800

1.800

1.25

1.15

–520
–165

4.2

3.8

400

8

29

0.2

14.5

15.5
5

4.65

790
590

l

0 10 A

l

l

0.02 0.15 %

0.04 0.15 %

290
330

3 ms

175 400 μs

40
40

20
20

1.827

1.827

2 V

–460
–110

4.5
4

µA
µA

mV

mA
mA
mA

mA
mA
mA

mA
mA

P-P

kHz
kHz

mV
mV

V
V

V

V
V

A

μs
µs

4

4641fe

For more information www.linear.com/LTM4641

LTM4641

elecTrical characTerisTics

The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V
shown in Figure 45, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

OUT(PK)

I

VINH(IOUT_SHORT)

Control Section

V

FB

I

TRACK/SS

V

FCB

I

FCB

t

ON(MIN)

t

OFF(MIN)

V

OSNS(DM)

V

OSNS(CM)

R

IN(VOSNS+)

, DRVCC, 1V

INTV

CC

V

INTVCC

∆V

INTVCC(LOAD)

V

INTVCC

V

INTVCC(LOWLINE)

DRV

CC(UVLO)

I

DRVCC

V

1VREF(DC)

PGOOD Output

V

PGOOD(TH)

V

PGOOD(HYST)

V

PGOOD(VOL)

t

PGOOD(DELAY)

Output Current Limit 5.1kΩ Pull-Up from PGOOD to 5V Source, I

Ramped Up Until V

Below PGOOD Lower

OUT

Threshold, PGOOD Pulls Logic Low

Power Stage Input Current During

V

Electrically Shorted to GND 45 mA

OUT

Output Short Circuit

Differential Feedback Voltage from
V

OSNS

+

to V

OSNS

–

TRACK/SS Pull-Up Current V

I

= 0A

OUT

TRACK/SS

= 0V –0.45 –1 μA

FCB Threshold 0.76 0.8 0.84 V

FCB Pin Current V

= 0.8V 0 ±1 μA

FCB

Minimum On-Time (Note 4) 43 75 ns

Minimum Off-Time (Note 4) 220 300 ns

Remote Sense Pin-Pair Differential
Mode Input Range

Remote Sense Pin-Pair Common
Mode Input Range

Input Resistance V

REF

Valid Differential V
(Use R

Valid V
Valid V
(Use R

OSNS

= R

SET1A

–

Common Mode Range

OSNS

+

Common Mode Range

OSNS

= R

SET1A

+

to GND 16318 16400 16482 Ω

OSNS

SET1B

SET1B

+

-to- V

≤ 8.2k)

≤ 8.2k)

OSNS

Internal VCC Voltage 6V ≤ VIN ≤ 38V, INTVCC Not Connected to DRVCC,

DRV

= 5.3V

CC

INTVCC Load Regulation RUN = 0V, INTVCC Not Connected to DRVCC,

DRV

= 5.3V and:

CC

I

Varied from 0mA to –20mA

INTVCC

I

Varied from 0mA to –30mA

INTVCC

INTVCC Voltage at Low Line VIN = 4.5V, R

R

Value Recommended in Table 1)

fSET

SET1A

= R

= 0Ω (~0.6V

SET1B

DRVCC Undervoltage Lockout DRVCC Rising

DRV

Falling

CC

DRVCC Current INTVCC Not Connected to DRVCC, DRVCC = 5.3V,

R

, R

1V

DC Voltage Regulation I

REF

Power Good Window, Logic State
Transition Thresholds

OUT
OUT

SET1A

SET1B

, R

fSET

, R

fSET

= R

and R

SET1B

= Open, 0A ≤ I

SET1A

1.8V

6.0V
(Use R

1VREF

I

1VREF

= 0mA
= ±1mA

Ramping Differential V
Up, PGOOD Goes Logic Low → High

Setting V

SET2

= 2MΩ, 0A ≤ I

≤ 8.2k)

+

– V

OSNS

OUT
OUT

OSNS

Up, PGOOD Goes Logic High → Low
Down, PGOOD Goes Logic Low → High
Down, PGOOD Goes Logic High → Low

Hysteresis Differential V

Logic-Low Output Voltage I

PGOOD

= 5mA

OSNS

+

PGOOD Logic-Low Blanking Time Delay Between Differential V

– V

–

Voltage Returning 8 16 24 mV

OSNS

+

OSNS

Voltage Exiting PGOOD Valid Window to PGOOD
Going Logic Low (Note 4)

INH

–

Range

to:

OUT

≤ 10A
≤ 10A

–

Voltage:

– V

OSNS

= V

= 28V, per the typical application

INL

OUT

l

591 600 609 mV

l

l

–0.3

l

l

5.1 5.3 5.4 V

24 A

0 2.7 V

–0.7

–1

OUT

,

4.2 4.3 V

l

3.9

3.2

4.05

3.35

l

l

11
20

l

0.985

l

0.980

l

–

533
645
621
525

1.000

1.000

556
660
644
540

75 400 mV

12 μs

3

±2
±3

4.2

3.5

18
27

1.015

1.020

579
675
667
555

mA
mA

mV
mV
mV
mV

V
V

%
%

V
V

V
V

For more information www.linear.com/LTM4641

4641fe

5

LTM4641

elecTrical characTerisTics

The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V
shown in Figure 45, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power-Interrupt MOSFET Drive

V

VING

Gate Drive Voltage for Power­Interrupt MOSFET, MSP

I

VING(UP)

I

VING_DOWN(CROWBAR
ACTIVE,CROWBAR
INACTIVE)

t

VING(OVP_DELAY)

I

VINGP(LEAK)

V

INGP(CLAMP)

V

V

V

Zener Diode Leakage Current V

Zener Diode Breakdown Voltage V

Fault Pins and Functions

V

OVPGM

Default Output Overvoltage Program
Setting

I

OVPGM(UP)

I

OVPGM(DOWN)

OVP

TH

OV

OV

Output Overvoltage Protection
Inception Threshold

OVP

ERR

Output Overvoltage Protection
Inception Error

t

CROWBAR(OVP_DELAY)

V

CROWBAR(OH)

CROWBAR Response Time OVPGM Driven from 650mV to 550mV

CROWBAR Output, Active High
Voltage

V

CROWBAR(OL)

CROWBAR Output, Passive Low
Voltage

V

CROWBAR(OVERSHOOT)

CROWBAR Peak Voltage Overshoot
at V

V

CROWBAR(TH)

V

TEMP

OT

TH(INCEPTION)

CROWBAR Latchoff Threshold CROWBAR Ramped Up Until HYST Goes Logic

TEMP Voltage RUN = 0V, TA = 25°C

TEMP Overtemperature Inception
Threshold

OT

TH(RECOVER)

TEMP Overtemperature Recovery
Threshold

UVOV

TH

UVLO/OVLO/IOVRETRY
Undervoltage/Overvoltage Inception
Thresholds

Pull-Up Current V

ING

Pull-Down Current V

ING

OVP Pull-Down Delay OV

ING

Pull-Up Current OV

PGM

Pull-Down Current OV

PGM

Start-Up and Shutdown

INL

VIN = 4.5V, 0A ≤ I
V

= 28V, 0A ≤ I

IN

V

= 38V, 0A ≤ I

IN

V

= 4V (Ramped Down from 4.5V), I

IN

V

Sourcing 1µA

ING

Tied to V

ING

V

= 4.5V, V

IN

V

= 28V, V

IN

Tied to V

ING

≤ 10A, V

OUT

≤ 10A, V

OUT

≤ 10A, V

OUT

, and:

INGP

Pulled to 6.5V

ING

Pulled to 30V

ING

, Pulled to 33V, and:

INGP

ING

Sourcing 1µA

ING

Sourcing 1µA

ING

RUN Pulled to 0V (CROWBAR Inactive)
OV

Pulled to 0V (CROWBAR Active)

PGM

Driven from 650mV to 550mV, V

PGM

Discharge Response Time

Driven to (V

INGP

-to-V

INGP

OV

INH

Electrically Open Circuit

PGM

= 0V

PGM

= 1V

PGM

Ramping Up Differential V

+ 10V) 1 nA

INH

Differential Voltage; I

+

-to-V

OSNS

Voltage Until CROWBAR Outputs Logic High

Difference Between OVPTH and V
(OVP

TH-VOVPGM

)

OVPGM

OVPGM Pulled to 0V and:
I

CROWBAR

I

CROWBAR

I

CROWBAR

V

INL

= –100μA, I
= –4mA, I

INTVCC

INTVCC

= –20mA

= –20mA

= 1μA

Ramped Up from/Down to 0V

Low

RUN = 0V, T

= 125°C

A

(See Figure 10 for Reference)

Ramping TEMP Downward Until HYST Outputs
Logic Low

Ramping TEMP Upward Until HYST Outputs
Logic High

Ramping UVLO, OVLO or IOVRETRY Positive
Until HYST Toggles Its State

= V

INH

Sourcing 1µA

OUT

ING

VINGP

OSNS

= 28V, per the typical application

INL

l

= 0A,

l
l
l

l
l

l
l

l

11.5

10.5

35
45

350
425

3

24

13.3

38.4

48.4

11.5

475
550

20
27

1.3 2.6 µs

= 5mA 15 V

l

650 666 680 mV

l

–2.07 –2 –1.91 μA

l

0.945 1 1.06 μA

–

l

647 666 683 mV

l

–12 0 12 mV

l

l

4.3

l

4.2

l

l

l

1.4 1.5 1.6 V

400 500 ns

4.65

4.55

260 500 mV

550 900 mV

950 980

585

l

428 438 448 mV

l

501 514 527 mV

l

488 500 512 mV

15.5
41

51.5

14.2

600
675

µA
µA

30
30

mA
mA

5

4.9

1010 mV

mV

V
V
V
V

V
V

6

4641fe

For more information www.linear.com/LTM4641

LTM4641

elecTrical characTerisTics

The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V
shown in Figure 45, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

UVOVD

I

UVOV

V

HOUSEKEEPING(UVLO)

V

HYST(SWITCHING ON)

V

HYST(SWITCHING OFF,

RUN)

V

HYST(SWITCHING OFF,

FAULT)

TMR

UOTO

V

LATCH(IH)

V

LATCH(IL)

I

LATCH

I

TMR(UP)

I

TMR(DOWN)

V

TMR(DIS)

OTBH

VIL

OTBH

VZ

I

OTBH(MAX)

UVLO/OVLO/IOVRETRY/ TEMP
Response Time

Input Current of UVLO, OVLO and
IOVRETRY

Housekeeping Circuitry UVLO Voltage on INTVCC, INTVCC Rising (Note 4)

HYST Voltage (M

HYST

Off, RUN

Logic High)

HYST Voltage (M

HYST

Off, RUN

Logic Low)

HYST Voltage, Switching Action
Inhibited (M

HYST

On)

Timeout and Power-On Reset Period C

LATCH Clear Threshold Input High
LATCH Clear Threshold Input Low
LATCH Input Current V

TMR Pull-Up Current V

TMR Pull-Down Current V

Timer Disable Voltage Referenced to INTV

OTBH Low Level Input Voltage

OTBH Pin Voltage When Left
Electrically Open Circuit

Maximum OTBH Current OTBH Electrically Shorted to SGND

±50mV Overdrive (All Pins)
±5mV Overdrive, UVLO/OVLO/IOVRETRY Pins
Only (Note 4)

UVLO = 0.55V or OVLO = 0.45V or
IOVRETRY = 0.45V

Hysteresis, INTV

Returning (Note 4)

CC

RUN Electrically Open Circuit
RUN = 1.8V

RUN = 0V

UVLO < UVOV
IOVRETRY > UVOV
or CROWBAR > V
DRV

< DRVCC

CC

or OVLO > UVOVTH or

TH

or TEMP < OT

TH

CROWBAR(TH)

UVLO(FALLING)

or

(See Figures 62, 63)

= 1nF, Time from Fault Clearing to HYST

TMR

Being Released by Internal Circuitry

= 7.5V

LATCH

= 0V

TMR

= 1.6V

TMR

CC

–10μA ≤ I

OTBH

≤ 10μA

= V

INH

TH(INCEPTION)

= 28V, per the typical application

INL

l

25

50

125

l

1.9
5

l

4.9

l

1.85

l

170 350 480 mV

l

5.1

2.1

100
500

±30 nA

2

25

2.1
50

5.25

2.35

30 65 mV

l

5 9 14 ms

l

1.2 V

l

l

l

–1.2 –2.1 –2.8 μA

l

1.2 2.1 2.8 μA

l

–180 –270 mV

l

l

0.6 0.9 1.2 V

l

0.8 V

±1 μA

0.4 V

30 μA

µs
µs

mV

V

V
V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

The LTM4641 SW absolute maximum rating of 40V is verified in ATE by
regulating V

while at 40VIN, in a controlled manner guaranteed to not

OUT

affect device reliability or lifetime. Static testing of SW leakage current at
40V

is performed at control IC wafer level only.

IN

Note 2: The LTM4641 is tested under pulsed load conditions such that
T

≈ TA. The LTM4641E is guaranteed to meet performance specifications

J

from 0°C to 125°C junction temperature. Specifications over the

For more information www.linear.com/LTM4641

–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM4641I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTM4641MP is tested and guaranteed over the
full –55°C to 125°C operating temperature range. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.

Note 3:

See output current derating curves for different V

, V

and TA.

IN

OUT

Note 4: 100% tested at wafer level only.

4641fe

7

LTM4641

4641 G05

Typical perForMance characTerisTics

(Figure 45 circuit with R

per Table 1 and R

fSET

SET1A

, R

SET1B

and R

per Table 2, unless otherwise noted)

SET2

Efficiency vs Load Current at 36V

95

90

85

80

75

EFFICIENCY (%)

70

65

60

0

1

2

OUTPUT CURRENT (A)

6.0V

OUT

5.0V

OUT

3.3V

OUT

2.5V

OUT

1.8V

OUT

3

6 8

5

4

Efficiency vs Load Current at 6V

95

90

85

80

75

EFFICIENCY (%)

70

65

60

0

2

1

OUTPUT CURRENT (A)

3.3V

OUT

2.5V

OUT

1.8V

OUT

1.5V

OUT

3

6 8

5

4

IN

1.5V

OUT

1.2V

OUT

1.0V

OUT

0.9V

OUT

9

4641 G01

10

7

Efficiency vs Load Current at 24V

95

90

85

80

75

EFFICIENCY (%)

70

65

60

0

1

2

6.0V

OUT

5.0V

OUT

3.3V

OUT

2.5V

OUT

1.8V

OUT

3

OUTPUT CURRENT (A)

6 8

5

4

IN

1.5V

OUT

1.2V

OUT

1.0V

OUT

0.9V

OUT

9

4641 G02

10

7

Efficiency vs Load Current at 12V

95

90

85

80

75

EFFICIENCY (%)

70

65

60

0

1

2

6.0V

OUT

5.0V

OUT

3.3V

OUT

2.5V

OUT

1.8V

OUT

3

OUTPUT CURRENT (A)

6 8

5

4

IN

1.5V

OUT

1.2V

OUT

1.0V

OUT

0.9V

OUT

9

4641 G03

10

7

Pulse-Skipping vs Forced
Continuous Mode Efficiency,

IN

1.2V

OUT

1.0V

OUT

0.9V

OUT

9

4641 G04

10

7

28VIN to 3.3V

90

80

70

60

(PULSE-SKIPPING)

50

40

EFFICIENCY (%)

30

20

10

0

0.001

OUT

FCB = INTV

CC

0.01
OUTPUT CURRENT (A)

0.1

FCB = SGND
FORCED
CONTINUOUS

1

50mV/DIV

AC-COUPLED

10

1V Transient Response, 38V

V

OUT

I

OUT

2.5A/DIV

0A TO 5A LOAD STEPS AT 5A/µs
FRONT PAGE CIRCUIT WITH

= OPEN CIRCUIT

OV

PGM

20µs/DIV

IN

4641 G06

V

OUT

50mV/DIV

AC-COUPLED

I

OUT

2.5A/DIV

8

1V Transient Response, 4.5V

0A TO 5A LOAD STEPS AT 5A/µs
FRONT PAGE CIRCUIT WITH

= OPEN CIRCUIT

OV

PGM

20µs/DIV

IN

4641 G07

3.3V Transient Response,
28VIN to 3.3V

V

OUT

50mV/DIV

AC-COUPLED

I

OUT

2.5A/DIV

0A TO 5A LOAD STEPS AT 5A/µs
FIGURE 46 CIRCUIT

For more information www.linear.com/LTM4641

OUT

20µs/DIV

4641 G08

V

OUT

1V/DIV

200mA/DIV

RUN

5V/DIV

Output Start-Up, No Load

I

IN

VIN = 24V
C

IN(MLCC)

800µs/DIV

= 2 × 10µF X7R

4641 G09

4641fe

Typical perForMance characTerisTics

4641 G18

(Figure 45 circuit with R

per Table 1 and R

fSET

SET1A

, R

SET1B

and R

per Table 2, unless otherwise noted)

SET2

LTM4641

Output Start-Up, 10A Load

V

OUT

1V/DIV

I

IN

1A/DIV

RUN

5V/DIV

VIN = 24V
C

IN(MLCC)

800µs/DIV

= 2 × 10µF X7R

Output Short-Circuit,
10A Initial Load

V

OUT

1V/DIV

I

IN

1A/DIV

VIN = 24V
C

IN(MLCC)

20µs/DIV

= 2 × 10µF X7R

4641 G10

4641 G13

V

OUT

1V/DIV

I

LOAD

1mA/DIV

200mA/DIV

RUN

5V/DIV

V

20V/DIV

V

INH

2V/DIV

V

OUT

200mV/DIV

CROWBAR

5V/DIV

Output Start-Up,
Pre-Bias Condition

I

IN

VIN = 24V
C

IN(MLCC)

Start-Up with V
Node, 1V

IN

FRONT PAGE CIRCUIT WITH V
CIRCUITED TO SW PRIOR TO POWER-UP.
APPLYING UP TO 38V

800µs/DIV

= 2 × 10µF X7R

INH

OUT(NOM)

400µs/DIV

. NO LOAD

IN

Shorted to SW

INH

SHORT

4641 G11

4641 G14

V

OUT

1V/DIV

1A/DIV

V

10V/DIV

V

INH

5V/DIV

V

OUT

1V/DIV

CROWBAR

5V/DIV

Output Short-Circuit,
No Initial Load

I

IN

VIN = 24V
C

IN(MLCC)

Start-Up with V
Node, 3.3V

IN

FIGURE 46 CIRCUIT WITH V
CIRCUITED TO SW PRIOR TO POWER-UP.
APPLYING UP TO 38V

20µs/DIV

= 2 × 10µF X7R

INH

OUT(NOM)

800µs/DIV

IN

Shorted to SW

SHORT

INH

. NO LOAD

4641 G12

4641 G15

V

10V/DIV

V

INH

10V/DIV

V

OUT

1V/DIV

CROWBAR

5V/DIV

Autonomous Restart with V
Shorted to SW Node, 3.3V

IN

FIGURE 46 CIRCUIT, SHORT CIRCUITING V
TO SW IN SITU, OPERATING AT 38VIN AND
NO LOAD. LATCH CONNECTED TO INTV

= 47nF

C

TMR

100ms/DIV

INH

OUT(NOM)

4641 G16

INH

AND

CC

Paralleled Modules, Current­Sharing Performance. cf.
Figure 66 Circuit. 28V

12

10

8

6

4

2

MODULE OUTPUT CURRENT (A)

0

–2

0

For more information www.linear.com/LTM4641

U1 I

4 8 12 20
TOTAL OUTPUT CURRENT (A)

OUT

U2 I

IN

OUT

16

BANDGAP VOLTAGE (V)

FB

V

4641 G17

Control IC Bandgap and 1V
Voltages vs Temperature. 28V

0.606

0.604

0.602

0.600

0.598

0.596

0.594
–50 0

–75

JUNCTION TEMPERATURE (°C)

–25

V

FB

V

1VREF(DC)

50 150

25

REF

IN

1.006

1.004

1V

REF

1.002
VOLTAGE (V)

1.000

0.998

0.996

125

0.994

4641fe

100

75

9

LTM4641

pin FuncTions

SGND (A1-A3; B1-B3; C1-C4; K1, K3; L3; M1-M3): Signal
Ground Pins. This is the return ground path for all analog
control and low power circuitry. SGND is tied to GND in

­ternal to the µModule regulator in a manner that promotes
the best internal signal integrity—therefore, SGND should
not be connected to GND in the user’s PCB layout. See
the Layout Checklist/Example section of the Applications
Information section for more information pertaining to
SGND and layout. All SGND pins are electrically connected
to each other, internally.

HYST (A4): Input Undervoltage Hysteresis Programming
Pin. Normally used as an output, but can be used as an
input. If the LTM4641’s inherent, default undervoltage
lockout (UVLO) settings are satisfactory, 4.5V

MAX)

and 4V

IN(FALLING, MAX)

, HYST can be left electrically

IN(RISING,

open circuit. See the Applications Information section to
customize the LTM4641’s UVLO thresholds.

HYST is a logic-high output with moderate pull-up strength
that commands LTM4641’s internal control IC to regulate
the module’s output voltage when conditions on the RUN,
UVLO, OVLO, IOVRETRY, TEMP, CROWBAR, INTV
and DRV

pins permit it (any recent latchoff events

CC

CC

notwithstanding, otherwise OTBH and LATCH can also
play a role). When a fault condition is detected, internal
circuitry (M

; see Figure 1) drives HYST logic low and

HYST

the LTM4641’s output is turned off. HYST can be used as
a fault-indicator. See the Applications Information section.

may be deasserted when TEMP subsequently exceeds
514mV (nominally corresponding to a cool-off hysteresis
of ~10°C), depending on the OTBH setting. (See

OTBH and

the Applications Information section.)

To disable the µModule regulator
shutdown feature, connect the TEMP and 1V

’s overtemperature

pins. The

REF

thermal shutdown inception threshold can also be modi­fied, see the Applications Information section.

IOVRETR

Y (A6): Nonlatching Input Over

voltage Threshold
Programming Pin. The LTM4641 pulls HYST low to inhibit
regulation of its output voltage when IOVRETRY exceeds

0.5V. The LTM4641 can resume switching action when
IOVRETRY is below 0.5V. If no nonlatching input over
voltage shutdown behavior is desired, connect this pin to
SGND. Do not leave this pin open circuit.

GND (A7-A12; B6-B8, B11-B12; C7-C8; D6-D8; E1-E8;
F1-F12; G1-G12; H3-H9, H11-H12; J5-J12; K5-K6, K11­K12; L4-L6; M4-M6): Power ground pins for input and

output returns. See the Layout Checklist/Example section
of the Applications Information section. All GND pins are
electrically connected to each other, internally.

UVLO (B4): Input Undervoltage Lockout Programming
Pin. The LTM4641 pulls HYST low to inhibit regulation
of its output voltage whenever UVLO is less than 0.5V.
The LTM4641 can resume switching action when UVLO
exceeds 0.5V. Do not leave this pin open circuit.

-

HYST is pulled low when the RUN pin is pulled low, via
an internal Schottky diode. HYST can be driven low by
external open-collector/open-drain circuitry directly—as
an alternate to the RUN pin interface. However, external
circuitry should never drive HYST high, since doing so
(indiscriminately) could cause thermal overstress to
M

HYST

, when M

HYST

is on.

TEMP (A5): Power Stage Temperature Indicator and
Overtemperature Detection Pin. When left electrically open
circuit, TEMP’s voltage varies according to an internal NTC
(negative temperature coefficient) thermistor, residing in
close proximity to LTM4641’s power stage. When TEMP
falls below 438mV (corresponding to a thermistor and
power stage temperature of ~145°C), the LTM4641 pulls
HYST low to inhibit regulation of its output voltage. HYST

10

For more information www.linear.com/LTM4641

the LTM4641’s default UVLO settings are

If

4.5V

IN(RISING, MAX)

and 4V

IN(FALLING, MAX)

pin should be electrically connected to 1V

, then the UVLO

REF

used,

or INTVCC.
Otherwise, see HYST and the Applications Information
section for using a resistor-divider network to implement
personalized UVLO rising and UVLO falling settings.

OVLO (B5): Input Overvoltage Latchoff Programming Pin.
LTM4641 pulls HYST low to inhibit regulation of its output
voltage when OVLO exceeds 0.5V. If OVLO subsequently
falls below 0.5V, the module’s output remains latched
off; the LTM4641 cannot resume regulation of the output
voltage until either the LATCH pin is toggled high or V

INL

is power cycled. If input overvoltage latchoff behavior is
not desired, electrically short this pin to SGND. Do not
leave this pin open circuit.

4641fe

pin FuncTions

LTM4641

CROWBAR (B9): Crowbar Output Pin. Normally logic low,
with moderate pull-down strength to SGND.

When an output overvoltage (OOV) condition is detected,
the LTM4641’s fast OOV comparator pulls CROWBAR logic
high through a series-connected internal diode. If utilizing
LTM4641’s OOV feature, CROWBAR should connect to
the gate of a logic-level N-channel MOSFET configured to
crowbar the module’s output voltage (MCB, in Figure 1).

Furthermore, the LTM4641 latches off its output when
CROWBAR nominally exceeds 1.5V and latches HYST
logic low (see HYST).

If not using the OOV protection features of the LTM4641,
leave CROWBAR electrically open circuit.

OV

(B10): Output Overvoltage Threshold Programming

PGM

Pin. The voltage on this pin sets the trip threshold for the
inverting input pin of LTM4641’s fast OOV comparator.
When left electrically open circuit, resistors internal to the
LTM4641 nominally bias OV
above the nominal V

feedback voltage (600mV) that the

FB

to 666mV (OV

PGM

)—11%

PTH

control loop strives to present to the noninverting input pin
of LTM4641’s fast OOV comparator. The aforementioned
voltages correspond proportionally to the module’s OOV
inception threshold and V
tion, respectively. Altering the OV

’s nominal voltage of regula-

OUT

voltage provides a

PGM

means to adjust the OOV threshold; its DC-bias setpoint
can be tightened with simple connections to external
components (see the Applications Information section).
Trace route lengths and widths to this sensitive analog
node should be minimized. Minimize stray capacitance to
this node unless altering the OOV threshold as described
in the Applications Information section and Appendix F.

LATCH (C5): Latchoff Reset Pin. When a latchoff fault oc
curs, the LTM4641 turns off its output and latches M

-

HYST

on to indicate a fault condition has occurred (see HYST). To
configure the LTM4641 for latched off response to latchoff
faults, connect LATCH to SGND. As long as LATCH is logic

CC

-

;

low, the LTM4641 will not unlatch. Regulation can be re
sumed by

cycling V

or by toggling LATCH from logic low

INL

to high. It is also permissible to connect LATCH to INTV
this configures the LTM4641 for autonomous restart with
a timeout delay (programmed by C

—see TMR).

TMR

If no latchoff faults are present when LATCH transitions
from logic low to logic high, the LTM4641 immediately un­latches. If any latchoff fault is present when LATCH is
high, a timeout delay timing requirement is imposed: the
LTM4641 will not unlatch

until all latchoff fault-monitoring

pins meet operationally valid states for the full duration
of the timeout delay. If LATCH becomes logic low before
that timeout delay has expired, the LTM4641 remains
latched off and the timeout delay is reset. Unlatching the
LTM4641 can be reattempted by pulling LATCH logic high
at a later time.

The following are latchoff fault conditions:

• CROWBAR activates (see CROWBAR)

• Input latchoff overvoltage fault (see OVLO)

• Latchoff overtemperature fault (when OTBH is logic

low; see TEMP and OTBH)
LATCH is a high impedance input and must not be left elec-

trically open

circuit. LATCH can

be driven by a μController

in intelligent systems: a reasonable implementation for
unlatching the LTM4641 is to pull LATCH logic high for
the maximum anticipated timeout delay time—after which,
HYST can be observed to indicate whether the LTM4641
has become unlatched.

(C6): Buffered 1V Reference Output Pin. Minimize

1V

REF

capacitance on this pin, to assure the OV

and TEMP

PGM

pins are operational in a timely manner at power-up. 1V
should never be externally loaded except as explained in
the Applications Information section.

(C9-C12; D9-D12; E9-E12): Power Output Pins of

V

OUT

the LTM4641 DC/DC Converter Power Stage. All V
pins are electrically connected to each other, internally.
Apply output load between these pins and the GND pins.
It is recommended to place output decoupling capacitance
directly between these pins and the GND pins. Review
Table 9. See the Layout Checklist/Example section of the
Applications Information section.

+

(D1): V

V

ORB

+

V

internal to the µModule regulator. It is recom-

OSNS

mended to route this pin (differentially with V

+

Readback Pin. This pin connects to

OSNS

ORB

–

) to a test

point so as to allow the user a way to confirm the integrity

logic

REF

OUT

For more information www.linear.com/LTM4641

4641fe

11

LTM4641

pin FuncTions

of the remote-sense connections prior to powering up the

+

LTM4641. V
feedback connection to V

–

(D2): V

V

ORB

–

V

internal to the µModule regulator. It is recom-

OSNS

mended to route this pin (differentially with V

can also be connected as a redundant

ORB

OSNS

–

Readback Pin. This pin connects to

+

on the user’s motherboard.

OSNS

ORB

+

) to a test
point so as to allow the user a way to confirm the integrity
of the remote-sense connections prior to powering up the

–

LTM4641. V
feedback connection to V

can also be connected as a redundant

ORB

–

on the user’s motherboard.

OSNS

OTBH (D3): Overtemperature Behavior Programming
Pin. When an overtemperature condition is detected (see
TEMP), HYST pulls logic low to inhibit switching. If OTBH
is connected to SGND, the LTM4641 latches HYST low. If
OTBH is left floating, output voltage regulation can resume
when the overtemperature event clears.

TMR (D4): Timeout Delay Timer and Power-On Reset (POR)
Programming Pin. Connect a capacitor (C

) from TMR

TMR

to SGND to program the POR and timeout delay time of the
LTM4641; 9ms delay time per nanofarad of capacitance.
The minimum delay time

is ~90μs, when TMR is left
electrically open circuit. Even though they use the same
capacitor, the power-on reset and timeout delay timers
operate independently of each other. Any nonlatching fault
or latching fault will reset the respective timer to the full
delay time without impacting the other timer.

The timeout delay time programmed by a C
can be negated by pulling TMR to INTV

CC

TMR

.

capacitor

RUN (D5): Run (On/Off) Control Pin. A RUN pin voltage
below 0.8V will turn off the module. A voltage above 2V
will command the module to turn on, if HYST is not as
serted low by M
(10k) pull-up resistor from HYST to INTV

. The LTM4641 contains a moderate

HYST

, and a pull-up

CC

-

Schottky diode from RUN to HYST (see Figure 1). When
RUN is pulled logic low, HYST is pulled logic low via the
internal Schottky diode. RUN is compatible with direct­drive (totem-pole output drive) as well as open-collector/
open-drain interfaces.

+

V

(H1): Positive Input to the Remote Sense Differ-

OSNS

ential Amplifier. This pin connects to the positive side of
the output voltage remote sense point (V
a resistor (R

). When regulating the output voltage,

SET1A

potential) via

OUT

the LTM4641 control loop drives the differential voltage
between V
SS and 0.6V. V

OSNS

+

OSNS

the module (see V
V

OSNS

+

to V

OSNS

–

and V

+

is connected to V

+

ORB

for some output voltage settings. (See

–

to the lesser of TRACK/

OSNS

+

internal to

ORB

). A resistor may be needed from

the Applications Information section: Setting the Output
Voltage.) Minimize stray capacitance to this pin to protect
the integrity of the output voltage feedback signal.

–

V

(H2): Negative Input to the Remote Sense Dif-

OSNS

ferential Amplifier. This pin connects to the negative side
of the output voltage remote sense point (GND potential)
via a resistor (R

). When switching action is on,

SET1B

the LTM4641 control loop drives the differential voltage
between V
SS and 0.6V. V

OSNS

+

OSNS

the module (see V
V

OSNS

+

to V

OSNS

–

and V

–

is connected to V

–

ORB

for some output voltage settings. (See

–

to the lesser of TRACK/

OSNS

–

internal to

ORB

). A resistor may be needed from

the Applications Information section.) Minimize stray ca­pacitance to this pin to protect the integrity of the output
voltage feedback signal.

SW (H10): Switching Node of the Power Stage. Mainly
used for testing purposes, however, one may optionally
connect a snubber (series-configured capacitor C
resistor R

) from SW to GND to reduce radiated EMI—in

SW

SW

and

exchange for a minor compromise to power conversion
efficiency. (See the Applications Information section.)

COMP (J1): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold of
LTM4641’s valley current mode control loop—and corre­spondingly, the commanded trough of

the power inductor
current—increases as this control voltage increases. It can
be useful to make COMP available for observation on a
PCB via or test pad with an oscilloscope probe. However,
stray capacitance and trace lengths to this sensitive analog
node should be minimized.

(J2): Switching Frequency Setting and Adjustment Pin.

f

SET

This pin interfaces directly to the ION pin of LTM4641’s
internal control IC. Current flow into the ION pin programs
the on-time of the control loop’s one-shot timer and power
control MOSFET, M

. Minimize stray capacitance and

TOP

any tracelengths to this pin.

For applications requiring regulated output voltages of 3V
or less at any time including during voltage rail tracking,

4641fe

12

For more information www.linear.com/LTM4641

pin FuncTions

LTM4641

an on-time adjustment with a resistor to f
Otherwise, f

can be left open circuit. See the Applica-

SET

is required.

SET

tions Information section for details.

(J3): Input Voltage Pin, Low Current for Power

V

INL

Control and Logic Bias. Feeds LTM4641’s internal 5.3V
LDO (see INTV

). Apply input voltage bias between this

CC

pin and GND. Decouple to GND with a capacitor (0.1µF
to 1µF). This pin powers the heart of LTM4641’s DC/DC
controller and internal housekeeping ICs. V
rent is within ~5mA of the sum of INTV

CC

bias cur-

INL

and CROWBAR

loading currents.

If using the advanced output overvoltage (OOV) protection
features of the LTM4641, connect V

to either the drain of

INL

the external power-interrupt power MOSFET, identified on
the front page schematic as MSP, or a separate input bias
supply. If not making use of the advanced OOV protection
features, V

INL

and V

can connect directly to the same

INH

input power source.

LDO losses can be eliminated by connecting V
and DRV

if a low power auxiliary ~5V rail is available to

CC

, INTVCC,

INL

power the resulting node. (See the Applications Informa­tion section, Figure 47 and Figure 49.)

RVCC (J4): Power MOSFET Driver Input Power Pin. DRVCC

D

is normally connected to INTV
diode drops (2 • V

or ~1.2V at 25°C) of INTVCC. DRVCC

BE

. It must be kept within two

CC

powers the internal MOSFET driver that interfaces to the
switching MOSFETs (M

TOP

and M

power stage. It is pinned out separately from INTV

) within LTM4641’s

BOT

CC

to
allow gate-driver current to be observed, and to allow an
auxiliary ~5V to 6V bias supply to optionally provide the
MOSFET driver bias current. The INTV

/DRVCC pin pair

CC

can be biased from up to 6V (absolute maximum) from
an external supply with 50mA peak sourcing capability, to
reduce the LTM4641’s INTV
tions Information section and Figure
connected directly to INTV

LDO losses (see Applica-

CC

51). When DRVCC is

, no bypass capacitance is

CC

needed except in rare applications where very fast output
voltage ramp up is required (e.g., no soft-start capacitor
on TRACK/SS, or rail-tracking rails with sub-60µs turn-on
rise-time). Otherwise, ~2.2µF to 4.7μF X7R MLCC local
bypassing to GND is recommended. Higher impedance
sources may require higher bypass capacitance, to mitigate
DRV

CC

sag during V

start-up.

OUT

An undervoltage lockout detector monitors DRV
pulled low and switching action is inhibited if DRV

. HYST is

CC

is less

CC

than 4.2V rising (maximum) and 3.5V falling (maximum).

FCB (K2): Forced Continuous/Pulse-Skipping Mode Opera

­tion Programming Pin. Connect this pin to SGND to force
continuous mode operation of the synchronous power
MOSFETs (M

TOP

and M

Connect this pin to INTV

) at all output load conditions.

BOT

to enable pulse-skipping mode

CC

operation: the freewheeling power switching MOSFET

) is turned off of to prevent reverse flow of output

(M

BOT

current (I

) at light loads. See Appendix E for more

OUT

details. This is a high impedance input and must not be
left electrically open circuit.

INTV

of V
housekeeping circuitry. INTV
DRV

(K4): Internal 5.3V LDO Output. LDO operates off

CC

. The INTVCC rail biases low power control and

INL

is usually connected to

CC

to power the MOSFET drivers interfacing to the

CC

switching power MOSFETs. No decoupling capacitance is
needed on this pin unless it is being used to bias external
circuitry (not common); do not apply more than 4.7µF
(±20% tolerance) of external decoupling capacitance. The
INTV

/DRVCC pin pair can be overdriven by an external

CC

supply, from up to 6V (absolute maximum) with 50mA peak
sourcing capability, to eliminate power losses otherwise
incurred by the LTM4641’s V

-to-INTVCC linear regulator

INL

(see the Applications Information section and Figure 51).

(K7-10; L7-12; M7-8, 11-12): Input Voltage Pin, High

V

INH

Current to the Power Converter Stage of the LTM4641.
All V
ternally. Devote a large copper
of the V

pins are electrically connected to each other in-

INH

plane to connect as many

pins to each other as is feasible. This will help

INH

form a low impedance electrical connection between the
input source and the LTM4641’s power stage. It will also
provide a thermal path for removing heat from the BGA
package and minimize junction temperature rise of the
LTM4641 for a given application.

If utilizing the advanced output overvoltage (OOV) protec
tion features of the LTM4641, connect V

to the source

INH

-

pin(s) of the external power-interrupt MOSFET, identified on
the front page schematic as MSP, with a short wide trace,
or preferably a small copper plane capable of adequately

4641fe

For more information www.linear.com/LTM4641

13

LTM4641

pin FuncTions

handling the input current to LTM4641’s power stage.
Do not decouple the V

pins with any bypass capacitance

INH

in this case. Instead, place all decoupling capacitance
directly between the drain of MSP to GND.

If not utilizing the advanced OOV protection features of
the LTM4641, do decouple the V

pins to GND with

INH

local ceramic and bulk decoupling capacitance (see the
Applications Information section).

PGOOD (L1): Output Voltage Power Good Indicator. This
is an open-drain logic output pin that is pulled to ground
when the output voltage (and accordingly, the divided-down
representation of the output voltage, V

, as presented to

FB

the control loop) is outside ±10% of the nominal target
for regulation.

TRACK/SS (L2): Output Voltage Tracking and Soft-Start
Programming Pin. This pin has a 1.0μA pull-up current
source, typical. A capacitor can be placed from this pin to

SGND to obtain an output voltage soft-start ramp-up rate
whose turn-on time is 0.6ms per nanofarad of capacitance.
Alternatively, when a voltage is applied to TRACK/SS
through a resistor-divider network from another rail, the
LTM4641 output is able to track the external voltage to
satisfy
requirements.

V

coincident and ratiometric rail-voltage sequencing

See the Applications Information section.

(M9): Gate Drive Output Pin. If utilizing the advanced

ING

output overvoltage (OOV) protection features of the
LTM4641, connect V

ING

to V

external power-interrupt N-channel MOSFET feeding V

and to the gate of the

INGP

INH

identified on the front page schematic as MSP; otherwise,
leave this pin electrically open circuit.

(M10): Gate Drive Protection Pin. If utilizing the ad-

V

INGP

vanced OOV protection features of the LTM4641, connect

to V

V

INGP

N-channel MOSFET feeding V

and to the gate of the external power-interrupt

ING

, MSP; otherwise, leave

INH

this pin electrically open circuit.

,

14

4641fe

For more information www.linear.com/LTM4641

siMpliFieD block DiagraM

LTM4641

R

BOVPGM

V

IN

R

HYST

R

TUV

R

BUV

V

IN

R

TOV

R

MOV

R

BOV

C

TMR

C

SS

R

TOVPGM

C

OVPGM

HYST

UVLO

IOVRETRY

OVLO

1V

TEMP

OTBH
TMR

LATCH

FCB
COMP

DRV

CC

INTV

CC

PGOOD

TRACK/SS
1V

REF

OV

PGM

RUN

DASHED BOXES INDICATE OPTIONAL COMPONENTS
*R

REQUIRED FOR CERTAIN VIN/V

fSET

SEE APPLICATIONS INFORMATION SECTION
SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND
ROUTES/PLANES SEPARATE FROM GND, ON MOTHERBOARD

REF

3.48k

NTC

PROTECTION

COMPARATORS

FAULT LATCHES

OSC

REF

499k

1M

AND

INTERNAL

4µF

M

COMP

COMBINATIONS

OUT

HYST

INTV

CC

10k

ENABLE
SWITCHING
ACTION

VALLEY MODE

SYNCHRONOUS

CONTROLLER

TO E/A

FAST OUTPUT

OVERVOLTAGE

COMPARATOR

POWER

CONTROL

CONSTANT

ON-TIME

BUCK

V

FB

ENABLE

8.2k

0.1µF

I

ON

15V

ZENER

M

TOP

0.8µH

M

BOT

–

+

8.2k

R C

8.2k

8.2k

V

1.3M
f

SET

V

ING

V

INGP

V

INH

2.2µF

SW

V

OUT

10µF

GND

SGND

CROWBAR

V

ORB

V

OSNS

V

OSNS

V

ORB

4641 F01

INL

C

MSP

OUT(BULK)

SET1B

SET1A





= R

R

SET1A

8.2kΩ

SET1B

IN(MLCC)

*

R

fSET

+

C

MCB

–

–

+

+

R

R

SET2

R

V

= 0.6 1+

OUT

USE R

SET1A

REQUIRED FOR V

R

SET2

NOT NECESSARY FOR V

R

SET2

+

V

OUT

0.6V TO 6V
UP TO 10A

C

OUT(MLCC)

2 •R

+

R

SET2

≤8.2k

OUT

V

IN

4V TO 38V
(4.5V START-UP)

C

IN(BULK)



SET1A




> 1.2V

≤ 1.2V

OUT

Figure 1. Simplified Block Diagram. cf. Functional Block Diagram in Appendix A, Figure 62

Decoupling requireMenTs

SYMBOL PARAMETER CONDITIONS

C

IN(MLCC)

C

IN(BULK)

C

OUT(MLCC)

C

OUT(BULK)

+

+

External Input Capacitor Requirement I

External Output Capacitor Requirement I

For more information www.linear.com/LTM4641

= 10A, 2 × 10μF or 4 × 4.7μF

OUT

= 10A, 3 × 100μF or 6 × 47μF

OUT

MIN TYP MAX

20

300

UNITS

μF

μF

4641fe

15

LTM4641

operaTion

Introduction

The LTM4641 contains a buck-topology regulator employ-

constant on-time current mode control scheme,

ing a
including built-in power

MOSFET devices with fast
switching speed and a power inductor. In its most basic
configuration (see Figure 45), the module operates as a
standalone nonisolated switching mode DC/DC step-down
power supply. It can provide up to 10A of output current
with a few external input and output capacitors and output
feedback resistors. The supported output voltage range is
from 0.6V DC to 6V DC. The supported input voltage range
is 4V to 38V, with a maximum start-up voltage of 4.5V
(over temperature). Power conversion from lower input
voltages can be realized if an auxiliary bias supply is avail

­able to power LTM4641’s control and housekeeping bias
input pin, V

. The LTM4641 Simplified Block Diagram is

INL

found in Figure 1. For a more detailed look, the Functional
Block Diagram is found in Appendix A, Figure 62.

Motivation

Pulsed loading conditions and abnormal disturbances
within the electrical systems found in industrial, vehicle,
aeronautic, and military applications can induce wildly
varying voltage transients (surges) on what is nominally
a 24V DC to 28V DC distributed bus (28V DC
duration of such disturbances

can extend for periods of

bus). The

time between a millisecond to a minute in length, with
excursions sometimes reaching (or exceeding) 40V and
falling below 6V.

While switching buck regulators are of universal inter­est due to their compact size and ability to deliver DC/
DC power conversion at

high efficiency, FMEA (failure
modes and effects analysis) leads one to believe that
there is no way to reduce the severity rating and effects
of an electrical short from the input source to the output
load—however improbable. The LTM4641 challenges
this notion by protecting the load from seeing excessive
voltage stress, even when its high side switching MOSFET
is short circuited.

Power µModule Regulator Reliability

First and foremost, Linear Technology μModule products
adhere to rigorous testing and high reliability control,
fabrication, and manufacturing processes—as is required
of all its products. Furthermore, as part of its commit
ment to
program periodically updates its

excellence, the Linear Technology Quality Control

Reliability Data report

-

for LTM4600 series products to include cumulative data
obtained from ongoing and routine in-house testing relating
to operational life, highly accelerated stress, power and
temperature cycling, thermal and mechanical shock, and

more. To view the latest report visit http://www.

much
linear.com/docs/13557.

The LTM4641 easily supports high step-down ratios
with few external components. The additional protection
features when implemented provide an extra degree of
insurance beyond other μModule regulators.

Overview

When configured as shown in Figure 46, the LTM4641
can regulate an output voltage between 0.6V and 6V from
an input voltage between 4V and 38V (4.5V

start-up,

IN

maximum).

If an optional N-channel power MOSFET, MSP, is placed
between the input power source (V
stage input pins (V

), MSP’s role becomes that of a

INH

) and the power

IN

resettable electronic power-interrupt switch. The gate of
MSP is operated by V

, and its gate-to-source voltage

ING

is assured to be clamped by a built-in 15V Zener diode
accessed via V

charges the gate of MSP to nominally 10V above

V

ING

potential—suitable for driving a standard-logic MOS-

V

INH

FET—and MSP becomes enhanced to

. When switching action is engaged,

INGP

pull V

up to the

INH

input source supply’s electrical potential. The switching
regulator steps down V

potential to V

INH

when MSP is

OUT

on. When switching action is inhibited by pulling the RUN
pin low or when

a fault condition is detected by LTM4641’s
internal circuitry—such as an output overvoltage (OOV)
condition—the gate of MSP is discharged and MSP turns
off. The input source supply is thus disconnected from
LTM4641’s power stage input (V

INH

).

16

4641fe

For more information www.linear.com/LTM4641

applicaTions inForMaTion—power supply FeaTures

LTM4641

The operation of MSP as a power interrupter provides a
critical element of robust OOV protection: it removes a
means for input power to flow through a damaged power
stage to any precious loads on the output voltage rail, even
when input power is cycled.

For even greater resilience to a short-circuit between V

INH

and the SW switching node of the power stage, an external
logic-level N-channel power MOSFET, MCB, is optionally
placed—in a crowbar configuration—on the output of
the power module. When an OOV condition is detected,
CROWBAR turns on MCB (within 500ns, maximum) to
discharge the output capacitors and transform any residual
energy in LTM4641’s power stage into a trivial amount of
heat—energy which would otherwise have only served to
inject charge into (further pump up the voltage on) the
output capacitors, where precious loads reside.

The control and monitoring circuitry within the LTM4641
power module provide the following:

• Fast, accurate, latching output overvoltage detector
(<500ns response time, <±12mv threshold error)

• N-channel output overvoltage crowbar power MOSFET
drive

• Accurate (<±2.4%) nonlatching and resettable latching
input overvoltage shutdown thresholds

• N-channel overvoltage power-interrupt MOSFET

Accurate (<±2.4%) Input UVLO rising and UVLO falling

•

drive

thresholds

• Built-in and adjustable overtemperature shutdown
protection, programmable for resettable latching or
nonlatching (hysteretic restart) response

• Analog temperature indicator output pin

• Adjustable power-on reset and timeout delay time

• Latchoff behavior that can be altered to instead provide

autonomous restart after timeout delay time expires

• Parallelable for higher output power

• Differential remote sensing of POL voltage

• Internal loop compensation

• Output current foldback protection

• Selectable pulse-skipping mode operation

• Output voltage soft-start and rail tracking

• Power-up into pre-biased conditions without sinking

current from the output capacitors

• Adjustable switching frequency

• Power good indicator

• RUN enable pin

Novel and simple circuit implementations with LTM4641
and a few external components enable surge ride-through
protection and overtemperature detection of a power­interrupt MOSFET. (See Figure 47, for example.) The
aforementioned features enabled by LTM4641 are grouped
by function and described in the remainder of the Applica
tions Information section.

Power (V

) and Bias (V

INH

LTM4641’s power stage (V

) Input Pins

INL

) and control bias (V

INH

input pins are brought out separately to allow freedom
for implementing more sophisticated system configura
tions, such as: fully utilizing LTM4641’s advanced output
overvoltage (OOV) protection features to protect
(e.g., front page schematic or Figure 46); providing rudi­mentary input

surge ride-through protection

(Figure47);
performing DC/DC down conversion from a power rail
below LTM4641’s inherent UVLO thresholds (from a 3.3V
bus in Figure 49).

If V
recommended to power up V
with V

3.5V within 2ms of V
dation to sequence V

INH

and V

. V

INH

are powered from separate rails, it is

INL

prior to or concurrently

INL

should have a final value of at minimum

INL

exceeding 3.5V. The recommen-

INH

ahead of or closely with V

INL

not related at all to module device reliability but stems
rather from a desire to assure that the control section of
LTM4641 drives the MOSFETs in LTM4641’s power stage
deterministically whenever any appreciable V
is present. It is always permissible for V
present—regardless of the state of V
that there is no UVLO detection on V

—however, realize

INH

INH

INH

voltage to be

INL

.

To prevent the control section from trying to regulate
through a dropout condition or commencing switching
activity in the absence of V

potential, it is recommended

INH

-

)

INL

-

the load

is

INH

voltage

4641fe

For more information www.linear.com/LTM4641

17

LTM4641

0.7V • 10pF

ION

V

1.3MΩ

V

2ms/DIV

4641 F02

500mV/DIV

applicaTions inForMaTion—power supply FeaTures

to implement a custom UVLO falling setting above the
dropout curve in Figure 4 (see also Figure 11).

LT3010-5 is shown in Figure 47 to provide bias for V
to enable ride-through of 80V transients on V
detection of V
a discharge path for V

and V

V

INH

ing requirement, only that V
whenever V

and V

V

INL

is realized in this example by D2 creating

IN

in the event of loss of VIN.

INL

have no specific power-down sequenc-

INL

should stay above 3.5V

INL

is above 3.5V.

INH

sequencing is inherently addressed by the

INH

IN

,

INL

. UVLO

LTM4641 in the Figure 45 and Figure 46 circuits.

The V

and V

IN

start-up and shutdown waveforms of the

INL

Figure 47 circuit—but with 1Ω output load and TMR tied
to INTV
ing capacitor, C

—are shown in Figure 2. The effect of the tim-

CC

, that normally generates a power-on

TMR

reset (POR) delay at start-up is negated by tying TMR to
INTV

. The ~3ms VIN-to-V

CC

start-up delay time seen in

OUT

Figure 2 is due to POR of the LTM4641’s fault-monitoring
circuitry and soft-start ramp (C

V

IN

5V/DIV

V

INL

5V/DIV

V

OUT

SS

).

scheme. During a load transient step-up, the control
loop will command a
compensate fo

r a defi

higher inductor trough current to

ciency in output voltage; the effective
switching frequency will increase until the output voltage
returns to normal (an overcurrent event, notwithstanding).
During a load transient step-down, the control loop will
command a lower inductor trough current to compensate
for an excess of output voltage; the effective switching
frequency will decrease until the output voltage returns to
normal. The control loop perceives inductor current-sense
information via the voltage signal that appears across the
synchronous power MOSFET, M

, when M

BOT

(this is commonly referred to in the industry as R

BOT

is on

DS(ON)

current sensing).

The on-time of the one-shot timer—and hence the power
control MOSFET, M

tON=

where I

I

is in units of amperes. For output voltages

ION

,—is given, in units of seconds, by:

TOP

(1)

greater than 3V, and for non-rail-tracking applications,
no external R

resistor is needed, and the I

fSET

(units: amperes) is set solely by the V
volts) and the internal 1.3MΩ V

I

ION

INL

=

INL

-to-f

voltage (units:

INL

SET

current

ION

resistor:

(2)

Figure 2. Start-Up and Shutdown Waveforms of Figure 47
Circuit. TMR Tied to INTVCC to Highlight VIN and V
Sequencing without POR Delay. 1Ω Load

INL

Switching Frequency (On Time) Selection and Voltage
Dropout Criteria (Achievable V

IN

-to-V

Step-Down

OUT

Ratios)

The LTM4641 controller employs a current mode constant
on-time architecture, in which the COMP voltage corre
sponds to the trough inductor current at which the internal
high side power MOSFET

(M

) is commanded on by

TOP

the control loop—for a duration of time proportional to
controller’s I

pin current (Refer to Figure 1). Regulation

ON

is maintained by a pulsed frequency modulation (PFM)

18

For more information www.linear.com/LTM4641

The switching frequency of operation of the LTM4641’s
buck converter power stage at full load in this scenario
is given, in Hz, by:

fSW=

where V

0.7V • 1.3MΩ • 10pF

is the desired nominal output voltage, in units

OUT

OUT

(3)

of volts.

An external R
greater than 3V, if desired, to obtain increased switching

-

resistor can be applied when setting V

fSET

OUT

frequency. Usually, increasing switching frequency comes
from a desire to reduce output voltage ripple and/or output
capacitance requirement—but at a moderate penalty to
DC/DC conversion efficiency. There are some limitations
to how low an R

value can be applied in practice due

fSET

4641fe

applicaTions inForMaTion—power supply FeaTures

V

V

fSET

V

fSET

V

( )

V

ON

V

• I

LTM4641

to non-zero minimum off-time, dropout voltage, and
maximum achievable switching frequency of operation.

When an R
nected between V
on-time setting, the total I

resistor external to the LTM4641 is con-

fSET

INL

and f

to decrease the default

SET

current (units: amperes) is

ON

given by:

I

ION

where V
R

fSET

equal to 3V

INL

=

1.3MΩ

is in units of volts and R

INL

is needed for output voltage settings less than or

OUT

INL

+

=

R

INL

1.3MΩ ||R

fSET

is in units of ohms.

, and for rail-tracking applications.

(4)

The minimum on-time the LTM4641 supports is 43ns, typi­cal, but
Therefore, for a conser
than 75ns, typical. From Equation 1, it follows that I

guard banded conservatively to 75ns, maximum.

vative design, t

should be larger

ON

ION

should be designed to be less than 93.3μA.

When an external R

fSET

(and V

INL

and R

resistor is applied between V

fSET

and V

are operating from the same

INH

INL

rail—Figure 45 and Figure 46), the switching frequency of
operation of the power stage at full load, in Hz, is given by:

fSW=

where R

0.7V • 1.3MΩ|| R

is in ohms, and V

fSET

OUT

• 10pF

fSET

OUT

is the desired nominal

(5)

output voltage, in units of volts.

In the general case, the switching frequency of the buck
converter power stage at full load is given, in Hz, by:

fSW=

V

INH

OUT

• t

=

OUT

V

• 0.7V • 10pF

INH

ION

(6)

• When V

INL

and V

are operated from separate

INH

supplies…

… why should R

source rather than V

…when is it okay for R

ordinarily connect to the VIN power

fSET

(Figure 49)?

INH

to connect to V

fSET

INH

(Figure 47)?

For application circuits

of the form found in Figure 45,
Figure 46, Figure 47 and Figure 51: see Figure 3 for the
maximum recommended value of R

as a function

fSET

of nominal target output voltage, and resulting full-load
switching frequency corresponding to those R

fSET

values.

Figure 3 can also be interpreted to provide the lowest
recommended switching frequency for a given target
output voltage. Table 1 summarizes nominal values of

endorsed for some popular output voltages; use

R

fSET

of commonly available ±5% tolerance resistors or better
with ±100ppm/°C temperature coefficient or better is
recommended.

fSET

4641 F03

700

TYPICAL f

600

500

SW

AT FULL LOAD (kHz)

400

300

200

100

0

100

R

vs V

fSET

50

VALUE (MΩ)

10

fSET

5

1

0.5

MAXIMUM RECOMMENDED R

0.1
0 0.5 1 1.5

OUT

REGION

TO AVOID

MAX RECOMMENDED R
SWITCHING FREQUENCY

2 2.5 3 3.5 4 4.5 5 5.5 6

NOMINAL OUTPUT VOLTAGE (V)

R

NOT

fSET

NEEDED FOR

> 3V

V

OUT

See Appendix C for a detailed discussion on the following
topics:

Figure 3. Maximum Recommended R
Non-Tracking Applications, and Resulting Full-Load Operating
Switching Frequency vs Nominal Output Voltage

(Nominal Values) for

fSET

• Why should the switching controller be operated at a
higher switching frequency (i.e., programmed for a
shorter on-time with R
internal 1.3MΩ V

INL

-to-f

) than that yielded by the

fSET

resistor alone…

SET

…for nominal output voltages of 3V and less?

…in rail-tracking applications?

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19

LTM4641





1

applicaTions inForMaTion—power supply FeaTures

Table 1. Endorsed R
Non-Tracking Applications—and Resulting Full-Load Switching
Frequency (cf. Figure 45, Figure 46, Figure 47, and Figure 51
Circuits)

V

Greater Than 3.0 ∞ (Not Used) See Figure 2

(V)

OUT(NOM)

0.6 0.787 175

0.7 0.825 200

0.8 0.887 215

0.9 0.931 235

1.0 1.00 255

1.2 1.13 285

1.5 1.43 315

1.8 2.00 325

2.0 2.55 330

2.5 5.76 335

3.3 ∞ (Not Used) 360

5.0 ∞ (Not Used) 550

6.0 ∞ (Not Used) 660

Resistor Value vs Output Voltage for

fSET

(MΩ) (Nearest

R

fSET

EIA-Standard Values) f

SW

(kHz)

In rail-tracking applications, it is recommended to use the

value corresponding to the lowest voltage needed

R

fSET

to be regulated during output voltage ramp down. For
example: to ramp V

down to 0.5V requires R

OUT

fSET

to be

not more than 750kΩ (nominal) per Figure 3.

It is often permissible to use lower R

values than those

fSET

indicated in Figure 3 and Table 1 if, for example, lower
output ripple voltage and/or a lower output capacitance
is desired. However, be aware of three guiding principles:

I. Minimum On-Time. Ensure I

< 93.3µA. See Equa-

ION

tions1 and 4.

Minimum Off-Time and Dropout Operation. The mini-

II.

mum off

-time, t

OFF(MIN)

, is the shortest time required
for the LTM4641 to perform the following tasks: turn
on its power synchronous

MOSFET (M
control loop’s current comparator, and turn off M
The minimum input voltage on V

, in volts, that one

INH

), trip the

BOT

BOT

.

can regulate the output at and still avoid dropout is
given by:

t

V

IN(DROPOUT)

= V

OUT

• 1+




OFF(MIN)

t

ON




+ R

PS•IOUT

(7)

where:

• V

• t

is nominal output voltage in volts.

OUT

OFF(MIN)

be on, after M

is the minimum length of time M

turns off. For a conservative de-

TOP

sign, use a value of 300ns, taken from the Electrical
Characteristics Table.

is the on-time of the power control MOSFET,

t

•

ON

, as programmed by the current flowing into

M

TOP

the I

• R
stage, from V

pin of LTM4641’s internal control IC.

ON

is the series resistance of the module’s power

PS

INH

to V

. For VIN ≥ 6V, this is less

OUT

than 50mΩ, even at extreme temperatures (T
125°C). For V
increases due to drop in INTV

< 6V, the effective series resistance

IN

voltage and cor-

CC

responding decreased gate-drive enhancement of

. Printed circuit board (PCB) and/or cable

M

TOP

resistance present in the copper planes and/or wires
that physically connect the output of the module to
the load adds to R

• I

is the load current on V

OUT

’s effective value.

PS

in amperes.

OUT

For applications of the form shown in Figure 45, Fig­ure46 and

Figure 47: the minimum allowable V
voltage of operation to avoid dropout for 3V < V
≤ 6V is shown in Figure 4. The curves are a result of
realizing that V

IN(DROPOUT)

equals V

(neglecting

INH

MSP voltage drop) when dropout actually occurs, and
that Equations 1 and 2 yield an expression for t

. M

a function of V

INH

during its on-time if DRV
value of 5.3V (for example, when V
DRV
R

bias is provided by INTVCC). DRVCC’s effect on

CC

at low line is illustrated in Figure 4.

PS

III. Maximum Attainable f

will be less fully enhanced

TOP

is less than its nominal

CC

< 6V and when

INL

. The maximum attainable

SW

switching frequency of operation (in units of Hz) for a
given on-time (t

f

MAX

=

tON+ t

, in seconds) is governed simply by:

ON

OFF(MIN)

where a conservative value of 300ns can be used for

t

OFF(MIN)

.

BOT

can

J

INH

OUT

ON

≈

as

(8)

4641fe

20

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applicaTions inForMaTion—power supply FeaTures

OUT

SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP
MODULE SGND ROUTES/PLANES SEPARATE FROM GND
ON MOTHERBOARD

C

, C

: FEEDFORWARD CAPACITORS YEILD IMPROVED TRANSIENT

LTM4641

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

LINE DROPOUT VOLTAGE (V)

4.0

3.5

3.0

3.5

3

OUTPUT VOLTAGE SETTING (V)

10A OUTPUT, DRVCC BIASED FROM INTVCC (5.3V
10A OUTPUT, DRV
NO LOAD, DRV

(UVLO FALLING)

4.5

5

4

BIASED TO 5.3V BY EXTERNAL SUPPLY

CC

≥ 4.2V(UVLO RISING) AND 3.5V

CC

5.5

4641 F04

6

NOM

)

Figure 4. Line Dropout Voltage vs Output Voltage at No Load
and Full Load. Figure 45, Figure 46 and Figure 47 Circuit
Applications. R
Setting V

OUT

= Open and R

fSET

SET1A

, R

SET1B

for Regulation at or Above 3V

, R

SET2

Values

Given that the PFM control scheme increases switching

frequency (to as high as f

) to maintain regulation

MAX

during a transient load step-up, the design guidance
is: set the steady-state operating frequency f
less than f

. Furthermore, when the LTM4641 is

MAX

SW

to be

in dropout operation, the switching frequency of the
converter is f

MAX

.

It is best to avoid operation in dropout scenarios, because
the control loop will rail COMP high to command M

TOP

at highest possible duty cycle. If input voltage “snaps
upwards” at a sufficiently high slew rate when COMP has
railed, the control loop may be unable provide satisfactory
line rejection.

See Figure 11 to set the UVLO falling response of LTM4641
above the computed V
switching action for V

IN(DROPOUT)

< V

IN

IN(DROPOUT)

voltage; this will inhibit

. Input voltage ripple,

and any line sag between the input source supply and the

pins—and voltage drop across the power interrupt

V

INH

MOSFET, MSP, if used—must be taken into account by
the system designer.

Setting the Output Voltage; the Differential Remote
Sense Amplifier

A built-in differential remote-sense amplifier enables preci

­sion regulation at the point-of-load (POL), compensating
for any voltage drops in the system’s output distribution
path: the total variation of LTM4641’s output DC voltage
over line, load, and temperature is better than ±1.5%.

The basic feedback connection between the POL and the
module’s feedback sense pins is shown in Figure 5.

V

FB

TO ERROR

AMPLIFIER

TRUE DIFFERENTIAL REMOTE

Figure 5. Basic Feedback Remote Sense Connections and Techniques; Setting the Output Voltage

FFA

RESPONSE WHEN FILTERING V
(C

OUT(MLCC)

V

OUT

LTM4641

ICT
TEST

+

V

ORB

8.2k
V

8.2k

8.2k

OSNS

V

OSNS

V

SGND

ORB

GND

+

SENSE AMPLIFIER

–

8.2k

POINT

+

R

–

–

ICT
TEST
POINT

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FFB

)

R

SET2

R

PLACE ALL

FEEDBACK
COMPONENTS
LOCAL TO THE

LTM4641

C

FFA

SET1A

SET1B

C

FFB

WITH ONLY MLCC OUTPUT CAPACITORS

OUT

+

C

OUT(BULK)

ROUTE FEEDBACK SIGNAL AS

A DIFFERENTIAL PAIR (OR

TWISTED PAIR IF USING WIRES).

SANDWICH BETWEEN GROUND

PLANES TO FORM A PROTECTIVE SHIELD

GUARDING AGAINST STRAY NOISE

C

OUT(MLCC)

V

LOAD

4641 F05

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21