Gain Match: ±0.35dB Max, Passband
Phase Match: ±1.2° Max, Passband
Single-Ended or Differential Inputs
n
< –90dBc Distortion in Passband
n
2.1nV/√Hz Op Amp Noise Density
n
Pin-Selectable Gain (0dB/12dB/14dB)
n
Pin-Selectable Power Consumption (0.35mA/
16.2mA/33.1mA)
n
Rail-to-Rail Output Swing
Adjustable Output Common Mode Voltage Control
Buffered, Low Impedance Outputs
n
2.7V to 5.25V Supply Voltage
n
Small 22-Pin 6mm × 3mm × 0.75mm DFN Package
APPLICATIONS
n
Broadband Wireless ADC Driver/Filter
n
Antialiasing Filter
n
Single-Ended to Differential Conversion
n
DAC Smoothing Filter
n
Zero-IF Direct Conversion Receivers
DESCRIPTION
The LTC®6605-10 contains two independent, fully differential amplifi ers confi gured as matched 2nd order 10MHz
lowpass fi lters. The f
range of 9.7MHz to 14MHz.
The internal op amps are fully differential, feature very
low noise and distortion, and are compatible with 16-bit
dynamic range systems. The inputs can accept singleended or differential signals. An input pin is provided
for each amplifi er to set the common mode level of the
differential outputs.
Internal laser-trimmed resistors and capacitors determine
a precise, very well matched (in gain and phase) 10MHz
2nd order fi lter response. A single optional external resistor per channel can tailor the frequency response for
each amplifi er.
Three-state BIAS pins determine each amplifi er’s power
consumption, allowing a choice between shutdown, medium power or full power.
The LTC6605-10 is available in a compact 6mm × 3mm
22-pin leadless DFN package and operates over a –40°C
to 85°C temperature range.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
of the fi lters is adjustable in the
–3dB
TYPICAL APPLICATION
Dual, Matched 9.7MHz Lowpass Filter
+
3V
V
INA
–
+
3V
V
INB
–
1
2
+
3
4
–
5
LTC6605-10
6
7
8
+
9
10
–
11
22
21
20
19
18
17
16
15
14
13
12
660510 TA01
0.1μF
0.1μF
0.1μF
0.1μF
Channel to Channel Phase Matching
120
352 TYPICAL UNITS
= 25°C
T
3V
V
–
OUTA
+
3V
V
–
OUTB
+
A
= 10MHz
f
100
IN
80
60
40
NUMBER OF UNITS
20
0
–1.0
–0.6–0.2–0.4–0.8
00.6 0.80.40.21.0
PHASE MATCH (DEG)
660510 TA01b
660510f
1
LTC6605-10
(Note 1)
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V–) ................................5.5V
Input Current (Note 2) ..........................................±10mA
Operating Temperature Range (Note 4).... –40°C to 85°C
Specifi ed Temperature Range (Note 5) ....–40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range ................... –65°C to 150°C
ORDER INFORMATION
TOP VIEW
+IN4 A
1
+IN1 A
2
BIAS A
3
–IN1 A
4
–IN4 A
5
–
V
6
+IN4 B
7
+IN1 B
8
BIAS B
9
–IN1 B
10
–IN4 B
11
22-LEAD (6mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 23) IS V
DJC PACKAGE
T
= 150°C, θJA = 46.5°C/W
JMAX
22
–OUT A
+
A
21
V
–
V
20
V
19
OCMA
+OUT A
18
17
16
15
14
13
12
–
V
–OUT B
+
B
V
–
V
V
OCMB
+OUT B
23
–
, MUST BE SOLDERED TO PCB
LEAD FREE FINISHTAPE AND REELPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE
LTC6605CDJC-10#PBFLTC6605CDJC-10#TRPBF 66051022-Lead (6mm × 3mm) Plastic DFN0°C to 70°C
LTC6605IDJC-10#PBFLTC6605IDJC-10# TRPBF 66051022-Lead (6mm × 3mm) Plastic DFN–40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
DC ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3V, V– = 0V, V
R
= 10k. The fi lter is confi gured for a gain of 1, unless otherwise noted. VS is defi ned as (V+ – V–). V
BAL
V
–OUT
)/2. V
is defi ned as (V
INCM
INP
+ V
INM
)/2. V
is defi ned as (V
OUTDIFF
+OUT
– V
INCM
–OUT
). V
= V
= mid-supply, BIAS tied to V+, RL = Open,
OCM
is defi ned as (V
INDIFF
is defi ned as (V
OUTCM
– V
INP
). See Figure 1.
INM
+OUT
+
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V
OS
Differential Offset Voltage (at Op Amp
VS = 2.7V to 5V
l
±0.25±1mV
Inputs) (Note 6)
ΔVOS/ΔTDifferential Offset Voltage Drift (at Op
Amp Inputs)
I
B
Input Bias Current (at Op Amp Inputs)
(Note 7)
I
OS
Input Offset Current
BIAS = V
+
BIAS = Floating
BIAS = V
+
BIAS = Floating
l
l
l
–60
l
–30
±1
±1
–25
–12.5
μV/°C
μV/°C
0
0
μA
μA
±1μA
(at Op Amp Inputs) (Note 7)
2
660510f
LTC6605-10
DC ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
R
= 10k. The fi lter is confi gured for a gain of 1, unless otherwise noted. VS is defi ned as (V+ – V–). V
BAL
V
–OUT
)/2. V
is defi ned as (V
INCM
INP
+ V
INM
)/2. V
= 25°C. V+ = 3V, V– = 0V, V
A
is defi ned as (V
OUTDIFF
+OUT
– V
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V
INCM
Input Common Mode Voltage Range
(Note 8)
CMRRCommon Mode Rejection Ratio
(ΔV
/ΔVOS) (Note 9)
INCM
PSRRPower Supply Rejection Ratio
(ΔV
/ΔVOS) (Note 10)
S
V
V
V
R
V
I
SC
V
I
S
OSCM
OCM
MID
VOCM
OUT
S
Common Mode Offset Voltage
(V
– V
OUTCM
OCM
)
Output Common Mode Range
(Valid Range for V
Self-Biased Voltage at the V
Input Resistance of V
Output Voltage Swing, High
(Measured Relative to V
Output Voltage Swing, Low
(Measured Relative to V
Pin) (Note 8)
OCM
OCM
+
)
–
)
OCM
Pin
Output Short-Circuit Current (Note 3)VS = 3V
Supply Voltage
Supply Current (per Channel)VS = 2.7V to 5V; BIAS = V
PinVS = 3V
VS = 3V
V
= 5V
S
= 3V; ΔV
V
S
V
= 5V; ΔV
S
= 2.7V to 5V
V
S
= 3V
V
S
V
= 5V
S
= 3V
V
S
V
= 5V
S
= 3V; IL = 0mA
V
S
V
= 3V; IL = 5mA
S
V
= 3V; IL = 20mA
S
V
= 5V; IL = 0mA
S
V
= 5V; IL = 5mA
S
V
= 5V; IL = 20mA
S
= 3V; IL = 0mA
V
S
V
= 3V; IL = –5mA
S
V
= 3V; IL = –20mA
S
V
= 5V; IL = 0mA
S
V
= 5V; IL = –5mA
S
V
= 5V; IL = –20mA
S
V
= 5V
S
INCM
INCM
= 1.5V
= 2.5V
VS = 2.7V to 5V; BIAS = Floating
V
= 2.7V to 5V; BIAS = V
R
t
t
BIAS
ON
OFF
S
BIAS Pin Range for ShutdownReferenced to V
BIAS Pin Range for Medium PowerReferenced to V
BIAS Pin Range for Full PowerReferenced to V
BIAS Pin Self-Biased Voltage (Floating) Referenced to V
BIAS Pin Input Resistance
Turn-On TimeVS = 3V, V
Turn- O f f TimeVS = 3V, V
BIAS
BIAS
–
–
–
–
= V– to V
= V+ to V
+
–
–OUT
+
–
INCM
). V
= V
= mid-supply, BIAS tied to V+, RL = Open,
OCM
is defi ned as (V
INDIFF
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
–0.2
–0.2
1.1
1.1
1.4751.51.525V
12.51823.5kΩ
±40
±50
2.75.25V
2.3V
1.051.151.25V
100150200kΩ
is defi ned as (V
OUTCM
– V
INP
46
46
). See Figure 1.
INM
74
74
6695dB
±10
±10
245
285
415
350
390
550
120
135
195
175
200
270
±70
±95
33.1
16.2
0.35
00.4V
11.5V
400ns
400ns
1.7
4.7
±15
±15
2
4
450
525
750
625
700
1000
225
250
350
325
360
475
45
26.5
1.6
S
+OUT
+
V
V
dB
dB
mV
mV
V
V
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
mA
mA
V
660510f
3
LTC6605-10
AC ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
= 25°C. V+ = 3V, V– = 0V, V
A
otherwise noted. Filter confi gured as in Figure 2, unless otherwise noted. VS is defi ned as (V+ – V–). V
V
)/2. V
–OUT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
GainFilter GainΔV
PhaseFilter PhaseΔV
ΔGainGain Match (Channel-to-Channel)ΔV
ΔPhasePhase Match (Channel-to-Channel)V
4V/V GainFilter Gain in 4V/V Confi guration
TCFilter Cut-Off Frequency Temperature
f
O
NoiseIntegrated Output Noise
e
n
i
n
HD22nd Harmonic Distortion
HD33rd Harmonic Distortion
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All pins are protected by steering diodes to either supply. If any
pin is driven beyond the LTC6605-10’s supply voltage, the excess input
current (current in excess of what it takes to drive that pin to the supply
rail) should be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefi nitely. Long-term application of output currents in excess of the
Absolute Maximum Ratings may impair the life of the device.
Note 4: Both the LTC6605C and the LTC6605I are guaranteed functional
over the operating temperature range –40°C to 85°C.
is defi ned as (V
INCM
+IN
+ V
–IN
)/2. V
OUTDIFF
Inputs at ±IN1 Pins, ±IN4 Pins Floating
Channel SeparationV
Coeffi cient
(BW = 10kHz to 20MHz)
Input Referred Noise Density (f = 1MHz) BIAS = V
Voltage Noise Density Referred to
Op Amp Inputs (f = 1MHz)
Current Noise Density Referred to
Op Amp Inputs (f = 1MHz)
f
= 5MHz; VIN = 2V
IN
f
= 5MHz; VIN = 2V
IN
Single-Ended
P-P
Single-Ended
P-P
is defi ned as (V
= ±0.125V, DC
IN
V
= 0.5V
INDIFF
V
INDIFF
V
INDIFF
V
INDIFF
V
INDIFF
= ±0.125V, DC
IN
V
INDIFF
V
INDIFF
V
INDIFF
= ±0.125V, DC
IN
V
INDIFF
V
INDIFF
V
INDIFF
INDIFF
V
INDIFF
V
INDIFF
ΔVIN = ±0.125V, DC
INDIFF
BIAS = V
BIAS = Floating
Figure 4, Gain = 1
Figure 4, Gain = 4
Figure 4, Gain = 5
BIAS = V
BIAS = Floating
BIAS = V
BIAS = Floating
BIAS = V
BIAS = Floating, R
BIAS = V
BIAS = Floating, R
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 0.5V
= 1V
+
+
+
+
+
+
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
– V
+OUT
, f = 5MHz
, f = 7.5MHz
, f = 10MHz
, f = 20MHz
, f = 50MHz
, f = 5MHz
, f = 7.5MHz
, f = 10MHz
, f = 5MHz
, f = 7.5MHz
, f = 10MHz
, f = 5MHz
, f = 7.5MHz
, f = 10MHz
, f = 5MHz–96dB
= 400Ω
LOAD
= 400Ω
LOAD
Note 5: The LTC6605C is guaranteed to meet specifi ed performance
from 0°C to 70°C. The LTC6605C is designed, characterized and
expected to meet specifi ed performance from –40°C to 85°C, but is
not tested or QA sampled at these temperatures. The LTC6605I is
guaranteed to meet specifi ed performance from –40°C to 85°C.
Note 6: Output referred voltage offset is a function of gain. To determine
output referred voltage offset, or output voltage offset drift, multiply V
by the noise gain (1 + GAIN). See Figure 3.
Note 7: Input bias current is defi ned as the average of the currents
fl owing into the noninverting and inverting inputs of the internal amplifi er
and is calculated from measurements made at the pins of the IC. Input
offset current is defi ned as the difference of the currents fl owing into
the noninverting and inverting inputs of the internal amplifi er and is
calculated from measurements made at the pins of the IC.
INCM
–OUT
). V
= V
OCM
is defi ned as (V
INDIFF
= mid-supply, V
OUTCM
l
–0.25
l
–1.1
l
–2.35
l
–4.05
l
–11.75
l
–28
l
–0.2
l
–0.2
l
–0.3
l
–0.35
l
–1.1
l
–1.2
l
–1.2
l
11.851212. 25dB
= V+, unless
BIAS
is defi ned as (V
+ V
+IN
).
–IN
±0.05
–0.77
–1.89
–3.5
–11.1
–25.8
0.25
–0.4
–1.45
–3
–10.55
–24.8
0
–42.5
–63.2
–81.7
±0.05
±0.05
±0.05
±0.05
±0.2
±0.2
±0.2
0.2
0.2
0.3
0.35
1.1
1.2
1.2
–80
–260
69μV
20
5
4
2.1
2.6
3
2.1
–90
–75
–106
–82
+OUT
+
dB
dB
dB
dB
dB
dB
Deg
Deg
Deg
Deg
dB
dB
dB
dB
Deg
Deg
Deg
ppm/°C
ppm/°C
RMS
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
dBc
dBc
dBc
dBc
OS
660510f
4
ELECTRICAL CHARACTERISTICS
LTC6605-10
Note 8: See the Applications Information section for a detailed
discussion of input and output common mode range. Input common
mode range is tested by measuring the differential DC gain with V
= mid-supply, and again with V
at the input common mode range
INCM
limits listed in the Electrical Characteristics table, with ΔV
= ±0.25V,
IN
INCM
verifying that the differential gain has not deviated from the mid-supply
common mode input case by more than 0.5%, and that the common
mode offset (V
) has not deviated from the mid-supply common
OSCM
mode offset by more than ±10mV.
Output common mode range is tested by measuring the differential
DC gain with V
pin at the output common range limits listed in the Electrical
V
OCM
= mid-supply, and again with voltage set on the
OCM
Characteristics table verifying that the differential gain has not
deviated from the mid-supply common mode input case by more than
0.5%, and that the common mode offset (V
more than ±10mV from the mid-supply case.
Note 9: CMRR is defi ned as the ratio of the change in the input common
mode voltage at the internal amplifi er inputs to the change in differential
input referred voltage offset (V
Note 10: Power supply rejection ratio (PSRR) is defi ned as the ratio of
the change in supply voltage to the change in differential input referred
voltage offset (V
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs TemperatureFilter Gain vs Temperature