Linear LTC6601-1 Schematic

LTC6601-1

Low Noise, 0.5% Tolerance,

5MHz to 28MHz, Pin Conﬁ gurable

Filter/ADC Driver

FEATURES

n

Pin Conﬁ gurable Gain and Filter Response

Up to 28MHz

n

Few External Components Required

n

Resistors Trimmed to 0.5% Typical

n

Capacitors Trimmed to 0.5% Typical

n

Very Low Noise: 80dB S/N in 100MHz Bandwidth

n

Very Low Distortion (2V

P-P

): 1MHz: –100dBc 2nd, –123dBc 3rd 10MHz: –72dBc 2nd, –103dBc 3rd

n

Adjustable Output Common Mode Voltage

n

Rail-to-Rail Output Swing

n

Power Conﬁ gurability and Low Power Shutdown

n

Tiny 0.75mm 20-Lead (4mm × 4mm) QFN Package

APPLICATIONS

n

Differential Input A/D Converter Driver

n

Antialiasing/Reconstruction Filter

n

Single-Ended to Differential Conversion/Ampliﬁ cation

n

Low Voltage, Low Noise, Differential Signal

Processing

n

Common Mode Voltage Translation

DESCRIPTION

The LTC®6601-1 is a very easy-to-use fully differential 2nd order active RC ﬁ lter and driver. On-chip resistors, capacitors, and ampliﬁ er bandwidth are trimmed to provide consistent and repeatable ﬁ lter characteristics.

The ﬁ lter characteristics are pin-strap conﬁ gurable. Cutoff frequencies range from 5MHz to 28MHz. Gain is pin-strap programmable between –17dB and +17dB.

A three-state BIAS pin is provided to adjust ampliﬁ er power consumption. Select between high performance, low power (50% power reduction), and standby modes with the BIAS pin.

The LTC6601-1 is available in a compact 4mm × 4mm 16-pin leadless QFN package.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6271719.

TYPICAL APPLICATION

19MHz, 2nd Order Lowpass Filter. Gain = 6dB

20 19 18 17 16

LTC6601-1

1

+

V

IN

–

2

3

3V

4

5

+

–

6 7 8 9 10

15

14

13

12

11

66011 TA01a

0.1µF

3V

0.1µF

Frequency Response

10

5

0

–

V

OUT

+

–5

–10

GAIN (dB)

–15

–20

–25

–30

1 10 100

FREQUENCY (MHz)

66011 TA01b

66011f

1

LTC6601-1

(Note 1)

Total Supply Voltage (V+ to V–) ...............................5.5V

+

Input Voltage (Any Pin) (Note 2) ..V Input Current (V

, BIAS) ..................................±10mA

OCM

+ 0.3V to V– –0.3V

Input Current (Pins 1, 5) (Note 2) ........................±20mA

Input Current (Pins 2, 4) (Note 2) ........................±30mA

Input Current (Pins 6, 20) (Note 2) ......................±15mA

Input Current (Pins 7, 8, 9, 10, 16, 17, 18, 19)

(Note 2) ................................................................±10mA

Output Short-Circuit Duration (Note 3) ............ Indeﬁ nite

Operating Temperature Range (Note 4).... –40°C to 85°C

Speciﬁ ed Temperature Range (Note 5) ....–40°C to 85°C

Junction Temperature ........................................... 150°C

Storage Temperature Range ...................–65°C to 150°C

ORDER INFORMATION

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

TOP VIEW

IN4+C5C6C7

20 19 18 17 16

+

IN2

1

+

IN1

2

BIAS

3

–

IN1

4

–

IN2

5

20-LEAD (4mm s 4mm) PLASTIC QFN

T

= 150°C, θJA = 37°C/W, θJC = 2°C/W

JMAX

EXPOSED PAD (PIN 21) IS V

6 7 8

–

C1C2C3

IN4

UF PACKAGE

21

C8

–

OUT

15

+

V

14

–

V

13

V

12

OCM

+

OUT

11

9 10

C4

–

, MUST BE SOLDERED TO PCB

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC6601CUF-1#PBF LTC6601IUF-1#PBF

LTC6601CUF-1#TRPBF LTC6601IUF-1#TRPBF

66011 66011

20-Lead (4mm × 4mm) Plastic QFN 20-Lead (4mm × 4mm) Plastic QFN

0°C to 70°C –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. V+ = 3V, V– = 0V, V I

LOAD

(V

OUT

= 0, R

+

+ V

= 100k. The ﬁ lter is conﬁ gured for a gain of 1 unless otherwise noted. VS is deﬁ ned as (V+ – V–). V

BAL

–

OUT

)/2. V

is deﬁ ned as (V

INCM

INP

+ V

INM

)/2. V

is deﬁ ned as (V

OUTDIFF

INCM

OUT

+

= V

– V

= mid-supply, BIAS tied to V+ or ﬂ oating,

OCM

OUT

–

). V

is deﬁ ned as (V

INDIFF

is deﬁ ned as

OUTCM

– V

INP

INM

). See

Figure 1.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

(Note 6) Ampliﬁ er Differential Offset Voltage (Input

V

OSDIFF

Referred)

ΔV

OSDIFF

/ΔT

(Note 6) R

(Note 14) Input Resistance, BIAS = V

IN

Ampiﬁ er Differential Offset Voltage Drift (Input Referred)

Single Ended Input Resistance, Pin 2 or Pin 4 Differential Input Resistance

VS = 2.7V to 5.25V, BIAS = V

+

BIAS = Floating

= 2.7V to 5.25V 1 µV/°C

V

S

+

VS = 3V V

= 3V

S

l l

±0.25 ±0.25±1±1.5

133 200

mV mV

 

2

66011f

LTC6601-1

DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T I

LOAD

(V

OUT

= 0, R

+

+ V

= 100k. The ﬁ lter is conﬁ gured for a gain of 1 unless otherwise noted. VS is deﬁ ned as (V+ – V–). V

BAL

–

OUT

)/2. V

is deﬁ ned as (V

INCM

INP

+ V

= 25°C. V+ = 3V, V– = 0V, V

A

INM

)/2. V

is deﬁ ned as (V

OUTDIFF

Figure 1.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ΔR

(Note 14)

IN

(Note 7) Internal Ampliﬁ er Input Bias VS = 2.7V to 5V BIAS = V

I

B

(Note 7) Internal Ampliﬁ er Input Offset VS = 2.7V to 5V BIAS = V

I

OS

V

(Note 8) Input Signal Common Mode Range

INCM

CMRRI (Notes 9, 14)

CMRRO (Notes 9, 14)

Input Resistance Match, BIAS = V Single Ended Input Resistance, Pin 2 or Pin 4 VS = 3V

(V

+ V

INM

+ +

, V , V

)/2

OCM OCM

= 1.5V = 2.5V

OCM OCM

= 1.5V = 2.5V

INP

BIAS = V BIAS = V

BIAS Pin Floating, V BIAS Pin Floating, V

Input Common Mode Rejection Ratio (Ampliﬁ er Input Referred) ΔV ΔV

= 2.5V VS = 5V 74 dB

INCM

Output Common Mode Rejection Ratio (Ampliﬁ er Input Referred) ΔV ΔV

= 1V VS = 5V 70 dB

OCM

PSRR (Note 10) Power Supply Rejection Ratio

(Ampliﬁ er Input Referred) ΔVS/ΔV BIAS = V

+

BIAS Pin Floating

PSRRCM (Note 10) Common Mode Power Supply Rejection Ratio

(ΔV

/ΔV

S

g

cm

Common Mode Gain (ΔV ΔV

OCM

)V

OSCM

= 2V

Common Mode Gain Error = 100 • (gcm – 1) ΔV

= 2V VS = 5V

OCM

BAL

Output Balance (ΔV

OUTCM

Single-Ended Input Differential Input

V

OSCM

ΔV

OSCM

V

OUTCMR

R

INVOCM

V

MID

/ΔT

(Note 8) Output Signal Common Mode Range

Common Mode Offset Voltage (V

– V

OUTCM

OCM

)

Common Mode Offset Voltage Drift (V

– V

OUTCM

(Voltage Range for the V

Input Resistance, V Voltage at the V

)

OCM

Pin VS = 3V

OCM

PIn VS = 3V

OCM

+

BIAS = Floating

= 3V

V

S

V

= 5V

S

= 3V

V

S

V

= 5V

S

/ΔV

INCM

OSDIFF

/ΔV

OCM

OSDIFF

OUTCM

/ΔV

OSDIFF

/ΔV

OUTDIFF

OCM

)

= 2.7V to 5V

V

S

V

= 2.7V to 5V

S

= 2.7V to 5V

S

= 5V 1 V/V

V

S

ΔV V V

V

= 2V

OUTDIFF

= 5V

S

= 5V

S

= 2.7V to 5V BIAS = V

S

VS = 2.7V to 5V BIAS = Floating

= 2.7V to 5V BIAS = V

V

S

VS = 2.7V to 5V BIAS = Floating

Pin) VS = 3V BIAS = V

VS = 5V BIAS = V VS = 3V BIAS Pin Floating V

= 5V BIAS Pin Floating

S

INCM

OUT

+

= V

– V

= mid-supply, BIAS tied to V+ or ﬂ oating,

+

+ +

OCM

OUT

–

). V

is deﬁ ned as (V

INDIFF

l

–50

l

–25

l l

l

66

l

60

l

46 60 dB

l

l l

l

1.1

l

1.1

l

1.1

l

1.1

l

12.5 18 23.5 kΩ

l

1.475 1.5 1.525 V

±0.25 

–25

–12.5

0 0

±0.1 ±0.3 %

–62 –63

OUTCM

INP

±1 ±1

95 95

±5 ±8

5

20

is deﬁ ned as – V

0 0

±10

±5

1.7

4.7

1.8

4.8

–40 –40

±15 ±20

1.7 4

1.8 4

INM

). See

µA µA

V V

dB dB

mV mV

µV/°C µV/°C

V V V V

66011f

3

LTC6601-1

DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T I

LOAD

(V

OUT

= 0, R

+

+ V

= 100k. The ﬁ lter is conﬁ gured for a gain of 1 unless otherwise noted. VS is deﬁ ned as (V+ – V–). V

BAL

–

OUT

)/2. V

is deﬁ ned as (V

INCM

INP

+ V

= 25°C. V+ = 3V, V– = 0V, V

A

INM

)/2. V

is deﬁ ned as (V

OUTDIFF

Figure 1.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

OUT

Output Voltage, High, Either Output Pin (Note 11)

Output Voltage, Low, Either Output Pin (Note 11)

I

SC

Output Short-Circuit Current, Either Output Pin (Note 12)

V

S

I

S

Supply Voltage Range Supply Current, BIAS Pin Tied to V

+

Supply Current, BIAS Pin Floating V

I

SHDN

V

BIASSD

(Note 13) BIAS Input for Half Power Operation VS = 2.7V to 5V

V

BIASLP

BIAS Input for High Performance Operation VS = 2.7V to 5V

V

BIASHP

R

BIAS

BIAS Float Voltage VS = 2.7V to 5V

V

BIAS

t

ON

t

OFF

Supply Current, BIAS Pin Tied to V

BIAS Input Pin Range for Shutdown VS = 2.7V to 5V

BIAS Input Resistance VS = 2.7V to 5V

Turn-On Time VS = 3V, V Turn-Off Time VS = 3V, V

–

VS = 3V, IL = 0mA BIAS = V VS = 3V, IL = –5mA BIAS = V VS = 3V, IL = –20mA BIAS = V VS = 5V, IL = 0mA BIAS = V VS = 5V, IL = –5mA BIAS = V VS = 5V, IL = –20mA BIAS = V

V

= 3V, IL = 0mA, BIAS Pin Floating

S

V

= 3V, IL = –5mA, BIAS Pin Floating

S

V

= 3V, IL = –20mA, BIAS Pin Floating

S

V

= 5V, IL = 0mA, BIAS Pin Floating

S

V

= 5V, IL = –5mA, BIAS Pin Floating

S

V

= 5V, IL = –20mA, BIAS Pin Floating

S

V

= 3V, IL = 0mA BIAS = V

S

VS = 3V, IL = 5mA BIAS = V VS = 3V, IL = 20mA BIAS = V VS = 5V, IL = 0mA BIAS = V VS = 5V, IL = 5mA BIAS = V VS = 5V, IL = 20mA BIAS = V

V

= 3V, IL = 0mA, BIAS Pin Floating

S

V

= 3V, IL = 5mA, BIAS Pin Floating

S

V

= 3V, IL = 20mA, BIAS Pin Floating

S

V

= 5V, IL = 0mA, BIAS Pin Floating

S

V

= 5V, IL = 5mA, BIAS Pin Floating

S

V

= 5V, IL = 20mA, BIAS Pin Floating

S

VS = 3V V

= 5V

S

VS = 2.7V V

= 3V

S

V

= 5V

S

= 2.7V

S

V

= 3V

S

V

= 5V

S

VS = 2.7V V

= 3V

S

VS = 5V

= 0.25V to 3V 400 ns

SHDN

= 3V to 0.25V 400 ns

SHDN

INCM

OUT

+

= V

– V

= mid-supply, BIAS tied to V+ or ﬂ oating,

+ + + + + +

OCM

OUT

–

). V

is deﬁ ned as (V

INDIFF

l l l l l l

l

±45

l

±60

l

2.7 5.25 V

l l l

l

V

l

V– + 1.0 V– + 1.5 V

l

V– + 2.3 V

l

100 150 200 kΩ

l

V– + 1.05 V– + 1.12 V– + 1.25 V

245 285 415 350 390 550

240 290 470 370 430 650

120 135 195 175 200 270

110 120 170 150 170 225

±65 ±90

32.9

33.1

33.9

16.0

16.2

16.9

0.34

0.35

0.55

–

is deﬁ ned as

OUTCM

– V

INP

V– + 0.4 V

450 525 750 625 700

1000

450 525 850 675 775

1100

225 250 350 325 360 475

200 225 300 270 300 400

43

43.5 45

25

25.5

26.5

0.9 1

1.6

+

INM

). See

mV mV mV mV mV mV

mA mA

mA mA mA

V

4

66011f

LTC6601-1

AC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T ﬂ oating, unless otherwise noted. (See Figure 2 for the AC test conﬁ guration.) VS is deﬁ ned as (V+ – V–). V

–

V

OUT

)/2. V

is deﬁ ned as (V

ICM

INP

+ V

INM

)/2. V

= 25°C. V+ = 3V, V– = 0V, V

A

is deﬁ ned as (V

OUTDIFF

OUT

+

– V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

GAIN Filter Gain, See Figure 2,

BIAS Pin Tied to V

+

,

AC Gain Measurements Relative to 1MHz

PHASE Filter Phase, See Figure 2,

BIAS Pin Tied to V

NOISE Wide Band Output Noise, 14.45MHz Cutoff,

BIAS Pin Tied to V

SNR BIAS Pin Tied to V

+

= ±0.25V, f

ΔV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

P-P P-P P-P P-P P-P P-P P-P

ΔVIN = ±0.25V, f V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

P-P P-P P-P P-P P-P P-P P-P

BW = 100MHz BW = 20MHz

BW = 100MHz

= DC (Note 14)

TEST

, f

= 1MHz

TEST

, f

= 2MHz

TEST

, f

= 5MHz

TEST

, f

= 10MHz

TEST

, f

= 14.45MHz

TEST

, f

= 20MHz

TEST

, f

= 50MHz

TEST

= DC

TEST

, f

= 1MHz

TEST

, f

= 2MHz

TEST

, f

= 5MHz

TEST

, f

= 10MHz

TEST

, f

= 14.45MHz

TEST

, f

= 20MHz

TEST

, f

= 50MHz

TEST

BW = 20MHz

DISTORTION V

IN

= 2V

, 10MHz, BIAS Pin Tied to V+ HD2, Single-Ended Input

P-P

HD3, Single-Ended Input HD2, Differential Input HD3, Differential Input

f

TC Cutoff Frequency Temperature Coefﬁ cient –120 ppm/°C

O

GAIN Filter Gain, See Figure 2,

BIAS Pin Floating (Remaining AC Measurements Relative to 1MHz)

PHASE Filter Phase, See Figure 2,

BIAS Pin Floating

NOISE Output Noise, See Figure 2,

BIAS Pin Floating

ΔV

= ±0.25V, f

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

ΔV

= ±0.25V, f

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

V

= 600mV

IN

BW = 100MHz BW = 20MHz

= DC (Note 14)

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

= DC

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

, f

P-P

TEST

= 1MHz = 2MHz = 5MHz = 10MHz = 14.45MHz = 20MHz = 50MHz

SNR BIAS Pin Floating BW = 100MHz

BW = 20MHz

Distortion V

IN

= 2V

, 10MHz, BIAS Pin Floating HD2, Single-Ended Input

P-P

HD3, Single-Ended Input HD2, Differential Input HD3, Differential Input

f

TC Cutoff Frequency Temperature Coefﬁ cient –120 ppm/°C

O

OUT

INCM

–

). V

= V

= mid-supply, V

OCM

is deﬁ ned as (V

INDIFF

l l l l l l l l

OUTCM

–0.25

–0.08 –0.01 –0.54 –2.75 –7.14

–23.70

–6.0 –12.0 –30.7 –67.6

–100.1 –127.3

–0.25

–0.08 –0.01 –0.54 –2.90 –7.43

–23.90

–6.0 –12.4 –31.8 –70.2

–103.5 –130.1

is tied to V+ or

BIAS

is deﬁ ned as (V

– V

INP

INM

±0.05

0

0.02

0.11 –0.34 –2.35 –6.24

–21.70

0

–5.4 –10.8 –28.2 –62.6 –94.1

–122.3 –169.3

71 54

80

82.3 –70

–103

–72

–103

±0.05

0

0.02

0.11

–0.34 –2.50 –6.53

–21.90

0

–5.5 –11.2 –29.3 –65.2 –97.5

–125.1 –173.6

78 58

79

81.7 –64

–71 –70 –72

).

0.25

0.12

0.23 –0.14 –1.95 –5.34

–19.70

–4.8

–9.6 –25.7 –57.6 –88.1

–117.3

0.25

0.12

0.23 –0.14 –2.10 –5.63

–19.90

–4.8 –10.0 –26.8 –60.2 –91.5

–120.1

OUT

µV µV

+

dB dB dB dB dB dB dB dB

Deg Deg Deg Deg Deg Deg Deg Deg

RMS RMS

dB dB

dBc dBc dBc dBc

dB dB dB dB dB dB dB dB

Deg Deg Deg Deg Deg Deg Deg Deg

RMS RMS

dB dB

dBc dBc dBc dBc

66011f

5

LTC6601-1

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All pins are protected by steering diodes to either supply. If any pin is driven beyond the part’s supply voltage, the excess input current (current in excess of what it takes to drive that pin to the supply rail) should be limited to less than 10mA.

Note 3: A heat sink may be required to keep the junction temperature below the Absolute Maximum Rating when the output is shorted indeﬁ nitely. Long-term application of output currents in excess of the Absolute Maximum Ratings may impair the life of the device.

Note 4: The LTC6601C/LTC6601I are guaranteed functional over the operating temperature range –40°C to 85°C.

Note 5: The LTC6601C is guaranteed to meet speciﬁ ed performance from 0°C to 70°C. The LTC6601C is designed, characterized, and expected to meet speciﬁ ed performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LTC6601I is guaranteed to meet speciﬁ ed performance from –40°C to 85°C.

Note 6: Output referred voltage offset is a function of the low frequency gain of the LTC6601. To determine output referred voltage offset, or output voltage offset drift, multiply this speciﬁ cation by the noise gain (1 + GAIN). See Applications Information for more details.

Note 7: Input bias current is deﬁ ned as the average of the currents ﬂ owing into the noninverting and inverting inputs of the internal ampliﬁ er and is calculated from measurements made at the pins of the IC. Input offset current is deﬁ ned as the difference of the currents ﬂ owing into the noninverting and inverting inputs of the internal ampliﬁ er and is calculated from measurements made at the pins of the IC.

Note 8: Input common mode range is tested using the test circuit of Figure 1 by measuring the differential DC gain with V with V Characteristics table, verifying the differential gain has not deviated from

at the input common mode range limits listed in the Electrical

ICM

= mid-supply, and

ICM

the mid-supply common mode input case by more than 1%, and the common mode offset (V common mode offset by more than ±10mV.

The voltage range for the output common mode range is tested using the test circuit of Figure 1 by measuring the differential DC gain with V mid-supply, and again with a voltage set on the V Characteristics table limits, checking the differential gain has not deviated from the mid-supply common mode input case by more than 1%, and that the common mode offset (V from the mid-supply case.

Note 9: Input CMRR is deﬁ ned as the ratio of the change in the input common mode voltage at the ampliﬁ er input to the change in differential input referred voltage offset. Output CMRR is deﬁ ned as the ratio of the change in the voltage at the V referred voltage offset.

Note 10: Power supply rejection (PSRR) is deﬁ ned as the ratio of the change in supply voltage to the change in differential input referred voltage offset. Common mode power supply rejection (PSRRCM) is deﬁ ned as the ratio of the change in supply voltage to the change in the common mode offset, V

OUTCM/VOCM

Note 11: Output swings are measured as differences between the output and the respective power supply rail.

Note 12: Extended operation with the output shorted may cause junction temperatures to exceed the 150°C limit and is not recommended.

Note 13: Floating the BIAS pin will reliably place the part into the halfpower mode. The pin does not have to be driven. Care should be taken, however, to prevent external leakage currents in or out of this pin from pulling the pin into an undesired state.

Note 14: The variable contact resistance of the high speed test equipment limits the accuracy of this test. These parameters only show a typical value, or conservative minimum and maximum value.

.

) has not deviated from the mid-supply

OCMOS

pin at the Electrical

OCM

) has not deviated by more than ±10mV

OCMOS

pin to the change in differential input

OCM

=

6

66011f

TYPICAL PERFORMANCE CHARACTERISTICS

LTC6601-1

Low Power Supply Current vs Temperature and Supply Voltage

18.0 V

= V

= MID-SUPPLY

OCM

5V

3V

TEMPERATURE (°C)

500 100

17.5

17.0

16.5

(mA)

CC

I

16.0

15.5

15.0

–50

INCM

BIAS PIN FLOATING

Supply Current vs Bias Pin Voltage and Temperature

50

V

= V

INCM

= 3V

V

S

40

30

(mA)

CC

I

20

10

0

BIAS PIN VOLTAGE WITH RESPECT TO V– (V)

= MID-SUPPLY

OCM

1.50.5 2.5

2.7V

66011 G01

–40°C 25°C 125°C

66011 G04

High Performance Supply Current vs Temperature and Supply Voltage

35

V

= V

INCM

BIAS PIN TIED TO V

34

33

(mA)

CC

I

32

31

12525–25 75

30

–50

= MID-SUPPLY

OCM

+

TEMPERATURE (°C)

500 100

5V

3V

2.7V

12525–25 75

66011 G02

Shutdown Supply Current vs Supply Voltage and Temperature

1

125°C

–40°C

0.1

(mA)

CC

I

0.01

V

INCM

0.001

312

0

SUPPLY VOLTAGE (V)

25°C

= V

= MID-SUPPLY

OCM

BIAS PIN TIED TO V

31

–

524

66011 G05

Shutdown Supply Current vs Temperature and Supply Voltage

0.8 V

= V

BIAS PIN TIED TO V

0.7

0.6

0.5

0.4

(mA)

CC

I

0.3

0.2

0.1

0

–50

INCM

= MID-SUPPLY

OCM

5V

3V

TEMPERATURE (°C)

–

2.7V

500 100

Low Power Mode Supply Current vs Supply Voltage and Temperature

100

125°C

10

1

(mA)

CC

I

0.1

0.01

0.001 0

–40°C

25°C

V

= V

INCM

SUPPLY VOLTAGE (V)

= MID-SUPPLY

OCM

BIAS PIN FLOATING

31

12525–25 75

66011 G03

524

66011 G06

High Performance Supply Current vs Supply Voltage and Temperature

100

125°C

10

–40°C

25°C

V

= V

INCM

SUPPLY VOLTAGE (V)

= MID-SUPPLY

OCM

BIAS PIN TIED TO V

31

(mA)

CC

I

0.1

0.01

0.001

1

0

+

524

66011 G07

High Performance Mode Differential VOS vs Temperature

1.00 VS = 3V

= V

V

INCM

0.75 BIAS PIN TIED TO V

5 REPRESENTATIVE UNITS

0.50

0.25

0.00

–0.25

INPUT REFERRED (mV)

OS

–0.50

V

–0.75

–1.00

–50

= MID-SUPPLY

OCM

+

25–25

TEMPERATURE (°C)

66011 G08

1.00

0.75

0.50

0.25

0.00

–0.25

INPUT REFERRED (mV)

OS

–0.50

V

–0.75

1250 50 75 100

–1.00

Low Power Mode Differential VOS vs Temperature

VS = 3V

= V

V

INCM

BIAS PIN FLOATING 5 REPRESENTATIVE UNITS

–50

= MID-SUPPLY

OCM

25–25

TEMPERATURE (°C)

1250 50 75 100

66011 G09

66011f

7

LTC6601-1

TYPICAL PERFORMANCE CHARACTERISTICS

High Performance Common Mode VOS vs Temperature

10

5

(mV)

0

OSCM

V

–5

VS = 3V

= V

V

INCM

BIAS PIN TIED TO V 5 REPRESENTATIVE UNITS

–10

–50

= MID-SUPPLY

OCM

+

25–25

TEMPERATURE (°C)

BIAS Pin Input Resistance vs Temperature

200

VS = 3V

= V

= MID-SUPPLY

OCM

175

V

INCM

66011 G10

Low Power Common Mode VOS vs Temperature

15

10

5

(mV)

0

OSCM

V

–5

VS = 3V

–10

V

= V

INCM

BIAS PIN FLOATING 5 REPRESENTATIVE UNITS

–15

1250 50 75 100

–50

= MID-SUPPLY

OCM

25–25

TEMPERATURE (°C)

1250 50 75 100

66011 G11

BIAS Pin Float Voltage vs Temperature

1.20

VS = 3V

= V

= MID-SUPPLY

OCM

1.15

V

INCM

Internal Ampliﬁ er Input Bias Current vs Temperature

–5

LOW POWER MODE

–10

–15

(µA)

BIAS

I

–20

–25

–30

–50

(BIAS PIN FLOATING)

HIGH PERFORMANCE MODE

(BIAS PIN TIED TO V

VS = 3V

= V

V

INCM

= MID-SUPPLY

OCM

TEMPERATURE (°C)

Filter Input Resistance vs Temperature

1.0050 VS = 3V

= V

= MID-SUPPLY

OCM

= 200 DIFFERENTIAL = 133.3 SINGLE-ENDED

1.0025

(/)

V

INCM

R

NOMINAL

R

NOMINAL

SEE FIGURE 1 FOR CONFIGURATION

+

)

25–25

1250 50 75 100

66011 G12

150

RESISTANCE ()

125

100

–50

Low Frequency Gain vs Temperature

1.010 VS = 3V

= V

V

INCM

5 REPRESENTATIVE UNITS

1.005

1.000

GAIN (V/V)

0.995

0.990

–50

25–25

TEMPERATURE (°C)

= MID-SUPPLY

OCM

25–25

TEMPERATURE (°C)

66011 G13

66011 G16

1.10

FLOAT VOLTAGE (V)

1.05

1.00

1250 50 75 100

–50

25–25

TEMPERATURE (°C)

66011 G14

High Performance Mode Frequency Response of 12 Possible Filter Conﬁ gurations

10

0

–10

GAIN (dB)

–20

VS = 3V

= V

V

INCM

BIAS PIN TIED TO V

1250 50 75 100

–30

0.1 10 1001

= MID-SUPPLY

OCM

+

FREQUENCY (MHz)

66011 G17

NOMINAL

1.0000

0.9975

RESISTANCE/R

SINGLE-ENDED

0.9950

1250 50 75 100

–50

25–25

TEMPERATURE (°C)

DIFFERENTIAL

1250 50 75 100

66011 G15

Low Power Mode Frequency Response of 12 Possible Filter Conﬁ gurations

10

0

–10

GAIN (dB)

–20

VS = 3V

= V

V

INCM

BIAS PIN FLOATING

–30

0.1 10 1001

= MID-SUPPLY

OCM

FREQUENCY (MHz)

66011 G18

8

66011f

TYPICAL PERFORMANCE CHARACTERISTICS

High Performance Mode Gain and Phase Repeatability of 10 Random Units

0.20 VS = 3V

= V

V

INCM

0.15 BIAS PIN TIED TO V

SEE FIGURE 2

0.10

MAX – AVERAGE

0.05

00

–0.05

MIN – AVERAGE

GAIN DEVIATION (dB)

–0.10

–0.15

–0.20

0.1 10 1001

= MID-SUPPLY

OCM

+

ϕ

– ϕ

MAX

AVERAGE

ϕ

– ϕ

MIN

AVERAGE

FREQUENCY (MHz)

66011 G19

4

3

PHASE DEVIATION (DEG)

2

1

–1

–2

–3

–4

Low Power Mode Gain and Phase Repeatability of 10 Random Units

0.20 VS = 3V

V

0.15 BIAS PIN FLOATING

SEE FIGURE 1

0.10

0.05

00

–0.05

GAIN DEVIATION (dB)

–0.10

–0.15

–0.20

0.1 10 1001

= V

INCM

MAX – AVERAGE

MIN – AVERAGE

= MID-SUPPLY

OCM

ϕ

MAX

ϕ

MIN

FREQUENCY (MHz)

– ϕ

AVERAGE

LTC6601-1

4

3

PHASE DEVIATION (DEG)

2

1

–1

–2

–3

–4

66011 G20

High Performance Mode Gain Error of 10 Random Units Normalized to 1MHz

3

VS = 3V

= V

OCM

= 25°C

+SPECIFICATION

= MID-SUPPLY

–SPECIFICATION

FREQUENCY (MHz)

V

ICM

BIAS PIN TIED TO V+

2

10 RANDOM UNITS PLOTTED T

A

1

0

–1

GAIN ERROR (dB)

–2

–3

1 10 100

Low Power Mode Phase Error of 10 Random Units

15

VS = 3V

= V

= 25°C

= MID-SUPPLY

OCM

–SPECIFICATION

FREQUENCY (MHz)

+SPECIFICATION

V

ICM

BIAS PIN FLOATING

10

10 RANDOM UNITS PLOTTED T

A

5

0

–5

PHASE ERROR (DEG)

–10

–15

1 10 100

66011 G21

66011 G24

Low Power Mode Gain Error of 10 Random Units Normalized to 1MHz

3

VS = 3V

= V

V

ICM

BIAS PIN FLOATING

2

10 RANDOM UNITS PLOTTED T

A

1

0

–1

GAIN ERROR (dB)

–2

–3

1 10 100

= MID-SUPPLY

OCM

= 25°C

+SPECIFICATION

–SPECIFICATION

FREQUENCY (MHz)

Turn On and Turn Off Transient Response

5

4

3

2

1

(V)

0

OUTDIFF

–1

V

–2

–3

–4

–5

VS = 5V

V

0

OUTDIFF

BIAS PIN

2

TIME (µs)

66011 G22

66011 G25

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

61345

High Performance Mode Phase Error of 10 Random Units

15

VS = 3V

= V

OCM

= 25°C

–SPECIFICATION

= MID-SUPPLY

FREQUENCY (MHz)

V

ICM

BIAS PIN TIED TO V+

10

10 RANDOM UNITS PLOTTED T

A

5

0

–5

PHASE ERROR (DEG)

–10

–15

1 10 100

Pulse Response

2

VS = 3V

1

V

BIAS

(V)

PIN (V)

0

OUTDIFF

V

–1

–2

0

2

TIME (µs)

+SPECIFICATION

66011 G23

81 34567

66011 G26

66011f

9

LTC6601-1

TYPICAL PERFORMANCE CHARACTERISTICS

Differential Output Noise

100

VS = 3V FIGURE 2

INTEGRATED NOISE, BIAS PIN FLOATING

INTEGRATED NOISE, BIAS TIED TO V

10

SPECTRAL DENSITY, BIAS PIN FLOATING

NOISE SPECTRAL DENSITY (nV/√Hz)

1

0.001 0.01 10 10010.1

+

FREQUENCY (MHz)

% Change of fO vs Temperature

0.5

0

(%)

–0.5

O

–1.0

CHANGE OF f

–1.5

–2.0

–50

25–25

TEMPERATURE (°C)

SPECTRAL DENSITY, BIAS TIED TO V

+

66011 G27

66011 G30

Distortion vs Frequency

100

10

1

INTEGRATED NOISE (µV

–100

HARMONIC (dBc)

RMS

–110

)

–120

–130

–60

VS = 5V

= 2V

V

IN

–70

= V

V

ICM

BIAS PIN TIED TO V+ FIGURE 2

–80

–90

0.1 10 1001

INPUT

P-P

= MID-SUPPLY

OCM

FREQUENCY (MHz)

HD2

HD3

SINGLE ENDED INPUT DIFFERENTIAL INPUT

66011 G28

Passband Gain and Phase vs Temperature

0.5

0

–0.5

–1.0

–1.5

GAIN (dB)

VS = 3V

–2.0

–2.5

1250 50 75 100

–3.0

= V

V

ICM

OCM

BIAS PIN TIED TO V+ TEMPERATURES PLOTTED: –45°C, –10°C, 25°C, 70°C, 95°C, 125°C

110

PHASE

= MID-SUPPLY

FREQUENCY (MHz)

GAIN

0

–15

–30

–45

–60

–75

–90

–105

66011 G31

Distortion vs Frequency

–60

VS = 5V

= 2V

IN ICM

= V

P-P

OCM

INPUT

SINGLE ENDED INPUT DIFFERENTIAL INPUT

FREQUENCY (MHz)

V

–70

V = MID-SUPPLY

–80

BIAS PIN FLOATING FIGURE 2

–90

–100

HARMONIC (dBc)

–110

–120

–130

0.1 10 1001

Gain Error Relative to 1MHz vs Temperature

3

VS = 3V

= V

V

ICM

BIAS PIN TIED TO V+

2

TEMPERATURES PLOTTED:

PHASE (DEG)

–45°C, –10°C, 25°C,

1

70°C, 95°C, 125°C

0

–1

GAIN ERROR (dB)

–2

–3

1 10 100

= MID-SUPPLY

OCM

–SPECIFICATION

FREQUENCY (MHz)

66011 G29

+SPECIFICATION

66011 G32

Phase Error vs Temperature

15

VS = 3V

= V

V

ICM

BIAS PIN TIED TO V+

10

TEMPERATURES PLOTTED: –45°C, –10°C, 25°C,

5

70°C, 95°C, 125°C

0

–5

PHASE ERROR (dB)

–10

–15

1 10 100

= MID-SUPPLY

OCM

–SPECIFICATION

FREQUENCY (MHz)

10

+SPECIFICATION

66011 G33

Normalized 100 Resistor Trim Normalized 125 Resistor Trim

900

800

700

600

500

400

FREQUENCY

300

200

100

0

0.993 NORMALIZED RESISTANCE

AVERAGE = 100Ω STD. DEV = 0.19Ω

1.0091.0010.997

1.005

66011 G34

1000

AVERAGE = 125Ω

900

STD. DEV = 0.22Ω

800

700

600

500

400

FREQUENCY

300

200

100

0

0.99 NORMALIZED RESISTANCE

1.0061.002

1.010.9980.994

66011 G35

66011f

TYPICAL PERFORMANCE CHARACTERISTICS

LTC6601-1

Normalized 200 Resistor Trim

1000

AVERAGE = 200Ω

900

STD. DEV = 0.37Ω

800

700

600

500

400

FREQUENCY

300

200

100

0

0.99 NORMALIZED RESISTANCE

Normalized 21.1pF Capacitor Trim

1200

AVERAGE = 21.1pF STD. DEV = 0.07pF

1000

800

600

FREQUENCY

400

200

0

0.984 NORMALIZED CAPACITANCE

Normalized Input 400 Resistor Trim

900

AVERAGE = 400.01Ω STD. DEV = 1.0Ω

800

700

600

500

400

FREQUENCY

300

200

100

0

1.010.9980.994

1.0061.002

66011 G36

0.99 NORMALIZED RESISTANCE

1.010.9980.994

1.0061.002

66011 G37

Normalized 33.3pF Capacitor Trim

1000

AVERAGE = 33.3pF

900

STD. DEV = 0.09pF

800

700

600

500

400

FREQUENCY

300

200

100

1.0091.003

1.0150.9970.990

66011 G39

0

0.988 NORMALIZED CAPACITANCE

1.0160.9990.993

1.0101.005

66011 G40

Normalized Feedback 400 Resistor Trim

1000

AVERAGE = 400.01Ω

900

STD. DEV = 0.87Ω

800

700

600

500

400

FREQUENCY

300

200

100

0

0.99 NORMALIZED RESISTANCE

Normalized 48.2pF Capacitor Trim

1200

AVERAGE = 48.2pF STD. DEV = 0.08pF

1000

800

600

FREQUENCY

400

200

0

0.9950.992 NORMALIZED CAPACITANCE

1.010.9980.994

1.0061.002

66011 G38

1.0101.0010.998

1.0071.004

66011 G41

Normalized 81.5pF Capacitor Trim

1000

AVERAGE = 81.5pF

900

STD. DEV = 0.1pF

800

700

600

500

400

FREQUENCY

300

200

100

0

0.9960.993

NORMALIZED CAPACITANCE

1.0071.004

66011 G42

Normalized 10.55pF Capacitor Trim

400

AVERAGE = 10.55pF STD. DEV = 0.03pF

350

300

250

200

FREQUENCY

150

100

50

1.0101.0020.999

0

0.9910.987

NORMALIZED CAPACITANCE

1.0091.005

1.0141.0000.996

66011 G43

Normalized 16.1pF Capacitor Trim

350

AVERAGE = 16.1pF STD. DEV = 0.05pF

300

250

200

150

FREQUENCY

100

50

0

NORMALIZED CAPACITANCE

0.9950.9920.988

1.0101.006

1.0141.0030.999

66011 G44

66011f

11

LTC6601-1

PIN FUNCTIONS

(Refer to the Block Diagram)

IN1+, IN2+, IN4+ (Pins 2, 1, 20): Input to a trimmed 100Ω,

200Ω, 400Ω resistor which feeds a noninverting summing

–

node. Can accept an input signal, be ﬂ oated or tied to OUT

. For best performance, stray capacitance should be kept as low as possible by keeping printed circuit connections as short and direct as possible. If necessary, strip back the surrounding ground plane away from these pins.

BIAS (Pin 3): Input to a three-state comparator whose three states allow the user to tailor ampliﬁ er power. The pin impedance appears as a 150k resistor whose default

–

open-circuit potential is 1.15V with respect to the V supply. If BIAS is driven to within 0.4V of the V

power

–

supply, the ampliﬁ er is placed into a low power shutdown, consuming typically 350µA. When BIAS is ﬂ oated, the ampliﬁ er operates in its low power active state. Forcing the pin 2.3V

–

above V

places the part into the high performance active

state. See Applications Information for more detail.

–

, IN2–, IN4– (Pins 4, 5, 6): Input to a trimmed 100Ω,

IN1

200Ω, 400Ω resistor which feeds an inverting summing node. Can accept an input signal, be ﬂ oated or tied to

+

. For best performance, it is highly recommended

OUT that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins.

C1, C2 (Pins 7, 8): Input to a trimmed 16.1pF, 33.3pF capacitor which feeds a noninverting summing node.

–

Typically, either ﬂ oat or tie to OUT pins is tied to a low impedance source other than OUT

. If either of these

–

, a resistance of at least 25Ω should be placed in series. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins.

C3, C4 (Pins 9, 10): Input to a trimmed 10.55pF, 21.1pF capacitor which feeds the ampliﬁ er inverting summing

+

node. Typically, either ﬂ oat or tie to OUT

. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins.

+

, OUT– (Pins 11, 15): Output Pins. Besides driving

OUT

the internal feedback network, each pin can drive an additional 50Ω to ground with typical short-circuit current limiting of ±65mA. Capacitive loading of these pins should be minimized by resistively decoupling the outputs from the load with at least 25Ω.

(Pin 12): Output Common Mode Reference Voltage.

V

OCM

The voltage on V

sets the output common mode voltage

OCM

level (which is deﬁ ned as the average of the voltages on the OUT

and OUT– pins). The V

pin is the midpoint

OCM

+

of an internal resistive voltage divider between the supplies, developing a (default) mid-supply voltage potential to maximize output signal swing. The V

pin can be

OCM

overdriven by an external voltage reference capable of driving the input impedance presented by the V The V

pin has an input resistance of approximately 18k

OCM

pin.

to a mid-supply potential. It should be bypassed with a high quality ceramic bypass capacitor (for instance of X7R dielectric) of at least 0.01F, (unless using symmetrical split supplies, then connect directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the IC.

12

66011f

LTC6601-1

PIN FUNCTIONS

V+, V– (Pins 14, 13): Power Supply Pins. It is critical that close attention be paid to supply bypassing. For single supply applications (Pin 13 grounded), it is recommended that a high quality 0.1F surface mount ceramic bypass capacitor (X7R dielectric for instance) be placed between Pins 14 and 13, with direct short connections. Pin 13 should be tied directly to a low impedance ground plane with minimal routing. For dual (split) power supplies, it is recommended that at least two additional high quality

0.1F ceramic capacitors are used to bypass V

–

to ground, again with minimal routing. For driving

and V large loads (< 200Ω), additional bypass capacitance may be added for optimal performance. Keep in mind that small geometry (e.g., 0603) surface mount ceramic capacitors have a much lower ESL than do leaded capacitors, and perform best in high speed applications.

C7, C8 (Pins 17, 16): Input to a trimmed 10.55pF, 21.1pF capacitor which feeds the ampliﬁ er noninverting summing node. Typically, either ﬂ oat or tie to OUT performance, stray capacitance should be kept as low as possible by keeping printed circuit connections as short and direct as possible.If necessary, strip back the surrounding ground plane away from these pins.

(Refer to the Block Diagram)

+

to ground

–

. For best

C5, C6 (Pins 19, 18): Input to a trimmed 16.1pF, 33.3pF capacitor which feeds an inverting summing node. Typically, either ﬂ oat or tie to OUT tied to a low impedance source other than OUT sistance of at least 25Ω should be placed in series. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding reference plane away from these pins.

Exposed Pad (Pin 21): Always tie the underlying Exposed Pad to V

the pad to ground. Tie it to V

–

(Pin 13). If split supplies are used, do not tie

+

. If either of these pins are

–

.

+

, a re-

66011f

13

Linear LTC6601-1 Schematic [ru]