Linear 1351A, LTC4269IDKD-2 Quick Start Manual

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1351A

DESCRIPTION

SINGLE OUTPUT, HIGH POWER, HIGH EFFICIENCY POE

LTC4269IDKD-2

Demonstration circuit 1351A is a high-power supply
featuring the LTC®4269IDKD-2. This board acts as

an IEEE 802.3at compliant, high power Power-over­Ethernet (PoE), Powered Device (PD) and connects
at the RJ45 to a compatible high power Power
Sourcing Equipment (PSE) device, such as the
DC1366A.

The LTC4269IDKD-2 provides IEEE802.3at standard
(PoE+) PD interfacing and power supply control.
When the PD is fully powered, the PD interface
switches power over from the PSE to the switcher
through an internal, low resistance, high power

trols a high-power, small-sized power supply that
utilizes a highly-efficient isolated forward topology
with synchronous rectification. The DC1351A sup­plies a 5V output at up to 5A.

DC1351A also demonstrates the use of an auxiliary
48V wall adapter. When present, the auxiliary supply
becomes the dominant supply over PoE to provide
power.

Design files for this circuit board are available.
Call the LTC factory.

, LTC and LT are registered trademarks of Linear Technology Corporation.

MOSFET. The highly integrated LTC4269IDKD-2 con-

Table 1. Performance Summary (TA = 25°C)

PARAMETER CONDITION VALUE

Port Voltage (V

Auxiliary Voltage (V

Output Voltage (V

Maximum Output Current V

Typical Output Voltage Ripple VIN = 50V, I

Output Regulation Over Entire Input Voltage and Output Current Range < ±0.1% (typ)

) At Ethernet port 37V – 57V

PORT

) From Aux- to Aux+ terminals 44V – 57V

AUX

) Initial Set-point V

OUT

= 37V to 57V, I

PORT

= 42V 4.6A (min)

PORT

= 4.6A 40mV

OUT

= 0A to 5A 5.05V ± 1%

OUT

P–P

(typ)

Load Transient Response

Switching Frequency 225kHz (typ)

Efficiency V

OPERATING PRINCIPLES

A compatible high power PSE board, such as the
DC1366A, is connected to the DC1351A at the RJ45
connector J2 (see the schematic). As required by
IEEE802.3at, a diode bridge is used across the data
pairs and signal pairs. Schottky diodes (D5-8, D12-

15) are used at the input to improve efficiency over

Peak to Peak Deviation with Load Step of 2.5A to 5A ±120mV (< ±2.5%) (typ)

Settling Time (within 1% of V

PORT

= 42V, I

= 5A, not incl. diode bridge 92.5% (typ)

OUT

) 150us (typ)

OUT

standard diode bridges. The LTC4269IDKD-2 pro­vides an IEEE802.3at standard PoE 25k signature re­sistance and is set for a power class 4. When the PD
is powered and voltage is above the PoE ‘‘On Volt­age’’, the LTC4269IDKD-2 switches the port voltage
over to the power supply controller through its inter-

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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1351A

SINGLE OUTPUT, HIGH POWER, HIGH EFFICIENCY POE

nal MOSFET which lies between the V

PORTN

and V

NEG

pins. This voltage charges C11 through a trickle
charge resistor, R3 to power the bias pin, Vin, of the
power supply controller. Once the bias power gets to
its V

threshold, the IC begins a controlled soft-

IN(ON)

start of the output. As this voltage rises, bias power
is taken over by T2, D1/2, and L1.

When the soft-start period is over, the output voltage
is regulated by the combination of the optoisolator
(U2) and the reference/error amplifier (D21) pulling

QUICK START PROCEDURE

Demonstration circuit 1351A is easy to set up to
evaluate the performance of the LTC4269IDKD-2 in a
PoE+ PD application. Refer to Figure 1 for proper
equipment setup and follow the procedure below:

NOTE:

When measuring the input or output voltage
ripple, care must be taken to avoid a long ground lead
on the oscilloscope probe. Measure the output (or
input) voltage ripple by touching the probe tip and
probe ground directly across the +VOUT and –VOUT
(or VPORT_P and VPORT_N) terminals. See Figure 2
for proper scope probe technique.

1.

Place test equipment (voltmeter, ammeter, and

electronic load) across output.

2.

Input supplies:

down on the COMP pin. The OUT and SOUT pins
which drive Q3 and Q2, respectively, are Pulse Width
Modulated (PWM) in order to keep the output voltage
constant. The synchronous rectifiers (Q4 and Q5) on
the secondary side are self-driven by T2. This re­duces the gate drive part’s count and complexity
since no external driver ICs or delay circuits are
needed to achieve synchronous rectification. The high
efficiency that is expected with synchronous rectifica­tion is maintained.

a.

Connect a PoE+ capable PSE with a CAT-5 cable

to the RJ45 connector, J2. See Figure 1.

b.

Or, connect a 37V to 57V capable power supply
(‘‘Power Supply’’ in Figure 1) across VPORT_P and
VPORT_N.

c.

If evaluating the auxiliary power supply (‘‘Auxil­iary Supply’’ in Figure 1) capability, connect a 44V
to 57V capable power supply across AUX+ to AUX-.

3.

Check for the proper output voltage of 5V.

4.

Once the proper output voltage is confirmed, adjust
the load within the operating range and observe the
output voltage regulation, ripple voltage, efficiency
and other parameters.

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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1351A

SINGLE OUTPUT, HIGH POWER, HIGH EFFICIENCY POE

Figure 1. Proper Measurement Equipment Setup

Figure 2. Measuring Input or Output Ripple

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