Linear LTC3875 Datasheet

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Page 1

Dual, 2-Phase, Synchronous

3875 TA01b

Controller with Low Value DCR Sensing

and Temperature Compensation

FEATURES DESCRIPTION

LTC3875

Low Value DCR Current Sensing

Programmable DCR Temperature Compensation

±0.5% 0.6V Output Voltage Accuracy

Dual True Remote Sensing Differential Amplifiers

Optional Fast Transient Operation

Phase-Lockable Fixed Frequency 250kHz to 720kHz

Dual, 180° Phased Controllers Reduce Required

Input Capacitance and Power Supply Induced Noise

Dual N-Channel MOSFET Synchronous Drive

Wide VIN Range: 4.5V to 38V Operation

Output Voltage Range with Low DCR: 0.6V to 3.5V,

without Low DCR: 0.6V to 5V

Adjustable Soft-Start Current Ramping or Tracking

Foldback Output Current Limiting

Clock Input and Output for Up to 12-Phase Operation

Short-Circuit Soft Recovery

Output Overvoltage Protection

Power Good Output Voltage Monitor

40-Lead QFN Packages

APPLICATIONS

Servers and Instruments

Telecom Systems

DC Power Distribution Systems

The LT C®3875 is a dual output current mode synchronous step-down DC/DC controller that drives all N-channel synchronous power MOSFET stages. It employs a unique architecture which enhances the signal-to-noise ratio of the current sense signal, allowing the use of very low DC resistance power inductors to maximize the efficiency in high current applications. This feature also reduces the switching jitter commonly found in low DCR applications.

The LTC3875 features two high speed remote sense differential amplifiers, programmable current sense limits from 10mV to 30mV and DCR temperature compensation to limit the maximum output current precisely over temperature.

A unique thermal balancing function adjusts per phase current in order to minimize the

thermal stress for multichip single output applications. The LTC3875 also features a precise 0.6V reference with guaranteed accuracy of ±0.5% that provides an accurate output voltage from 0.6V to 3.5V. A 4.5V to 38V input voltage range allows it to support a wide variety of bus voltages. The LTC3875 is available in a low profile 40-lead 6mm × 6mm (0.5mm pitch) and 40-lead 5mm × 5mm (0.4mm pitch) QFN packages.

L, LT, LT C , LT M, Linear Technology, the Linear logo OPTI-LOOP, Burst Mode and PolyPhase are registered trademarks and No R All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258.

is a trademark of Linear Technology Corporation.

SENSE

TYPICAL APPLICATION

High Efficiency Dual Phase 1.2V/60A Step-Down Converter

INTV

4.7µF

(OPTIONAL) (OPTIONAL)

THERMAL

SENSOR

0.3µH

(0.32mΩ DCR)

OUT

470µF

2.5V ×2 SP

INTV

RUN1,2 ILIM ENTMPB TG1

BOOST1 BOOST2

SW1 EXTV BG1 TAVG TRSET1 SNSA1

SNS1 SNSD1

TCOMP1 V

V I

TH1

OSNS1 OSNS1

LTC3875

–

+ –

TK/SS2TK/SS1

PHASMD

CLKOUT

PGOOD

IFAST

MODE/PLLIN

TG2

SW2

BG2

PGND TRSET2 SNSA2

SNS2

SNSD2

TCOMP2

FREQ

OSNS2

0.1µF

+ – +

+ –

TH2

122k

1500pF

15k

For more information www.linear.com/LTC3875

V 6V TO 14V

22µF 16V ×4

THERMAL

SENSOR

0.3µH

(0.32mΩ DCR)

20k

Efficiency and Power Loss

vs Load Current

50 60

POWER LOSS (W)

3875fb

100

12V

1.8V

~400kHz CCM

EFFICIENCY (%)

0.32mΩ

OUT

1.2V 60A

470µF

2.5V ×2 SP

3875 TA01a

20 30 40

LOAD CURRENT (A)

1.5mΩ

0.32mΩ PLOSS

1.5mΩ PLOSS

Page 2

LTC3875

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Input Supply Voltage (VIN) ......................... 40V to –0.3V

Topside Driver Voltages

(BOOST1, BOOST2).................................... 46V to –0.3V

Switch Voltage (SW1, SW2) INTV

, RUN(s), PGOOD, EXTVCC

.......................... 40V to –5V

(BOOST-SW1), (BOOST2-SW2).................... 6V to –0.3V

SNSA SNS

(s), SNSD+(s),

–

(s) Voltages .................................. INTVCC to –0.3V

PIN CONFIGURATION

TOP VIEW

TK/SS1

OSNS1

OSNS2

TK/SS2

SNSA2

SNS2

SNSA1+SNS1–SNSD1+TCOMP1/ITEMP1

3940 38 37 36 35 34 33 32 31

–

TH1

TH2

–

12 13 14 15

11 20

SNSD2

SGND/PGND

TAVG

TRSET2

TRSET1

ILIM

RUN1

16 17 18 19

FREQ

RUN2

IFAST

MODE/PLLIN

PHASMD

CLKOUT

SW2

PGOOD

ENTMPB

SW1

TG1

BOOST1

BG1

INTV

EXTV

BG2

BOOST2

TG2

MODE/PLLIN, ILIM, FREQ, IFAST, ENTMPB

OSNS(s)

TH1

, V

OSNS(s)

, I

, PHASMD, TRSET1, TRSET2,

TH2

TCOMP1, TCOMP2, TAVG Voltages INTV

Peak Output Current ................................100mA

–

Voltages ...............INTVCC to –0.3V

.......INTVCC to –0.3V

Operating Junction Temperature Range (Notes 2, 3) Storage Temperature Range

............................................ –40°C to 125°C

.................. –65°C to 125°C

TOP VIEW

TK/SS1

OSNS1

OSNS2

TK/SS2

SNSA2

SNS2

SNSA1+SNS1–SNSD1+TCOMP1/ITEMP1

3940 38 37 36 35 34 33 32 31

–

TH1

TH2

–

12 13 14 15

11 20

SNSD2

SGND/PGND

TAVG

TRSET2

TRSET1

ILIM

RUN1

16 17 18 19

FREQ

RUN2

IFAST

MODE/PLLIN

PHASMD

CLKOUT

SW2

PGOOD

ENTMPB

SW1

TG1

BOOST1

BG1

INTV

EXTV

BG2

BOOST2

TG2

TCOMP2/ITEMP2

40-LEAD (6mm × 6mm) PLASTIC QFN

EXPOSED PAD (PIN 41) IS SGND/PGND, MUST BE SOLDERED TO PCB

JMAX

UJ PACKAGE

= 125°C, θJA = 33°C/W, θJC = 2.0°C/W

For more information www.linear.com/LTC3875

TCOMP2/ITEMP2

EXPOSED PAD (PIN 41) IS SGND/PGND, MUST BE SOLDERED TO PCB

40-LEAD (5mm × 5mm) PLASTIC QFN

JMAX

UH PACKAGE

= 125°C, θJA = 44°C/W, θJC = 7.3°C/W

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LTC3875

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3875EUH#PBF LTC3875EUH#TRPBF 3875 40-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C LTC3875IUH#PBF LTC3875IUH#TRPBF 3875 40-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C

LTC3875EUJ#PBF LTC3875EUJ#TRPBF LTC3875

LTC3875IUJ#PBF LTC3875IUJ#TRPBF LTC3875

40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN

Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

The l denotes the specifications which apply over the specified operating

ELECTRICAL CHARACTERISTICS

junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, V

= 5V unless otherwise noted.

RUN1,2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops

OUT

OSNS1,2

REFLNREG

LOADREG

m1,2

Input Voltage Range 4.5 38 V Output Voltage Range SNSD+ Pin to V

Regulated V

Feedback Voltage

OUT

Including Diffamp Error

SNSD

Pin to GND

(Note 4); I (Note 4); I

OUT

Voltage = 1.2V, –40°C to 85°C

TH1,2

Voltage = 1.2V,–40°C to 125°C

TH1,2

Feedback Current (Note 4) –30 –100 nA Reference Voltage Line Regulation VIN = 4.5V to 38V (Note 4) 0.002 0.005 %/V Output Voltage Load Regulation (Note 4)

Measured in Servo Loop; ∆I Measured in Servo Loop; ∆I

Transconductance Amplifier g

= 1.2V; Sink/Source 5µA (Note 4) 2.2 mmho

TH1,2

Voltage = 1.2V to 0.7V

Voltage = 1.2V to 1.6V

l l

Thermal Functions

TCOMP1,2

SHDN

HYS

Thermal Sensor Current 29 30 31 µA Internal Thermal Shutdown (Note 8) 160 °C Internal TS Hysteresis (Note 8) 10 °C

Fast Transient Functions

FAST

Fast Transient Program Current

Current Sensing Functions

SENSE(AC)

SENSE(DC)

VT(SNS)

AC Sense Pins Bias Current Each Channel; V DC Sense Pins Bias Current Each Channel; V Total Sense Gain to Current Comp 5 V/V

= 3.3V ±0.5 ±2 µA

SNSA+(S)

SNSD+(S)

= 3.3V

–40°C to 125°C

to 125°C

–40°C

0.6

0.597

0.5965

0.600

0.01

–0.01

3.5 5

0.603

0.6045

0.1

–0.1

9 10 11 µA

±30 ±50 nA

V V

% %

For more information www.linear.com/LTC3875

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LTC3875

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SENSE(MAX)(DC)

SENSE(MAX)(NODE)

MISMATCH

Maximum Current Sense Threshold with SNSD

Pin to V

Pin to GND

OUT

Channel-to-Channel Current Mismatch

Input DC Supply Current Normal Mode

Shutdown UVLO Undervoltage Lockout V UVLO Hyst UVLO Hysteresis 0.5 V V

OVL

TK/SS1,2

RUN1,2

RUN1,2HYS

Feedback Overvoltage Lockout Measured at V

Soft-Start Charge Current V

RUN Pin On Threshold V

RUN Pin On Hysteresis 80 mV

Driver Functions

TG1,2 t TG1,2 t

BG1,2 t BG1,2 t

TG/BG t

r f

TG Transition Time

Rise Time

Fall Time

BG Transition Time

Rise Time

Fall Time

Top Gate Off to Bottom Gate On

Delay Synchronous Switch-On

Delay Time BG/TG t

Bottom Gate Off to Top Gate On

Delay Synchronous Switch-On

Delay Time t

ON(MIN)

Minimum On-Time (Note 7) 90 ns

0°C to 85°C V V

= 1.2V, ILIM = 0V

SNS–(s)

= 1.2V, ILIM = 1/4 INTV

SNS–(s)

= 1.2V, ILIM = 1/2 INTV

SNS–(s)

= 1.2V, ILIM = 3/4 INTV

SNS–(s)

= 1.2V, ILIM = INTV

SNS–(s)

CC CC CC

–40°C to 125°C V V

V V V V V

= 1.2V, ILIM = 0V

SNS–(s)

= 1.2V, ILIM = 1/4 INTV

SNS–(s)

= 1.2V, ILIM = 1/2 INTV

SNS–(s)

= 1.2V, ILIM = 3/4 INTV

SNS–(s)

= 1.2V, ILIM = INTV

SNS–(s)

= 1.2V, ILIM = 0V

SNS–(s)

= 1.2V, ILIM = 1/4 INTV

SNS–(s)

= 1.2V, ILIM = 1/2 INTV

SNS–(s)

= 1.2V, ILIM = 3/4 INTV

SNS–(s)

= 1.2V, ILIM = INTV

SNS–(s)

CC CC CC

ILIM = Float, ENTMPB = Float (Thermal Balance Disabled)

(Note 5) V

= 15V (without EXTVCC Enabled)

= 0V

RUN1,2

Ramping Down 3.5 3.7 4.0 V

INTVCC

OSNS1,2

= 0V

TK/SS1,2

, V

RUN2

Rising

RUN1

(Note 6) C

= 3300pF

LOAD

= 3300pF

LOAD

(Note 6) C

= 3300pF

LOAD

= 3300pF

LOAD

= 3300pF Each Driver 30 ns

LOAD

= 3300pF Each Driver 30 ns

LOAD

= 5V unless otherwise noted.

RUN1,2

9 14 19

23.5

28.5

8.5

13.5

17.5

26.5

117.5

142.5

0.625 0.645 0.665 V

100 125 150

1.0 1.25 1.5 µA

1.1 1.22 1.35 V

10 15 20 25 30

50 75

25 25

11 16 21

26.5

31.5

11.5

16.5

22.5 28

33.5 55

105

132.5

157.5 5 %

10 60

mV mV mV mV mV

µA

ns ns

3875fb

For more information www.linear.com/LTC3875

Page 5

LTC3875

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Linear Regulator

INTV

INTVCC

INT INTVCC Load Regulation ICC = 0mA to 20mA 0.5 2.0 %

LDO

EXTVCC

EXT EXTVCC Voltage Drop ICC = 20mA, V

LDO

LDOHYS

Oscillator and Phase-Locked Loop

NOM

LOW

HIGH

MODE/PLLIN

FREQ

CLKOUT Phase (Relative to Controller 1) PHASMD = GND

CLK High Clock Output High Voltage V CLK Low Clock Output Low Voltage 0.2 V V

PGL

PGOOD

On-Chip Driver

TG R

DOWN

BG R

DOWN

Internal VCC Voltage 6V < VIN < 38V 5.3 5.5 5.7 V

EXTVCC Switchover Voltage EXTVCC Ramping Positive

= 5.5V 50 100 mV

EXTVCC

EXTVCC Hysteresis 200 mV

Nominal Frequency V Lowest Frequency V Highest Frequency V

= 1.2V 450 500 550 kHz

FREQ

= 0V 220 250 270 kHz

FREQ

≥ 2.4V 650 720 790 kHz

FREQ

MODE/PLLIN Input Resistance 250 kΩ Frequency Setting Current 9.5 10 10.5 µA

PHASMD = FLOAT

PGOOD Voltage Low I PGOOD Leakage Current V PGOOD Trip Level, Either Controller V

TG Pull-Up R TG Pull-Down R BG Pull-Up R BG Pull-Down R

DS(ON)

PHASMD = INTV

= 5.5V 4.5 5.5 V

INTVCC

= 2mA 0.1 0.3 V

PGOOD

= 5.5V ±2 µA

PGOOD

with Respect to Set Output Voltage

OSNS

TG High 2.6 Ω TG Low 1.5 Ω BG High 2.4 Ω BG Low 1.1 Ω

Ramping Negative

Ramping Positive

= 5V unless otherwise noted.

RUN1,2

4.5 4.7 V

60 90

120

–7.5

7.5

Deg Deg Deg

% %

Stresses beyond those listed under Absolute Maximum Ratings

Note 1:

may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: The LTC3875 is tested under pulsed load conditions such that T

≈ TA. The LTC3875E is guaranteed to meet specifications from

0°C to 85°C junction temperature. Specifications over the –40°C to 125°

C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3875I is guaranteed over the full –40° to 125° operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors.

For more information www.linear.com/LTC3875

Note 3: T dissipation, P

is calculated from the ambient temperature, TA, and power

, according to the formula:

TJ = TA + (PD • θJA°C/W) where θ

= 44°C/W for the 5mm × 5mm QFN and θJA = 33°C/W for

the6mm×6mmQFN. Note 4: The LTC3875 is tested in a feedback loop that servos V

specified voltage and measures the resultant V

OSNS1,2

ITH1,2

to a

Note 5: Dynamic supply current is higher due to the gate charge being delivered

at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels.

Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ≥40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section). Note 8: Guaranteed by design.

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LTC3875

3875 G01

3875 G02

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Output Current and Mode (Figure 16 Application Circuit)

100

Burst Mode

OPERATION

EFFICIENCY (%)

0.01 1 10 100

0.1 LOAD CURRENT (A)

CCM

PULSE-SKIPPING

VIN = 12V V

OUT

= 1.5V

Efficiency vs Output Current and Mode (Figure 16 Application Circuit)

100

Burst Mode

OPERATION

EFFICIENCY (%)

0.01 1 10 100

0.1

CCM

PULSESKIPPING

LOAD CURRENT (A)

VIN = 12V

= 1V

OUT

LOAD

40A/DIV

5A TO 30A

L1, IL2

10A/DIV

OUT

100mV/DIV

AC-COUPLED

Load Step (Figure 16 Application Circuit) (Burst Mode Operation)

VIN = 12V

= 1.5V

OUT

10µs/DIV

3875 G03

Load Step (Figure 16 Application Circuit) (Forced Continuous Mode)

LOAD

40A/DIV

5A TO 30A

L1, IL2

10A/DIV

OUT

100mV/DIV

AC-COUPLED

VIN = 12V V

OUT

Coincident Tracking

RUN

2V/DIV

OUT1

OUT2

1V/DIV

VIN = 12V

= 1.5V, R

OUT1

= 1V, R

OUT2

= 1.5V

LOAD

2.5ms/DIV = 12Ω, CCM

LOAD

= 6Ω, CCM

10µs/DIV

OUT1

OUT2

3875 G07

3875 G04

40A/DIV

5A TO 30A

10A/DIV

100mV/DIV

AC-COUPLED

TK/SS1 TK/SS2

2V/DIV

OUT1

OUT2

500mV/DIV

Load Step (Figure 16 Application Circuit) (Pulse-Skipping Mode)

LOAD

L1, IL2

OUT

VIN = 12V

= 1.5V

OUT

10µs/DIV

Tracking Up and Down with External Ramp

OUT2

OUT1

VIN = 12V

= 1V, 1Ω LOAD

OUT1

= 1.5V, 1.5Ω LOAD

OUT2

10ms/DIV

3875 G08

500mV/DIV

3875 G05

SUPPLY CURRENT (mA)

Prebiased Output at 1V

OUT

1V/DIV

OSNS

TK/SS

VIN = 12V

= 1.5V

OUT

CCM: NO LOAD

2.5ms/DIV

Quiescent Current vs Temperature without EXTV

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0 –30 10

–50

–10

TEMPERATURE (°C)

50 130

3875 G06

110

3875 G09

3875fb

For more information www.linear.com/LTC3875

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS

LTC3875

Line Regulation

INTV

VOLTAGE (V)

INTV

10 20

5 15

INPUT VOLTAGE (V)

Maximum Current Sense Threshold vs Feedback Voltage (Current Foldback)

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0.1 0.2 FEEDBACK VOLTAGE (V)

ILIM = INTV

ILIM = 3/4 INTV

ILIM = 1/2 INTV

ILIM = 1/4 INTV

ILIM = GND

0.4 0.6

0.3 0.5

3875 G10

3875 G13

Current Sense Threshold vs ITH Voltage

CURRENT SENSE THRESHOLD (mV)

–5

–10

TK/SS Pull-Up Current vs Temperature

1.40

1.35

1.30

1.25

1.20

1.15

TK/SS CURRENT (µA)

1.10

1.05

1.00 –30 130

–50

ILIM = 0 ILIM = 1/4 INTV ILIM = 1/2 INTV ILIM = 3/4 INTV ILIM = INTV

–10

0.5 ITH VOLTAGE (V)

TEMPERATURE (°C)

Maximum Current Sense Threshold vs Common Mode Voltage

CC CC CC

1.5

3875 G11

CURRENT SENSE THRESHOLD (mV)

ILIM = INTV

ILIM = 3/4 INTV

ILIM = 1/2 INTV

ILIM = 1/4 INTV

1 2 4

COMMON MODE VOLTAGE (V)

SENSE

ILIM = GND

3875 G12

Shutdown (RUN) Threshold vs Temperature

1.30

1.25

1.20

1.15

1.10

RUN PIN THRESHLD (V)

1.05

110

3875 G14

1.00 –50

OFF

0 50

TEMPERATURE (°C)

100 150

4320 G01

Regulated Feedback Voltage vs Temperature

0.6045

0.6035

0.6025

0.6015

0.6005

0.5995

0.5985

FEEDBACK VOLTAGE (V)

0.5975

0.5965

0.5955 –50 –30 –10

10 30 50 130

TEMPERATURE (°C)

FREQUENCY (kHz)

70 90 110

3875 G16

For more information www.linear.com/LTC3875

Oscillator Frequency vs Temperature

900

800

700

600

500

400

300

200

100

–50

TEMPERATURE (°C)

FREQ

= INTV

= 1.22V

= GND

100

150

3875 G17

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Page 8

LTC3875

3875 G22

TYPICAL PERFORMANCE CHARACTERISTICS

Undervoltage Lockout Threshold (INTVCC) vs Temperature

5.0

4.8

4.6

4.4

4.2

4.0

3.8

3.6

UVLO THRESHOLD (V)

3.4

3.2

3.0 –50

RISING

FALLING

TEMPERATURE (°C)

100

3875 G18

150

Oscillator Frequency vs Input Voltage

900

800

700

600

500

400

300

200

OSCILLATOR FREQUENCY (kHz)

100

= INTV

FREQ

INPUT VOLTAGE (V)

= 1.22V

= GND

3875 G19

Shutdown Current vs Input Voltage

SHUTDOWN CURRENT (µA)

5 15

INPUT VOLTAGE (V)

Quiescent Current vs Input

Shutdown Current vs Temperature Very Low Output Voltage Ripple

SHUTDOWN CURRENT (µA)

–30 130

–50

–10

TEMPERATURE (°C)

110

3875 G21

Voltage without EXTV

QUIESCENT CURRENT (mA)

INPUT VOLTAGE (V)

OUT

TYPICAL

FRONT PAGE

10mV/DIV

AC-COUPLED

OUT

LOW RIPPLE

FIGURE 20

10mV/DIV

AC-COUPLED

VIN = 12V

= 2.5V

OUT

2µs/DIV

3875 G20

3875 G23

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For more information www.linear.com/LTC3875

Page 9

PIN FUNCTIONS

LTC3875

TK/SS1, TK/SS2 (Pin 1, Pin 8): Output Voltage Tracking and Soft-Start Inputs. When one channel is configured to be the master, a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When the channel is configured to be the slave, the feedback voltage of the master channel is reproduced by a resistor divider and applied to

this pin. Internal soft-start currents

of 1.25µA charge these pins.

OSNS1

, V

OSNS2

(Pin 2, Pin 6): Positive Inputs of Remote

Sensing Differential Amplifiers. These pins receive the remotely sensed feedback voltage from external resistive divider across the output. The differential amplifier outputs are connected directly to the error amplifiers’ inputs internally inside the IC.

OSNS1

–

, V

OSNS2

–

(Pin 3, Pin 7): Negative Inputs of Remote Sensing Differential Amplifiers. Connect these pins to the negative terminal of the output capacitors when remote sensing is desired. Connect these pins to local signal ground if remote sensing is not used.

, I

TH1

(Pin 4, Pin 5): Current Control Threshold and

TH2

Error Amplifier Compensation Points. The current comparators’ tripping thresholds increase with these control voltages.

TAVG (Pin 13): Average Temperature Summing Point

. Connect a resistor to ground to sum all currents together for multi-channels or multi-IC operations when temperature balancing function is enabled. The value of the resistor should be the TRSET resistor value divided by the number of channels in the system. Float this pin if thermal balancing is not used.

FREQ (Pin 15): There is a precision 10µA current flowing out of this

pin. A resistor to ground sets a voltage which

in turn programs the frequency. Alternatively, this pin can

be driven with a DC voltage to vary the frequency of the

internal oscillator.

IFAST (Pin 17): Programmable Pin for Fast Transient Operation for Channel 2 Only. A resistor to ground programs the threshold of the output load transient excursion. Float this pin to disable this function. See the Applications

Information section for more details.

ENTMPB (Pin 18): Enable Pin for Temperature Balancing Function. Ground this pin to enable the temperature balancing function. Float this pin for normal operation.

PGOOD (Pin 19): Power Good Indicator Output. Open-drain logic that is pulled to ground when either channel’s output exceeds ±7.5% regulation window, after the internal 20µs power bad mask timer expires.

EXTV

Connected to INTV

(Pin 24): External Power Input to an Internal Switch

. This switch closes and supplies the

IC power, bypassing the internal low dropout regulator, whenever EXTV on this pin and make sure that EXTV

INTV

(Pin 25): Internal 5.5V Regulator Output. The con-

is higher than 4.7V. Do not exceed 6V

< VIN at all times.

trol circuits are powered from this voltage. Decouple this pin to PGND with

a minimum of 4.7µF low ESR tantalum

or ceramic capacitor.

(Pin 26): Main Input Supply. Decouple this pin to

PGND with a capacitor (0.1µF to 1µF).

BG1, BG2 (Pin 27, Pin 23): Bottom Gate Driver Outputs. These pins drive the gates of the bottom N-channel MOSFETs between INTV

and PGND.

BOOST1, BOOST2 (Pin 28, Pin 22): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capaci-

connect to these pins. These pins swing from a diode

tors voltage drop below INTV

up to VIN + INTVCC.

TG1, TG2 (Pin 29, Pin 21): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to INTV

superimposed on the switch node voltage.

SW1, SW2 (Pin 30, Pin 20): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to V

CLKOUT (Pin 31): Clock Output Pin. Clock output with phase changeable by PHASMD to enable usage of multiple LTC3875s in multiphase systems signal swing is from INTV

to ground.

For more information www.linear.com/LTC3875

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Page 10

LTC3875

PIN FUNCTIONS

PHASMD (Pin 32): Phase Programmable Pin. This pin can be tied to SGND, INTV

or left floating. It determines the

relative phases between the internal controllers as well as the phasing of the CLKOUT signal. See Table 1 in the Operation section for details.

MODE/PLLIN (Pin 33): Forced Continuous Mode, Burst Mode or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin.

Connect this pin to SGND to force the IC into continuous mode of operation. Connect to INTV

to enable pulse-skipping

mode of operation. Leave the pin floating to enable Burst

Mode operation. A clock on the pin will force the IC into

continuous mode of operation and synchronize the internal oscillator with the clock on this pin. The PLL compensation

network is integrated into the IC

RUN1, RUN2 (Pin 34, Pin 16): Run Control Inputs. A volt-

age above 1.22V on either pin turns on the IC. However,

forcing both pins below 1.14V causes the IC to shut down. There is a 1.0µA pull-up current for both pins. Once the RUN pin rises above 1.22V, an additional 4.5µA pull-up current is added to the pin.

ILIM (Pin 35): Current Comparators’ Sense Voltage Range

Input. A resistor divider sets the maximum current sense threshold to five different levels for the current comparators.

TRSET1, TRSET2 (Pin 36, Pin 14): Input of the Temperature Balancing Circuitries. Connect these pins through resistors to ground to convert the TCOMP pin voltages to currents. These currents are then mirrored to pin TAVG and are added together for all channels. Float this pin if

thermal balancing is

not used.

TCOMP1/ITEMP1, TCOMP2/ITEMP2 (Pin 37, Pin 12): Input of the Temperature Balancing Circuitries. Connect these pins to external NTC resistors or temperature sensing ICs placed near inductors. These pins are used to sense temperature of each channel and balance the temperature of the whole system accordingly. When thermal balancing function is disabled, these pins can be programmed to compensate the temperature coefficient of the DCR. Con nect to an NTC (negative tempco) resistor placed near the output inductor to compensate for its DCR change over temperature. Floating this pin

disables the DCR temperature

compensation function.

SNSD1

, SNSD2+ (Pin 38, Pin 11): DC Current Sense Com-

parator Inputs. The (+) input to the DC current comparator is normally connected to a DC current sensing network. Ground these pins to disable the novel DCR sensing enable normal DCR sensing with five times current limit.

–

, SNS2– (Pin 39, Pin 10): AC and DC Current

SNS1

Sense Comparator Inputs. The (–) inputs to the current comparators are connected to the output.

SNSA1

Comparator Inputs. The (+) input to the AC current com-

, SNSA2+ (Pin 40, Pin 9): AC Current Sense

parator is normally connected to a DCR sensing network.

When combined with the SNSD

pin, the DCR sensing network can be skewed to increase the AC ripple voltage by a factor of 5.

SGND/PGND (Exposed Pad Pin 41): Signal/Power Ground Pin. Connect this pin closely to the sources of the bottom N-channel MOSFETs, the (–) terminal of C the (–) terminal of C

. All small-signal components and

compensation components should connect to this ground.

VCC

and

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Page 11

LTC3875

BLOCK DIAGRAM

FREQ

CLKOUT

IFAST

(CHANNEL 2

ONLY)

ILIM

0.6V REF

0.55V

PLL-SYNC

50k

THB

SLEEP

–

MODE/PLLIN

OSC

CMP

–

INTV

MODE/SYNC

DETECT

PHASMD

–

SLOPE

COMPENSATION

ACTIVE CLAMP

(Functional diagram shows one channel only)

EXTV

1.22V

4.7V

–

BURST EN

FCNT

SWITCH

LOGIC

AND

ANTISHOOT-

THROUGH

RUN

–

1.25µA

REV

UVLO

–

S R

TCOMP/ITEMP

TEMPSNS

0.5V

0.6V

–

5.5V REG

INTV

BOOST

SNSA

–

SNS

PGND

PGOOD

0.555V

VCC

–

OUT

SNSD

OUT

SGND

AMP

0.66V

–

DIFFAMP

–

SNS

–

20k

OSNS

–

OSNS

20k

1µA/5.5µA

20k

TCOMP/ITEMP

ENTMPB

30µA

ITH

MIRROR

RUN TK/SS

AMP

–

TRSET

TCOMP

For more information www.linear.com/LTC3875

*n EQUALS THE NUMBER OF CHANNELS IN PARALLEL

TAVG

TCOMP

–

REPEAT FOR MULTICHIP OPERATIONS

3875 BD

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Page 12

LTC3875

OPERATION

Main Control Loop

The LTC3875 is a constant frequency, current mode step-

down controller with two channels operating 180° or 240°

out of phase. During normal operation, each top MOSFET

is turned on when the clock for that channel sets the R

latch, and turned off when the main current comparator,

, resets the RS latch. The peak inductor current at

CMP

which I

on the I

resets the RS latch is controlled by the voltage

CMP

pin, which is the output of each error amplifier

EA. The remote sense amplifier (DIFFAMP) converts the sensed differential voltage across the output feedback resistor divider to an internal voltage (V SGND. The V

signal is then compared to the internal

) referred to

0.6V reference voltage by the EA. When the load current

increases, it causes

the 0.6V reference, which in turn causes the I

a slight decrease in VFB relative to

voltage

to increase until the average inductor current matches the new load current. After the top MOSFET has turned off,

the bottom MOSFET is turned on until either the inductor

current starts to reverse, as indicated by the reverse cur-

rent comparator, I

INTV

/EXTVCC Power

, or the beginning of the next cycle.

REV

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTV

When the EXTV

pin is left open or tied to a voltage less

than 4.5V, an internal 5.5V linear regulator supplies INTV

power from V

. If EXTVCC is taken above 4.7V, the 5.5V

regulator is turned off and an internal switch is

connecting EXTV voltage has to be higher than EXTV has to come before EXTV current will flow back to V

to INTVCC. When using EXTVCC, the VIN

voltage at all time and

is applied. Otherwise, EXTVCC

through the internal switch’s

pin.

turned on

body diode and potentially damage the device. Using the EXTV

pin allows the INTVCC power to be derived from

a high efficiency external source.

Each top MOSFET driver is biased from the floating bootstrap capacitor, C

, which normally recharges dur-

ing each off cycle through an external diode when the top

MOSFET turns off. If the input voltage, V a voltage close to V

, the loop may enter dropout and

OUT

, decreases to

attempt to turn on the top MOSFET continuously. The dropout detector detects

this and forces the top MOSFET

off for about one-twelfth of the clock period plus 100ns

every third cycle to allow C

to recharge. However, it is

recommended that a load be present or the IC operates at low frequency during the drop-out transition to ensure that C

Shutdown and Start-Up

is recharged.

(RUN1, RUN2 and TK/SS1, TK/SS2 Pins)

two channels of the LTC3875 can be independently

The shut down using the RUN1 and RUN2 pins. Pulling either of these pins below 1.14V shuts down the main control loop for that channel. Pulling both pins low disables both channels and most internal circuits, including the INTV regulator. Releasing either RUN pin allows an internal 1µA current to pull up the pin and enable the controller. Alternatively

, the RUN pins may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on these pins.

The start-up of each channel’s output voltage, V controlled by the voltage on its TK/SS pin. When the voltage on the TK/SS pin is less than the 0.6V internal reference, the LTC3875 regulates the

VFB voltage to the TK/SS pin voltage instead of the 0.6V reference. This allows the TK/SS pin to be used to program the soft-start period by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.25µA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly beyond), the output voltage V

from 0V to 0.6V (and

rises smoothly from zero

OUT

to its final value. Alternatively the TK/SS pin can be used to cause the start-up of V

to “track” that of another

OUT

supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the corresponding controller, or when INTV

RUN pin is pulled low to disable a

drops below its undervoltage

lockout threshold of 3.7V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, both controllers are disabled and the external MOSFETs are held off.

Internal Soft-Start

By default, the start-up of the output voltage is normally controlled by an internal soft-start ramp.

The internal

soft-start ramp represents one of the noninverting inputs

OUT

, is

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Page 13

OPERATION

LTC3875

to the error amplifier. The VFB signal is regulated to the lower of the error amplifier’s three noninverting inputs (the internal soft-start ramp, the TK/SS pin or the internal

600mV reference). As the ramp voltage rises from 0V to

0.6V, over approximately 600µs, the output voltage rises smoothly from its pre-biased value to its final set value. Certain applications can require

the start-up of the converter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. In order to prevent the output from discharging under these conditions, the top and bottom MOSFETs are disabled until soft-start is greater than V

Light Load Current Operation (Burst Mode Operation, Pulse-Skipping, or Continuous Conduction)

The LTC

3875 can be enabled to enter high efficiency Burst Mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to a DC voltage below 0.6V (e.g., SGND). To select pulse-skipping mode of operation, tie the MODE/PLLIN pin to INTV

. To

select Burst Mode operation, float the MODE/PLLIN pin.

When a controller

is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the I

pin indicates a lower value. If the aver-

age inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the I pin. When the I

voltage drops below 0.5V, the internal

sleep signal goes high (enabling sleep mode) and both external MOSFETs are turned off.

In forced continuous operation, the inductor current is allowed to

reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the I

pin. In this mode, the efficiency at

light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry.

When the MODE/PLLIN pin is connected to INTV LTC3875 operates in

PWM pulse-skipping mode at light loads. At very light loads, the current comparator, I may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise

and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation.

Multichip Operations (PHASMD and CLKOUT Pins)

The PHASMD pin determines the relative phases between the internal channels as well as the CLKOUT signal as shown in Table 1. The phases tabulated are relative to zero phase being defined as

Table 1

PHASMD GND FLOAT INTV

Phase 1 0° 0° 0°

Phase 2 180° 180° 240°

CLKOUT 60° 90° 120°

the rising edge of the clock of phase 1.

, the

CMP

In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output

begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the

next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is

not allowed to reverse. The reverse current comparator

) turns off the bottom external MOSFET just before

REV

the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates

in discontinuous operation.

For more information www.linear.com/LTC3875

The CLKOUT signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss

is proportional to the RMS current squared. A 2-stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s).

3875fb

Page 14

LTC3875

OPERATION

Single Output Multiphase Operation

The LTC3875 can be used for single output multiphase

converters by making these connections

• Tie all of the ITH pins together;

• Tie all of the V

pins together;

OSNS

• Tie all of the TK/SS pins together;

• Tie all of the RUN pins together.

Examples of single output multiphase converters are shown in the Typical Applications section.

Sensing the Output Voltage

The LTC3875 includes two low offset, high input impedance, unity gain, high bandwidth differential amplifier for applications that require true remote sensing. Differentially sensing the load greatly improves regulation in high current, low voltage applications, where board interconnection losses can

be a significant portion of the total error

budget. The LTC3875 differential amplifier’s positive

terminal V

sistor divider and its negative terminal V

senses the divided output through a re-

OSNS

–

senses the

remote ground of the load. The differential amplifier output

is connected to the negative terminal of the internal error amplifier inside the controller. Therefore, its differential output signal (V

) is not accessible from outside the IC. In

a typical application where differential sensing is desired,

connect the V divider across the output load, and the V

pin to the center tap of the feedback

OSNS

–

pin to the

load ground. When differential sensing is not used, the

–

The LTC3875 differential amplifier has a typical output

pin can be connected to local ground. See Figure 1.

OSNS

slew rate of 2V/µs. The amplifier is configured for unity gain, meaning that the difference between V

OSNS

and V

OSNS

–

translated to its output, relative to SGND. Care should be taken to route the V

OSNS

and V

–

PCB traces parallel

OSNS

to each other all the way to the remote sensing points on the board. In addition, avoid routing these sensitive traces

any high speed switching nodes in the circuit. Ideally,

near the V

OSNS

and V

–

traces should be shielded by a

OSNS

low impedance ground plane to maintain signal integrity.

Current Sensing with Very Low Inductor DCR

For low output voltage, high current applications, it’s common to use low winding resistance (DCR) inductors to minimize the winding conduction loss and maximize the supply efficiency. Inductor DCR current sensing

is also used to eliminate the current sensing resistor and its conduction loss. Unfortunately, with a very low inductor DCR value, 1mΩ or less, the AC current sensing signal ripple can be less than 10mV

. This makes the current loop sensitive

P-P

to PCB switching noise and causes switching jitter.

The LTC3875 employs a unique and proprietary current sensing architecture to enhance its signal-to-

noise ratio in these situations. This enables it to operate with a small sense signal of a very low value inductor DCR, 1mΩ or less. The result is improved power efficiency, and reduced jitter due to switching noise which could corrupt the signal. The LTC3875 can sense a DCR value as low as 0.2mΩ with careful PCB layout. The LTC3875 uses two positive sense

pins, SNSD

and SNSA+ to acquire signals. It processes

them internally to provide the response as with a DCR sense signal that has a 14dB (5×) signal-to-noise ratio improvement without affecting output voltage feedback loop. In the meantime, the current limit threshold is still a function of the inductor peak current times its DCR value and its accuracy is also improved five times and can

be accurately

set from 10mV to 30mV in a 5mV steps with the ILIM pin

OUT

OUT2

10Ω

OUT1

10Ω

FEEDBACK DIVIDER

Figure 1. Differential Amplifier Connection

For more information www.linear.com/LTC3875

OSNS

–

DIFFAMP

–

0.6V

INTSS

TK/SS

LTC3875

– +

3875 F01

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Page 15

OPERATION

LTC3875

(see Figure 4b for inductor DCR sensing connections). The

filter time constant, R1 • C1, of the SNSD

L/DCR of the output inductor, while the filter at SNSA

have a bandwidth of five times larger than that of SNSD

should match the

should

i.e, R2 • C2 equals one-fifth of R1 • C1.

Thermal Balancing For Multiphase Operation

When LTC3875 is used as a single

output multiphase converter, the temperature of the whole system can be balanced by enabling the thermal balancing function. This prevents hot spots due to imperfection of current matching and component mismatch. Therefore, it improves the overall reliability of the power supply system.

Refer to Figure 2 for the following discussion of thermal balancing for the LTC3875.

30µA

TCOMP1

The thermal balancing can be enabled by setting the ENTMPB

pin to ground. Each channel has a TCOMP/ITEMP pin which sources a 30µA precision current. By connecting a linearized NTC network or a temperature sensing IC

placed near the hot spot of the converter from this pin to SGND, the temperature of each channel can be sensed. The sensed voltage from each channel is converted to a current, which is programmable with resistor, R

TRSET pin. The current from each channel is then

at the summed together at the TAVG pin. The resistor value at the TAVG is R

/n, where n is the number of phases.

TCOMP

The voltage at TAVG is then a representation of the average temperature of the whole system. By comparing the phase temperature and average temperature, an internal transconductance amplifier then adjusts the phase current accordingly to

match the phase temperature to the average

temperature of the system.

MIRROR

1:1

TCOMP

CHANNEL 1

CHANNEL 2

THERMAL

SENSOR

OR NTC

ADJUST CHANNEL CURRENT

THERMAL

SENSOR

OR NTC

ADJUST CHANNEL CURRENT

TCOMP2

–

30µA

–

AMP

TRSET1

TCOMP

TAVG

–

AVG

MIRROR

1:1

REPEAT FOR

TRSET2

TCOMP

MULTICHIP OPERATIONS

–

3875 F02

Figure 2. Thermal Balancing Technique for Multichip Operations

For more information www.linear.com/LTC3875

3875fb

Page 16

LTC3875

2.2– V

1.5

OPERATION

Inductor DCR Sensing Temperature Compensation

Inductor DCR current sensing provides a lossless method of sensing the instantaneous current. Therefore, it can provide higher efficiency for applications of high output currents. However the DCR of a copper inductor typically has a positive temperature coefficient. As the temperature of the inductor rises, its DCR value increases. The current limit of the controller is therefore reduced.

LTC3875 offers a method

to counter this inaccuracy by allowing the user to place an NTC temperature sensing resistor near the inductor. The ENTMPB pin has to be floating to enable the inductor DCR sensing temperature compensation function. The TCOMP/ITEMP pin, when left floating, is at a voltage around 5.5V and DCR temperature compensation is also disabled. A constant 30µA precision current flows out the TCOMP/ITEMP pin. By connecting

a linearized NTC resistor network from the TCOMP/ITEMP pin to SGND, the maximum current sense threshold can be varied over temperature according the following equation:

SENSEMAX(ADJ)

= V

SENSE(MAX )

•

ITEMP

where:

SENSEMAX(ADJ)

is the maximum adjusted current sense

threshold.

SENSE(MAX)

is the maximum current sense threshold specified in the electrical characteristics table. It is typically 10mV, 15mV, 20mV, 25mV or 30mV depending on the setting ILIM pins. V

is the voltage of the TCOMP/

ITEMP

ITEMP pin.

The valid voltage range for DCR temperature compensation on the TCOMP/ITEMP pin is between

0.7V to SGND

with 0.7V or above being no DCR temperature correction.

An NTC resistor has a negative temperature coefficient, meaning that its value decreases as temperature rises. The V increases and in turn V

voltage, therefore, decreases as temperature

ITEMP

SENSEMAX(ADJ)

will increase to compensate the DCR temperature coefficient. The NTC resistor, however, is nonlinear, but the user can linearize its value by building

a resistor network with regular

resistors. Consult the NTC manufacturer’s data sheets for detailed information.

Another use for the TCOMP/ITEMP pins, in addition to NTC compensated DCR sensing, is adjusting V

SENSE(MAX)

to values between the nominal values of 10mV,15mV, 20mV, 25mV and 30mV for a more precise current limit setting. This is done by applying a voltage less than 0.7V

TCOMP/ITEMP pin. V

to the

SENSE(MAX)

will be varied per the above equation. The current limit can be adjusted using this method either with a sense resistor or DCR sensing. The ENTMPB pin also needs to be floating to use this function.

For more information see the NTC Compensated DCR Sensing paragraph in the Applications Information section.

Frequency Selection and Phase-Locked Loop (FREQ and MODE

/PLLIN Pins)

The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3875’s controllers can be selected using the FREQ pin. If the MODE/PLLIN pin is not being driven by an

external clock source, the FREQ pin can be used to program the controller’s operating frequency from 250kHz to 720kHz. There is a precision 10µA current flowing out of the FREQ pin, so the user can program the controller’s switching frequency with a single resistor to SGND. A curve is provided later in the application section showing the relationship between the voltage on the FREQ

and switching frequency. A phase-locked loop (PLL)

pin is integrated on the LTC3875 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller is operating in forced continuous mode when it is synchronized. The PLL loop filter network is also integrated inside the LTC3875. The phase-locked loop is capable of locking any frequency within the

range of 250kHz to 720kHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock to minimize the transient.

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Page 17

OPERATION

LTC3875

Power Good (PGOOD Pin)

When both V

pins’ voltages are not within ±7.5% of

OSNS

the 0.6V reference voltage, the PGOOD pin is pulled low. The PGOOD pin is also pulled low when the RUN pins are below 1.14V or when the LTC3875 is in the soft-start, UVLO or tracking phase. The PGOOD pin will flag power

good immediately when both the V

pins are within

OSNS

the ±7.5% of the reference window. However, there is an

internal 20µs power bad mask when V

OSNS

voltages go out of the ±7.5% window. The PGOOD pin is allowed to be pulled up by an external resistor to sources of up to 6V.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In

such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared.

Fast Transient Operation

The plots in Figure 3 show the improvement with and without the transient improvement circuit for a typical 12V (V

) to 1.5V (V

) high current application. The

OUT

circuit with fast transient shows a near 30% improvement for the worst case transient steps. For this application, IFAST pin voltage is programmed to be around 0.62V and the circuit is not very sensitive to this programmed voltage. During the double frequency operation, care has to be taken not to violate the minimum on-time requirement of the LTC3875. The fast transient mode is only enabled in forced continuous mode for channel 2 and is disabled automatically during start-up, or when output is out of regulation window.

In order to properly take advantage of the fast transient

OSC

satisfied:



OUT

1–

















circuit, the following equation needs to be

SENSE(MAX )

30mV

• 5k ≥ 5• ∆I

•

•DCR



0.7– V

 

25k

IFAST

0.9375

The LTC3875 also has a transient improvement function implemented on channel 2. In normal operation, IFAST pin is floated. This will disable the transient improvement circuit. To enable the transient improvement function, connect a resistor from IFAST pin to ground. The voltage difference between

0.7V and IFAST pin voltage programs the window of sensitivity of when a transient condition is detected. During the load step-up, a comparator monitoring the ripple voltage will compare with the scaled version of the programmed window voltage and trip. This indicates that a load step is detected. The LTC3875 will immediately turn on the top gate and also double the switching frequency for

about 20 cycles.

where,

SENSE(MAX)

IFAST

is the programmed switching frequency

OSC

is the converter’s output voltage

OUT

is the maximum sense threshold voltage

is the programmed voltage on the IFAST pin

VIN is the converter’s input voltage ΔIL is the inductor ripple current DCR is the winding resistance of the inductor

As a rule of thumb, the value of the left side of the equa-

should be 20% larger than the value of the right side

tion of the equation.

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Page 18

LTC3875

OPERATION

Fast Transient Disabled Fast Transient Enabled

50mV/DIV

SW NODE

10V/DIV

10A/DIV

Figure 3. Worst-Case Transient Comparison Between Normal Mode Operation and Fast Transient Mode of Operation for 12V/1.5V Application with 15A Load Step

95mV

0A TO 15A 0A TO 15A

APPLICATIONS INFORMATION

67.5mV

3875 F03

The Typical Application on the first page of this data sheet is a basic LTC3875 application circuit configured as a dual phase single output power supply. The LTC3875 has an optional thermal balancing function that balances the thermal stress between phases, thus increasing the reliability of the whole system. In addition, the LTC3875 is designed and optimized for use with a very low value DCR inductor by utilizing a novel approach to reduce the noise sensitivity of the sensing signal by a factor of 14dB. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, as the DCR value drops below 1mΩ, the signal-to-noise ratio is low and current sensing is difficult. The LTC3875 uses an

proprietary technique to solve this issue with mini-

LTC

mum additional external components. In general, external component selection is driven by the load requirement, and begins with the DCR and inductor value. Next, power MOSFETs are selected. Finally, input and output capacitors are selected.

Current Limit Programming

The ILIM pin is a 5-level logic input which sets the maximum current limit of the controller. The input impedance of

the

ILIM pin is 250kΩ. When ILIM is grounded, floated, or tied

to INTV

, the typical value for the maximum current sense

threshold will be 10mV, 20mV, or 30mV, respectively. Setting ILIM to one-fourth INTV

and three-fourths INTVCC

provides maximum current sense thresholds of 15mV or 25mV. The user should select the proper ILIM level based on the inductor DCR value and

SNSD

The SNSA

, SNSA+ and SNS– Pins

and SNS– pins are the direct inputs to the cur-

rent comparators, while the SNSD

targeted current limit level.

pin is the input of an

internal DC amplifier. The operating input voltage range

of 0V to 3.5V is for SNSA

, SNSD+ and SNS– in a typical

application. All the positive sense pins that are connected

the current comparator or the DC amplifier are high

to impedance with input bias currents of less than 1µA, but

–

there is a resistance of about 300k from the SNS

–

to ground. The SNS to V

. The SNSD+ pin connects to the filter that has a

OUT

pin should be connected directly

R1 • C1 time constant equals L/DCR of the inductor. The

pin is connected to the second filter, R2 • C2,

SNSA with the time constant equals (R1 • C1)/5. Care must be taken not to float these pins. Filter components, especially capacitors, must be placed close to the LTC3875, and the sense lines should run close together to a Kelvin connection underneath the current sense element (Figure 4a). Because the LTC3875 is designed to be used with a very low DCR value to sense inductor current, without proper care, the parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable. As shown in Figure 4b, resistors R1 and R2 are placed close to the

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APPLICATIONS INFORMATION

Figure 4a. Sense Lines Placement with Inductor DCR

TO SENSE FILTER, NEXT TO THE CONTROLLER

3875 F04a

INDUCTOR

LTC3875

OUT

INTV

BOOST

LTC3875

ITEMP

22.6k

NTC

100k

90.9k

TCOMP/ITEMP

PGND

SNSD

SNS

SNSA

SGND

PLACE C1, C2 NEXT TO IC PLACE R1, R2 NEXT TO INDUCTOR R1C1 = 5 • R2C2

Figure 4b. Inductor DCR Current Sensing

output inductor and capacitors C1 and C2 are close to the IC pins to prevent noise coupling to the sense signal.

For applications where the inductor DCR is large, the LTC3875 could also be used like any typical current mode controller with conventional DCR sensing by

disabling the SNSD R

resistor or a DCR sensing RC filter can be used

SENSE

pin, shorting it to ground. An

to sense the output inductor signal and connects to the

SNSA

pin. If the RC filter is used, its time constant, R • C, equals L/DCR of the output inductor. In these applications, the current limit, V the value of V

SENSE(MAX)

with DC loop enabled, and the

operating voltage range of SNSA

, will be five times

and SNS– is from 0V to

5V. An output voltage of 5V can be generated.

Low Inductor DCR Sensing and Current Limit Estimation

The LTC3875 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor DCR in the sub

milliohm range (Figure 4b). The DCR is the inductor DC

INDUCTOR

DCRL

3875 F04b

OUT

1mΩ for high

–

winding resistance, which is often less than current inductors. In high current and low output voltage applications, conduction loss of a high DCR inductor or a sense resistor will cause a significant reduction in power efficiency. For a specific output requirement and inductor, choose the current limit sensing level that provides proper margin for maximum load current, and uses the relationship of the sense pin filters to output inductor characteristics

DCR=

L/DCR =R1•C1= 5 •R2•C2

as depicted below.

SENSE(MAX )

∆I

MAX

where:

SENSE(MAX)

is the maximum sense voltage for a given

ILIM threshold.

is the maximum load current.

MAX

ΔIL is the inductor ripple current. L/DCR is the output inductor characteristics.

3875fb

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Page 20

LTC3875

( )

VIN– V

OSC

APPLICATIONS INFORMATION

R1 • C1 is the filter time constant of the SNSD+ pin. R2 • C2 is the filter time constant of the SNSA+ pin.

For example, for a 12VIN, 1.2V/30A step-down buck con-

verter running at 400kHz frequency, a 0.15µH, 0.4mΩ inductor is chosen. This inductor provides 15A peak-topeak ripple current, which is 50% of the 30A full load current. At full load,

the inductor peak current is 30A +

15A/2 = 37.5A.

IL(PK) • DCR = 37.5A • 0.4mΩ = 15mV.

In this case, choose the 20mV ILIM setting which is the

closest but higher than 15mV to provide margin for cur-

rent limit.

Select the two R/C sensing network:

Filter on SNSD+ pin: R1 • C1 = L/DCR,

Filter on SNSA+ pin: R2 • C2 = (L/DCR)/5.

In this case, the ripple sense signal across SNSA

–

SNS

pins is ΔIL

• DCR • 5 = 15A • 0.4mΩ • 5 = 30mV.

P-P

and

This signal should be more than 15mV for good signal-to-

noise ratio. In this case, it is certainly sufficient.

The peak inductor current at current limit is:

ILIM(PK) = 20mV/DCR = 20mV/0.4mΩ = 50A.

The average inductor current, which is also the output

current, at current limit is :

ILIM(AVG) = ILIM(PK

) – ΔIL

/2 = 50A – 15A/2 = 42.5A.

P-P

To ensure that the load current will be delivered over the full

operating temperature range, the temperature coefficient of DCR resistance, approximately 0.4%/°C, should be taken

into account. The LTC3875 features a DCR temperature compensation circuit that uses an NTC temperature sensing

resistor for this purpose. See the Inductor DCR Sensing Temperature Compensation section for details.

Typically, C1 and C2 are

selected in the range of 0.047µF

to 0.47µF. If C1 and C2 are chosen to be 100nF, and an

inductor of 150nH with 0.4mΩ DCR is selected, R1 and R2

will be 4.64k and 931Ω respectively. The bias current at

SNSD

and SNSA+ is about 30nA and 500nA respectively,

and it causes some small error to the sense signal.

There will be some power loss in R1

and R2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage:

LOSS

( )

IN(MAX)

– V

OUT

• V

OUT

Ensure that R1 and R2 have a power rating higher than this value. However, DCR sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. To maintain a good signal-to-noise ratio for the current sense signal, using ∆V

tween SNSA on the current sense across SNSA

and SNS– pins or an equivalent 3mV ripple

signal. The actual ripple voltage

and SNS– pins will be determined by the

of 15mV be-

SENSE

following equation:

∆V

SENSE

OUT

• R2•C2• f

OUT

Inductor DCR Sensing Temperature Compensation with NTC Thermistor

For DCR sensing applications, the temperature coefficient of the inductor winding resistance should be taken into account when the accuracy of the current limit is critical over a wide range of temperature. The main element used in inductors is copper; that has a positive tempco of approximately 4000ppm/°C. The LTC3875 provides a feature to correct for this

variation through the use of the TCOMP/ITEMP pin. There is a 30µA precision current source flowing out of the TCOMP/ITEMP pin. A thermistor with a NTC (negative temperature coefficient) resistance can be used in a network, R

(Figure 4b) connected to

ITEMP

maintain the current limit threshold constant over a wide operating temperature. The TCOMP/ITEMP voltage range that activates the correction is from 0.7V or pin is floating, its voltage will be at INTV

less. If this

potential, about

5.5V. When the TCOMP/ITEMP voltage is higher than 0.7V, the temperature compensation is inactive. Floating the ENTMPB pin enables the temperature compensation function.

The following guidelines will help to choose components for temperature correction. The initial compensation is for 25°C ambient temperature:

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APPLICATIONS INFORMATION

LTC3875

1. Set the TCOMP/ITEMP pin resistance to 23.33k at 25°C. With 30µA flowing out of the TCOMP/ITEMP pin, the voltage on the TCOMP/ITEMP pin will be 0.7V at room temperature. Current limit correction will occur for inductor temperatures greater than 25°C.

2. Calculate the TCOMP/ITEMP pin resistance and the maximum inductor temperature which is typically 100°C. Use the following equations:

ITEMP100C

•0.4

 

 



0.7–1.5



MAX

  



= 0.25V

•DCR (Max)•

SENSE(MAX )

100°C– 25°C

( )

100

from the following equation:

R =RO•exp B•





T+273



–

TO+273







where:

R = Resistance at temperature T, which is in degrees C.

= Resistance at temperature TO, typically 25°C.

B = B-constant of the thermistor.

Figure 5 shows a typical resistance curve for a 100k thermistor and the TCOMP/ITEMP pin network over temperature.

Starting values for the NTC compensation network are:

• NTC R

= 100k

• RS = 3.92k

Since V

SENSE(MAX)

ITEMP100C

where:

ITEMP100C

SENSE(MAX)

room temperature.

= Maximum inductor peak current.

MAX

DCR (Max) = Maximum DCR value.

Calculate the values for the NTC network’s parallel and

series resistors, R the following R

and R

RS = R

on the x-axis.

ITEMP25C

ITEMP100C

Next, find the value of RP that satisfies both equations

which will be the point where the curves intersect. Once

is known, solve for RS.

The resistance of the NTC thermistor can be obtained from the vendor’s data sheet either in the form of graphs, tabulated data, or formulas. The approximate value for the NTC thermistor

= I

ITEMP100C

• DCR (Max):

MAX

= 8.33k

30µA

= TCOMP/ITEMP pin resistance at 100°C.

= TCOMP/ITEMP pin voltage at 100°C.

= Maximum current sense threshold at

and RS. A simple method is to graph

versus RP equations with RS on the y-axis

– R

NTC25C

NTC100C

||R

for a given temperature can be calculated

• RP = 24.3k

But, the final values should be calculated

using the above equations and checked at 25°C and 100°C. After determining the components for the temperature compensation network, check the results by plotting I

versus inductor

MAX

temperature using the following equations:

DC(MAX)

∆V

SENSEMAX(ADJ)

DCR(MAX) at 25°C• 1+ T

where:

10000

THERMISTOR RESISTANCE

= 100k, TO = 25°C

1000

100

RESISTANCE (kΩ)

–40

Figure 5. Resistance Versus Temperature for I

Pin Network and the 100k NTC

TEMP

B = 4334 for 25°C/100°C

RITMP

= 20kΩ

= 43.2kΩ

100k NTC

0 40–20 20 80

INDUCTOR TEMPERATURE (°C)



( )





–

L(MAX)

SENSE

–25°C

3875 F05

0.4



•





100

12060 100

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Page 22

LTC3875

2.2– V

APPLICATIONS INFORMATION

SENSEMAX(ADJ)

ITEMP

DC(MAX)

= V

SENSE(MAX )

= 30µA • (RS + RP||R

NTC

•

)

= Maximum average inductor current.

ITEMP

1.5

TC is the inductor temperature.

The resulting current limit should be greater than or equal to I

for inductor temperatures between 25°C and 100°C.

MAX

Typical values for the NTC compensation network are:

• NTC RO = 100k, B-constant = 3000 to 4000

• RS ≈ 3.92k

• RP ≈ 24.3k

Generating the I

versus inductor temperature curve plot

MAX

first using the above values as a starting point, and then adjusting the R approach. Figure 6 shows a curve of I temperature. For PolyPhase

and RP values as necessary, is another

versus inductor

applications, tie the TCOMP/

MAX

ITEMP pins together and calculate for an TCOMP/ITEMP pin current of 30µA • #phases.

For the most accurate

temperature detection, place the thermistors next to the inductors as shown in Figure 7. Take care to keep the TCOMP/ITEMP pins away from the switch nodes.

Slope Compensation and Inductor Peak Current

CONNECT TO

ITEMP1

NETWORK

NTC1

GND

OUT1

SW1

OUT2

SW2

3875 F07a

GND

CONNECT TO ITEMP2 NETWORK

NTC2

(7a) Dual Output Dual Phase DCR Sensing Application

OUT

SW1

NTC

SW2

3875 F07b

(7b) Single Output Dual Phase DCR Sensing Application

Figure 7. Thermistor Locations. Place Thermistor Next to Inductor(s) for Accurate Sensing of the Inductor Temperature, but Keep the ITEMP Pins away from the Switch Nodes and Gate Traces

Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty

cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3875 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles.

Inductor Value Calculation

NOMINAL

(A)

MAX

RS = 3.92k

= 24.3k

NTC THERMISTOR:

= 100k

= 25°C

B = 4334

–40

INDUCTOR TEMPERATURE (°C)

Figure 6. Worst-Case I

0 40–20 20 80

MAX

CORRECTED I

UNCORRECTED

MAX

12060 100

3875 F06

vs Inductor Temperature Curve with

and without NTC Temperature Compensation

For more information www.linear.com/LTC3875

Given the desired input and output voltages, the inductor value and operating frequency, f the inductor’s peak

RIPPLE

-to-peak ripple current:



OUT

VIN– V





OSC

OUT

•L

, directly determine

OSC

 



Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor.

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Page 23

APPLICATIONS INFORMATION

VIN– V

LTC3875

A reasonable starting point is to choose a ripple current that is about 40% of I

OUT(MAX)

. Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to:

L ≥

OSC

OUT

•I

RIPPLE

OUT

• V

Inductor Core Selection

Once the inductance value is determined, the type of in-

ductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are

preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura-

tion. Ferrite core material saturates “hard,” which means

that inductance collapses abruptly when the peak design

current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!

Power MOSFET and Schottky Diode (Optional) Selection

At least

two external power MOSFETs need to be selected: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchronous) switch. The number, type and on-resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much

smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output

voltage that is less than one-third of the input voltage. In applications where V

>> V

, the top MOSFETs’ on-

OUT

resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide

reasonably low on-resistance

with significantly reduced input capacitance for the main

switch application in switching regulators.

The peak-to-peak MOSFET gate drive levels are set by the internal regulator voltage, V

, requiring the use of

INTVCC

logic-level threshold MOSFETs in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to

or less. Selection criteria for the power MOSFETs

30V include the on-resistance, R

, input capacitance,

DS(ON)

input voltage and maximum output current. MOSFET input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (Figure 8). The curve is generated by forcing a constant input current into the gate of a common source, current source

loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain

-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given V voltage, but can be adjusted for different V multiplying the ratio of the application V specified V

values. A way to estimate the C

voltages by

to the curve

MILLER

is to take the change in gate charge from points a and b on a manufacturer’s data sheet and divide by the stated

voltage specified. C

is the most important

MILLER

selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. C definitions of

and COS are specified sometimes but

RSS

these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by:

MILLER EFFECT

a b

MILLER

= (QB – QA)/V

Figure 8. Gate Charge Characteristic

–

3875 F08

drain

term

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Page 24

LTC3875

APPLICATIONS INFORMATION

Main Switch Duty Cycle=

Synchronous Switch Duty Cycle=

OUT



– V





OUT

 



The power dissipation for the main and synchronous MOSFETs at maximum output current are given by:

( )

OUT

( )

MAIN

 

INTVCC



– V

SYNC

where δ is the temperature dependency of R

MAX

 



OUT

MAX

– V

1+δ

( )



( )





MILLER

( )

MAX

DS(ON)

( )

1+δ

( )

MILLER

DS(ON)

•



• f

 

DS(ON)

, RDR

is the effective top driver resistance (approximately 2Ω at

= V

in drain potential in the particular application. V

), VIN is the drain potential and the change

MILLER

is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. C

is the calculated capacitance

MILLER

using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have

R losses while the topside N-channel equation includes

I an additional term for transition losses, which peak at the highest input voltage. For V

< 20V, the high cur-

rent efficiency generally improves with larger MOSFETs, while for V to the point lower C

> 20V, the transition losses rapidly increase

that the use of a higher R

actually provides higher efficiency. The

MILLER

DS(ON)

device with

synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period.

The term (1 + δ ) is generally given for a MOSFET in the form of a normalized R

vs temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low voltage MOSFETs.

An optional Schottky diode across the synchronous MOSFET conducts during the dead time between the conduction of the two large power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse-recovery period which

could cost as much as several percent in efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition loss due to their larger junction capacitance.

Soft-Start and Tracking

The LTC3875 has the ability to either soft-start by itself with a capacitor or track the output

of another channel or external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. This channel is in the shutdown state if its RUN pin voltage is below 1.14V. Its TK/SS pin is actively pulled to ground in this shutdown state.

Once the RUN pin voltage is above 1.22V, the channel pow-

up. A soft-start current of 1.25µA then starts to charge

ers its soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current fold-back is disabled during this phase to ensure smooth soft-start or tracking. The soft-

start or tracking range is defined to be the voltage range from 0V to 0.6V on the TK/SS pin. The total soft-start time can be calculated as:

SOFTSTART

= 0.6 •

1.25µA

Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse-skipping mode up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.56V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.56V. The output ripple is minimized during the 60mV forced continuous mode window ensuring a clean PGOOD signal.

When the channel

is configured to track another supply,

the feedback voltage of the other supply is duplicated by

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APPLICATIONS INFORMATION

LTC3875

a resistor divider and applied to the TK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible

. In order to track down another channel or supply after the soft-start phase expires, the LTC3875 is forced into continuous mode of operation as soon as V

is below the undervoltage threshold of

0.55V regardless of the setting on the MODE/PLLIN pin. However, the LTC3875 should always be set in forced continuous mode tracking down when there is no load. After TK/SS

drops below 0.1V, its channel will operate in

discontinuous mode.

The LTC3875 allows the user to program how its output

ramps up and down by means of the TK/SS pins. Through these pins, the output can be set up to either coincidentally or ratiometrically track another supply’s output, as shown in Figure 9. In the following discussions, V

OUT1

refers to

the LTC3875’s output

1 as a master channel and V

OUT2

refers to the LTC3875’s output 2 as a slave channel. In practice, though, either phase can be used as the master. To implement the coincident tracking in Figure 9a, connect an additional resistive divider to V

and connect

OUT1

its midpoint to the TK/SS pin of the slave channel. The ratio of this divider should be the

same as that of the slave channel’s feedback divider shown in Figure 10a. In this tracking mode, V

must be set higher than V

OUT1

OUT2

To implement the ratiometric tracking in Figure 10b, the ratio of the V

divider should be exactly the same as

OUT2

the master channel’s feedback divider shown in Figure 9b. By selecting different resistors, the LTC3875 can achieve different

modes of tracking including the two in Figure 9.

So which mode should be programmed? While either mode in Figure 9 satisfies most practical applications, some trade-offs exist. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. When the master channel’s output experiences dynamic excursion (under load transient, for example),

OUTPUT VOLTAGE

TIME

(9a) Coincident Tracking

Figure 9. Tw o Different Modes of Output Voltage Tracking

OUT1

TK/SS2

R3 R1

R4 R2

TO V

OSNS1

(10a) Coincident Tracking Setup

OUT1

OUT2

OUTPUT VOLTAGE

TIME

3875 F09

OUT1

OUT2

(9b) Ratiometric Tracking

OUT2

OSNS2

OUT1

TK/SS2

TO V

OSNS1

OSNS2

OUT2

3875 F10

(10b) Ratiometric Tracking Setup

Figure 10. Setup for Coincident and Ratiometric Tracking

For more information www.linear.com/LTC3875

3875fb

Page 26

LTC3875

APPLICATIONS INFORMATION

the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric.

Pre-Biased Output Start-Up

There may be situations that require the power supply to start up with a pre-bias on the output capacitors. In this case, it is desirable to start up without discharging that output pre-bias. The LTC3875 can safely

power up into a pre-biased output without discharging it. The LTC3875 accomplishes this by disabling both TG and BG until the

TK/SS pin voltage and the internal soft-start voltage are

above the V

pin voltage. When V

OSNS

is higher than

OSNS

TK/SS or the internal soft-start voltage, the error amp output is low. The control loop would like to turn

BG on, which

would discharge the output. Disabling BG and TG prevents

the pre-biased output voltage from being discharged. When TK/SS and the internal soft-start both cross 500mV

or V

, whichever is lower, TG and BG are enabled. If

OSNS

the pre-bias is higher than the OV threshold, the bottom gate is turned on immediately to pull the output back into the regulation

INTV

window.

Regulators and EXTV

The LTC3875 features a PMOS LDO that supplies power to INTV

from the VIN supply. INTVCC powers the gate

drivers and much of the LTC3875’s internal circuitry. The

linear regulator regulates the voltage at the INTV

5.5V when V INTV

through a P-channel MOSFET and can supply the

is greater than 6V. EXTVCC connects to

pin to

needed power when its voltage is higher than 4.7V. Each of these can supply a peak current of 100mA and must be bypassed to ground with a minimum of a 4.7µF ceramic capacitor or a low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1µF ceramic capacitor placed directly adjacent to the INTV and PGND pins is highly

recommended. Good bypassing

is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels.

High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3875 to be exceeded. The INTV the gate charge current, may be supplied

5.5V linear regulator or EXTV the EXTV

pin is less than 4.7V, the linear regulator is

current, which is dominated by

by either the

. When the voltage on

enabled. Power dissipation for the IC in this case is highest and is equal to V

• I

. The gate charge current

INTVCC

is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by

using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3875 INTV supply in the UJ package and not using the EXTV

current is limited to less than 44mA from a 38V

TJ = 70°C + (44mA)(38V)(33°C/W) = 125°C

To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = SGND) at maximum V EXTV

rises above 4.7V, the INTVCC linear regulator is

turned off and the EXTV The EXTV to EXTV

remains on as long as the voltage applied

remains above 4.5V. Using the EXTVCC allows

. When the voltage applied to

is connected to the INTVCC.

the MOSFET driver and control power to be derived from one of the LTC3875’s switching regulator outputs during normal operation and from the INTV

when the output

is out of regulation (e.g., start-up, short-circuit). If more current is required through the EXTV

external Schottky diode can be added between the

an EXTV the EXTV

and INTVCC pins. Do not apply more than 6V to

pin and make sure that EXTVCC < VIN.

than is specified,

Significant efficiency and thermal gains can be realized by powering INTV

from the output, since the VIN cur-

rent resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Tying the EXTV

pin to a 5V supply reduces the junction

Efficiency).

temperature in the previous example from 125°C to:

TJ = 70°C + (44mA)(5V)(33°C/W) = 77°C

However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTV

power from the output.

supply:

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Page 27

APPLICATIONS INFORMATION

LTC3875

The following list summarizes the four possible connections for EXTV

1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5.5V regulator resulting in an efficiency penalty at high input voltages.

2. EXTVCC connected directly to V

. This is the normal

OUT

connection for a 5V regulator and provides the highest efficiency.

3. EXTVCC connected to an external supply. If a 5V external supply is available, it may be used to power EXTV

providing it is compatible with the MOSFET gate drive requirements.

4. EXTV

connected to an output-derived boost network.

For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTV

to an

output-derived voltage that has been boosted to greater than 4.7V.

For applications where the main input power is below 5V,

tie the V

and INTVCC pins together and tie the combined

pins to the 5V input with a 1Ω or 2.2Ω resistor as shown

in Figure 11 to minimize the voltage drop caused by the

gate charge current. This will override the INTV

regulator and will prevent INTV due to the is at or exceeds the R

dropout voltage. Make sure the INTVCC voltage

DS(ON)

from dropping too low

test voltage for the MOSFET

linear

which is typically 4.5V for logic level devices.

LTC3875

INTV

Figure 11. Setup for a 5V Input

INTVCC

4.7µF

1Ω

VIN

3875 F11

MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to V and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply:

where V

The value of the boost capacitor, C

= VIN + V

BOOST

is the diode forward voltage drop.

INTVCC

– V

, needs to be 100 times

that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than V

IN(MAX)

. When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency.

Undervoltage Lockout

The LTC3875 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTV to ensure that an adequate gate-drive voltage It locks out the switching action when INTV

is present.

3.7V. To prevent oscillation when there is a disturbance on the INTV

, the UVLO comparator has 500mV of preci-

sion hysteresis.

Another way to detect an undervoltage condition is to monitor the V

supply. Because the RUN pins have a

precision turn-on reference of 1.22V, one can use a resistor divider to

VIN to turn on the IC when VIN is high enough. An extra 4.5µA of current flows out of the RUN pin once the RUN pin voltage passes 1.22V. One can program the hysteresis of the run comparator by adjusting the values of the resistive divider. For accurate V detection, V

needs to be higher than 4.5V.

undervoltage

voltage

is below

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitor, C

, connected to the BOOST

pin supplies the gate drive voltages for the topside MOSFET. Capacitor C external diode D

in the Functional Diagram is charged though

from INTVCC when the SW pin is low.

When the topside MOSFET is to be turned on, the driver places the C

voltage across the gate source of the

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and C

The selection of

Selection

OUT

CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller

)(I

with the highest (V

OUT

) product needs to be used

OUT

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LTC3875

APPLICATIONS INFORMATION

in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution.

In continuous mode, the is a square wave of duty cycle (V

source current of the top MOSFET

)/(VIN). To prevent

OUT

large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by:

MAX

CINRequiredI

RMS

≈



( )

OUT



VIN– V

( )

This formula has a maximum at VIN = 2V I

RMS

= I

/2. This simple worst-case condition is com-

OUT

, where

1/2





monly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher

temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3875, ceramic capacitors can also be used for C

. Always consult the manufacturer

if there is any question.

The benefit of the LTC3875 2-phase operation can be calculated by using the equation above for the higher power controller and then

calculating the loss that would

have resulted if both controller channels switched on at

the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design.

Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs

should be placed within 1cm of each common C

(s). Separating the sources and CIN may pro-

duce undesirable voltage and current resonances at V

other and share a

A small (0.1µF to 1µF) bypass capacitor between the chip

pin and ground, placed close to the LTC3875, is also

suggested. A 2.2Ω to 10Ω resistor placed between C and the V

pin provides further isolation between the

two channels.

The selection of

is driven by the effective series

OUT

resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆V

∆V

OUT

≈I

RIPPLE

where f is the operating frequency, C capacitance and I

) is approximated by:

OUT



ESR+





RIPPLE

8fC

is the ripple current in the induc-

OUT

 



is the output

OUT

tor. The output ripple is highest at maximum input voltage since I

increases with input voltage.

RIPPLE

Setting Output Voltage

The LTC3875 output voltages are each set by an external feedback resistive divider carefully placed across the output, as shown in Figure 1. The regulated output voltage is determined by:

= 0.6V • 1+

OUT

 









To improve the frequency response, a feed-forward capacitor, C route the V

, may be used. Great care should be taken to

line away from noise sources, such as the

inductor or the SW line.

Fault Conditions: Current Limit and Current Foldback

The LTC3875 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 50%

of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start or tracking up. Under short-circuit conditions

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Page 29

APPLICATIONS INFORMATION

1/ 3V

LTC3875

with very low duty cycles, the LTC3875 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The shortcircuit ripple current is determined by the minimum on-time, t

ON(MIN)

, of the LTC3875 (≈90ns), the input volt-

age and inductor value:

∆I

L(SC)

= t

ON(MIN)

•

The resulting short-circuit current is:

–

∆I

L(SC)

ISC=

SENSE(MAX )

SENSE

Overcurrent Fault Recovery

When the output of the power supply is loaded beyond its preset current limit, the regulated output voltage will collapse depending on the load. The output may be shorted to ground through a very low impedance path or it may be a resistive short, in which case the output will collapse partially, until the load current equals the preset current limit. The controller will

continue to source current into the short. The amount of current sourced depends on the ILIM pin setting and the V

voltage as shown in the

Current Foldback graph in the Typical Performance Characteristics section. Upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. In the absence of this feature, the output capacitors would have been

charged at current limit, and

in applications with minimal output capacitance this may

have resulted in output overshoot. Current limit foldback is not disabled during an overcurrent recovery. The load must step below the folded back current limit threshold in order to restart from a hard short.

The internal thermal shutdown is set for approximately 160°C with 10°C of hysteresis. When the chip reaches 160°C, both TG and BG are disabled until the chip

cools

down below 150°C.

Phase-Locked Loop and Frequency Synchronization

The LTC3875 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (V

) and a phase

detector. This allows the turn-on of the top MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. The turn-on of controller 2’s top MOSFET

is thus 180° out-of-phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock.

The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network

. There is a precision 10µA of current flowing out of FREQ pin. This allows the user to use a single resistor to SGND to set the switching frequency when no external clock is applied to the MODE/PLLIN pin. The internal switch between FREQ pin and the integrated PLL filter network is on, allowing the filter network to be precharged to the same voltage potential as the

FREQ pin. The relationship between the voltage on the FREQ pin and the operating frequency is shown in Figure 12 and specified in the Electrical Characteristic table. If an external clock is detected on the MODE/PLLIN pin, the internal switch mentioned above will turn off and isolate the influence of FREQ pin. Note that the LTC3875 can only be synchronized to an external clock whose internal V

frequency is within range of the LTC3875’s

. This is guaranteed to be between 250kHz and

720kHz. A simplified block diagram is shown in Figure 13.

Thermal Protection

Excessive ambient temperatures, loads and inadequate

airflow or heat sinking can subject the chip, inductor,

FETs etc. to high

temperatures. This thermal stress reduces component life and if severe enough, can result in immediate catastrophic failure (Note 1). To protect the power supply from undue thermal stress, the LTC3875 has a fixed chip temperature-based thermal shutdown.

For more information www.linear.com/LTC3875

If the external clock frequency is greater than the internal oscillator’s frequency, f

, then current is sourced

OSC

continuously from the phase detector output, pulling up the filter network. When the external clock frequency is

less than

, current is sunk continuously, pulling down

OSC

the filter network. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to

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Page 30

LTC3875

APPLICATIONS INFORMATION

900

800

700

600

500

400

300

FREQUENCY (kHz)

200

100

0.5 1.5

FREQ PIN VOLTAGE (V)

Figure 12. Relationship Between Oscillator Frequency and Voltage at the FREQ Pin

2.4V 5V

MODE/

EXTERNAL

OSCILLATOR

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

SYNC

2.5

3875 F12

10µA

FREQ

SET

VCO

cycle applications may approach this minimum on-time limit and

care should be taken to ensure that:

ON(MIN)

VIN• f

( )

OUT

If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3875 is approximately 90ns, with reasonably good PCB layout, minimum 30% inductor current ripple and at least 2mV ripple on the current sense

or equivalent 10mV between SNSA

and SNS– pins. The

signal

minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak sense voltage decreases the minimum on-time gradually increases to 110ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-

time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.

3875 F13

Figure 13. Phase-Locked Loop Block Diagram

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage.

Typically, the external clock (on MODE/PLLIN pin) input

high threshold is 1.6V, while the input low threshold is 1V.

It is not

recommended to apply the external clock when

IC is in shutdown.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time duration that the LTC3875 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty

Efficiency Considerations

The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can

expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage of input power.

Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3875 circuits: 1) IC V

regulator current, 3) I

R losses, 4) Topside MOSFET

current, 2) INTVCC

transition losses.

1. The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. V

current typically results

in a small (<0.1%) loss.

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APPLICATIONS INFORMATION

LTC3875

2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTV rent out of INTV control circuit current. In continuous mode, I

to ground. The resulting dQ/dt is a cur-

that is typically much larger than the

GATECHG

= f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs.

Supplying INTVCC power through EXTVCC from an

output-derived source will scale the V

current required

for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTV

2.5mA of V

current. This reduces the midcurrent loss

current results in approximately

from 10% or more (if the driver was powered directly

VIN) to only a few percent.

from

3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor (if used). In continuous mode, the average output current flows through L, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same R

DS(ON)

then the resistance of one MOSFET can simply be summed with the resistances Efficiency varies as the inverse square of V

of L to obtain I2R losses.

for the

OUT

same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system!

4. Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from:

Transition Loss = (1.7) V

O(MAX) CRSS

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional efficiency

degradation in portable systems. It is very important to include these “system” level losses during the design

phase. The internal battery and fuse resistance losses can be minimized by making sure that C storage and very low ESR

at the switching frequency. The

has adequate charge

LTC3875 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V amount equal to ∆I

LOAD (ESR)

series resistance of C discharge C

generating the feedback error signal that

OUT

, where ESR is the effective

. ∆I

also begins to charge or

LOAD

DC (resistive)

shifts by an

OUT

forces the regulator to adapt to the current change and return V time

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. The availability of the I

pin not only allows optimization of

control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system,

phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The I

external components shown

in the Typical Application circuit will provide an adequate starting point for most applications. The I

series RC-CC

filter sets the dominant pole-zero loop compensation.

values can be modified slightly (from 0.5 to 2 times

The their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µ

pin waveforms that will give a sense of the overall

s to 10µs will produce output voltage and

loop stability without breaking the feedback loop. Placing

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LTC3875

APPLICATIONS INFORMATION

a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load-step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is

better to look at the ITH pin

signal which is in the feedback loop and is the filtered and

compensated control loop response. The gain of the loop

will be increased by increasing R loop will be increased by decreasing C by the same factor that C

will be kept

the same, thereby keeping the phase shift the

is decreased, the zero frequency

and the bandwidth of the

. If RC is increased

same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance.

A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in with C

, causing a rapid drop in V

OUT

. No regulator can

OUT

parallel

alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of C

LOAD

to C

is greater than 1:50, the switch rise time

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C

. Thus a 10µF capacitor would

LOAD

require a 250µs rise time, limiting the charging current

to about 200mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 14. Figure 15 illustrates the current

waveforms present in the various branches of

the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout:

Are the top N-channel MOSFETs M1 and M3 located within 1cm of each other with a common drain connection at

? Do not attempt to split the input decoupling for the

two channels as it can cause a large resonant loop.

2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of C

must return to the combined C

INTVCC

terminals. The V

and ITH traces should be as short

OUT

(–)

as possible. The path formed by the top N-channel MOSFET, Schottky diode and the C

capacitor should

have short leads and PC trace lengths. The output capacitor (–) terminals

should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above.

3. Are the SNSD

, SNSA+ and SNS– printed circuit traces

routed together with minimum PC trace spacing? The

filter capacitors between SNSD should be as close as possible to the pins

Connect the SNSD

and SNSA+ pins to the filter resistors

, SNSA+ and SNS–

of the IC.

as illustrated in Figure 4.

4. Do the (+) plates of C

connect to the drain of the

topside MOSFET as closely as possible? This capacitor provides the pulsed current to the MOSFET.

5. Keep the switching nodes, SW, BOOST and TG away

from sensitive small-signal nodes (SNSD SNS

–

, V

OSNS

, V

–

). Ideally the SW, BOOST and

OSNS

, SNSA+,

TG printed circuit traces should be routed away and separated from the IC and especially the quiet side of the IC. Separate the high dv/dt traces from sensitive small-signal nodes with ground traces or ground planes.

6. The INTV mediately adjacent to the IC between the INTV and PGND plane. A 1µF

decoupling capacitor should be placed im-

ceramic capacitor of the X7R

or X5R type is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the bottom MOSFETs. An additional

4.7µF to 10µF of ceramic, tantalum or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet.

7. Use a modified “star ground

” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC.

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APPLICATIONS INFORMATION

LTC3875

CLKOUT

TH1

LTC3875

OSNS1

–

OSNS

SNSA1

–

SNS1

SNSD1

FREQ I

LIM

MODE/PLLIN

RUN1 RUN2 SGND

–

SNSA2

–

SNS2

SNSD2

–

OSNS2

TH2

TK/SS2

TK/SS1

PGOOD

PHASMD

IFAST

TG1

SW1

BOOST1

BG1

PGND

EXTV

INTV

BG2

BOOST2

SW2

TG2

PU2

PGOOD

1µF

PULL-UP

INTVCC

4.7µF

M1 M2

2.2Ω

VIN

1µF

10µF ×2

CERAMIC

Figure 14. Recommended Printed Circuit Layout Diagram

10µF ×2

CERAMIC

3875 F14

D1 (OPT)

OUT1

OUT2

D2 (OPT)

OUT1

GND

OUT2

BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH.

SW1

SW2

OUT1

OUT2

Figure 15. Branch Current Waveforms

3875 F15

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LTC3875

APPLICATIONS INFORMATION

8. Use a low impedance source such as a logic gate to drive the MODE/PLLIN pin and keep the lead as short as possible.

9. The 47pF to 330pF ceramic capacitor between the ITH pin and signal ground should be placed as close as possible to the IC. Figure 15 illustrates all branch currents in a switching regulator. It becomes very clear after studying the current

waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these loops just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives

rise to the noise generated by a switching regulator. The ground terminations of the synchronous MOSFET and Schottky diode should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched

currents are present. External OPTI-LOOP

compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure.

PC Board Layout Debugging

Start with one controller at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in

the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold— typically 10% of the maximum designed current level in

Burst Mode

operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a sub-harmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is

not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when

one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter.

Reduce V

from its nominal level to verify operation of

the regulator in dropout. Check the operation of the undervoltage lockout circuit by

further lowering VIN while

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins

needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between C

, Schottky and the top

MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC.

Design Example

As a design example for a single output dual phase high current regulator, assume V (maximum), V

= 1.5V, I

OUT

= 12V(nominal), VIN = 20V

= 30A, and f = 400kHz

MAX1,2

(see Figure 16).

The regulated output voltages are determined by:

= 0.6 • 1+

OUT

Shorting the V





OSNS1

ing 20k, 1% resistor from V









pins and V

OSNS

OSNS2

pins together. Us-

node to remote ground, the top feedback resistor is (to the nearest 1% standard value) 30.1k.

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APPLICATIONS INFORMATION

1.5V

DCR•C2 •5

INTV

60k

20k

INTV

OUT

THERMAL

SENSOR

0.33µH

(0.32mΩ DCR)

931Ω

OUT3

470µF ×2

4.64k

OUT4

100µF ×2

4.7µF

CMDSH-3 M1 BSC050NE2LS

0.1µF

M2 BSC010NE2LSI

R 5k

TRSET1

220nF

TAVG

10k

INTV

LTC3875

–

+ –

TK/SS2TK/SS1

PHASMD

CLKOUT

PGOOD

IFAST

MODE/PLLIN

TG2

BOOST2

SW2

PGND

TRSET2

SNSA2

SNS2

SNSD2

TCOMP2

FREQ

OSNS2

TH2

0.1µF

RUN1,2 ILIM ENTMPB TG1

BOOST1

SW1 EXTV BG1 BG2 TAVG

TRSET1 SNSA1

SNS1

SNSD1 TCOMP1

OSNS1

TH1

LTC3875

10µF ×4

D2 CMDSH-3

BSC050NE2LS

0.1µF

BSC010NE2LSI

10k

TRSET2

220nF

–

220nF

+ –

100k

10k

1.5nF

4.64kR2931Ω

RB 30.1k

20k

4.5V TO 20V

270µF 50V

THERMAL

SENSOR

0.33µH

(0.32mΩ DCR)

C 100µF ×2

OUT1

OUT

1.5V 60A

OUT2

470µF ×2

Figure 16. High Efficiency Dual Phase 400kHz, 1.5V/60A Step-Down Converter with Optional Thermal Balancing

The frequency is set by biasing the FREQ pin to 1V (see Figure 12).

The inductance values are based on a 35% maximum

ripple current assumption (10.5A for each channel). The highest value of ripple current occurs at the maximum input voltage:

f • ∆I

OUT

L(MAX)

L =



1–





IN(MAX)

OUT

 



This design will require 0.33µH. The Würth 744301033,

0.32µH inductor is chosen. At the nominal input voltage

(12V), the ripple current will be:



∆I

L(NOM)

OUT

f •L

1–





IN(NOM)

OUT

 



3875 F16

It will have 10A (33%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current, or 35A.

The minimum on-time occurs at the maximum V

, and

should not be less than 90ns:

IN(MAX)

OUT

20V 400kHz

( )

=187ns

ON(MIN)

DCR sensing is used in this circuit. If C1 and C2 are chosen to be 220nF, based on the chosen 0.33µH inductor with

0.32mΩ DCR, R1 and R2 can be calculated as:

R1=

= 4.69k

DCR•C1

R2=

= 937Ω

For more information www.linear.com/LTC3875

3875fb

Page 36

LTC3875

1.5V

= 721mW

( )

20V –1.5V

APPLICATIONS INFORMATION

Choose R1 = 4.64k and R2 = 931Ω.

The maximum DCR of the inductor is 0.34mΩ. The V

SENSE(MAX)

The current limit is chosen to be 15mV. If temperature variation is considered, please refer to Inductor DCR Sensing Temperature Compensation with NTC Thermistor.

The power dissipation on the topside MOSFET can be easily estimated. Choosing an Infineon BSC050NE2LS MOSFET results in: R

2.8V, C (estimated) = 75°C:

MAIN

For a 0.32mΩ DCR, a short-circuit to near ground will result in a folded back current of:

ISC=

is calculated as:

= I

≅ 35pF. At maximum input voltage with TJ

MILLER

20V

0.0071Ω

( )

 

5.5V – 2.8V



= 599mW+122mW

15mV

1/ 3

0.0032Ω

• DCR (Max) = 12mV

PEAK

= 7.1mΩ (max), V

DS(ON)

30A

( )





+ 20V

( )



–





1+ 0.005

( )

2.8V

90ns 20V

0.33µH

75°C– 25°C

( )

30A









 



( )





400kHz

( )

 



2Ω

=12.9A

MILLER

35pF

( )

•

•

An Infineon BSC010NE2LS, R for the bottom FET. The resulting power loss is:

SYNC

CIN is chosen for an equivalent RMS current rating of at least 13.7A. C

4.5mΩ for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage.

The output voltage ripple due to ESR is approximately:

ORIPPLE

Further reductions in output voltage ripple can be made by placing a 100µF ceramic capacitor across C

Thermal Balancing Converter Example

If thermal balancing function is desired, connecting ENTMPB pin to ground enables the temperature balancing function, but disables the inductor DCR sensing temperature compensation function. For a 4-phase design select TRSET1,2,3,4 = 10k, then R

temperature slope of NTC connected to the TCOMP

vs pin need to be modified according to the inductor current correction range. Please refer to temperature balancing with NTC thermistor example shown in Figure 17.

20V

1+ 0.005



( )



=1.14W

OUT

= R

ESR

30A

( )

• 75°C– 25°C

( )

is chosen with an equivalent ESR of

(∆IL) = 0.0045Ω • 10A = 45mV

TAVG

= 1.1mΩ, is chosen

DS(ON)

•

•0.001Ω

OUT

= 2.5k. The resistance

P-P

3875fb

For more information www.linear.com/LTC3875

Page 37

TYPICAL APPLICATIONS

VIN4.5V TO 14V

GND

IN1

270µF

16V

OSNS

R16, 10Ω

R12

715Ω

R11

3.57k

IN2

10µF

1210

IN3

10µF

1210

OUT

GND

1V/120A

OUT2

330µF

2.5V

OUT1

100µF

6.3V

0.25µH

DCR = 0.32mΩ

7343

×2

1210

×2

744301025

BSC010NE2LSI

–

OSNS

R20, 10Ω

LTC3875

OUT

OUT4

330µF

2.5V

OUT3

100µF

6.3V

IN5

10µF

1210

IN4

10µF

1210

0.25µH 744301025

DCR = 0.32mΩ

R35

R34

7343

1210

715Ω

3.57k

3875 F17a

×2

R9, 3.01k

TK/SS

CC1

C14

–

OSNS2

1.5nF

4.7µF

C13

EXTV

OSNS2

R19, 10k

CC1

INTV

CMDSH-3

10V

C18

1µF

TG2

BG2

BOOST2

TK/SS2

SNSA2+SNS2–SGND/PGND

C16

0.1µF

220nF

SW2

BSC050NE2LS

IFAST ENTMPB PGOOD

FREQ RUN2

TAVG TRSET2TCOMP2

11 12 13 14 15 16 17 18 19

SNSD2

RUN

R32

100k

TAVG TRSET2TCOMP2

C19, 220nF

BSC010NE2LSI

THERMAL SENSOR

TCOMP1

R37, 10k

TRSET1

R40, 10k

TRSET2

THERMAL SENSOR

Figure 17a. 4-Phase 1.0V/120A Step-Down Converter with Thermal Balancing

TCOMP2

R43, 2.49k

TAVG

CC1

INTV

D1, CMDSH-3

TG1

BOOST1

–

OSNS1

OSNS

R18, 2.2Ω

BG1

ITH1

ITH2

ITH

C11, 100pF

INTV

LTC3875

C12

CLKOUT

RUN

TCOMP1 TRSET1

OSNS

BSC050NE2LS

0.1µF

3029282726252423222120

31323334353637383940

SW1

MODE/PLLIN PHASMD CLKOUT

ILIM RUN1

TCOMP1 TRSET1

SNSD1

–

SNS1

SNSA1

TK/SS1

123456789

R13

13.3k

R14

20k

–

CC1

INTV

R10

220nF

0.1µF

3875fb

For more information www.linear.com/LTC3875

Page 38

LTC3875

TYPICAL APPLICATIONS

1210

BSC050NE2LS

OUT

OUT13

330µF

OUT15

100µF

0.25µH

DCR = 0.32mΩ

2.5V

7343

×2

6.3V

1210

×2

744301025

R36

715Ω

R39

3.57k

BSC010NE2LSI

3875 F17b

OUT

OUT10

330µF

2.5V

7343

×2

OUT9

100µF

6.3V

1210

×2

R15

715Ω

R23

IN7

10µF

1210

IN6

0.25µH 744301025

3.57k

10µF

1210

BSC050NE2LS

31323334353637383940

DCR = 0.32mΩ

BSC010NE2LSI

CC2

INTV

D3, CMDSH-3

0.1µF R21, 2.2Ω

3029282726252423222120

TG1

BG1

SW1

BOOST1

IN8

10µF

IN9

10µF

CC2

INTV

CC2

INTV

C23

4.7µF

10V

C15

1µF

BG2

INTV

EXTV

BOOST2

CMDSH-3

C20

0.1µF

TG2

SW2

CC2

INTV

R17, 3.01k

R22

CLKOUT

MODE/PLLIN PHASMD CLKOUT

RUN

ILIM RUN1

TCOMP1 TRSET1

TCOMP3 TRSET3

TK/SS

SNSD1

–

SNS1

OSNS1

SNSA1

TK/SS1

123456789

–

OSNS

220nF

–

OSNS1

ITH1

ITH2

ITH

C17, 100pF

LTC3875

OSNS2

–

OSNS2

TK/SS2

IFAST ENTMPB PGOOD

FREQ RUN2

TAVG TRSET2TCOMP2

SNSD2

SNSA2+SNS2–SGND/PGND

C24

220nF

11 12 13 14 15 16 17 18 19

RUN

R33

100k

TAVG TRSET4TCOMP4

C21, 220nF

THERMAL SENSOR

TCOMP3

R38, 10k

TRSET3

R41, 10k

TRSET4

THERMAL SENSOR

TCOMP4

Figure 17b. 4-Phase 1.0V/120A Step-Down Converter with Thermal Balancing

3875fb

For more information www.linear.com/LTC3875

Page 39

TYPICAL APPLICATIONS

OUT

5V/50A

R12

3.48k

1210

OSNS

R16, 10Ω

OUT

1µH

VIN11V TO 13V

GND

IN1

270µF

16V

IN2

10µF

1210

IN3

10µF

GND

OUT2

330µF

6.3V

7343

OUT3

100µF

6.3V

1210

DCR = 1.3mΩ

BSC010NE2LSI

LTC3875

OUT

–

OSNS

×2

OUT5

330µF

6.3V

OUT7

100µF

×2

R20, 10Ω

IN5

10µF

1210

IN4

10µF

1210

6.3V

1µH

DCR = 1.3mΩ

R35

3.48k

7343

1210

3875 F18

×2

CC1

INTV

OSNS2

C14

C13

–

4.7µF

EXTV

OSNS2

CC1

INTV

CMDSH-3

10V

C18

1µF

TG2

BG2

BOOST2

TK/SS2

SNSA2+SNS2–SGND/PGND

0.1µF

SW2

BSC024NE2LS

IFAST ENTMPB PGOOD

FREQ RUN2

TAVG TRSET2TCOMP2

11 12 13 14 15 16 17 18 19

SNSD2

RUN

R32

100k

TAVG TRSET2TCOMP2

BSC010NE2LSI

TCOMP1

R37, 10k

THERMAL SENSOR

TCOMP2

R40, 10k

THERMAL SENSOR

Figure 18. 5.0V/50A 2-Phase Step-Down Converter with Remote Sensing

R43, 5k

CC1

INTV

D1, CMDSH-3

TG1

BOOST1

–

OSNS1

R18, 2.2Ω

BG1

ITH1

ITH2

INTV

LTC3875

CLKOUT

RUN

TCOMP1 TRSET1

BSC024NE2LS

0.1µF

3029282726252423222120

31323334353637383940

SW1

MODE/PLLIN PHASMD CLKOUT

ILIM RUN1

TCOMP1 TRSET1

SNSD1

–

SNS1

SNSA1

TK/SS1

123456789

220nF

TK/SS

TRSET2

TAVG

0.1µF

OSNS

R13

ITH

C12

C11, 100pF

2.2nF

R19, 20k

147k

R14

20k

–

OSNS

C16

220nF

TRSET1

3875fb

For more information www.linear.com/LTC3875

Page 40

LTC3875

TYPICAL APPLICATIONS

OUT

GND

1V/80A

OUT

OUT2

330µF

2.5V

OSNS

OUT1

100µF

6.3V

OUT1VOUT2

U102

VRA001-4COG

IN1VIN2

PWMH

1754326

INTV

D1, CMDSH-3

0.1µF

VIN7V TO 14V

IN1

270µF

16V

IN2

10µF

GND

R11

1210

R16, 10Ω

4.75k

IN3

10µF

1210

7343

1210

×2

TEMP

PWML

NCN

TEMP

GATE

GND

INTV

R18, 2.2Ω

–

OSNS

R20, 10Ω

GND

C14

4.7µF

C13

OUT

OUT4

330µF

2.5V

7343

×2

IN5

10µF

1210

IN4

10µF

1210

GND

INTV

10V

C18

1µF

U103

CMDSH-3

0.1µF

OUT1VOUT2

VRA001-4COG

IN1VIN2

1754326

OUT3

100µF

6.3V

1210

×2

R34

4.75k

NCN

TEMP

GATE

GND

PWMH

TEMP

PWML

3875 F19

TK/SS

3029282726252423222120

SW1

TK/SS1

20k

–

OSNS1

OSNS

BOOST1

–

OSNS1

BG1

ITH1

ITH2

ITH

C11, 100pF

INTV

LTC3875

OSNS2

C12

1.5nF

–

31323334353637383940

CLKOUT

RUN

TCOMP1 TRSET1

OSNS

MODE/PLLIN PHASMD CLKOUT

ILIM RUN1

TCOMP1 TRSET1

SNSD1

–

SNS1

SNSA1

123456789

R13

13.3k

R14

INTV

47nF

0.1µF

TG1

BG2

EXTV

OSNS2

TK/SS2

R19, 10k

TG2

SW2

BOOST2

IFAST ENTMPB PGOOD

FREQ RUN2

TAVG TRSET2TCOMP2

SNSD2

SNSA2+SNS2–SGND/PGND

C16

47nF

11 12 13 14 15 16 17 18 19

RUN

R32

100k

TAVG TRSET2TCOMP2

C19, 47nF

Figure 19. 1.0V/80A 2-Phase High Efficiency Step-Down Converter with AcBel Power Block

3875fb

For more information www.linear.com/LTC3875

Page 41

TYPICAL APPLICATIONS

LTC3875

VIN12V TO 25V

IN1

270µF

INTV

R9, 1k

R10

16V

FREQ RUN2 IFAST ENTMPB PGOOD

IN5

–

O1SNS

R20, 10Ω

R24, 10Ω

10µF

1210

Q103

FDMS3610S

R32

100k

O2SNS

RS2

OUT2

0.006Ω

GND

3.3V/2A J6

OUT5

330µF

OUT8

100µF

R34

11µH

DCR = 15.8mΩ

R35

2.5V

6.3V

7343

1210

10Ω

402Ω

3875 F20a

–

O2SNS

R36, 10Ω

3875 F20c

THERMAL SENSOR

TCOMP2

THERMAL SENSOR

TCOMP1

R43, 5k

3.8mV

3.1mV

2µs/DIV

= 2.5V/2A

= 25V

OUT

10mV/DIV

3875 F20b

2µs/DIV

OUT1

GND

O1SNS

GND

2.5V/2A

OUT2

330µF

2.5V

7343

OUT1

R16, 10Ω

RS1

R17

10Ω

0.006Ω

1210

TG1

INTV

BOOST1

11µH

CMDSH-3

R18, 2.2Ω

BG1

R12

402Ω

IN2

10µF

Q102

FDMS3610S

0.1µF

3029282726252423222120

31323334353637383940

SW1

MODE/PLLIN PHASMD CLKOUT

ILIM RUN1

DCR = 15.8mΩ

INTV

C14

4.7µF

C13

INTV

EXTV

LTC3875

OUT1

100µF

6.3V

1210

INTV

CMDSH-3

10V

C18

0.1µF

1µF

TG2

BG2

SW2

BOOST2

R38

50Ω

C21

0.1µF

TAVG

R37, 10k

TRSET1

R40, 10k

TRSET2

= 2.5V/2A

= 12V

OUT

5mV/DIV

Figure 20. Dual Output Ultralow Ripple 2.5V/2A, 3.3V/2A Step-Down Converter

3875fb

TAVG TRSET2TCOMP2

SNSD2

R19

C12

11 12 13 14 15 16 17 18 19

174k

220pF

TAVG TRSET2TCOMP2

C19, 1nF

R39

50Ω

C17

68pF

O2SNS

R21

90.9k

R25

20k

–

O2SNS

TCOMP1 TRSET1

O1SNS

SNSD1

–

SNS1

–

OSNS1

SNSA1

TK/SS1

123456789

C15

68pF

R13

63.4k

R14

20k

–

O1SNS

OSNS1

ITH1

220pF

ITH2

R15

OSNS2

–

10pF

174k

OSNS2

TK/SS2

SNSA2+SNS2–SGND/PGND

C16

470nF

C11, 10pF

1nF

470nF

0.1µF

For more information www.linear.com/LTC3875

Page 42

LTC3875

TYPICAL APPLICATIONS

VIN4.5V TO 14V

715

R12

GND

IN1

270µF

16V

R11

3.57k

O1SNS

OUT1

R16, 10Ω

IN2

10µF

1210

IN3

10µF

1210

OUT1

1V/30A

0.25µH

744301025

GND

OUT2

330µF

2.5V

7343

OUT1

100µF

6.3V

1210

DCR = 0.32mΩ

–

O2SNS

R24, 10Ω

OUT2

GND

1.5V/30A J6

OUT4

330µF

OUT3

100µF

0.33µH 744301033

2.5V

7343

×2

6.3V

1210

×2

R35

931Ω

DCR = 0.32mΩ

R34

4.64Ω

–

O2SNS

R36, 10Ω

3875 F21

O1SNS

×2

R20, 10Ω

×2

IN5

10µF

1210

IN4

10µF

1210

INTV

R9, 3.01k

R10

OSNS2

C14

C13

–

EXTV

OSNS2

INTV

4.7µF

10V

C18

1µF

BG2

BOOST2

TK/SS2

SNSA2+SNS2–SGND/PGND

CMDSH-3

0.1µF

TG2

SW2

BSC050NE2LS

FREQ RUN2 IFAST ENTMPB PGOOD

TAVG TRSET2TCOMP2

11 12 13 14 15 16 17 18 19

SNSD2

R32

100k

C19, 220nF

BSC010NE2LSI

TCOMP1

THERMAL SENSOR

TCOMP2

THERMAL SENSOR

Figure 21. Dual Output 1V/30A, 1.5V/30A Step-Down Converter with Remote Sensing

BSC050NE2LS

0.1µF

3029282726252423222120

31323334353637383940

SW1

MODE/PLLIN PHASMD CLKOUT

ILIM RUN1

TCOMP1 TRSET1

220nF

0.1µF

SNSD1

–

SNS1

SNSA1

TK/SS1

123456789

TG1

OSNS1

INTV

BOOST1

–

OSNS1

BSC010NE2LSI

CMDSH-3

R18, 2.2Ω

BG1

ITH1

ITH2

INTV

LTC3875

O1SNS

R13

13.3k

R14

20k

–

O1SNS

C8, 1.5nF

R15

150pF

10k

C16

220nF

C12

1.5nF

C11, 150pF

R19

10k

O2SNS

R21

30.1k

R25

20k

–

O2SNS

C21

0.1µF

3875fb

For more information www.linear.com/LTC3875

Page 43

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC3875#packaging for the most recent package drawings.

UH Package

40-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1746 Rev B)

0.70 ±0.05

LTC3875

3.50 ±0.05

0.20 ±0.05

0.40 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

5.00 ±0.10 (4 SIDES)

PIN 1 TOP MARK (SEE NOTE 5)

4.10 ±0.05

3.60 REF

(4 SIDES)

PACKAGE OUTLINE

0.75 ±0.05

5.50 ±0.05

R = 0.05

TYP

3.60 REF

(4-SIDES)

R = 0.100

TYP

3.50 ±0.10

4039

0.40 ±0.10

PIN 1 NOTCH

R = 0.30 TYP

OR 0.35 × 45°

CHAMFER

0.200 REF

0.00 – 0.05

NOTE:

1. DRAWING CONFIRMS TO JEDEC PACKAGE OUTLINE MO-220

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

For more information www.linear.com/LTC3875

3.50 ±0.10

(UH40) QFN REV B 0415

0.20 ± 0.05

0.40 BSC

BOTTOM VIEW—EXPOSED PAD

3875fb

Page 44

LTC3875

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC3875#packaging for the most recent package drawings.

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 ±0.05

4.42 ±0.05

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

6.00 ±0.10 (4 SIDES)

PIN 1 TOP MARK (SEE NOTE 6)

5.10 ±0.05

4.50 ±0.05 (4 SIDES)

PACKAGE OUTLINE

0.75 ±0.05

6.50 ±0.05

R = 0.10

TYP

4.50 REF

(4-SIDES)

R = 0.115

TYP

4.42 ±0.10

PIN 1 NOTCH

R = 0.45 OR

0.35 × 45° CHAMFER

4039

0.40 ±0.10

0.200 REF

0.00 – 0.05

NOTE:

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

For more information www.linear.com/LTC3875

4.42 ±0.10

(UJ40) QFN REV Ø 0406

0.25 ±0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

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Page 45

LTC3875

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 4/15 Corrected typographical errors

Modifications to figures Simplified schematics

B 11/15 Added UH Package

Removed Temp Dot from I

SENSE(AC)

1 to 30 28 to 35 36 to 44

1, 2, 3, 5, 43

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC3875

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Page 46

LTC3875

TYPICAL APPLICATION

High Efficiency Dual Phase 1V/60A Step-Down Converter

INTV

(OPTIONAL) (OPTIONAL)

BSC050NE2LS

OUT

THERMAL

SENSOR

0.25µH

(0.32mΩ DCR)

220nF

470µF

2.5V ×2 SP

715 3.57k

4.7µF

0.1µF

BSC010NE2LSI

INTV

RUN1,2 ILIM ENTMPB TG1

BOOST1 BOOST2

SW1 EXTV BG1 TAVG TRSET1 SNSA1

SNS1 SNSD1

TCOMP1 V

OSNS1

TH1

LTC3875

–

+ –

TK/SS2TK/SS1

PHASMD

CLKOUT

PGOOD

IFAST

MODE/PLLIN

TG2

SW2

BG2

PGND TRSET2 SNSA2

SNS2

SNSD2

TCOMP2

FREQ

OSNS2

0.1µF

TH2

6V TO 14V

22µF 16V ×4

BSC050NE2LS

0.1µF

BSC010NE2LSI

+ –

100k

1500pF

10k

THERMAL

(0.32mΩ DCR)

3.57k 715

20k

SENSOR

0.25µH

220nF

13.3k

OUT

1.2V 60A

470µF

2.5V ×2 SP

3875 TA02

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC3774 Dual, Multiphase Current Mode Synchronous Step-Down DC/DC

Controller for Sub-Milliohm DCR Sensing

LTC3866 Single Output Current Mode Synchronous Controller with Sub-Milliohm

DCR Sensing

LTC3855 Dual, Multiphase, Synchronous Step-Down DC/DC

Controller with

Differential Output Sensing and DCR Temperature Compensation

LTC3838/LTC3838-1/ LTC3838-2

LTC3890/LTC3890-1/ LTC3890-2/LTC3890-3

Dual, Fast, Accurate Step-Down Controlled On-Time DC/DC Controller with Differential Output Sensing

Dual, High V

, Low IQ 2-Phase Synchronous Step-Down DC/DC

Controller

LTC3861/LTC3861-1 Dual, Multiphase, Synchronous Step-Down Voltage Mode DC/DC

Controller with Diff Amp and Accurate Current Sharing

LTC3856 Single Output, Dual Channel Synchronous Step-Down DC/DC Controller

with Differential Output Sensing and DCR Temperature Compensation

LTC3869 Dual 2-Phase, Synchronous Step-Down DC/DC Controller Synchronous Fixed Frequency 250kHz to 780kHz, 4.5V

LTC3857/LTC3857-1 LTC3858/LTC3858-1

38V Low I Controller with 99% Duty Cycle

, Dual Output 2-Phase Synchronous Step-Down DC/DC

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

For more information www.linear.com/LTC3875

●

www.linear.com/LTC3875

Operates with DrMOS, Power Blocks or External Drives/MOSFETs, 4.5V ≤ V

0.6V ≤ V

OUT

≤ 3.5V

≤ 38V,

Synchronous Fixed Frequency 250kHz to 770kHz,

4.5V ≤ V

≤ 38V, 0.6V ≤ V

OUT

≤ 3.5V

PLL Fixed Frequency 250kHz to 770kHz,

4.5V ≤ V

≤ 38V, 0.8V ≤ V

OUT

≤ 12V

Synchronizable Fixed Frequency 200kHz to 2MHz,

4.5V ≤ V

≤ 38V, 0.8V ≤ V

OUT

≤ 5.5V

PLL Capable Fixed Frequency 50kHz to 900kHz, 4V ≤ V

≤ 60V, 0.8V ≤ V

≤ 24V, IQ = 50µA

OUT

Operates with DrMOS, Power Blocks or External

OUT

≤ 24V

≤ 5V

OUT

≤ 12.5V

Drivers/MOSFETs, 3V ≤ V

Phase-Lockable Fixed 250kHz to 770kHz Frequency,

4.5V ≤ V

≤ V

≤ 38V, 0.8V ≤ V

≤ 38V, 0.6V ≤ V

PLL Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ V

≤ 38V, 0.8V ≤ V

 LINEAR TECHNOLOGY CORPORATION 2013

≤ 24V, IQ = 50µA/170µA

OUT

LT 1115 REV B • PRINTED IN USA

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