Linear LT1713CMS8, LT1713IMS8, LT1714CGN, LT1714IGN Schematic [ru]

LT1713/LT1714

Single/Dual, 7ns, Low Power,

3V/5V/±5V Rail-to-Rail Comparators

U

FEATURES

■

Ultrafast: 7ns at 20mV Overdrive

8.5ns at 5mV Overdrive

■

Rail-to-Rail Inputs

■

Rail-to-Rail Complementary Outputs
(TTL/CMOS Compatible)

■

Specified at 2.7V, 5V and ±5V Supplies

■

Low Power (Per Comparator): 5mA

■

Output Latch

■

Inputs Can Exceed Supplies Without Phase Reversal

■

LT1713: 8-Lead MSOP Package

■

LT1714: 16-Lead Narrow SSOP Package

U

APPLICATIO S

■

High Speed Automatic Test Equipment

■

Current Sense for Switching Regulators

■

Crystal Oscillator Circuits

■

High Speed Sampling Circuits

■

High Speed A/D Converters

■

Pulse Width Modulators

■

Window Comparators

■

Extended Range V/F Converters

■

Fast Pulse Height/Width Discriminators

■

Line Receivers

■

High Speed Triggers UltraFast is a trademark of Linear Technology Corporation.

DESCRIPTIO

The LT®1713/LT1714 are UltraFastTM 7ns, single/dual
comparators featuring rail-to-rail inputs, rail-to-rail
complementary outputs and an output latch. Optimized
for 3V and 5V power supplies, they operate over a single
supply voltage range from 2.4V to 12V or from ±2.4V to
±6V dual supplies.

The LT1713/LT1714 are designed for ease of use in a
variety of systems. In addition to wide supply voltage
flexibility, rail-to-rail input common mode range extends
100mV beyond both supply rails and the outputs are
protected against phase reversal for inputs extending
further beyond the rails. Also, the rail-to-rail inputs may be
taken to opposite rails with no significant increase in input
current. The rail-to-rail matched complementary outputs
interface directly to TTL or CMOS logic and can sink 10mA
to within 0.5V of GND or source 10mA to within 0.7V of V+.

The LT1713/LT1714 have internal TTL/CMOS compatible
latches for retaining data at the outputs. Each latch holds
data as long as its latch pin is held high. Latch pin
hysteresis provides protection against slow moving or
noisy latch signals. The LT1713 is available in the 8-lead
MSOP package. The LT1714 is available in the 16-lead
narrow SSOP package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

A 4× NTSC Subcarrier Voltage-Tunable Crystal Oscillator

1M

1M

100pF

LT1713

MV-209

VARACTOR

DIODE

1M

15pFY1** 100pF

2k

* 1% FILM RESISTOR
** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz

390Ω

5V

2k

+

–

200pF

U

1N4148

1M*

0.047µF
C SELECT
(CHOOSE FOR CORRECT
PLL LOOP RESPONSE)

5V

47k*

LT1004-2.5

3.9k*

1k*

FREQUENCY
OUTPUT

171314 TA01

V

IN

0V TO 5V

LT1713/LT1714 Propagation Delay

vs Input Overdrive

9.0

8.5

8.0

7.5

7.0

6.5

6.0

PROPAGATION DELAY (ns)

5.5

5.0
0

+

t

PD

–

t

PD

10 20 40

INPUT OVERDRIVE (mV)

TA = 25°C

+

= 5V

V

–

V

= 0V

= 100mV

V

STEP

50

30

60

171314 TA02

1

LT1713/LT1714

GN PACKAGE

16-LEAD PLASTIC SSOP

1
2
3
4
5
6
7
8

TOP VIEW

16
15
14
13
12
11
10

9

–IN A
+IN A

V

–

V

+

V

+

V

–

+IN B
–IN B

GND
Q A
Q A
Q B
Q B
GND

LATCH
ENABLE B

LATCH
ENABLE A

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Supply Voltage

V+ to V–............................................................ 12.6V

V+ to GND ........................................................ 12.6V

V– to GND .............................................– 10V to 0.3V

Differential Input Voltage ................................... ±12.6V

Latch Pin Voltage...................................................... 7V

Input and Latch Current..................................... ±10mA

UU

W

PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

TOP VIEW

+

V

1
2

+IN

3

–IN

–

4

V

MS8 PACKAGE

8-LEAD PLASTIC MSOP

T

= 150°C, θJA = 250°C/W

JMAX

8

Q OUT

7

Q OUT

6

GND

5

LATCH
ENABLE

LT1713CMS8
LT1713IMS8

MS8 PART MARKING

LTRD
LTUK

Output Current (Continuous) ..............................±20mA

Operating Temperature Range ................ – 40°C to 85°C

Specified Temperature Range (Note 2)... –40°C to 85°C

Junction Temperature.......................................... 150°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART

NUMBER

LT1714CGN
LT1714IGN

GN PART MARKING

1714
1714I

T

= 150°C, θJA = 120°C/W

JMAX

Consult factory for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

+

V
V

OS

∆VOS/∆T Input Offset Voltage Drift ● 5 µV/°C
I

OS

I

B

V

CM

CMRR Common Mode Rejection Ratio V+ = 5V, 0V ≤ VCM ≤ 5V 60 70 dB

2

Positive Supply Voltage Range ● 2.4 7 V
Input Offset Voltage (Note 4) RS = 50Ω, VCM = V+/2 0.5 4 mV

Input Offset Current 0.1 1 µA

Input Bias Current (Note 5) –7 –1.5 2 µA

Input Voltage Range (Note 9) ● –0.1 V+ + 0.1 V

= 0.8V, C

LATCH

RS = 50Ω, VCM = V+/2 (Note 11) ● 5mV

= 50Ω, VCM = 0V 0.7 mV

R

S

= 50Ω, VCM = V

R

S

+

= 5V, 0V ≤ VCM ≤ 5V ● 58 dB

V

+

= 2.7V, 0V ≤ VCM ≤ 2.7V 57 70 dB

V
V+ = 2.7V, 0V ≤ VCM ≤ 2.7V ● 55 dB

LOAD

= 10pF, V

+

OVERDRIVE

= 20mV, unless otherwise specified.

1mV

● 2 µA

● –15 5 µA

LT1713/LT1714

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PSRR+Positive Power Supply Rejection Ratio 2.4V ≤ V+ ≤ 7V, VCM = 0V 65 80 dB

PSRR–Negative Power Supply Rejection Ratio –7V ≤ V– ≤ 0V, V+ = 5V, VCM = 5V 65 80 dB

A

V

V

OH

V

OL

+

I

–

I

V

IH

V

IL

I

IL

t

PD

∆t

PD

t

r

t

f

t

LPD

t

SU

t

H

t

DPW

f

MAX

t

JITTER

Small-Signal Voltage Gain (Note 10) 1.5 3 V/mV
Output Voltage Swing HIGH I

Output Voltage Swing LOW I

Positive Supply Current (Per Comparator) V+ = 5V, V

Negative Supply Current (Per Comparator) V+ = 5V, V

Latch Pin High Input Voltage ● 2.4 V
Latch Pin Low Input Voltage ● 0.8 V
Latch Pin Current V
Propagation Delay (Note 6) ∆VIN = 100mV, V

Differential Propagation Delay (Note 6) ∆VIN = 100mV, V
Output Rise Time 10% to 90% 4 ns
Output Fall Time 90% to 10% 4 ns
Latch Propagation Delay (Note 7) 8ns
Latch Setup Time (Note 7) 1.5 ns
Latch Hold Time (Note 7) 0ns
Minimum Latch Disable Pulse Width (Note 7) 8 ns
Maximum Toggle Frequency VIN = 100mV
Output Timing Jitter VIN = 630mV

LATCH

= 0.8V, C

I

I

∆V
∆V

LOAD

= 1mA, V+ = 5V, V

OUT

= 10mA, V+ = 5V, V

OUT

= –1mA, V

OUT

= –10mA, V

OUT

= V

LATCH

= 100mV, V

IN

= 100mV, V

IN

= 10pF, V

OVERDRIVE

OVERDRIVE

OVERDRIVE

OVERDRIVE

+

OVERDRIVE
OVERDRIVE
OVERDRIVE

OVERDRIVE

Sine Wave 65 MHz

P-P

(0dBm) Sine Wave, f = 30MHz 15 ps

P-P

OVERDRIVE

OVERDRIVE

OVERDRIVE

= 50mV ● 0.20 0.4 V

= 50mV ● 0.35 0.5 V

= 1V 5 6.5 mA

= 1V 3 4.0 mA

= 20mV 8.0 11.0 ns
= 20mV ● 12.5 ns
= 5mV 9.0 ns

= 20mV 0.5 3 ns

= 20mV, unless otherwise specified.

● 60 dB

● 60 dB

= 50mV ● V+ – 0.5 V+ – 0.2 V

= 50mV ● V+ – 0.7 V+ – 0.4 V

● 8.0 mA

● 4.5 mA

● 10 µA

RMS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

+

V

–

V
V

OS

∆VOS/∆T Input Offset Voltage Drift ● 5 µV/°C
I

OS

I

B

Positive Supply Voltage Range ● 2.4 7 V
Negative Supply Voltage Range (Note 3) ● –7 0 V
Input Offset Voltage (Note 4) RS = 50Ω, VCM = 0V 0.5 3 mV

Input Offset Current 0.1 1 µA

Input Bias Current (Note 5) –7 –1.5 2 µA

LATCH

= 0.8V, C

= 10pF, V

LOAD

R

S

R

S

R

S

OVERDRIVE

= 50Ω, VCM = 0V ● 4mV
= 50Ω, VCM = –5V 0.7 mV
= 50Ω, VCM = 5V 1 mV

= 20mV, unless otherwise specified.

● 2 µA

● –15 5 µA

3

LT1713/LT1714

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CM

CMRR Common Mode Rejection Ratio –5V ≤ VCM ≤ 5V 62 70 dB

PSRR+Positive Power Supply Rejection Ratio 2.4V ≤ V+ ≤ 7V, VCM = –5V 68 80 dB

PSRR–Negative Power Supply Rejection Ratio –7V ≤ V– ≤ 0V, VCM = 5V 65 80 dB

A

V

V

OH

V

OL

+

I

–

I

V

IH

V

IL

I

IL

t

PD

∆t

PD

t

r

t

f

t

LPD

t

SU

t

H

t

DPW

f

MAX

t

JITTER

Input Voltage Range ● –5.1 5.1 V

Small-Signal Voltage Gain (Note 10) 1V ≤ V
Output Voltage Swing HIGH (Note 8) I

Output Voltage Swing LOW (Note 8) I

Positive Supply Current (Per Comparator) V

Negative Supply Current (Per Comparator) V

Latch Pin High Input Voltage ● 2.4 V
Latch Pin Low Input Voltage ● 0.8 V
Latch Pin Current V
Propagation Delay (Note 6) ∆VIN = 100mV, V

Differential Propagation Delay (Note 6) ∆VIN = 100mV, V
Output Rise Time 10% to 90% 4 ns
Output Fall Time 90% to 10% 4 ns
Latch Propagation Delay (Note 7) 8ns
Latch Setup Time (Note 7) 1.5 ns
Latch Hold Time (Note 7) 0ns
Minimum Latch Disable Pulse Width (Note 7) 8 ns
Maximum Toggle Frequency VIN = 100mV
Output Timing Jitter VIN = 630mV

LATCH

= 0.8V, C

LOAD

= 10pF, V

OUT

= 1mA, V

OUT

I

= 10mA, V

OUT

= –1mA, V

OUT

I

= –10mA, V

OUT

OVERDRIVE

OVERDRIVE

= V

LATCH

∆V

= 100mV, V

IN

∆V

= 100mV, V

IN

OVERDRIVE

= 20mV, unless otherwise specified.

● 60 dB

● 65 dB

● 60 dB

≤ 4V, RL = ∞ 1.5 3 V/mV

OVERDRIVE

= 50mV ● 4.5 4.8 V

OVERDRIVE

OVERDRIVE

= 50mV ● 4.3 4.6 V

= 50mV ● 0.20 0.4 V

OVERDRIVE

= 50mV ● 0.35 0.5 V

= 1V 5.5 7.5 mA

● 9.0 mA

= 1V 3.5 4.5 mA

● 5.0 mA

+

OVERDRIVE
OVERDRIVE
OVERDRIVE

OVERDRIVE

Sine Wave 65 MHz

P-P

(0dBm) Sine Wave, f = 30MHz 15 ps

P-P

= 20mV 7 10 ns
= 20mV ● 12 ns
= 5mV 8.5 ns

= 20mV 0.5 3 ns

● 10 µA

RMS

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LT1713C/LT1714C are guaranteed to meet specified
performance from 0°C to 70°C. They are designed, characterized and
expected to meet specified performance from –40°C to 85°C but are not
tested or QA sampled at these temperatures. The LT1713I/LT1714I are
guaranteed to meet specified performance from –40°C to 85°C.

Note 3: The negative supply should not be greater than the ground pin
voltages and the maximum voltage across the positive and negative
supplies should not be greater than 12V.

Note 4: Input offset voltage (V

) is defined as the average of the two

OS

voltages measured by forcing first one output, then the other to V+/2.
Note 5: Input bias current (I

) is defined as the average of the two input

B

currents.

4

Note 6: Propagation delay (t
the actual VOS. Differential propagation delay is defined as:
∆tPD = t

PD

+

–

– t

. Load capacitance is 10pF. Due to test system

PD

) is measured with the overdrive added to

PD

requirements, the LT1713/LT1714 propagation delay is specified with a
1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V
single supplies.

Note 7: Latch propagation delay (t

) is the delay time for the output to

LPD

respond when the latch pin is deasserted. Latch setup time (tSU) is the
interval in which the input signal must remain stable prior to asserting the
latch signal. Latch hold time (tH) is the interval after the latch is asserted in
which the input signal must remain stable. Latch disable pulse width
(t

) is the width of the negative pulse on the latch enable pin that

DPW

latches in new data on the data inputs.

ELECTRICAL CHARACTERISTICS

LT1713/LT1714

Note 8: Output voltage swings are characterized and tested at V+ = 5V and
V– = 0V. They are designed and expected to meet these same
specifications at V– = –5V.

Note 9: The input voltage range is tested under the more demanding
conditions of V

+

= 5V and V– = –5V. The LT1713/LT1714 are designed

Note 10: The LT1713/LT1714 voltage gain is tested at V+ = 5V and
V– = –5V only. Voltage gain at single supply V+ = 5V and V+ = 2.7V is
guaranteed by design and correlation.

Note 11: Input offset voltage over temperature at V
by design and characterization.

and expected to meet these specifications at V– = 0V.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Input Offset Voltage
vs Temperature

2.5
V+ = 5V

–

2.0

V

= 0V

= 2.5V

V

CM

1.5

1.0

0.5

0
–0.5
–1.0
–1.5

INPUT OFFSET VOLTAGE (mV)

–2.0
–2.5

–50

0

–25

TEMPERATURE (°C)

25

50

75

100

171314 G01

125

Propagation Delay
vs Load Capacitance

14

12

10

8

6

TA = 25°C

+

= 5V

V

4

–

V

PROPAGATION DELAY (ns)

= 0V

= 2.5V

V

CM

2

= 20mV

V

OD

= 100mV

V

STEP

0

0 60 100

20

LOAD CAPACITANCE (pF)

t

PD

t

40

+

–

PD

80 120

171314 G02

Propagation Delay
vs Temperature

16

V+ = 5V

–

V

= 0V

14

= 2.5V

V

CM

= 20mV

V

OD

12

10

PROPAGATION DELAY (ns)

= 100mV

V

STEP

= 10pF

C

LOAD

8

6

4

2

0

–25 25 75 125

–50

050

TEMPERATURE (°C)

+

= 2.7V is guaranteed

+

t

PD

–

t

PD

100

171314 G03

Propagation Delay
vs Input Common Mode Voltage

10.0

9.5

9.0

8.5

8.0

7.5

7.0

PROPAGATION DELAY (ns)

6.5

6.0

0.5 1.5 3.5

–0.5

INPUT COMMON MODE (V)

+

t

PD

–

t

PD

2.5

TA = 25°C

+

V

= 5V

–

= 0V

V
V

= 20mV

OD

V

= 100mV

STEP

= 10pF

C

LOAD

4.5

171314 G04

5.5

Propagation Delay
vs Positive Supply Voltage

10.0
TA = 25°C

–

V

= 0V

9.5
= 2.5V

V

CM

V

= 20mV

OD

9.0

V

= 100mV

STEP

= 10pF

C

LOAD

8.5

8.0

7.5

7.0

PROPAGATION DELAY (ns)

6.5

6.0
24 8

0

POSITIVE SUPPLY VOLTAGE (V)

6

+

t

PD

–

t

PD

10 12 14

171314 G05

Positive Supply Current
vs Positive Supply Voltage

7.0
TA = 25°C

= 100mV

∆V

IN

6.5

I

= 0

OUT

V– = –5V

6.0

5.5

5.0

4.5

4.0

2

POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)

4

POSITIVE SUPPLY VOLTAGE (V)

V– = 0V

6810

171314 G06

12

5

LT1713/LT1714

LOADING SINK CURRENT (mA)

0.01

0

OUTPUT VOLTAGE (V)

0.1

0.3

0.4

0.5

1.0

0.7

1

171314 G12

0.2

0.8

0.9

0.6

0.1

10

TA = 25°C
V

+

= 5V

V

–

= 0V

∆V

IN

= 100mV

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Positive Supply Current
vs Switching Frequency

40

TA = 25°C

+

= 5V

V

35

–

V

= 0V

= 10pF

C

LOAD

30

25

20

15

10

5

0

0

POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)

10

SWITCHING FREQUENCY (MHz)

20

30

40

171314 G07

Input Bias Current
vs Temperature

0

V+ = 5V

–

V

= 0V

= 2.5V

V

CM

–1

–2

–3

INPUT BIAS CURRENT (µA)

–4

–25 25 75 125

–50

050

TEMPERATURE (°C)

100

171314 G10

Negative Supply Current
vs Negative Supply Voltage

4.0
TA = 25°C

3.8

∆V

= 100mV

IN

= 0

I

OUT

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

0

NEGATIVE SUPPLY CURRENT (PER COMPARATOR) (mA)

–2

–1

NEGATIVE SUPPLY VOLTAGE (V)

V+ = 5V

V+ = 2.7V

–4

–3

–5

–6

171314 G08

–7

Output High Voltage
vs Source Current

5.0

4.9

4.8

4.7

(V)

4.6

4.5

4.4

4.3

OUTPUT VOLTAGE

TA = 25°C

4.2

+

V

= 5V

–

V

= 0V

4.1
= 100mV

∆V

IN

4.0

0.01

0.1

LOADING SOURCE CURRENT (mA)

1

10

171314 G11

Input Bias Current
vs Input Common Mode Voltage

3

TA = 25°C

+

= 5V

V

2

–

= 0V

V

1

= 0mV

∆V

IN

0

–1

–2

–3

–4

INPUT BIAS CURRENT (µA)

–5

–6

–1

1026

INPUT COMMON MODE VOLTAGE (V)

345

Output Low Voltage
vs Sink Current

171314 G09

200
180

)

160

RMS

140

120

100

80
60
40

OUTPUT TIMING JITTER (ps

20

6

Output Timing Jitter
vs Switching Frequency

TA = 25°C
V
V
V
V
(0dBm) SINE WAVE

0

0

20

40

FREQUENCY (MHz)

+

= 5V

–

= 0V

= 2.5V

CM

= 630mV

IN

Output Rising Edge, 5V Supply

V

IN

P-P

V

OUT

171314 G14 171314 G15

60

80

171314 G13

Output Falling Edge, 5V Supply

V

IN

V

OUT

LT1713/LT1714

U

UU

PI FU CTIO S

LT1713
V+ (Pin 1): Positive Supply Voltage, Usually 5V.

+IN (Pin 2): Noninverting Input.
–IN (Pin 3): Inverting Input.
V– (Pin 4): Negative Supply Voltage, Usually 0V or –5V.
LATCH ENABLE (Pin 5): Latch Enable Input. With a logic

high the output is latched.

LT1714
–IN A (Pin 1): Inverting Input of A Channel Comparator.

+IN A (Pin 2): Noninverting Input of A Channel

Comparator.
V– (Pins 3, 6): Negative Supply Voltage, Usually – 5V. Pins

3 and 6 should be connected together externally.
V+ (Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins

4 and 5 should be connected together externally.
+IN B (Pin 7): Noninverting Input of B Channel

Comparator.

–IN B (Pin 8): Inverting Input of B Channel Comparator.
LATCH ENABLE B (Pin 9):

Comparator. With a logic high, the B output is latched.

Latch Enable Input of B Channel

GND (Pin 6): Ground Supply Voltage, Usually 0V.
Q (Pin 7): Noninverting Output.
Q (Pin 8): Inverting Output.

Q B (Pin 11): Noninverting Output of B Channel

Comparator.
Q B (Pin 12): Inverting Output of B Channel

Comparator.
Q A (Pin 13): Inverting Output of A Channel

Comparator.
Q A (Pin 14): Noninverting Output of A Channel

Comparator.
GND (Pin 15): Ground Supply Voltage of A Channel

Comparator, Usually 0V
LATCH ENABLE A (Pin 16): Latch Enable Input of A Chan-

nel Comparator. With a logic high, the A output is latched.

GND (Pin 10): Ground Supply Voltage of B Channel
Comparator, Usually 0V.

7

LT1713/LT1714

WUUU

APPLICATIO S I FOR ATIO

Common Mode Considerations

The LT1713/LT1714 are specified for a common mode
range of –5.1V to 5.1V on a ±5V supply, or a common
mode range of – 0.1V to 5.1V on a single 5V supply. A more
general consideration is that the common mode range is
from 100mV below the negative supply to 100mV above
the positive supply, independent of the actual supply volt­age. The criteria for common mode limit is that the output
still responds correctly to a small differential input signal.

When either input signal falls outside the common mode
limit, the internal PN diode formed with the substrate can
turn on resulting in significant current flow through the
die. Schottky clamp diodes between the inputs and the
supply rails speed up recovery from excessive overdrive
conditions by preventing these substrate diodes from
turning on.

Input Bias Current

Input bias current is measured with the outputs held at

2.5V with a 5V supply voltage. As with any rail-to-rail
differential input stage, the LT1713/LT1714 bias current
flows into or out of the device depending upon the com­mon mode level. The input circuit consists of an NPN pair
and a PNP pair. For inputs near the negative rail, the NPN
pair is inactive, and the input bias current flows out of the
device; for inputs near the positive rail, the PNP pair is
inactive, and these currents flow into the device. For inputs
far enough away from the supply rails, the input bias
current will be some combination of the NPN and PNP bias
currents. As the differential input voltage increases, the
input current of each pair will increase for one of the inputs
and decrease for the other input. Large differential input
voltages result in different input currents as the input
stage enters various regions of operation. To reduce the
influence of these changing input currents on system
operation, use a low source resistance.

Latch Pin Dynamics

The internal latches of the LT1713/LT1714 comparators
retain the input data (output latched) when their respective
latch pin goes high. The latch pin will float to a low state
when disconnected, but it is better to ground the latch
when a flow-through condition is desired. The latch pin is
designed to be driven with either a TTL or CMOS output.
It has built-in hysteresis of approximately 100mV, so that
slow moving or noisy input signals do not impact latch
performance. For the LT1714, if only one of the compara­tors is being used at a given time, it is best to latch the
second comparator to avoid any possibility of interactions
between the two comparators in the same package.

High Speed Design Techniques

A substantial amount of design effort has made the
LT1713/LT1714 relatively easy to use. As with most high
speed comparators, careful attention to PC board layout
and design is important in order to prevent oscillations.
The most common problem involves power supply by­passing which is necessary to maintain low supply im­pedance. Resistance and inductance in supply wires and
PC traces can quickly build up to unacceptable levels,
thereby allowing the supply voltages to move as the
supply current changes. This movement of the supply
voltages will often result in improper operation. In addi­tion, adjacent devices connected through an unbypassed
supply can interact with each other through the finite
supply impedances.

Bypass capacitors furnish a simple solution to this prob­lem by providing a local reservoir of energy at the device,
thus keeping supply impedance low. Bypass capacitors
should be as close as possible to the LT1713/LT1714
supply pins. A good high frequency capacitor, such as a

0.1µF ceramic, is recommended in parallel with a larger
capacitor, such as a 4.7µF tantalum.

8

WUUU

APPLICATIO S I FOR ATIO

LT1713/LT1714

Poor trace routes and high source impedances are also
common sources of problems. Keep trace lengths as
short as possible and avoid running any output trace
adjacent to an input trace to prevent unnecessary cou­pling. If output traces are longer than a few inches,
provide proper termination impedances (typically 100Ω
to 400Ω) to eliminate any reflections that may occur. Also
keep source impedances as low as possible, preferably
much less than 1kΩ.

The input and output traces should also be isolated from
one another. Power supply traces can be used to achieve

this isolation as shown in Figure 1, a typical topside layout
of the LT1713/LT1714 on a multilayer PC board. Shown is
the topside metal etch including traces, pin escape vias and
the land pads for a GN16 LT1713/LT1714 and its adjacent
X7R 0805 bypass capacitors. The V+, V– and GND traces
all shield the inputs from the outputs. Although the two V
pins are connected internally, they should be shorted to­gether externally as well in order for both to function as
shields. The same is true for the two V+ pins. The two GND
pins are not connected internally, but in most applications
they are both connected directly to the ground plane.

–

1714 F01

Figure 1. Typical LT1714 Topside Metal for Multilayer PCB Layout

9

LT1713/LT1714

WUUU

APPLICATIO S I FOR ATIO

Hysteresis

Another useful technique to avoid oscillations is to provide
positive feedback, also known as hysteresis, from the
output to the input. Increased levels of hysteresis, how­ever, reduce the sensitivity of the device to input voltage
levels, so the amount of positive feedback should be
tailored to particular system requirements. The

REF

50k

+

LT1713 LT1713

–

Q

V

+

IN

LT1713

50Ω

V

IN

–

V

50Ω

50k

Q

V
V
V
(ALL 3 CASES)

+

= 5V

–

= –5V

HYST

= 5mV

Figure 2. Various Configurations for Introducing Hysteresis

LT1713/LT1714 are completely flexible regarding the ap­plication of hysteresis, due to rail-to-rail inputs and the
complementary outputs. Specifically, feedback resistors
can be connected from one or both outputs to their
corresponding inputs without regard to common mode
considerations. Figure 2 shows several configurations.

100k

Q

Q

50Ω

+

V

IN

50Ω

–

V

IN

+

–

100k

Q

Q

171314 F02

10

TYPICAL APPLICATIO S

LT1713/LT1714

U

Simultaneous Full Duplex 75Mbaud Interface
with Only Two Wires

The circuit of Figure 3 shows a simple, fully bidirectional,
differential 2-wire interface that gives good results to
75Mbaud, using the LT1714. Eye diagrams under condi­tions of unidirectional and bidirectional communication
are shown in Figures 4 and 5. Although not as pristine as
the unidirectional performance of Figure␣ 4, the perfor­mance under simultaneous bidirectional operation is still
excellent. Because the LT1714 input voltage range ex­tends 100mV beyond both supply rails, the circuit works
with a full ±3V (one whole VS up or down) of ground
potential difference.

750k

3V

4

2

RxD

TxD

14

13

750k

49.9Ω

49.9Ω

16

LE

1/2

LT1714

3

15

7

8

+

LT1714

LE

–

9

+

–

1/2

1

100k

3V

5

11

12

10

6

100k

R2A

2.55k

R3A
124Ω

R3B
124Ω

R2B

2.55k

3V 3V

R1A
499Ω

R

OA

140Ω

6-FEET

R1B
499Ω

TWISTED PAIR

≈ 120Ω

Z

O

DIODES: BAV99
×4

The circuit works well with the resistor values shown, but
other sets of values can be used. The starting point is the
characteristic impedance, ZO, of the twisted-pair cable.
The input impedance of the resistive network should
match the characteristic impedance and is given by:

RR

=

2

••

IN O

RRRR

O

RRR

123

++

2123

+

||( )

•||( )

[]

This comes out to 120Ω for the values shown. The
Thevenin equivalent source voltage is given by:

RRR

+

(–)

VV

=

TH S

231

•
RRR

++

()

231

R

•

RRRR

++

2123

O

R1C

499Ω

R

140Ω

R1D

499Ω

2.55k

OB

124Ω

124Ω

2.55k

O

•||( )

[]

2

1

100k

R2C

R3C

R3D

R2D

3V

5

11

1/2

LT1714

12

6

10

100k

+

LT1714

–

LE

9

1/2

750k

3V

4

14

16

750k

49.9Ω

49.9Ω

RxD

13

TxD

LE

15

3

7

+

8

–

171314 F03

Figure 3. 75Mbaud Full Duplex Interface on Two Wires

11

LT1713/LT1714

TYPICAL APPLICATIO S

U

171112 F04

Figure 4. Performance of Figure 3’s Circuit When
Operated Unidirectionally. Eye is Wide Open

This amounts to an attenuation factor of 0.0978 with the
values shown. (The actual voltage on the lines will be cut
in half again due to the 120Ω ZO.) The reason this
attenuation factor is important is that it is the key to
deciding the ratio between the R2-R3 resistor divider in
the receiver path. This divider allows the receiver to reject
the large signal of the local transmitter and instead sense
the attenuated signal of the remote transmitter. Note that
in the above equations, R2 and R3 are not yet fully
determined because they only appear as a sum. This
allows the designer to now place an additional constraint
on their values. The R2-R3 divide ratio should be set to
equal half the attenuation factor mentioned above or:

R3/R2 = 1/2 • 0.09761.

Having already designed R2 + R3 to be 2.653k (by allocat­ing input impedance across RO, R1 and R2 + R3 to get the
requisite 120Ω), R2 and R3 then become 2529Ω and

123.5Ω respectively. The nearest 1% value for R2 is 2.55k
and that for R3 is 124Ω.

Voltage-Tunable Crystal Oscillator

The front page application is a variant of a basic crystal
oscillator that permits voltage tuning of the output fre­quency. Such voltage-controlled crystal oscillators (VCXO)
are often employed where slight variation of a stable
carrier is required. This example is specifically intended to
provide a 4× NTSC sub-carrier tunable oscillator suitable
for phase locking.

171112 F05

Figure 5. Performance When Operated Simultaneous
Bidirectionally (Full Duplex). Crosstalk Appears as Noise.
Eye is Slightly Shut But Performance is Still Excellent

The LT1713 is set up as a crystal oscillator. The varactor
diode is biased from the tuning input. The tuning network
is arranged so a 0V to 5V drive provides a reasonably
symmetric, broad tuning range around the 14.31818MHz
center frequency. The indicated selected capacitor sets
tuning bandwidth. It should be picked to complement loop
response in phase locking applications. Figure 6 is a plot
of tuning input voltage versus frequency deviation. Tuning
deviation from the 4× NTSC 14.31818MHz center fre­quency exceeds ±240ppm for a 0V to 5V input.

1

Using the design value of R2 + R3 = 2.653k rather than the implementation value of 2.55k +

124Ω = 2.674k.

9

8

7

6

5

14.31818MHz

4

3

2

FREQUENCY DEVIATION (kHz)

1

14.314.0MHz

0

0

13

2

INPUT VOLTAGE (V)

Figure 6. Control Voltage vs Output Frequency for the First Page
Application Circuit. Tuning Deviation from Center Frequency
Exceeds ±240ppm

14.3217MHz

4

5

171112 F06

12

TYPICAL APPLICATIO S

LT1713/LT1714

U

1MHz Series Resonant Crystal Oscillator
with Square and Sinusoid Outputs

Figure 7 shows a classic 1MHz series resonant crystal
oscillator. At series resonance, the crystal is a low imped­ance and the positive feedback connection is what brings
about oscillation at the series resonant frequency. The RC
feedback around the other path ensures that the circuit
does not find a stable DC operating point and refuse to
oscillate. The comparator output is a 1MHz square wave
(top trace of Figure 8) with jitter measured at better than
28ps

on a 5V supply and 40ps

RMS

on a 3V supply. At

RMS

Pin 2 of the comparator, on the other side of the crystal, is
a clean sine wave except for the presence of the small high
frequency glitch (middle trace of Figure 8). This glitch is

R10

1k

1MHz

R4

AT-CUT

V

S

2

3

+

–

C1

0.1µF

V

LT1713

LE

6

R1
1k

R2
1k

210Ω

S

1

7

8

4

5

R3
1k

R5

6.49k

C5
100pF

SQUARE

caused by the fast edge of the comparator output feeding
back through crystal capacitance. Amplitude stability of
the sine wave is maintained by the fact that the sine wave
is basically a filtered version of the square wave. Hence,
the usual amplitude control loops associated with sinusoi­dal oscillators are not necessary.2 The sine wave is filtered
and buffered by the fast, low noise LT1806 op amp. To
remove the glitch, the LT1806 is configured as a bandpass
filter with a Q of 5 and unity-gain center frequency of
1MHz, with its output shown as the bottom trace of
Figure␣ 8. Distortion was measured at – 70dBc and – 60dBc
on the second and third harmonics, respectively.

2

Amplitude will be a linear function of comparator output swing, which is supply dependent
and therefore adjustable. The important difference here is that any added amplitude
stabilization or control loop will not be faced with the classical task of avoiding regions of
nonoscillation versus clipping.

C4

100pF

R6
162Ω

C3
100pF

R9

2k

V

S

C2

0.1µF

R8
2k

V

R7

S

15.8k

–

LT1806

+

7

4

171314 F07

6

SINE

1

2

3

Figure 7. LT1713 Comparator is Configured as a Series Resonant Xtal Oscillator.
LT1806 Op Amp is Configured in a Q = 5 Bandpass with fC = 1MHz

3V/DIV

1V/DIV

1V/DIV

200ns/DIV

171112 F08

Figure 8. Oscillator Waveforms with VS = 3V. Top is Comparator Output. Middle is
Xtal Feedback to Pin 2 at LT1713 (Note the Glitches). Bottom is Buffered, Inverted
and Bandpass Filtered with a Q = 5 by LT1806

13

LT1713/LT1714

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

MS8 Package

8-Lead Plastic MSOP

(LTC DWG # 05-08-1660)

0.118 ± 0.004*
(3.00 ± 0.102)

8

7

6

5

0.193 ± 0.006
(4.90 ± 0.15)

12

0.043
(1.10)

MAX

0.007
(0.18)

0.021

± 0.006

(0.53 ± 0.015)

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

° – 6° TYP

0

SEATING

PLANE

0.009 – 0.015
(0.22 – 0.38)

0.0256
(0.65)

BSC

4

3

0.118 ± 0.004**
(3.00 ± 0.102)

0.034

(0.86)

REF

0.005

± 0.002

(0.13 ± 0.05)

MSOP (MS8) 1100

14

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

16-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.189 – 0.196*
(4.801 – 4.978)

16

15

14

12 11 10

13

LT1713/LT1714

0.009

(0.229)

9

REF

0.015

0.004

±

(0.38 ± 0.10)

0.007 – 0.0098

(0.178 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0° – 8° TYP

× 45°

U

TYPICAL APPLICATIO

Rail-to-Rail Pulse Width Modulator
Using the LT1714

Binary modulation schemes are used in order to improve
efficiency and reduce physical circuit size. They do this by
reducing the power dissipation in the output driver tran­sistors. In a normal Class A or Class AB amplifier, voltage
drop and current flow exist simultaneously in the output
transistors and power losses proportional to V • I occur.
In a binary modulation scheme, the output transistors,
whether bipolar or FET, are switched hard-on and hard-off
so that voltage drops do not occur simultaneously with

0.229 – 0.244

(5.817 – 6.198)

0.053 – 0.068

(1.351 – 1.727)

0.008 – 0.012

(0.203 – 0.305)

12

5

4

3

678

0.004 – 0.0098
(0.102 – 0.249)

0.0250

(0.635)

BSC

0.150 – 0.157**
(3.810 – 3.988)

GN16 (SSOP) 1098

current flow. The circuit of Figure 9 shows an example of
a binary modulation scheme, in this case pulse width
modulation.

The LT1809 is configured as an integrator in order to
generate nice linear rail-to-rail voltage ramps. The polarity
of the ramp is determined by the output of the LT1714’s
comparator A into R4. The heavy hysteresis of R1 around
the LT1714’s comparator A combined with the feedback of
the LT1809 force the devices to perpetually reverse each
other, resulting in a 1MHz triangle wave. This constitutes
the usual first half of any pulse width modulator, but the

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LT1713/LT1714

TYPICAL APPLICATIO

U

forte of this particular implementation is that it is rail-to­rail allowing a full-scale analog input. Once the triangle
wave is achieved, the remainder of the pulse width modu­lator is easy, and is constituted by doing a simple compari­son using the second half of the LT1714. The triangle wave
and the relatively slow moving analog signal (the one to be
modulated or to do the modulation, depending on how you
look at it) are fed into the inputs of comparator B, whose
output is then the PWM representation of the analog input
voltage. The higher the analog input voltage, the wider the
output pulse. The time averaged output level is thus
proportional to the analog input voltage. This binary
output can then be fed into power transistors with direct
control over motor or speaker winding current, for

R1

26.1Ω

+

V

+

2

+

1/2 LT1714

1

–

3

+

V

= 2.7V TO 7V

V

4

14

A

13

16

15

R5
1k

+

V

R2
2k

R3
2k

R4

499Ω

500pF

C2

0.01µFR61k

ANALOG

C1

2

3

–

LT1809

+

INPUT

0.001µF

+

V

1

7

6

4

example, with their inherent lowpass characteristic. Care
must be taken to avoid cross conduction in the output
power transistors.

The linearity of the pulse width modulated signal can easily
be ascertained by putting a simple 2-pole RC filter at the
output (as shown in Figure 9). This demodulates the signal
which can then be viewed and compared with the original
input signal on an oscilloscope. Using a spectrum analyzer
and a 1kHz reference signal, this circuit’s distortion prod­ucts were measured as better than –50dBc (0.3%) to
about 3.5V
clips at 5V

ANTIALIASING

FILTER

1k

C4

21Ω

C3

100pF

1MHz
TRIANGLE
WAVE

7

8

, degrading to –30dBc (3%) as the circuit

P-P

on a single 5V supply.

P-P

+

V

+

B

1/2 LT1714

–

9

6

5

11

10

COMPLEMENTARY

1MHz PWM

OUTPUTS

16kHz ANALOG FILTER

FOR LINEARITY MEASUREMENT

1k 10k

0.01µF

C5

0.001µF

12

C6

171314 F09

Figure 9. Rail-to-Rail 1MHz Pulse Width Modulator

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1016 UltraFast Precision Comparator Industry Standard 10ns Comparator
LT1116 12ns Single Supply Ground Sensing Comparator Single Supply Version of the LT1016
LT1394 7ns, UltraFast Single Supply Comparator 6mA Single Supply Comparator
LT1671 60ns, Low Power, Single Supply Comparator 450µA Single Supply Comparator
LT1711/LT1712 Single/Dual, 4.5ns, 3V/5V/±5V Rail-to-Rail Comparators Faster Versions of LT1713/LT1714
LT1719 4.5ns, Single Supply 3V/5V Comparator 4mA Comparator with Rail-to-Rail Outputs
LT1720/LT1721 Dual/Quad, 4.5ns, Single Supply Comparator Dual/Quad Version of the LT1719

171314f LT/TP 0501 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2000

16

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

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