LT1225
Very High Speed
Operational Amplifier
EATU
F
■
Gain of 5 Stable
■
150MHz Gain Bandwidth
■
400V/µs Slew Rate
■
20V/mV DC Gain, RL = 500Ω
■
1mV Maximum Input Offset Voltage
■
±12V Minimum Output Swing into 500Ω
■
Wide Supply Range: ±2.5V to ±15V
■
7mA Supply Current
■
90ns Settling Time to 0.1%, 10V Step
■
Drives All Capacitive Loads
PPLICATI
A
■
Wideband Amplifiers
■
Buffers
■
Active Filters
■
Video and RF Amplification
■
Cable Drivers
■
Data Acquisition Systems
RE
S
O
U
S
DUESCRIPTIO
The LT1225 is a very high speed operational amplifier with
excellent DC performance. The LT1225 features reduced
input offset voltage and higher DC gain than devices with
comparable bandwidth and slew rate. The circuit is a
single gain stage with outstanding settling characteristics.
The fast settling time makes the circuit an ideal choice for
data acquisition systems. The output is capable of driving
a 500Ω load to ±12V with ±15V supplies and a 150Ω load
to ±3V on ±5V supplies. The circuit is also capable of
driving large capacitive loads which makes it useful in
buffer or cable driver applications.
The LT1225 is a member of a family of fast, high performance amplifiers that employ Linear Technology
Corporation’s advanced bipolar complementary
processing.
U
O
A
PPLICATITYPICAL
20MHz,AV = 50 Instrumentation Amplifier
+
LT1225
–
1k
+
V
IN
–
250Ω
250Ω
200pF
1k
–
LT1225
+
1k
1k
10k
+
LT1225
–
10k
V
OUT
LT1225 TA01
Gain of 5 Pulse Response
LT1225 TA02
1
LT1225
WU
U
PACKAGE
/
O
RDER I FOR ATIO
W
O
A
LUTEXI T
S
Total Supply Voltage (V+ to V–) .............................. 36V
Differential Input Voltage .........................................±6V
Input Voltage ............................................................±V
Output Short Circuit Duration (Note 1) ............Indefinite
Operating Temperature Range
LT1225C................................................ 0°C to 70°C
Maximum Junction Temperature
Plastic Package .............................................. 150°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
LECTRICAL C CHARA TERIST
E
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
I
OS
I
B
e
n
i
n
R
IN
C
IN
CMRR Common-Mode Rejection Ratio VCM = ±12V 94 115 dB
PSRR Power Supply Rejection Ratio VS = ±5V to ±15V 86 95 dB
A
VOL
V
OUT
I
OUT
SR Slew Rate (Note 3) 250 400 V/µs
GBW Gain Bandwidth f = 1MHz 150 MHz
tr, t
f
t
s
R
O
I
S
Input Offset Voltage (Note 2) 0.5 1.0 mV
Input Offset Current 100 400 nA
Input Bias Current 48 µA
Input Noise Voltage f = 10kHz 7.5 nV/√Hz
Input Noise Current f = 10kHz 1.5 pA/√Hz
Input Resistance VCM = ±12V 24 40 MΩ
Input Capacitance 2pF
Input Voltage Range + 12 14 V
Input Voltage Range – –13 –12 V
Large Signal Voltage Gain V
Output Swing RL = 500Ω±12.0 ±13.3 V
Output Current V
Full Power Bandwidth 10V Peak, (Note 4) 6.4 MHz
Rise Time, Fall Time A
Overshoot A
Propagation Delay 50% VIN to 50% V
Settling Time 10V Step, 0.1%, AV = –5 90 ns
Differential Gain f = 3.58MHz, AV = 5, RL = 150Ω 1.0 %
Differential Phase f = 3.58MHz, AV = 5, RL = 150Ω 1.7 Deg
Output Resistance A
Supply Current 79 mA
A
WUW
ARB
U
G
S
I
TOP VIEW
1
NULL
S
8-LEAD PLASTIC DIP
ICS
VS = ±15V, TA = 25°C, VCM = 0V unless otherwise noted.
Differential 70 kΩ
= ±10V, RL = 500Ω 12.5 20 V/mV
OUT
= ±12V 24 40 mA
OUT
= 5, 10% to 90%, 0.1V 7 ns
VCL
= 5, 0.1V 20 %
VCL
OUT
= 5, f = 1MHz 4.5 Ω
VCL
2
–IN
3
+IN
–
4
V
N8 PACKAGE
T
= 15O°C, θJA = 130°C/W (N8)
J MAX
= 15O°C, θJA = 220°C/W (S8)
T
J MAX
8
NULL
+
V
7
OUT
6
NC
5
S8 PACKAGE
8-LEAD PLASTIC SOIC
LT1225 PO01
7ns
ORDER PART
NUMBER
LT1225CN8
LT1225CS8
S8 PART MARKING
1225
2
LT1225
LECTRICAL C CHARA TERIST
E
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
I
OS
I
B
CMRR Common-Mode Rejection Ratio VCM = ±2.5V 94 115 dB
A
VOL
V
OUT
I
OUT
SR Slew Rate (Note 3) 250 V/µs
GBW Gain Bandwidth f = 1MHz 100 MHz
tr, t
f
t
s
I
S
Input Offset Voltage (Note 2) 1.0 2.0 mV
Input Offset Current 100 400 nA
Input Bias Current 48 µA
Input Voltage Range + 2.5 4 V
Input Voltage Range – –3 – 2.5 V
Large-Signal Voltage Gain V
Output Voltage RL = 500Ω±3.0 ±3.7 V
Output Current V
Full Power Bandwidth 3V Peak, (Note 4) 13.3 MHz
Rise Time, Fall Time A
Overshoot A
Propagation Delay 50% VIN to 50% V
Settling Time – 2.5V to 2.5V, 0.1%, AV = –4 70 ns
Supply Current 79 mA
ICS
VS = ±5V, TA = 25°C, VCM = 0V unless otherwise noted.
= ±2.5V, RL = 500Ω 10 15 V/mV
OUT
= ±2.5V, RL = 150Ω 13 V/mV
V
OUT
= 150Ω±3.0 ±3.3 V
R
L
= ±3V 20 40 mA
OUT
= 5, 10% to 90%, 0.1V 9 ns
VCL
= 5, 0.1V 10 %
VCL
OUT
9ns
LECTRICAL C CHARA TERIST
E
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
I
OS
I
B
CMRR Common-Mode Rejection Ratio VS = ±15V, VCM = ±12V and VS = ±5V, VCM = ±2.5V 93 115 dB
PSRR Power Supply Rejection Ratio VS = ±5V to ±15V 85 95 dB
A
VOL
V
OUT
I
OUT
SR Slew Rate VS = ±15V, (Note 3) 250 400 V/µs
I
S
Note 1: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefinitely.
Note 2: Input offset voltage is tested with automated test equipment
in <1 second.
Input Offset Voltage VS = ±15V, (Note 2) 0.5 1.5 mV
= ±5V, (Note 2) 1.0 2.5 mV
V
S
Input V
Input Offset Current VS = ±15V and VS = ±5V 100 600 nA
Input Bias Current VS = ±15V and VS = ±5V 4 9 µA
Large Signal Voltage Gain VS = ±15V, V
Output Swing VS = ±15V, RL = 500Ω±12.0 ±13.3 V
Output Current VS = ±15V, V
Supply Current VS = ±15V and VS = ±5V 7 10.5 mA
Drift 10 µV/°C
OS
= ±5V, V
V
S
= ±5V, RL = 500Ω or 150Ω ±3.0 ±3.3 V
V
S
= ±5V, V
V
S
0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
ICS
= ±10V, RL = 500Ω 10 12.5 V/mV
OUT
= ±2.5V, RL = 500Ω 8 10 V/mV
OUT
= ±12V 24 40 mA
OUT
= ±3V 20 40 mA
OUT
Note 3: Slew rate is measured between ±10V on an output swing of ±12V
on ±15V supplies, and ±2V on an output swing of ±3.5V on ±5V supplies.
Note 4: Full power bandwidth is calculated from the slew rate
measurement: FPBW = SR/2πVp.
3
LT1225
SUPPLY VOLTAGE (±V)
0
0
OUTPUT VOLTAGE SWING (V)
5
10
15
20
5101520
LT1225 TPC03
TA = 25°C
R
L
= 500Ω
∆V
OS
= 30mV
+V
SW
–V
SW
LOAD RESISTANCE (Ω)
10
50
OPEN-LOOP GAIN (dB)
80
90
100
100 1k 10k
LT1225 TPC06
70
60
TA = 25°C
VS = ±15V
VS = ±5V
TEMPERATURE (°C)
–50
25
OUTPUT SHORT-CIRCUIT CURRENT (mA)
35
40
50
55
–25 25 75 125
LT1225 TPC09
100500
30
45
VS = ±5V
SINK
SOURCE
UW
Y
PICA
20
15
LPER
F
O
R
AT
CCHARA TERIST
E
C
ICS
Input Common-Mode Range vs Output Voltage Swing vs
Supply Voltage Supply Current vs Supply Voltage Supply Voltage
8.0
TA = 25°C
< 1mV
∆V
OS
TA = 25°C
7.5
10
5
MAGNITUDE OF INPUT VOLTAGE (V)
0
0
+V
CM
–V
5101520
SUPPLY VOLTAGE (±V)
CM
LT1225 TPC01
7.0
SUPPLY CURRENT (mA)
6.5
6.0
0
5101520
SUPPLY VOLTAGE (±V)
LT1225 TPC02
Output Voltage Swing vs Input Bias Current vs Input Open-Loop Gain vs
Resistive Load Common-Mode Voltage Resistive Load
30
TA = 25°C
= 30mV
∆V
25
20
15
10
OUTPUT VOLTAGE SWING (Vp-p)
OS
5
0
10
100 1k 10k
LOAD RESISTANCE (Ω)
VS = ±15V
VS = ±5V
LT1225 TPC04
5.0
VS = ±15V
= 25°C
T
A
+ I
I
B+
B–
IB =
4.5
2
4.0
3.5
INPUT BIAS CURRENT (µA)
3.0
–10 0 10 15
–15
–5 5
INPUT COMMON-MODE VOLTAGE (V)
LT1225 TPC05
Supply Current vs Temperature Input Bias Current vs Temperature Temperature
10
VS = ±15V
9
8
7
6
SUPPLY CURRENT (mA)
5
4
4
–25 25 75 125
–50
TEMPERATURE (°C)
100500
LT1225 TPC07
INPUT BIAS CURRENT (µA)
5.0
4.75
4.5
4.25
4.0
3.75
3.5
–25 25 75 125
–50
TEMPERATURE (°C)
VS = ±15V
+ I
I
B+
B–
IB =
2
100500
LT1225 TPC08
Output Short-Circuit Current vs
UW
FREQUENCY (Hz)
1k
0
COMMON MODE REJECTION RATIO (dB)
20
40
60
80
100
120
10k 100k 1M 10M
LTXXXX • TPCXX
100M
VS = ±15V
T
A
= 25°C
FREQUENCY (HZ)
1M
4
VOLTAGE MAGNITUDE (dB)
8
12
16
20
24
10M 100M
VS = ±15V
T
A
= 25°C
A
V
= –5
C = 100pF
C = 0pF
C = 50pF
LT1225 TPC15
6
10
14
18
22
C = 1000pF
C = 500pF
Y
PICA
1000
100
LPER
F
O
R
AT
CCHARA TERIST
E
C
ICS
Power Supply Rejection Ratio vs Common-Mode Rejection Ratio vs
Input Noise Spectral Density Frequency Frequency
INPUT CURRENT NOISE (pA/√Hz)
100
VS = ±15V
= 25°C
T
80
60
A
+PSRR
10
i
n
1.0
LT1225
–PSRR
10M 100M
LT1225 TPC11
e
10
VS = ±15V
= 25°C
T
INPUT VOLTAGE NOISE (nV/√Hz)
A
= 101
A
V
= 100k
R
S
1
10 1k 10k 100k
100
n
FREQUENCY (Hz)
LT1225 TPC10
0.1
0.01
40
20
POWER SUPPLY REJECTION RATIO (dB)
0
100
10k 100k 1M
1k
FREQUENCY (Hz)
Voltage Gain and Phase vs Frequency Response vs
Frequency Output Swing vs Settling Time Capacitive Load
100
80
60
40
VOLTAGE GAIN (dB)
20
TA = 25°C
0
100
1k
VS = ±5V
V
= ±5V
V
S
10k 100k 1M
FREQUENCY (Hz)
= ±15V
S
VS = ±15V
10M 100M
LT1225 TPC13
100
80
60
40
20
0
10
VS = ±15
8
= 25°C
T
A
10mV SETTLING
PHASE MARGIN (DEG)
6
4
2
0
–2
OUTPUT SWING (V)
–4
–6
–8
–10
0
AV = –5
A
V
20
40
SETTLING TIME (ns)
= 5
AV = 5
AV = –5
60
80
100
LTC1225 TPC14
120
Closed-Loop Output Impedance vs
Frequency Gain Bandwidth vs Temperature Slew Rate vs Temperature
100
VS = ±15V
T
= 25°C
A
= 5
A
V
10
1
0.1
OUTPUT IMPEDANCE (Ω)
0.01
10k
100k
FREQUENCY (Hz)
1M
10M
LT1225 TPC16
100M
153
VS = ±15V
152
151
150
149
GAIN BANDWIDTH (MHz)
148
147
–50
–25 0
50 100 125
25 75
TEMPERATURE (˚C)
LT1225 TPC17
500
VS = ±15V
= –5
A
V
450
400
350
300
SLEW RATE (V/µs)
250
200
–50
–25 0
–SR
+SR
50 100 125
25 75
TEMPERATURE (˚C)
LT1225 TPC18
5
LT1225
PPLICATI
A
U
O
S
I FOR ATIO
WU
U
The LT1225 may be inserted directly into HA2541, HA2544,
AD847, EL2020 and LM6361 applications, provided that
the amplifier configuration is a noise gain of 5 or greater,
and the nulling circuitry is removed. The suggested nulling
circuit for the LT1225 is shown below.
Offset Nulling
+
V
5k
1
+
LT1225
–
8
7
4
–
V
3
2
0.1µF
6
0.1µF
LT1225 AI01
Layout and Passive Components
As with any high speed operational amplifier, care must be
taken in board layout in order to obtain maximum performance. Key layout issues include: use of a ground plane,
minimization of stray capacitance at the input pins, short
lead lengths, RF-quality bypass capacitors located close
to the device (typically 0.01µF to 0.1µF), and use of low
ESR bypass capacitors for high drive current applications
(typically 1µF to 10µF tantalum). Sockets should be
avoided when maximum frequency performance is
required, although low profile sockets can provide
reasonable performance up to 50MHz. For more details
see Design Note 50. Feedback resistor values greater than
5k are not recommended because a pole is formed with the
input capacitance which can cause peaking. If feedback
resistors greater than 5k are used, a parallel
capacitor of 5pF to 10pF should be used to cancel the input
pole and optimize dynamic performance.
Transient Response
Small Signal, AV = 5 Small Signal, AV = –5
LT1225 AI02
The large-signal response in both inverting and noninverting gain shows symmetrical slewing characteristics. Normally the noninverting response has a much faster rising
edge than falling edge due to the rapid change in input
common-mode voltage which affects the tail current of the
input differential pair. Slew enhancement circuitry has
been added to the LT1225 so that the noninverting slew
rate response is balanced.
Large Signal, AV = 5 Large Signal, AV = –5
LT1225 AI03
Input Considerations
Resistors in series with the inputs are recommended for
the LT1225 in applications where the differential input
voltage exceeds ±6V continuously or on a transient basis.
An example would be in noninverting configurations with
high input slew rates or when driving heavy capacitive
loads. The use of balanced source resistance at each input
is recommended for applications where DC accuracy must
be maximized.
The LT1225 gain-bandwidth is 150MHz when measured at
1MHz. The actual frequency response in gain of 5 is
considerably higher than 30MHz due to peaking caused by
a second pole beyond the gain of 5 crossover point. This
is reflected in the small-signal transient response. Higher
noise gain configurations exhibit less overshoot as seen in
the inverting gain of 5 response.
6
Capacitive Loading
The LT1225 is stable with all capacitive loads. This is
accomplished by sensing the load induced output pole and
adding compensation at the amplifier gain node. As the
capacitive load increases, both the bandwidth and phase
margin decrease so there will be peaking in the frequency
LT1225
PPLICATI
A
U
O
S
I FOR ATIO
WU
U
domain and in the transient response. The photo of the
small-signal response with 1000pF load shows 50% peaking. The large-signal response with a 10,000pF load shows
the output slew rate being limited by the short-circuit
current.
AV = –5, CL = 1000pF
AV = 5, CL = 10,000pF
LT1225 AI04
The LT1225 can drive coaxial cable directly, but for best
pulse fidelity the cable should be doubly terminated with
a resistor in series with the output.
Compensation
The LT1225 has a typical gain-bandwidth product of
150MHz which allows it to have wide bandwidth in high
gain configurations (i.e., in a gain of 10 it will have a
bandwidth of about 15MHz). The amplifier is stable in a
noise gain of 5 so the ratio of the output signal to the
inverting input must be 1/5 or less. Straightforward gain
configurations of 5 or –4 are stable, but there are a few
configurations that allow the amplifier to be stable for
lower signal gains (the noise gain, however, remains 5 or
more). One example is the summing amplifier shown in
the typical applications section below. Each input signal
has a gain of – RF/RIN to the output, but it is easily seen that
this configuration is equivalent to a gain of –4 as far as the
amplifier is concerned. Lag compensation can also be
used to give a low frequency gain less than 5 with a high
frequency gain of 5 or greater. The example below has a
DC gain of one, but an AC gain of 5. The break frequency
of the RC combination across the amplifier inputs should
be approximately a factor of 10 less than the gain bandwidth of the amplifier divided by the high frequency gain
(in this case 1/10 of 150MHz/5 or 3MHz).
CA
V
U
O
PPLICATITYPI
L
SA
Cable Driving
Lag Compensation
+
V
IN
R2
250Ω
LT1225
–
R1
1k
IN
500Ω
100pF
+
LT1225
–
2k
AV = 1, f < 3MHz
V
OUT
LT1225 TA03
R3
75 Ω
75 CABLE
Ω
R4
75
Ω
LT1225 TA04
V
OUT
Wein Bridge Oscillator
#327
LAMP
1.5k
100pF
–
LT1225
+
100pF
430Ω
1.5k
V
OUT
>10V
1MHz
LT1225 TA05
P-P
V
IN1
V
IN2
VINn
RIN =
Summing Amplifier
R
IN
R
IN
R
IN
nR
F
4
–
LT1225
+
R
F
V
OUT
LT1225 TA06
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
7
LT1225
E
NULL
1 8
W
A
W
SPL
I
IIFED S
CH
V+
7
3
4V–
PACKAGEDESCRIPTI
TI
O
C
BIAS 1
–IN+IN
2
BIAS 2
U
Dimensions in inches (millimeters) unless otherwise noted.
6 OUT
LT1224 • TA10
0.300 – 0.320
(7.620 – 8.128)
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
+0.025
0.325
–0.015
+0.635
8.255
()
–0.381
0.010 – 0.020
(0.254 – 0.508)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
TYP
0.045 ± 0.015
(1.143 ± 0.381)
(2.540 ± 0.254)
× 45°
0.008 – 0.010
(0.203 – 0.254)
0.045 – 0.065
(1.143 – 1.651)
0.100 ± 0.010
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
N8 Package
8-Lead Plastic DIP
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
S8 Package
8-Lead Plastic SOIC
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
0.020
(0.508)
MIN
0.228 – 0.244
(5.791 – 6.197)
0.400
(10.160)
MAX
876
12
8
3
0.189 – 0.197
(4.801 – 5.004)
7
6
5
4
5
0.250 ± 0.010
(6.350 ± 0.254)
N8 0392
0.150 – 0.157
(3.810 – 3.988)
8
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900
●
FAX
: (408) 434-0507
●
TELEX
: 499-3977
1
LINEAR TECHNOLOGY CORPORATION 1992
3
2
4
LT/GP 1092 5K REV A
SO8 0392
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