Linear LT1028CS8, LT1128CS8 Schematic

FEATURES

■

Voltage Noise

1.1nV/√Hz Max at 1kHz

0.85nV/√Hz Typ at 1kHz

1.0nV/√Hz Typ at 10Hz 35nV

■

Voltage and Current Noise 100% Tested

■

Gain-Bandwidth Product

Typ, 0.1Hz to 10Hz

P-P

LT1028: 50MHz Min LT1128: 13MHz Min

■

Slew Rate

LT1028: 11V/µs Min LT1128: 5V/µs Min

■

Offset Voltage: 40µV Max

■

Drift with Temperature: 0.8µV/°C Max

■

Voltage Gain: 7 Million Min

■

Available in 8-Pin SO Package

U

APPLICATIO S

LT1028/LT1128

Ultralow Noise Precision

High Speed Op Amps

U

DESCRIPTIO

The LT®1028(gain of –1 stable)/LT1128(gain of +1 stable) achieve a new standard of excellence in noise performance with 0.85nV/√Hz 1kHz noise, 1.0nV/√Hz 10Hz noise. This ultralow noise is combined with excellent high speed specifications (gain-bandwidth product is 75MHz for LT1028, 20MHz for LT1128), distortion-free output, and true precision parameters (0.1µV/°C drift, 10µV offset voltage, 30 million voltage gain). Although the LT1028/ LT1128 input stage operates at nearly 1mA of collector current to achieve low voltage noise, input bias current is only 25nA.

The LT1028/LT1128’s voltage noise is less than the noise of a 50Ω resistor. Therefore, even in very low source impedance transducer or audio amplifier applications, the LT1028/LT1128’s contribution to total system noise will be negligible.

, LTC and LT are registered trademarks of Linear Technology Corporation

■

Low Noise Frequency Synthesizers

■

High Quality Audio

■

Infrared Detectors

■

Accelerometer and Gyro Amplifiers

■

350Ω Bridge Signal Conditioning

■

Magnetic Search Coil Amplifiers

■

Hydrophone Amplfiers

TYPICAL APPLICATIO

Flux Gate Amplifier

SQUARE

WAVE DRIVE

1kHz

FLUX GATE TYPICAL SCHONSTEDT #203132

U

+

LT1028

–

DEMODULATOR SYNC

OUTPUT TO DEMODULATOR

1k

50Ω

1028/1128 TA01

VOLTAGE NOISE DENSITY (nV/√Hz)

Voltage Noise vs Frequency

10

MAXIMUM

1/f CORNER = 14Hz

TYPICAL

1

1/f CORNER = 3.5Hz

0.1

1

FREQUENCY (Hz)

10

VS = ±15V

= 25°C

T

A

100

1028/1128 TA02

1k

1

LT1028/LT1128

TOP VIEW

SW PACKAGE

16-LEAD PLASTIC SOL

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

9

NC NC

TRIM

–IN +IN

V

–

NC NC

NC NC TRIM V

+

OUT

NC NC

NOTE: THIS DEVICE IS NOT RECOMMENDED FOR NEW DESIGNS

OVERCOMP

+

–

A

W

O

LUTEXI TIS

S

A

WUW

U

(Note 1)

ARB

G

Supply Voltage

–55°C to 105°C ................................................ ±22V

105°C to 125°C ................................................ ±16V

Differential Input Current (Note 9) ......................±25mA

Input Voltage ............................ Equal to Supply Voltage

Output Short Circuit Duration .......................... Indefinite

PACKAGE

1

TRIM

V

OS

2

–IN

3

+IN

H PACKAGE

8-LEAD TO-5 METAL CAN

T

= 175°C, θJA = 140°C/W, θJC = 40°C/W

JMAX

/

O

RDER I FOR ATIO

TOP VIEW VOS TRIM

8

–

+

4

–

V

(CASE)

7

5

+

V

6

OUT

OVERCOMP

ORDER PART

LT1028AMH LT1028MH LT1028ACH LT1028CH

WU

NUMBER

U

OBSOLETE PACKAGE

Consider S8 or N8 Packages for Alternate Source

Operating Temperature Range

LT1028/LT1128AM, M (OBSOLETE). –55°C to 125°C

LT1028/LT1128AC, C (Note 11) ......... – 40°C to 85°C

Storage Temperature Range

All Devices........................................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec.)................. 300°C

ORDER PART

NUMBER

TOP VIEW

V

OS

1

TRIM

–IN

+IN

–

V

T

–

2

+

3

45

S8 PACKAGE

8-LEAD PLASTIC SOIC

= 135°C, θJA = 140°C/W

JMAX

8 7 6

V

OS

TRIM V+

OUT OVER-

COMP

LT1028CS8 LT1128CS8

S8 PART MARKING

1028 1128

V

OS

TRIM

–IN

+IN

–

V

T

Consult LTC Marketing for parts specified with wider operating temperature ranges.

2

TOP VIEW

V

1

–

2

+

3

45

N8 PACKAGE

8-LEAD PLASTIC DIP

= 130°C, θJA = 130°C/W

JMAX

J8 PACKAGE

8-LEAD CERAMIC DIP

T

= 165°C, θJA = 100°C/W

JMAX

OS

8

TRIM

V+

7 6

OUT OVER-

COMP

OBSOLETE PACKAGE

Consider N8 Package for Alternate Source

ORDER PART

NUMBER

LT1028ACN8 LT1028CN8 LT1128ACN8 LT1128CN8

LT1028AMJ8 LT1028MJ8 LT1028ACJ8 LT1028CJ8 LT1128AMJ8 LT1128MJ8 LT1128CJ8

T

= 140°C, θJA = 130°C/W

JMAX

ORDER PART

NUMBER

LT1028CSW

LECTRICAL C CHARA TERIST

E

ICS

VS = ±15V, TA = 25°C, unless otherwise noted.

LT1028/LT1128

LT1028AM/AC LT1128AM/AC

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V ∆Time Voltage Stability

I

OS

I

B

e

n

I

n

CMRR Common Mode Rejection Ratio VCM = ±11V 114 126 110 126 dB PSRR Power Supply Rejection Ratio VS = ±4V to ±18V 117 133 110 132 dB A

VOL

V

OUT

SR Slew Rate A

GBW Gain-Bandwidth Product fO = 20kHz (Note 7) LT1028 50 75 50 75 MHz

Z

O

I

S

Input Offset Voltage (Note 2) 10 40 20 80 µV Long Term Input Offset (Note 3) 0.3 0.3 µV/Mo

OS

Input Offset Current VCM = 0V 12 50 18 100 nA Input Bias Current VCM = 0V ±25 ±90 ±30 ±180 nA Input Noise Voltage 0.1Hz to 10Hz (Note 4) 35 75 35 90 nV

Input Noise Voltage Density fO = 10Hz (Note 5) 1.00 1.7 1.0 1.9 nV/√Hz

fO = 1000Hz, 100% tested 0.85 1.1 0.9 1.2 nV/√Hz

Input Noise Current Density fO = 10Hz (Note 4 and 6) 4.7 10.0 4.7 12.0 pA/√Hz

fO = 1000Hz, 100% tested 1.0 1.6 1.0 1.8 pA/√Hz

Input Resistance Common Mode 300 300 MΩ Differential Mode 20 20 kΩ

Input Capacitance 5 5 pF Input Voltage Range ±11.0 ±12.2 ±11.0 ±12.2 V

Large-Signal Voltage Gain RL ≥ 2k, VO = ±12V 7.0 30.0 5.0 30.0 V/µV

R

≥ 1k, VO = ±10V 5.0 20.0 3.5 20.0 V/µV

L

RL ≥ 600Ω, VO = ±10V 3.0 15.0 2.0 15.0 V/µV

Maximum Output Voltage Swing RL ≥ 2k ±12.3 ±13.0 ±12.0 ±13.0 V

RL ≥ 600Ω±11.0 ±12.2 ±10.5 ±12.2 V

= –1 LT1028 11.0 15.0 11.0 15.0 V/µs

VCL

A

= –1 LT1128 5.0 6.0 4.5 6.0 V/µs

VCL

fO = 200kHz (Note 7) LT1128 13 20 11 20 MHz Open-Loop Output Impedance VO = 0, IO = 0 80 80 Ω Supply Current 7.4 9.5 7.6 10.5 mA

LT1028M/C LT1128M/C

P-P

LECTRICAL C CHARA TERIST

E

ICS

The ● denotes the specifications which apply over the temperature range

–55°C ≤ TA ≤ 125°C. VS = ±15V, unless otherwise noted.

LT1028AM LT1128AM

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V ∆Temp

I

OS

I

B

CMRR Common Mode Rejection Ratio VCM = ±10.3V ● 106 122 100 120 dB PSRR Power Supply Rejection Ratio VS = ±4.5V to ±16V ● 110 130 104 130 dB A

VOL

V

OUT

I

S

Input Offset Voltage (Note 2) ● 30 120 45 180 µV Average Input Offset Drift (Note 8) ● 0.2 0.8 0.25 1.0 µV/°C

OS

Input Offset Current VCM = 0V ● 25 90 30 180 nA Input Bias Current VCM = 0V ● ±40 ±150 ±50 ±300 nA Input Voltage Range ● ±10.3 ±11.7 ±10.3 ±11.7 V

Large-Signal Voltage Gain RL ≥ 2k, VO = ±10V ● 3.0 14.0 2.0 14.0 V/µV

RL ≥ 1k, VO = ±10V 2.0 10.0 1.5 10.0 V/µV Maximum Output Voltage Swing RL ≥ 2k ● ±10.3 ±11.6 ±10.3 ±11.6 V Supply Current ● 8.7 11.5 9.0 13.0 mA

LT1028M LT1128M

3

LT1028/LT1128

LECTRICAL C CHARA TERIST

E

0°C ≤ TA ≤ 70°C. VS = ±15V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V ∆Temp

I

OS

I

B

CMRR Common Mode Rejection Ratio VCM = ±10.5V ● 110 124 106 124 dB PSRR Power Supply Rejection Ratio VS = ±4.5V to ±18V ● 114 132 107 132 dB A

VOL

V

OUT

I

S

E

–40°C ≤ TA ≤ 85°C. VS = ±15V, unless otherwise noted. (Note 11)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V ∆Temp

I

OS

I

B

CMRR Common Mode Rejection Ratio VCM = ±10.5V ● 108 123 102 123 dB PSRR Power Supply Rejection Ratio VS = ±4.5V to ±18V ● 112 131 106 131 dB A

VOL

V

OUT

I

S

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: Input Offset Voltage measurements are performed by automatic test equipment approximately 0.5 sec. after application of power. In addition, at T approximately 55°C to account for the chip temperature rise when the device is fully warmed up.

Note 3: Long Term Input Offset Voltage Stability refers to the average trend line of Offset Voltage vs. Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in V

OS

Note 4: This parameter is tested on a sample basis only. Note 5: 10Hz noise voltage density is sample tested on every lot with the

exception of the S8 and S16 packages. Devices 100% tested at 10Hz are available on request.

Note 6: Current noise is defined and measured with balanced source resistors. The resultant voltage noise (after subtracting the resistor noise

Input Offset Voltage (Note 2) ● 15 80 30 125 µV Average Input Offset Drift (Note 8) ● 0.1 0.8 0.2 1.0 µV/°C

OS

Input Offset Current VCM = 0V ● 15 65 22 130 nA Input Bias Current VCM = 0V ● ±30 ±120 ±40 ±240 nA Input Voltage Range ● ±10.5 ±12.0 ±10.5 ±12.0 V

Large-Signal Voltage Gain RL ≥ 2k, VO = ±10V ● 5.0 25.0 3.0 25.0 V/µV

Maximum Output Voltage Swing RL ≥ 2k ● ±11.5 ±12.7 ±11.5 ±12.7 V

Supply Current ● 8.0 10.5 8.2 11.5 mA

LECTRICAL C CHARA TERIST

Input Offset Voltage ● 20 95 35 150 µV Average Input Offset Drift (Note 8) ● 0.2 0.8 0.25 1.0 µV/°C

OS

Input Offset Current VCM = 0V ● 20 80 28 160 nA Input Bias Current VCM = 0V ● ±35 ±140 ±45 ±280 nA Input Voltage Range ● ±10.4 ±11.8 ±10.4 ±11.8 V

Large-Signal Voltage Gain RL ≥ 2k, VO = ±10V ● 4.0 20.0 2.5 20.0 V/µV

Maximum Output Voltage Swing RL ≥ 2k ● ±11.0 ±12.5 ±11.0 ±12.5 V Supply Current ● 8.5 11.0 8.7 12.5 mA

= 25°C, offset voltage is measured with the chip heated to

A

during the first 30 days are typically 2.5µV.

ICS

RL ≥ 1k, VO = ±10V 4.0 18.0 2.5 18.0 V/µV

RL ≥ 600Ω (Note 10) ±9.5 ±11.0 ±9.0 ±10.5 V

ICS

RL ≥ 1k, VO = ±10V 3.0 14.0 2.0 14.0 V/µV

The ● denotes the specifications which apply over the temperature range

LT1028AC LT1128AC

LT1028C LT1128C

The ● denotes the specifications which apply over the temperature range

LT1028AC LT1128AC

on an RMS basis) is divided by the sum of the two source resistors to obtain current noise. Maximum 10Hz current noise can be inferred from 100% testing at 1kHz.

Note 7: Gain-bandwidth product is not tested. It is guaranteed by design and by inference from the slew rate measurement.

Note 8: This parameter is not 100% tested. Note 9: The inputs are protected by back-to-back diodes. Current-limiting

resistors are not used in order to achieve low noise. If differential input voltage exceeds ±1.8V, the input current should be limited to 25mA.

Note 10: This parameter guaranteed by design, fully warmed up at T 70°C. It includes chip temperature increase due to supply and load currents.

Note 11: The LT1028/LT1128 are designed, characterized and expected to meet these extended temperature limits, but are not tested at –40°C and 85°C. Guaranteed I grade parts are available. Consult factory.

LT1028C LT1128C

=

A

4

LPER

TEMPERATURE (°C)

–50

0

RMS VOLTAGE DENSITY (nV/√Hz)

0.8

2.0

0

50

75

LT1028/1128 • TPC09

O.4

1.6

1.2

–25

25

100

125

VS = ±15V

AT 10Hz

AT 1kHz

F

O

10Hz Voltage Noise Distribution

180

160

140

120

100

80

60

NUMBER OF UNITS

40

20

0

0.6

158

148

70

57

28

8

7

4

232

22

1

1.6 2.0 2.2

0.8 1.2

1.0

VOLTAGE NOISE DENSITY (nV/√Hz)

1.4

R

ATYPICA

VS = ±15V T

= 25°C

A

500 UNITS MEASURED FROM 4 RUNS

3

2

11

1.8

LT1020/1120 • TPC01

UW

E

C

1

CCHARA TERIST

Wideband Noise, DC to 20kHz

VERTICAL SCALE = 0.5µV/DIV

HORIZONTAL SCALE = 0.5ms/DIV

ICS

LT1028/LT1128

Wideband Voltage Noise (0.1Hz to Frequency Indicated)

10

VS = ±15V

= 25°C

T

A

1

0.1

RMS VOLTAGE NOISE (µV)

0.01 100

BANDWIDTH (Hz)

100k 1M 10M

10k1k

LT1028/1128 • TPC03

Total Noise vs Matched Source Resistance

100

R

S

–

R

S

+

10

AT 10Hz

TOTAL NOISE DENSITY (nV/√Hz)

1

0.1 1

3 1k 10k

MATCHED SOURCE RESISTANCE (Ω)

2 RS NOISE ONLY

10 30 100 300 3k

0.1Hz to 10Hz Voltage Noise

VS = ±15V

= 25°C

T

A

AT 1kHz

VS = ±15V

= 25°C

T

A

LT1028/1128 • TPC04

Total Noise vs Unmatched Source Resistance Current Noise Spectrum

100

R

S

10

AT 10Hz

1

TOTAL NOISE DENSITY (nV/√Hz)

0.1 1

3 1k 10k

UNMATCHED SOURCE RESISTANCE (Ω)

2 RS NOISE ONLY

10 30 100 300 3k

0.01Hz to 1Hz Voltage Noise

VS = ±15V

= 25°C

T

A

AT 1kHz

VS = ±15V

= 25°C

T

A

LT1028/1128 • TPC05

100

MAXIMUM

10

1/f CORNER = 800Hz

TYPICAL

1

1/f CORNER = 250Hz

CURRENT NOISE DENSITY (pA/√Hz)

0.1 10

100 1k 10k

FREQUENCY (Hz)

Voltage Noise vs Temperature

LT1028/1128 • TPC06

10nV

2

08

4

TIME (SEC)

6

10

LT1028/1128 • TPC07

080

20

40

TIME (SEC)

60

100

LT1028/1128 • TPC08

5

LT1028/LT1128

COMMON MODE INPUT VOLTAGE (V)

–15

–80

INPUT BIAS CURRENT (nA)

–60

–20

0

20

–5

5

15

100

LT1028/1128 • TPC15

–40

–10 0

40

60

80

10

RCM =

20V

65nA

≈ 300MΩ

V

S

= ±15V

T

A

= 25°C

POSITIVE INPUT CURRENT

(UNDERCANCELLED) DEVICE

NEGATIVE INPUT CURRENT (OVERCANCELLED) DEVICE

LPER

F

O

R

ATYPICA

UW

CCHARA TERIST

E

C

ICS

Distribution of Input Offset Voltage

20

VS = ±15V

18

= 25°C

T

A

800 UNITS TESTED

16

FROM FOUR RUNS

14

12 10

UNITS (%)

8 6 4 2 0

–40

–30

24

20

16

12

8

–50

VS = ±15V T

–20

OFFSET VOLTAGE (µV)

= 25°C

A

–10

METAL CAN (H) PACKAGE

Offset Voltage Drift with Temperature of Representative Units

50

VS = ±15V

40 30 20

10

0

–10

–20

OFFSET VOLTAGE (µV)

–30 –40 –50

0

10

20

30

40

50

LT1028/1128 • TPC10

–50

–25

0

TEMPERATURE (°C)

50

25

75

LT1028/1128 • TPC11

100

125

Input Bias and Offset Currents Over Temperature

60

VS = ±15V

= 0V

V

CM

50

40

30

20

BIAS CURRENT

Long-Term Stability of Five Representative Units

10

VS = ±15V

8

= 25°C

T

A

t = 0 AFTER 1 DAY PRE-WARM UP

6 4 2

0 –2 –4

–6

OFFSET VOLTAGE CHANGE (µV)

–8

–10

1

0

TIME (MONTHS)

3

2

Bias Current Over the Common Mode RangeWarm-Up Drift

4

LT1028/1128 • TPC12

5

4

CHANGE IN OFFSET VOLTAGE (µV)

0

Voltage Noise vs Supply Voltage

1.5 TA = 25°C

1.25

1.0

0.75

RMS VOLTAGE NOISE DENSITY (nV/√Hz)

0.5

0

6

DUAL-IN-LINE PACKAGE PLASTIC (N) OR CERDIP (J)

1234

TIME AFTER POWER ON (MINUTES)

LT1028/1128 • TPC13

AT 10Hz

±5 ±10

SUPPLY VOLTAGE (V)

AT 1kHz

±15

LT1028/1128 • TPC16

±20

10

INPUT BIAS AND OFFSET CURRENTS (nA)

5

0

–50

–25 0

Supply Current vs Temperature

10

9 8 7 6 5 4 3

SUPPLY CURRENT (mA)

2 1 0

–50

–25

OFFSET CURRENT

50 100 125

25 75

TEMPERATURE (˚C)

VS = ±15V

VS = ±5V

50

25

0

TEMPERATURE (°C)

LT1028/1128 • TPC14

75

100

LT1028/1128 • TPC17

Output Short-Circuit Current vs Time

50 40 30 20

SOURCING

10

0 –10 –20 –30

SINKING

SHORT-CIRCUIT CURRENT (mA)

–40 –50

125

0

TIME FROM OUTPUT SHORT TO GROUND (MINUTES)

25°C

2

VS = ±15V

3

LT1028/1128 • TPC18

–50°C

125°C

–50°C

1

LPER

FREQUENCY (Hz)

10k

5

PEAK-TO-PEAK OUTPUT VOLTAGE (V)

20

25

30

100k 1M 10M

LT1028/1128 • TPC27

15

10

LT1128 LT1028

VS = ±15V T

A

= 25°C

R

L

= 2k

LT1028/LT1128

UW

R

F

O

ATYPICA

CCHARA TERIST

E

C

ICS

Voltage Gain vs Frequency

160

140

120

100

80

60

40

VOLTAGE GAIN (dB)

20

0

–20

0.01

LT1128 LT1028

0.1 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)

Gain Error vs Frequency Closed-Loop Gain = 1000

1

TYPICAL

PRECISION

OP AMP

0.1

GAIN ERROR (%)

0.01

CLOSED-LOOP GAIN

OPEN-LOOP GAIN

1 100 FREQUENCY (Hz)

0.001

GAIN ERROR =

0.1

VS = ±15V T R

LT1028/1128 • TPC19

LT1128

LT1028

10

LT1028/1128 • TPC22

= 25°C

A

= 2k

L

LT1028 Gain, Phase vs Frequency

70

60

50

40

30

20

VOLTAGE GAIN (dB)

10

VS = ±15V

0

= 25°C

T

A

C

= 10pF

L

–10

10k 1M 10M 100M

100k

PHASE

GAIN

FREQUENCY (Hz)

LT1028/1128 • TPC20

LT1128 Gain Phase vs Frequency

70

60

50

40

30

20

VOLTAGE GAIN (dB)

10

VS = ±15V

0

= 25°C

T

A

= 10pF

C

L

–10

10k 1M 10M 100M

100k

FREQUENCY (Hz)

PHASE

GAIN

LT1028/1128 • TPC23

70

60

50

40

30

20

10

0

–10

70

60

50

40

30

20

10

0

–10

OVERSHOOT (%)

PHASE MARGIN (DEG)

OVERSHOOT (%)

PHASE MARGIN (DEG)

LT1028 Capacitance Load Handling

80

70

60

50

40

30

20

10

0

R

S

10

30pF

2k

–

+

C

L

AV = –1, RS = 2k

AV = –10

R

= 200Ω

S

AV = –100

= 20Ω

R

S

100 1000 10000

CAPACITIVE LOAD (pF)

LT1128 Capacitance Load Handling

80

70

60

50

40

30

20

10

0

10

30pF

2k

R

S

–

+

C

L

AV = –1, RS = 2k

AV = –10

= 200Ω

R

S

AV = –100, RS = 20Ω

100 1000 10000

CAPACITIVE LOAD (pF)

VS = ±15V

= 25°C

T

A

LT1028/1128 • TPC21

VS = ±15V

= 25°C

T

A

V

= 10mV

O

LT1028/1128 • TPC 24

P-P

Voltage Gain vs Supply Voltage Voltage Gain vs Load Resistance

100

TA = 25°C

RL = 2k

10

VOLTAGE GAIN (V/µV)

1

0

±5

SUPPLY VOLTAGE (V)

R

= 600Ω

L

±10

±15

LT`1028/1128 • TPC25

±20

Maximum Undistorted Output vs Frequency

100

VS = ±15V

TA = –55°C

10

VOLTAGE GAIN (V/µV)

1

0.1

LOAD RESISTANCE (kΩ)

TA = 25°C

TA = 125°C

I

= 35mA AT –55°C

LMAX

= 27mA AT 25°C = 16mA AT 125°C

110

LT1028/1128 • TPC26

7

LT1028/LT1128

TEMPERATURE (°C)

–50

0

SLEW RATE (V/µs)

1

3

4

5

0

50

100

9

LT1028/1128 • TPC33

2

–25 25

6

7

8

75 125

20

10

30

GAIN-BANDWIDTH PRODUCT (f

O

= 200kHz), (MHz)

FALL

RISE

GBW

OVER-COMPENSATION CAPACITOR (pF)

1

SLEW RATE (V/µs)

10

1 100 1000 10000

LT1028/1128 • TPC36

0.1 10

100

1k

10k

GAIN AT 20kHz

COC FROM PIN 5 TO PIN 6 V

S

= ±15V

T

A

= 25°C

SLEW GBW

100

10

LPER

LT1028 Large-Signal Transient Response

10V

5V/DIV

–10V

F

O

R

ATYPICA

UW

CCHARA TERIST

E

C

LT1028 Small-Signal Transient Response

50mV

20mV/DIV

–50mV

ICS

LT1028 Slew Rate, Gain-Bandwidth Product Over Temperature

18

VS = ±15V

17

16

15

14

SLEW RATE (V/µs)

GBW

FALL

RISE

GAIN-BANDWIDTH PRODUCT (f

90

80

70

60

O

= 20kHz), (MHz)

50

1µs/DIV

= –1, RS = RF = 2k, CF = 15pF

A

V

LT1128 Large-Signal Transient Response

10V

0V

–10V

2µs/DIV

A

= –1, RS = RF = 2k, CF = 30pF

V

100

IO = 1mA

= ±15V

V

S

= 25°C

T

A

10

AV = 1000

1

0.1

OUTPUT IMPEDANCE (Ω)

0.01

0.001

8

100

10

LT1128

1k

FREQUENCY (Hz)

LT1028

A

10k

LT1028

= 5

V

100k

1M

LT1028/1128 • TPC34

0.2µs/DIV

AV = –1, RS = RF = 2k C

= 15pF, CL = 80pF

F

LT1128 Small-Signal Transient Response

50mV

0V

–50mV

0.2µs/DIV

A

= 1, CL = 10pF

V

LT1128 Slew Rate, Gain-Bandwidth Product vs Over-Compensation CapacitorClosed-Loop Output Impedance

100

GBW

10

1

SLEW RATE (V/µs)

0.1

0.1 1 100 1000 10000

1 100 1000 10000

GBW

SLEW RATE

10

OVER-COMPENSATION CAPACITOR (pF)

LT1028/1128 • TPC35

1k

GAIN AT 200kHz

100

10

1

13

12

–50

–25 0

TEMPERATURE (˚C)

50 100 125

25 75

LT1028/1128 • TPC30

LT1128 Slew Rate, Gain-Bandwidth Product Over Temperature

LT1028 Slew Rate, Gain-Bandwidth Product vs Over-Compensation Capacitor

40

30

LPER

LT1028/LT1128

UW

R

F

O

ATYPICA

CCHARA TERIST

E

C

ICS

Common Mode Limit Over Temperature

+

V –1

–25

0

VS = ±5V

= ±15V

V

S

VS = ±5V TO ±15V

50

25

TEMPERATURE (°C)

–2 –3

–4

4 3

COMMON MODE LIMIT (V)

2

REFERRED TO POWER SUPPLY

1

–

V

–50

LT1028 Total Harmonic Distortion vs Frequency and Load Resistance

0.1

AV = 1000

= 600Ω

R

L

AV = 1000

= 2k

R

L

75

100

LT1028/1128 • TPC37

125

Common Mode Rejection Ratio vs Frequency

140

120

100

80

60

40

20

COMMON MODE REJECTION RATIO (dB)

0

10

LT1128 LT1028

100 1k

FREQUENCY (Hz)

100k 10M

10k 1M

LT1028 Total Harmonic Distortion vs Closed-Loop Gain

0.1 VO = 20V

P-P

0.01

f = 1kHz

= ±15V

V

S

= 25°C

T

A

= 10k

R

L

NON-INVERTING

VS = ±15V T

A

LT1028/1128 • TPC38

GAIN

= 25°C

Power Supply Rejection Ratio vs Frequency

160

140

120

1k

NEGATIVE SUPPLY

10k

100

10

1

POSITIVE

SUPPLY

100

FREQUENCY (Hz)

80

60

40

20

POWER SUPPLY REJECTION RATIO (dB)

0

0.1

High Frequency Voltage Noise vs Frequency

10

VS = ±15V

= 25°C

T

A

1M

100k

LT1028/1128 • TPC39

10M

0.01

TOTAL HARMONIC DISTORTION (%)

0.001 1

10 100

FREQUENCY (kHz)

1.0

0.1

0.01

TOTAL HARMONIC DISTORTION (%)

0.001

1.0

AV = –1000

= 2k

R

L

AV = 1000

= 600Ω

R

L

VO = 20V VS = ±15V

= 25°C

T

A

LT1028/1128 • TPC40

P-P

0.001

TOTAL HARMONIC DISTORTION (%)

0.0001 10 1k 10k 100k

LT1128 Total Harmonic Distortion vs Frequency and Load Resistance

AV = 1000

= 600Ω

R

AV = 1000

= 2k

R

L

AV = –1000 R

= 2k

L

AV = 1000 R

= 600Ω

L

10 100

FREQUENCY (kHz)

VO = 20V VS = ±15V

= 25°C

T

A

LT1028/1128 • TPC43

P-P

100

CLOSED LOOP GAIN

INVERTING GAIN

MEASURED EXTRAPOLATED

LT1028/1128 • TPC41

LT1128 Total Harmonic Distortion vs Closed-Loop Gain

0.1 VO = 20V f = 1kHz

= ±15V

V

S

= 25°C

T

A

= 10k

R

L

0.01

0.001

TOTAL HARMONIC DISTORTION (%)

0.0001 10 1k 10k 100k

100

1.0

NOISE VOLTAGE DENSITY (nV/÷Hz)

0.1 10k

P-P

NON-INVERTING

CLOSED LOOP GAIN

FREQUENCY (Hz)

GAIN

INVERTING GAIN

MEASURED EXTRAPOLATED

LT1028/1128 • TPC44

100k 1M

LT1028/1128 • TPC42

9

LT1028/LT1128

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

– OISE

Voltage Noise vs Current Noise

The LT1028/LT1128’s less than 1nV/√Hz voltage noise is three times better than the lowest voltage noise heretofore available (on the LT1007/1037). A necessary condition for such low voltage noise is operating the input transistors at nearly 1mA of collector currents, because voltage noise is inversely proportional to the square root of the collector current. Current noise, however, is directly proportional to the square root of the collector current. Consequently, the LT1028/LT1128’s current noise is significantly higher than on most monolithic op amps.

Therefore, to realize truly low noise performance it is important to understand the interaction between voltage noise (en), current noise (In) and resistor noise (rn).

Total Noise vs Source Resistance

The total input referred noise of an op amp is given by

et = [e

2

+ r

n

+ (InReq)

n

2]1/2

2

where Req is the total equivalent source resistance at the two inputs, and

rn = √4kTReq = 0.13√Req in nV/√Hz at 25°C

As a numerical example, consider the total noise at 1kHz of the gain 1000 amplifier shown below.

largest term, as in the example above, and the LT1028/ LT1128’s voltage noise becomes negligible. As Req is further increased, current noise becomes important. At 1kHz, when Req is in excess of 20k, the current noise component is larger than the resistor noise. The total noise versus matched source resistance plot illustrates the above calculations.

The plot also shows that current noise is more dominant at low frequencies, such as 10Hz. This is because resistor noise is flat with frequency, while the 1/f corner of current noise is typically at 250Hz. At 10Hz when Req > 1k, the current noise term will exceed the resistor noise.

When the source resistance is unmatched, the total noise versus unmatched source resistance plot should be consulted. Note that total noise is lower at source resistances below 1k because the resistor noise contribution is less. When RS > 1k total noise is not improved, however. This is because bias current cancellation is used to reduce input bias current. The cancellation circuitry injects two correlated current noise components into the two inputs. With matched source resistors the injected current noise creates a common-mode voltage noise and gets rejected by the amplifier. With source resistance in one input only, the cancellation noise is added to the amplifier’s inherent noise.

100Ω

100k

–

LT1028 LT1128

+

1028/1128 AI01

Req = 100Ω + 100Ω || 100k ≈ 200Ω

rn = 0.13√200 = 1.84nV√Hz en = 0.85nV√Hz In = 1.0pA/√Hz

et = [0.852 + 1.842 + (1.0 × 0.2)

2]1/2

= 2.04nV/√Hz

Output noise = 1000 et = 2.04µV/√Hz

At very low source resistance (Req < 40Ω) voltage noise dominates. As Req is increased resistor noise becomes the

10

In summary, the LT1028/LT1128 are the optimum amplifiers for noise performance, provided that the source resistance is kept low. The following table depicts which op amp manufactured by Linear Technology should be used to minimize noise, as the source resistance is increased beyond the LT1028/LT1128’s level of usefulness.

Best Op Amp for Lowest Total Noise vs Source Resistance

SOURCE RESIS-

TANCE(Ω) (Note 1)

0 to 400 LT1028/LT1128 LT1028/LT1128 400 to 4k LT1007/1037 LT1028/LT1128 4k to 40k LT1001 LT1007/1037 40k to 500k LT1012 LT1001 500k to 5M LT1012 or LT1055 LT1012 >5M LT1055 LT1055

Note 1: Source resistance is defined as matched or unmatched, e.g.,

= 1k means: 1k at each input, or 1k at one input and zero at the other.

R

S

AT LOW FREQ(10Hz) WIDEBAND(1kHz)

BEST OP AMP

LT1028/LT1128

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

– OISE

Noise Testing – Voltage Noise

The LT1028/LT1128’s RMS voltage noise density can be accurately measured using the Quan Tech Noise Analyzer, Model 5173 or an equivalent noise tester. Care should be taken, however, to subtract the noise of the source resistor used. Prefabricated test cards for the Model 5173 set the device under test in a closed-loop gain of 31 with a 60Ω source resistor and a 1.8k feedback resistor. The noise of this resistor combination is 0.13√58 = 1.0nV/√Hz. An LT1028/LT1128 with 0.85nV/√Hz noise will read (0.852 +

1/2

1.02)

= 1.31nV/√Hz. For better resolution, the resistors should be replaced with a 10Ω source and 300Ω feedback resistor. Even a 10Ω resistor will show an apparent noise which is 8% to 10% too high.

The 0.1Hz to 10Hz peak-to-peak noise of the LT1028/ LT1128 is measured in the test circuit shown. The frequency response of this noise tester indicates that the

0.1Hz corner is defined by only one zero. The test time to measure 0.1Hz to 10Hz noise should not exceed 10 seconds, as this time limit acts as an additional zero to eliminate noise contributions from the frequency band below 0.1Hz.

Measuring the typical 35nV peak-to-peak noise performance of the LT1028/LT1128 requires special test precautions:

(a) The device should be warmed up for at least five

minutes. As the op amp warms up, its offset voltage changes typically 10µV due to its chip temperature increasing 30°C to 40°C from the moment the power supplies are turned on. In the 10 second measurement interval these temperature-induced effects can easily exceed tens of nanovolts.

(b) For similar reasons, the device must be well shielded

from air current to eliminate the possibility of thermoelectric effects in excess of a few nanovolts, which would invalidate the measurements.

(c) Sudden motion in the vicinity of the device can also

“feedthrough” to increase the observed noise.

A noise-voltage density test is recommended when measuring noise on a large number of units. A 10Hz noisevoltage density measurement will correlate well with a

0.1Hz to 10Hz peak-to-peak noise reading since both results are determined by the white noise and the location of the 1/f corner frequency.

0.1Hz to 10Hz Noise Test Circuit

0.1µF

100k

–

10Ω

VOLTAGE GAIN = 50,000

* DEVICE UNDER TEST

NOTE ALL CAPACITOR VALUES ARE FOR NONPOLARIZED CAPACITORS ONLY

*

+

2k

4.7µF

+

24.3k

LT1001

–

100k

0.1µF

4.3k

2.2µF

22µF

SCOPE × 1 R

IN

110k

1028/1128 AI02

= 1M

0.1Hz to 10Hz Peak-to-Peak Noise Tester Frequency Response

100

90

80

70

60

GAIN (dB)

50

40

30

0.01 1.0 10 100

0.1 FREQUENCY (Hz)

LT1028/1128 • AI03

11

LT1028/LT1128

FREQUENCY (Hz)

100

–50

NOISE FILTER LOSS (dB)

–10

0

10

1k 10k 100k

LT1028/1128 • AI05

–20

–40

–30

CURRENT

NOISE

VOLTAGE NOISE

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

– OISE

Noise Testing – Current Noise

Current noise density (In) is defined by the following formula, and can be measured in the circuit shown:

In =

2

– (31 × 18.4nV/√Hz)2]

[e

no

1/2

20k × 31

1.8k

10k

–

60Ω

10k

LT1028 LT1128

+

1028/1128 AI04

e

no

If the Quan Tech Model 5173 is used, the noise reading is input-referred, therefore the result should not be divided by 31; the resistor noise should not be multiplied by 31.

100% Noise Testing

10Hz voltage noise density is sample tested on every lot. Devices 100% tested at 10Hz are available on request for an additional charge.

10Hz current noise is not tested on every lot but it can be inferred from 100% testing at 1kHz. A look at the current noise spectrum plot will substantiate this statement. The only way 10Hz current noise can exceed the guaranteed limits is if its 1/f corner is higher than 800Hz and/or its white noise is high. If that is the case then the 1kHz test will fail.

Automated Tester Noise Filter

The 1kHz voltage and current noise is 100% tested on the LT1028/LT1128 as part of automated testing; the approximate frequency response of the filters is shown. The limits on the automated testing are established by extensive correlation tests on units measured with the Quan Tech Model 5173.

PPLICATI

A

General

The LT1028/LT1128 series devices may be inserted directly into OP-07, OP-27, OP-37, LT1007 and LT1037 sockets with or without removal of external nulling components. In addition, the LT1028/LT1128 may be fitted to 5534 sockets with the removal of external compensation components.

Offset Voltage Adjustment

The input offset voltage of the LT1028/LT1128 and its drift with temperature, are permanently trimmed at wafer testing to a low level. However, if further adjustment of VOS is necessary, the use of a 1k nulling potentiometer will not degrade drift with temperature. Trimming to a value other

O

U S

I FOR ATIO

WU

U

INPUT

1k

1

2

3

–

LT1028 LT1128

+

8

4

–15V

15V

7

6

OUTPUT

1028/1128 AI06

than zero creates a drift of (VOS/300)µV/°C, e.g., if VOS is adjusted to 300µV, the change in drift will be 1µV/°C.

The adjustment range with a 1k pot is approximately ±1.1mV.

Offset Voltage and Drift

Thermocouple effects, caused by temperature gradients across dissimilar metals at the contacts to the input

12

LT1028/LT1128

1028/1128 AI09

–

+

33pF

2k

LT1028

50Ω

–

+

LT1028

50Ω

500Ω

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

terminals, can exceed the inherent drift of the amplifier unless proper care is exercised. Air currents should be minimized, package leads should be short, the two input leads should be close together and maintained at the same temperature.

The circuit shown to measure offset voltage is also used as the burn-in configuration for the LT1028/LT1128.

Test Circuit for Offset Voltage

and Offset Voltage Drift with Temperature

10k*

15V

2

200Ω*

3

10k*

V

O

* RESISTORS MUST HAVE LOW THERMOELECTRIC POTENTIAL

–

LT1028 LT1128

+

= 100V

–15V

OS

7

6

4

V

O

1028/1128 AI08

Frequency Response

The LT1028’s Gain, Phase vs Frequency plot indicates that the device is stable in closed-loop gains greater than +2 or –1 because phase margin is about 50° at an open-loop gain of 6dB. In the voltage follower configuration phase margin seems inadequate. This is indeed true when the output is shorted to the inverting input and the noninverting input is driven from a 50Ω source impedance. However, when feedback is through a parallel R-C network (provided CF < 68pF), the LT1028 will be stable because of interaction between the input resistance and capacitance and the feedback network. Larger source resistance at the noninverting input has a similar effect. The following voltage follower configurations are stable:

Unity-Gain Buffer Applications (LT1128 Only)

When RF ≤ 100Ω and the input is driven with a fast, largesignal pulse (>1V), the output waveform will look as shown in the pulsed operation diagram.

R

F

–

OUTPUT

+

6V/µs

1028/1128 AI07

During the fast feedthrough-like portion of the output, the input protection diodes effectively short the output to the input and a current, limited only by the output short-circuit protection, will be drawn by the signal generator. With R

F

≥ 500Ω, the output is capable of handling the current requirements (IL ≤ 20mA at 10V) and the amplifier stays in its active mode and a smooth transition will occur.

As with all operational amplifiers when RF > 2k, a pole will be created with RF and the amplifier’s input capacitance, creating additional phase shift and reducing the phase margin. A small capacitor (20pF to 50pF) in parallel with R will eliminate this problem.

F

Another configuration which requires unity-gain stability is shown below. When CF is large enough to effectively short the output to the input at 15MHz, oscillations can occur. The insertion of RS2 ≥ 500Ω will prevent the LT1028 from oscillating. When RS1 ≥ 500Ω, the additional noise contribution due to the presence of RS2 will be minimal. When RS1 ≤ 100Ω, RS2 is not necessary, because RS1 represents a heavy load on the output through the CF short. When 100Ω < RS1 < 500Ω, RS2 should match RS1 . For example, RS1 = RS2 = 300Ω will be stable. The noise increase due to RS2 is 40%.

C1

R1

R

S1

R

S2

–

LT1028

+

1028/1128 AI10

13

LT1028/LT1128

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

If CF is only used to cut noise bandwidth, a similar effect can be achieved using the over-compensation terminal.

The Gain, Phase plot also shows that phase margin is about 45° at gain of 10 (20dB). The following configura-

10pF

10k

1.1k

–

LT1028

+

50Ω

1028/1128 AI11

U

TYPICAL APPLICATIO S

tion has a high (≈70%) overshoot without the 10pF capacitor because of additional phase shift caused by the feedback resistor – input capacitance pole. The presence of the 10pF capacitor cancels this pole and reduces overshoot to 5%.

Over-Compensation

The LT1028/LT1128 are equipped with a frequency overcompensation terminal (Pin 5). A capacitor connected between Pin 5 and the output will reduce noise bandwidth. Details are shown on the Slew Rate, Gain-Bandwidth Product vs Over-Compensation Capacitor plot. An additional benefit is increased capacitive load handling capability.

Strain Gauge Signal Conditioner with Bridge Excitation

15V

LT1021-5

350Ω

BRIDGE

3

2

5.0V

–

LT1028

+

3

2

15V

–15V

+

LT1128

–

7

4

7

4

–15V

6

330Ω

6

REFERENCE OUTPUT

301k*

10k ZERO TRIM

*RN60C FILM RESISTORS

330Ω

THE LT1028’s NOISE CONTRIBUTION IS NEGLIGIBLE COMPARED TO THE BRIDGE NOISE.

15V

7

3

–

LT1028

2

+

4

–15V

6

1µF

5k GAIN TRIM

0V TO 10V OUTPUT

30.1k*

49.9Ω*

1028/1128 TA05

28V

LT1021-10

Low Noise Voltage Regulator

1k

+

LT1028

–

330Ω

1000pF

10

28V

LT317A

10

+

2N6387

2k

121Ω

2.3k PROVIDES PRE-REG AND CURRENT LIMITING

20V OUTPUT

1028/1128 TA04

14

TYPICAL APPLICATIO S

LT1028/LT1128

U

Paralleling Amplifiers to Reduce Voltage Noise

+

A1

LT1028

1.5k

–

7.5Ω

+

LT1028

–

+

LT1028

470Ω

4.7k

A2

470Ω

An

1.5k

–

LT1028

+

–

7.5Ω

1. ASSUME VOLTAGE NOISE OF LT1028 AND 7.5Ω SOURCE RESISTOR = 0.9nV/√Hz.

2. GAIN WITH n LT1028s IN PARALLEL = n × 200.

3. OUTPUT NOISE = √n × 200 × 0.9nV/√Hz.

4. INPUT REFERRED NOISE = = nV/√Hz.

5. NOISE CURRENT AT INPUT INCREASES √n TIMES.

6. IF n = 5, GAIN = 1000, BANDWIDTH = 1MHz, RMS NOISE, DC TO 1MHz = = 0.9µV.

470Ω

OUTPUT NOISE

n × 200

0.9 √n

2µV

√5

OUTPUT

1028/1128 TA03

Phono Preamplifier

10Ω

787Ω

15V

100pF

47k

MAG PHONO

INPUT

2

3

–

LT1028

+

7

4

–15V

Tape Head Amplifier

499Ω

31.6k

10Ω

TAPE HEAD

ALL RESISTORS METAL FILM

INPUT

2

–

LT1028

3

+

0.1µF

10k

0.33µF

6

ALL RESISTORS METAL FILM

0.1µF

6

1028/1128 TA07

OUTPUT

1028/1128 TA06

OUTPUT

Low Noise, Wide Bandwidth Instrumentation Amplifier

–INPUT

+

LT1028

–

820Ω

50Ω

10Ω

300Ω

68pF

10k

–

RMS

68pF

RMS

300Ω

LT1028

+

10k

–

LT1028

+INPUT

GAIN = 1000, BANDWIDTH = 1MHz INPUT REFERRED NOISE = 1.5nV/√Hz AT 1kHz WIDEBAND NOISE –DC to 1MHz = 3µV IF BW LIMITED TO DC TO 100kHz = 0.55µV

+

820Ω

OUTPUT

1028/1128 TA08

SINE

DRIVE

Gyro Pick-Off Amplifier

GYRO TYPICAL–

NORTHROP CORP.

GR-F5AH7-5B

•

+

LT1028

–

OUTPUT TO SYNC DEMODULATOR

1k

100Ω

1028/1128 TA09

15

LT1028/LT1128

TYPICAL APPLICATIO S

U

Super Low Distortion Variable Sine Wave Oscillator

5.6k

10k

20k

R1

20Ω 2k

+

LT1028

–

10pF

100k

TRIM FOR

LOWEST

DISTORTION

15µF

LT1055

C2

0.047

+

22k

1V

OUTPUT

RMS

1.5kHz TO 15kHz 1

f =

()

2πRC

WHERE R1C1 = R2C2

–

MOUNT 1N4148s IN CLOSE PROXIMITY

4.7k

LT1004-1.2V

15V

+

10k

1028/1128 TA10

C1

0.047

20Ω

2k

R2

2.4k

2N4338

560Ω

<0.0018% DISTORTION AND NOISE. MEASUREMENT LIMITED BY RESOLUTION OF HP339A DISTORTION ANALYZER

INPUT

1028/1128 TA11

Chopper-Stabilized Amplifier

15V

1N758

3

2

0.1

100k

+

–

LT1052

1

–15V

7

4

1N758

130Ω

6

8

0.1

0.01

15V

68Ω

1

7

3

+

LT1028

2

–

4

–15V

30k

8

OUTPUT

10k

10Ω

16

LT1028/LT1128

S

CH

NULL

1

NON-

INVERTING

INPUT

3

INVERTING

INPUT

2

E

4.5µA

W

A

TI

Q1

BIAS

R5 130Ω

R1 3k

900µA

4.5µA

ICDAGRA

NULL

8

R6 130Ω

R2 3k

900µA

Q5

3

1

Q7

4.5µA

Q2

0

1.8mA

Q3

4.5µA

W

Q8

Q4

C1 257pF

+

V

7

1.1mA

R10

Q17

Q16

Q18

Q6

3

1

Q9

Q12

1.5µA

Q10

Q11

Q13

Q14

300µA

Q15

400Ω

Q19

R11 400Ω

R11

100Ω

250pF

C3

240Ω

R12

R10

500Ω

Q22

35pF

2.3mA

C4

400µA

500µA

C2

Q26

OUTPUT

6

Q27

Q23

Q24

Q25

–

V

4

C2 = 50pF for LT1028 C2 = 275pF for LT1128

R7 80Ω

R8 480Ω

Q20

Q21

5

OVERCOMP

600µA

1028/1128 TA13

17

LT1028/LT1128

PACKAGE DESCRIPTIO

U

OBSOLETE PACKAGE

(0.203 – 0.457)

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS

0.300 – 0.325

(7.620 – 8.255)

0.045 – 0.068

(1.143 – 1.727)

FULL LEAD

OPTION

0.300 BSC

(0.762 BSC)

0.008 – 0.018

J8 Package

8-Lead CERDIP (Narrow .300 Inch, Hermetic)

(Reference LTC DWG # 05-08-1110)

CORNER LEADS OPTION

(4 PLCS)

0° – 15°

0.023 – 0.045

(0.584 – 1.143)

HALF LEAD

OPTION

0.005

(0.127)

MIN

0.025

(0.635)

RAD TYP

0.045 – 0.065

(1.143 – 1.651)

0.014 – 0.026

(0.360 – 0.660)

87

12

N8 Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

0.405

(10.287)

MAX

65

3

4

0.220 – 0.310

(5.588 – 7.874)

0.015 – 0.060

(0.381 – 1.524)

0.100 (2.54)

BSC

0.200

(5.080)

MAX

0.125

3.175 MIN

J8 1298

0.400* (10.160)

MAX

876

5

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325 –0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

TYP

0.100

(2.54)

BSC

8-Lead Plastic Small Outline (Narrow .150 Inch)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

0.016 – 0.050

(0.406 – 1.270)

0.053 – 0.069

(1.346 – 1.752)

0°– 8° TYP

0.014 – 0.019

(0.355 – 0.483)

TYP

0.125

0.020

(3.175)

MIN

(0.508)

0.018 ± 0.003

(0.457 ± 0.076)

MIN

S8 Package

(Reference LTC DWG # 05-08-1610)

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

0.255 ± 0.015* (6.477 ± 0.381)

0.228 – 0.244

(5.791 – 6.197)

0.189 – 0.197* (4.801 – 5.004)

7

8

1

2

12

5

6

3

4

3

N8 1098

0.150 – 0.157** (3.810 – 3.988)

SO8 1298

18

PACKAGE DESCRIPTIO

U

S Package

16-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

0.386 – 0.394*

(9.804 – 10.008)

13

16

14

15

12

LT1028/LT1128

11

10

9

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

45°TYP

0.028 – 0.034

(0.711 – 0.864)

0.110 – 0.160

(2.794 – 4.064)

INSULATING

STANDOFF

*

LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE AND 0.045" BELOW THE REFERENCE PLANE

**

FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS

×

°

45

0.016 – 0.050

(0.406 – 1.270)

0° – 8° TYP

0.027 – 0.045

(0.686 – 1.143)

PIN 1

(5.842)

0.016 – 0.024

(0.406 – 0.610)

0.228 – 0.244

(5.791 – 6.197)

2

1

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

H Package

3-Lead TO-39 Metal Can

(Reference LTC DWG # 05-08-1330)

0.040

(1.016)

MAX

0.230

SEATING

TYP

PLANE

0.010 – 0.045* (0.254 – 1.143)

3

5

4

0.050

(1.270)

BSC

0.335 – 0.370

(8.509 – 9.398)

DIA

0.305 – 0.335

(7.747 – 8.509)

0.016 – 0.021** (0.406 – 0.533)

0.150 – 0.157** (3.810 – 3.988)

7

0.050

(1.270)

MAX

8

GAUGE PLANE

0.004 – 0.010

(0.101 – 0.254)

S16 1098

0.165 – 0.185

(4.191 – 4.699)

0.500 – 0.750

(12.700 – 19.050)

REFERENCE PLANE

H8 (TO-5) 0.230 PCD 1197

6

OBSOLETE PACKAGE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LT1028/LT1128

TYPICAL APPLICATIO

5V

10Ω

1k

33Ω

+

100µF

RADIATION

IR

PHOTO-

ELECTRIC

PICK-OFF

OPTICAL

CHOPPER

WHEEL

267Ω

1000µF

+

INFRA RED ASSOCIATES, INC. HgCdTe IR DETECTOR 13Ω AT 77°K

+

100µF

39Ω

U

Low Noise Infrared Detector

SYNCHRONOUS DEMODULATOR

10k* 10k*

5V

3

2

+

LT1028

–

–5V

7

6

8

4

10k

10Ω

1/4 LTC1043

13

14

12

16

2

3

+

LM301A

–

4

–5V

5V

7

1

6

8

1M

30pF

5V

2

3

+

LT1012

–

4

–5V

7

6

DC OUT

8

1

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1806/LT1807 325MHz, 3.5nV/√Hz Single and Dual Op Amps Slew Rate = 140V/µs, Low Distortion at 5MHz: –80dBc

1028/1128 TA12

20

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

1028fa LT/CP 0901 1.5K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1992

Linear LT1028CS8, LT1128CS8 Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual