LG.Philips LCD LC470WUD-SAB1 Specification

)
(
Preliminary Specification
)
(
Final Specification
LC470WUD
Product Specification
SPECIFICATION
FOR
APPROVAL
47.0WUXGA TFT LCDTitle
MODEL
APPROVED BY
/
/
/
GeneralBUYER
SIGNATURE
DATE
LG Display Co., Ltd.SUPPLIER
LC470WUD*MODEL SAB1(RoHS Verified)SUFFIX
*When you obtain standard approval,
APPROVED BY
J.H.Lee / Team Leader
REVIEWED BY
P.Y. Kim / Project Leader
PREPARED BY
H.J.Kim / Engineer
SIGNATURE
DATE
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 0.1
TV Product Development Dept.
LG Display Co., Ltd
1/ 38
Product Specification
CONTENTS
LC470WUD
COVER CONTENTS
GENERAL DESCRIPTION1 ABSOLUTE MAXIMUM RATINGS2 ELECTRICAL SPECIFICATIONS3 ELECTRICAL CHARACTERISTICS3-1 INTERFACE CONNECTIONS3-2 SIGNAL TIMING SPECIFICATIONS3-3
SIGNAL TIMING WAVEFORMS3-4 COLOR DATA REFERENCE3-5
POWER SEQUENCE3-6 OPTICAL SPECIFICATIONS4 MECHANICAL CHARACTERISTICS5
ITEMNumber
Page
1 2
3RECORD OF REVISIONS 4 5 6 6 8
11 12
13 14 16 20
Ver. 0.1
RELIABILITY6 INTERNATIONAL STANDARDS7 SAFETY7-1 EMC7-2 PACKING8 DESIGNATION OF LOT MARK8-1 PACKING FORM8-2
23 24 24 24 25 25 25
26PRECAUTIONS9 26MOUNTING PRECAUTIONS9-1 26OPERATING PRECAUTIONS9-2 27ELECTROSTATIC DISCHARGE CONTROL9-3 27PRECAUTIONS FOR STRONG LIGHT EXPOSURE9-4 27STORAGE9-5 27HANDLING PRECAUTIONS FOR PROTECTION FILM9-6
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Product Specification
RECORD OF REVISIONS
Preliminary Specification (First Draft) -June. 30, 20080.1
LC470WUD
DescriptionPageRevision DateRevision No.
Ver. 0.1
3/ 38
LC470WUD
Product Specification
1. General Description
LC470WUD is a Color Active Matrix Liquid Crystal Display with anCold Cathode Fluorescent Lamp(CCFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally black mode. It has a 46.96 inch diagonally measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array) Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot, thus presenting a palette of more than 1.07Billion of colors. Ithas been designed to apply the 10-bit 4 port LVDS interface. It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast moving picture response time are important.
Mini-LVDS(RGB)
SDA
Source Driver Circuit
Gate Driver Circuit
S1S1920
G1
LVDS
2Port
CN2
(41pin)
LVDS 3,4
SDRAM
MEM CTRL
RGB
EEPROM
SCL
+12.0V
LVDS
2Port
LVDS Selection
+24.0V, GND, VBR-A,VBR-B
CN1
(51pin)
+24.0V, GND
LVDS 1,2
Option signal
I2C
General Features
Timing Controller
(ASIC)
Power Circuit
Block
Inverter(Master)
Inverter(Slave)
46.96 inch (1192.87mm) diagonalActive Screen Size
1096.0(H) x 640.0 (V) x 53.1 mm(D) (Typ.)Outline Dimension
0.5415 mm x 0.5415 mm x RGBPixel Pitch 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangementPixel Format
10Bit , 1.07 Billion colorsColor Depth 500 cd/m2 (Center 1point ,Typ.)Luminance, White
TFT -LCD Panel
(1920 × RGB × 1080 pixels)
G1080
3PinX1CN(High)
Back light Assembly
3PinX1CN(High)
Ver. 0.1
Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))Viewing Angle (CR>10) Total 221.22 W (Typ.) [Logic=8.22W, Backlight=213W (VBR-A=1.65V)]Power Consumption
14.5 Kg (Typ.) Weight Transmissive mode, Normally blackDisplay Mode Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 13%)Surface Treatment
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LC470WUD
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
Value
Parameter Remark
Symbol
Unit
MaxMin
Power Input
Voltage
LCM
VDC+27.0-0.3VBLBacklight inverter VDC+5.5-0.3VON/OFFON/OFF Control Voltage VDC+5.00VBRBrightness Control Voltage
+500TOPOperating Temperature
+60-20TSTStorage Temperature
°C
°C
%RH9010HOPOperating Ambient Humidity %RH9010HSTStorage Humidity
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39 °C Max. and no condensation of water.
2. Gravity mura can be guaranteed under 40°C condition.
90%
60
60%
at 25 ± 2 °CVDC+14.0-0.3VLCD
Note 1,2
Ver. 0.1
Wet Bulb Temperature [°C]
20
10
0
10203040506070800-20 Dry Bulb Temperature [°C]
30
40
50
40%
10%
Storage
Operation
Humidity [(%)RH]
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Product Specification
3. Electrical Specifications 3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the CCFL backlight circuit.
Table 2. ELECTRICAL CHARACTERISTICS
LC470WUD
Parameter Symbol
Value
Circuit :
Power Input Voltage
Power Input Current
Power Consumption Rush current
LCD
I
LCD
LCD
RUSH
Notes: 1. The specified current and power consumption are under the V
condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.
2. The current is specified at maximum current pattern.
3. The duration of rush current is about 2ms and rising time ofpower input is 0.5ms (min.).
White : 1023 Gray Black : 0 Gray
MaxTypMin
12.612.011.4V
=12.0V, 25 ± 2°C, fV=120Hz
LCD
V
DC
NoteUnit
1mA891685479 2mA1235950665 1Watt10.6868.22-P
3A5--I
Ver. 0.1
Mosaic Pattern(8 x 6)
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Product Specification
Table 3. ELECTRICAL CHARACTERISTICS for IPB& Lamp (Continue)
LC470WUD
Parameter Symbol
Inverter :
Power Supply
Input Current
Power Consumption
Input Voltage for
Control System
Signals
Lamp:
On/Off
OnVdc5.0-2.5V on Off
Brightness Adjust
Values
NotesUnit
MaxTypMin
Vdc25.224.022.8VBLPower Supply Input Voltage
1 1Vp-p0.5--Power Supply Input Voltage Ripple
8.8-
10.3
VBR-A = 1.65V 1A
IBL_AAfter Aging
10.0-
11.0-
11.0
12.0
VBR-A = 3.3V 1A VBR-A = 1.65V 2A
IBL_BBefore Aging
12.0-
13.0
VBR-A = 3.3V 2A VBL = 22.8V
VBR-B = 3.3V
A14.0--IrushPower Supply Input Current (In-Rush)
VBR-A = 1.65V
-PBL
250213
VBR-A = 1.65V 1W
Vdc3.31.650.0VBR-ABrightness Adjust
Vdc0.80.0-0.3V off
V3.3-0VBR-B
3min3Ts
4Hrs30,000Life Time
Notes :
1. Electrical characteristics are determined after the unit has been ONand stable for approximately 120 minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage 24Vand VBR (VBR-A : 1.65V & VBR-B :100%), it is total power consumption.
The ripple voltage of the power supply input voltage is under 0.5 Vp-p. LPL recommend Input Voltage is
24.0V ± 5%.
2. Electrical characteristics are determined within 30 minutesat 25±2°C. The specified currents are under the typical supply Input voltage 24V.
3. The brightness of the lamp after lighted for 5minutes is defined as 100%. TS is the time required for the brightness of the center of the lamp to be not less than 95% at typical current.
The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.
4. Specified Values are for a single lamp which is aligned horizontally. The life time is determined as the time which luminance ofthe lamp is 50% compared to that of initial value at the typical lamp current (VBR-A : 1.65V & VBR-B :3.3V), on condition of continuous operating at 25± 2°C
5. The duration of rush current is about 10ms.
Ver. 0.1
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LC470WUD
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51pin(CN1) and 41pin(CN2) connectors are used for the module electronics two 3-pin Balance PCB connectors are used for the integral backlight system.
3-2-1. LCD Module
-LCD Connector(CN1): FI-RE51S-HF or Equivalent, Refer to below table.
-Mating Connector : FI-RE51HL
Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION
10 11 12 13 14
16 17 18 19
21 22 23 24 25 26
DescriptionSymbolNo
GND 2 3
5 6
8 9
NC NC
NC NC
NC NC NC
GND
RA1N RA1P RB1N
RC1N RC1P
GND
RCLK1N
GND
RD1N RD1P RE1N RE1P
GND
Ground1 Reserved Reserved ReservedNC4 Reserved Reserved ‘‘H=JEIDA , L= VESA LVDS Select7 Reserved Reserved
Reserved
Ground FIRST CHANNEL A­FIRST CHANNEL A+ FIRST CHANNEL B­FIRST CHANNEL B+RB1P15 FIRST CHANNEL C­FIRST CHANNEL C+ Ground FIRST CLOCK CHANNEL Clk­FIRST CLOCK CHANNEL Clk+RCLK1P20 Ground FIRST CHANNEL D­FIRST CHANNEL D+ FIRST CHANNEL E-
FIRST CHANNEL E+ Ground
No
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
-
Symbol
NC
RA2N RA2P RB2N RB2P RC2N RC2P
GND RCLK2N RCLK2P
GND
RD2N RD2P RE2N RE2P
GND
GND
GND
GND
GND
NC
VLCD VLCD VLCD VLCD
-
NC SECOND CHANNEL A­SECOND CHANNEL A+ SECOND CHANNEL B­SECOND CHANNEL B+ SECOND CHANNEL C­SECOND CHANNEL C+ Ground SECOND CLOCK CHANNEL Clk­SECOND CLOCK CHANNEL Clk+ Ground SECOND CHANNEL D­SECOND CHANNEL D+ SECOND CHANNEL E­SECOND CHANNEL E+ Ground Ground Ground (NSB) Ground Ground No connection Power Supply +12.0V Power Supply +12.0V Power Supply +12.0V Power Supply +12.0V
Description
-
Notes : 1. All GND(ground) pins should be connected together to the LCD modules metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 664 Standard.
4. Specific pins(pin No. #2~#6) are used for internal data process of the LCD module. If not used, these pins are no connection.
5. Specific pins(pin No. #8~#9) are used for Inverter test of the LCD module. If not used, these pins are no connection.
6. Specific pin No. #44 is used for No signal detectionof system signal interface. It should be GND for NSB(No Signal Black) during the system interface signal is not. If this pin is H, LCD Module displays AGP(Auto Generation Pattern).
Ver. 0.1
8/ 38
Product Specification
-LCD Connector(CN2): FI-RE41S-HF or Equivalent, Refer to below table
-Mating Connector : FI-RE41HL
Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
LC470WUD
10 11 12
14 15 16 17
19 20 21
DescriptionSymbolNo
NC 2 3
5 6 7 8 9
NC
NC
NC4
NC
NC
NC
NC
GND
RA3N RA3P RB3N RB3P13 RC3N RC3P
GND RCLK3N RCLK3P18
GND
RD3N RD3P
No connection(Reserved)1 No connection No connection
No connection No connection
No connection No connection No connection
Ground Third CHANNEL A-
Third CHANNEL A+ Third CHANNEL B­Third CHANNEL B+ Third CHANNEL C­Third CHANNEL C+
Ground Third CLOCK CHANNEL Clk-
Third CLOCK CHANNEL Clk+ Ground Third CHANNEL D­Third CHANNEL D+
No
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
-
Symbol
RE3N RE3P
GND
GND RA4N RA4P RB4N RB4P RC4N RC4P
GND
RCLK4N RCLK4P
GND RD4N RD4P RE4N RE4P
GND
GND
Third CHANNEL E­Third CHANNEL E+
Ground Ground
Fourth CHANNEL A­Fourth CHANNEL A+ Fourth CHANNEL B­Fourth CHANNEL B+ Fourth CHANNEL C­Fourth CHANNEL C+
Ground Fourth CLOCK CHANNEL Clk-
Fourth CLOCK CHANNEL Clk+ Ground
Fourth CHANNEL D­Fourth CHANNEL D+ Fourth CHANNEL E­Fourth CHANNEL E+
Ground Ground
Description
Note : 1. All GND(ground) pins should be connected together to the LCD modules metal frame.
[CN1]
CN1 CN2
#1
#51#1#41
-Part/No. : FI-RE51S-HF(JAE)
-Mating connector : FI-RE51HL (Manufactured by JAE)
[CN2]
#1#51
#1#41
-Part/No. : FI-RE41S-HF(JAE)
-Mating connector : FI-RE41HL (Manufactured by JAE)
Rear view of LCM
Ver. 0.1
9/ 38
Product Specification
3-2-2. Backlight Inverter
Master
-Inverter Connector : S14B-PH-SMC (JST) or Equivalent
-Mating Connector : PHR-14 or Equivalent
Table 5. INVERTER CONNECTOR PIN CONFIGULATION
LC470WUD
Slave
-Inverter Connector : S12B-PH-SMC (JST) or Equivalent
-Mating Connector : PHR-12 or Equivalent
Master
Slave
NoteDescriptionSymbolPin No 1 2 3 4 5 6 7 8 9
10 11
12 13
14
VBR-A
ON/OFF
V
VBR-B
GND
Power Supply +24.0VV BL Power Supply +24.0VV BL Power Supply +24.0VV BL Power Supply +24.0VV BL Power Supply +24.0VV BL Backlight GroundGND Backlight GroundGND Backlight GroundGND Backlight GroundGND Backlight GroundGND
Analog dimming voltage DC 0.0V ~ 3.3V (Typ : 1.65V)
0.0V ~ 5.0V Burst dimming voltage
DC 0.0V ~ 3.3V
Normal : Upper 3.0V
Abnormal : Under 0.7V
VBL VBL VBL VBL
VBL GND GND GND GND GND
VBR-B
Notes : 1. GND should be connected to the LCD modules metal frame.
2. If Pin #11 is open, VBR-A = 1.65V. When apply over 1.65V( ~ 3.3V) continuously, its luminance is increasing however lamps life time is decreasing. It could be usable for boost up luminance when using DCR (=Dynamic contrast ratio) function only.
3. Minimum Brightness : VBR-B =0V Maximum Brightness : VBR-B = 3.3V
4. Even though Pin #14 is open, there is no effecton inverter operating, The output terminal of inverter.
5. Each impedance of pin #11,12 and 13 is 143[KΩ], 41[KΩ],105[KΩ]
Dont careOn/Off
VBL VBL VBL VBL
VBL GND GND GND GND GND
-
1
2, 3Dont careVBR-A
3
4-Status
Rear view of LCM
14
1
Ver. 0.1
<Master>
PCB
PCB
1
12
<Slave>
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LC470WUD
Product Specification
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timing should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE for NTSC/ATSC (DE Only Mode)
Symbol
Display Period
Horizontal
Blank
Total
Display Period
VerticalLines864510
Blank
Total
tHV tHB tHP tVV tVB tVP
Symbol
fCLK
fH fV
Frequency
DCLK
Horizontal
Vertical
tclk2007040 tclk680550520
Lines-1080-
Lines116611251090
75.0074.2566.97
136.4135121.8
121.2120108.2
MHz
KHz
Hz
NotesUnitMaxTypMinITEM
1920/4tclk-480-
NotesUnitMaxTypMinITEM
Table 7 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timing should be satisfied with the following specification for normal operation.
Table7. TIMING TABLE for DVB/PAL (DE Only Mode)
Display Period
Symbol
tHV
-480-
tclk
NotesUnitMaxTypMinITEM
1920/4
Horizontal
Vertical
Frequency
Blank
Total
Display Period
Blank
Total
DCLK
Horizontal
Vertical
tHB tHP tVV tVB tVP
Symbol
fCLK
fH fV
2007040 680550520
-1080-
300270228
138013501308
75.0074.2566.97
136.4135121.8
103.710095
tclk
tclk Lines Lines Lines
NotesUnitMaxTypMinITEM
MHz
KHz
Hz
Note : The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
The performance of the electro-optical characteristics may be influenced by variance of the vertical refresh rate.
Ver. 0.1
11/ 38
Product Specification
LC470WUD
3-4. Signal Timing Waveforms
DE, Data
DCLK
tCLK
First data
Second data
Third data
Forth data
DE(Data Enable)
0.5 VDD
Invalid data
Invalid data
Invalid data
Invalid data
0.7VDD
Valid data
Pixel 0Pixel 4
Valid data
Pixel 1Pixel 5
Valid data
Pixel 2
Pixel 3
Pixel 6
Valid data
Pixel 7
0.3VDD
Invalid data
Invalid data
Invalid data
Invalid data
* Reference : Sync. Relation
HSync
DE(Data Enable)
VSync
DE(Data Enable)
Ver. 0.1
tWH
tHBP tHV
tWV
tVBP
* tHB = tHFP + tWH +tHBP * tVB = tVFP + tWV +tVBP
tHP
tHFP
tVP
tVV tVFP
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