LG Display LP173WD1-TLP4 Specification

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LP173WD1

Liquid Crystal Display

Product Specification

SPECIFICATION

FOR

APPROVAL

)

(

(

Preliminary Specification



)

Final Specification

17.3” HD+ TFT LCDTitle

LG Display Co., Ltd.SUPPLIER

LP173WD1*MODEL

TLP4Suffix

MODEL

APPROVED BY

/

/

HPBUYER

*When you obtain standard approval,

please use the above model name without suffix

APPROVED BY SIGNATURE

SIGNATURE

H. S. Kim / S.Manager

REVIEWED BY

C. I. Kim / Manager

PREPARED BY

/

S. J. Yun / Engineer

S. C. Jung / Engineer

Please return 1 copy for your confirmation with
your signature and comments.

Ver. 0.1 5. Sep, 2010

Product Engineering Dept.

LG Display Co., Ltd

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LP173WD1

Liquid Crystal Display

Product Specification

Contents

COVER

CONTENTS

RECORD OF REVISIONS

GENERAL DESCRIPTION1

ABSOLUTE MAXIMUM RATINGS2

ELECTRICAL SPECIFICATIONS3

ELECTRICAL CHARACTREISTICS3-1

INTERFACE CONNECTIONS3-2

LVDS SIGNAL TIMING SPECIFICATIONS3-3

SIGNAL TIMING SPECIFICATIONS3-4

SIGNAL TIMING WAVEFORMS3-5

COLOR INPUT DATA REFERNECE3-6

POWER SEQUENCE3-7

OPTICAL SFECIFICATIONS4

ITEMNo

Page

1

2

3

4

5

6

8

10

10

11

12

12

MECHANICAL CHARACTERISTICS5

RELIABLITY6

INTERNATIONAL STANDARDS7

SAFETY7-1

EMC7-2

PACKING8

DESIGNATION OF LOT MARK8-1

PACKING FORM8-2

PRECAUTIONS9

APPENDIX A. Enhanced Extended Display Identification DataA

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21

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LP173WD1

Liquid Crystal Display

Product Specification

RECORD OF REVISIONS

DescriptionPageRevision DateRevision No

First Draft-Sep. 05, 20100.1

EDID

ver

Ver. 0.1 5. Sep, 2010

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1. General Description

The LP173WD1 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally white mode. This TFT-LCD has 17.3 inches diagonally measured active display area with
WHD+ resolution(1600 horizontal by 900 vertical pixel array). Each pixel is divided into Red, Green and
Blue sub-pixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel
color is determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than
262,144 colors. The LP173WD1 has been designed to apply the interface method that enables low power,
high speed, low EMI. The LP173WD1 is intended to support applications where thin thickness, low power
are critical factors and graphic displays are important. In combination with the vertical arrangement of the
sub-pixels, the LP173WD1 characteristics provide an excellent flat display for office automation products
such as Notebook PC.

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LP173WD1

Liquid Crystal Display

Product Specification

User connector

40

Pin

General Features

EEPROM Block

EEPROM Block

for EDID

for EDID

EEPROM Block

EEPROM Block

for Tcon Operating

for Tcon Operating

Timing Control

LVDS

2port

VCC

VLED

LED_EN

PWM

Timing Control

(Tcon) Block

(Tcon) Block

DVCC

Power

Block

LED Driver

LED Driver

Block

TCLKs

Power

Block

Block

VGH, VGL, GMA

Control & Data Power

17.3 inches diagonal Active Screen Size

398.1(H, Typ.) Ý232.8 (V, Typ.) Ý 6.5(D, Max.) mmOutline Dimension

0.23868 X 0.23868 mmPixel Pitch

1600 horiz. by 900 vert. Pixels RGB strip arrangementPixel Format

6-bit, 262,144 colorsColor Depth

200 cd/m

Total : 6.0 W (Logic : typ. 2.0W @Mosaic, Back Light : typ. 4.0W)Power Consumption

585g (Max.)Weight

Transmissive mode, normally whiteDisplay Operating Mode

Anti Glare treatment of the front PolarizerSurface Treatment

YesRoHS Comply

Yes allBFR / PVC / As Free

2

(Typ., @I

M

i

n

i

-

L

V

D

S

AVCC, AVDD

GIP CLKs, DSC

=23mA)Luminance, White

LED

1

900

1600

TFT-LCD Panel

(HD, GIP, TN)

LED Backlight Ass’y

Source Driver

(Bottom Bent)

VOUT_LED

FB 1~5

EDID signal & Power

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୅

2. Absolute Maximum Ratings

The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.

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LP173WD1

Liquid Crystal Display

Product Specification

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Notes

Symbol

Values

MaxMin

Units

Power Input Voltage

Operating Temperature

Storage Temperature

Operating Ambient Humidity

OP

Storage Humidity

Note : 1. Temperature and relative humidity range are shown in the figure below.

Wet bulb temperature should be 39

Wet Bulb
Temperature [

10

0

20

]

30

qC Max, and no condensation of water.

90% 80%

60

50

40

60%

Humidity[(%)RH]

40%

20%

10%

Storage

Operation

at 25 r 5qCVdc4.0-0.3VCC

1qC500TOP

1qC60-20HST

1%RH9010H

1%RH9010HST

-20

10

20 30 40 50

60 70 800

Dry Bulb Temperature [୅]

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3. Electrical Specifications

3-1. Electrical Characteristics

The LP173WD1 requires two power inputs. The first logic is employed to power the LCD electronics and to

drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.

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LP173WD1

Liquid Crystal Display

Product Specification

Table 2. ELECTRICAL CHARACTERISTICS

LOGIC :

Power Supply Input Current

BACKLIGHT : ( with LED Driver)

PWM Jitter

Values

SymbolParameter

NotesUnit

MaxTypMin

CCPower Supply Input Voltage

CCMosaic

CC_maxBlack

CCPower Consumption

CC_PPower Supply Inrush Current

LVDSLVDS Impedance

LEDLED Power Input Voltage

LEDLED Power Input Current

LEDLED Power Consumption

LED_PLED Power Inrush Current

11010090Z

ȳ

1V3.63.33.0V

2mA690600-I

3mA920800-I

2W2.32.0-P

4mA1500--I

5

6V21.012.07.0V

7mA350330-I

7W4.24.0-P

8mA1500--I

9%100-6PWM Duty Ratio

-

10%0.2-0

PWMPWM Impedance

PWMPWM Frequency

PWM High Level Voltage

PWM Low Level Voltage

LED_EN High Voltage

LED_EN Low Voltage

Ver. 0.1 5. Sep, 2010

PWM_H

PWM_L

PWMLED_EN Impedance

V

LED_EN

LED_EN

V

_H

_L

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kȳ604020Z

11Hz1500-200F

V5.3-3.0V

V0.5-0V

kȳ604020Z

V5.3-3.0

V0.5-0

12Hrs--12,000Life Time

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Note)

1. The measuring position is the connector of LCM and the test conditions are under 25୅, fv = 60Hz,

Black pattern.

2. The specified Icc current and power consumption are under

the Vcc = 3.3V , 25୅, fv = 60Hz condition and Mosaic pattern.

3. This Spec. is the max load condition for the cable impedance designing.

4. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.

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LP173WD1

Liquid Crystal Display

Product Specification

Rising time
Vcc

0V

5. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.

6. The measuring position is the connector of LCM and the test conditions are under 25୅.

7. The current and power consumption with LED Driver are under the Vled = 12.0V , 25୅, Dimming of

Max luminance and White pattern with the normal frame frequency operated(60Hz).

8. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.

90%

10%

0.5ms

3.3V

Rising time

LED

V

0V

10%

12.0V

90%

0.5ms

9. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.

10. If Jitter of PWM is bigger than maximum, it may induce flickering.

11. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent

to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.

12. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum

value specified in table 7. under general user conditionU

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3-2. Interface Connections

This LCD employs two interface connections, a 40 pin connector is used for the module electronics interface
and the other connector is used for the integral backlight system.

.

Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)

10

11

12

13

14

15

16

17

18

19

20

21

19

23

24

19

26

27

19

29

30

31

32

33

34

35

36

37

38

39

40

1

2

3

4

5

6

7

8

9

ERX0+ Positive LVDS differential data input

NC

NC

No ConnectionNC
LCD Logic and driver power (3.3V Typ.)VCC
LCD Logic and driver power (3.3V Typ.)VCC
DDC Power (3.3V)V EEDID
No ConnectionNC
DDC ClockClk EEDID
DDC DataDATA EEDID
Negative LVDS differential data inputORX0­Positive LVDS differential data inputORX0+
LCM GroundGND
Negative LVDS differential data inputORX1­Positive LVDS differential data inputORX1+
LCM GroundGND
Negative LVDS differential data inputORX2­Positive LVDS differential data inputORX2+
LCM GroundGND
Negative LVDS differential clock inputORXC­Positive LVDS differential clock inputORXC+
LCM GroundGND
Negative LVDS differential data inputERX0-

LCM GroundGND
Negative LVDS differential data inputERX1­Positive LVDS differential data inputERX1+
LCM GroundGND
Negative LVDS differential data inputERX2­Positive LVDS differential data inputERX2+
LCM GroundGND
Negative LVDS differential clock inputERXC­Positive LVDS differential clock inputERXC+
LCM Ground (LED Backlight Ground)GND
LCM Ground (LED Backlight Ground)GND
LCM Ground (LED Backlight Ground)GND

No Connection
System PWM Signal input for dimmingPWM

LED Backlight On/OffLED_EN
No Connection

LED Backlight PowerVLED
LED Backlight PowerVLED
LED Backlight PowerVLED

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Product Specification

LP173WD1

Liquid Crystal Display

NotesDescriptionSymbolPin

[Interface Chip]

[Interface Chip]

1. LCD :
SiW, SW0617(LCD Controller)
Including LVDS Receiver.

2. System : SiW LVDSRx or equivalent
* Pin to Pin compatible with LVDS

[Connector]

LSMtron GT05Q-40S-H10 or equivalent

[Mating Connector]

Mating of IPEX 20455-040 of compatible

[Connector pin arrangement]



[LCD Module Rear View]



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3-3. LVDS Signal Timing Specifications

3-3-1. DC Specification

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LP173WD1

Liquid Crystal Display

Product Specification

Description

LVDS Common mode Voltage

LVDS Input Voltage Range

3-3-2. AC Specification

LVDS Clock to Data Skew Margin

Symb

ol

ID

CM

IN

SKEW

SKEW

NotesUnitMaxMin

|LVDS Differential Voltage

-mV600100|V

-V1.80.6V

-V2.10.3V

NotesUnitMaxMinSymbolDescription

85MHz > Fclk ˻

65MHz

65MHz > Fclk ˻

25MHz

- 600

ps+ 400- 400t

ps+ 600t

LVDS Clock to Clock Skew Margin (Even
to Odd)

SKEW_EO

Maximum deviation
of input clock frequency during SSC

DEV

Maximum modulation frequency
of input clock during SSC

Ver. 0.1 5. Sep, 2010

MOD

-1/7

+ 1/7t

T

clk

%· 3-F

KHz200-F

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