LG Display LP173WD1-TLE1 Specification

( ) Preliminary Specification (●) Final Specification
LP173WD1
Liquid Crystal Display
Product Specification
SPECIFICATION
FOR
APPROVAL
BUYER General
MODEL
APPROVED BY
/
/
/
SIGNATURE
SUPPLIER LG Display Co., Ltd.
*MODEL LP173WD1
Suffix TLE1
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY SIGNATURE
J. Y. Lee / S.Manager
REVIEWED BY
Y. S. Ha / Manager
PREPARED BY
C. W. Lee / Engineer B. H. Kim / Engineer
Please return 1 copy for your confirmation with your signature and comments.
Ver. 1.0 Jun. 14, 2012
Product Engineering Dept.
LG Display Co., Ltd
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Product Specification
Contents
LP173WD1
Liquid Crystal Display
No
COVER CONTENTS RECORD OF REVISIONS
1 2
3
4 OPTICAL SFECIFICATIONS
GENERAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS ELECTRICAL CHARACTREISTICS
3-1
INTERFACE CONNECTIONS
3-2
LVDS SIGNAL TIMING SPECIFICATIONS
3-3 3-4 SIGNAL TIMING SPECIFICATIONS 3-5 SIGNAL TIMING WAVEFORMS
3-6 COLOR INPUT DATA REFERNECE 3-7 POWER SEQUENCE
ITEM
Page
1 2 3 4 5
6-7
8
9-10
11 11
12 13
14-16
5 MECHANICAL CHARACTERISTICS 6 RELIABLITY 7 INTERNATIONAL STANDARDS
7-1 SAFETY 7-2 EMC
8 PACKING
8-1 DESIGNATION OF LOT MARK 8-2 PACKING FORM
9 PRECAUTIONS
A APPENDIX A. Enhanced Extended Display Identification Data
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21 22
23
24
26-28
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Product Specification
RECORD OF REVISIONS
LP173WD1
Liquid Crystal Display
Revision No Revision Date Page Description
0.0 Mar. 2, 2012 - First Draft (Preliminary Specification)
0.1 May.11, 2012 26-28 Update EDID 0.0
0.2 May.15, 2012 4 Update General Features 0.0 6 Update Electrical Specifications 8 Update Connector
14-15 Update Optical Specification
19 Update Rear View
1.0 Jun.14, 2012 3 Update EDID Ver. For Final Draft (v0.0 v1.0) 1.0
EDID
ver
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LP173WD1
Liquid Crystal Display
Product Specification
1. General Description
The LP173WD1 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally white mode. This TFT-LCD has 17.3 inches diagonally measured active display area with WHD+ resolution(1600 horizontal by 900 vertical pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144 colors. The LP173WD1 has been designed to apply the interface method that enables low power, high speed, low EMI. The LP173WD1 is intended to support applications where thin thickness, low power are critical factors and graphic displays are important. In combination with the vertical arrangement of the sub-pixels, the LP173WD1 characteristics provide an excellent flat display for office automation products such as Notebook PC.
EEPROM Block
for EDID
EEPROM Block
User connector
for Tcon Operating
1
TFT-LCD Panel
40
Pin
LVDS
2port
VCC
VLED
LED_EN
PWM
Timing Control
(Tcon) Block
DVCC
Power
Block
LED Driver
Block
TCLKs
VGH, VGL, GMA
Control & Data Power
900
AVCC, AVDD
GIP CLKs, DSC
(HD, GIP, TN)
Source Driver (Bottom Bent)
FB 1~4
EDID signal & Power
General Features
Active Screen Size 17.3 inches diagonal Outline Dimension Pixel Pitch 0.23868 X 0.23868 mm Pixel Format 1600 horiz. by 900 vert. Pixels RGB strip arrangement Color Depth 6-bit, 262,144 colors Luminance, White 220 cd/m2(Typ., @I Power Consumption Total : 6.1 W (Typ.) [ Logic : 1.3 W (Typ.) @Mosaic, Back Light : 4.8 W (Typ.) ] Weight 570g (Max.) Display Operating Mode Transmissive mode, normally white
Surface Treatment Glare treatment of the front Polarizer RoHS Comply Yes BFR / PVC / As Free Yes for all
398.1(H, Typ.) × 232.8(V, Typ.) × 6.0(D, Max.) mm
=27mA)
LED
1600
LED Backlight Ass‟y
VOUT_LED
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LP173WD1
Liquid Crystal Display
Product Specification
2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Power Input Voltage Operating Temperature Storage Temperature Operating Ambient Humidity Storage Humidity
VCC -0.3 4.0 Vdc at 25 5C
TOP 0 50 C 1 HST -20 60 C 1 HOP 10 90 %RH 1 HST 10 90 %RH 1
Values
Units Notes
Min Max
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39C Max, and no condensation of water.
90% 80%
60%
Humidity[(%)RH]
Storage
40%
Operation
20%
10%
Wet Bulb Temperature []
20
10
0
60
50
40
30
-20
10
20 30 40 50
60 70 800
Dry Bulb Temperature []
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LP173WD1
Liquid Crystal Display
Product Specification
3. Electrical Specifications 3-1. Electrical Characteristics
The LP173WD1 requires two power inputs. The first logic is employed to power the LCD electronics and to drive the TFT array and liquid crystal. The second backlight is the input about LED BL.with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS
Parameter Symbol
Unit Notes
Min Typ Max
LOGIC :
Power Supply Input Voltage VCC 3.0 3.3 3.6 V 1 Power Supply Input Current Mosaic ICC - 400 460 mA 2 Power Consumption PCC - 1.3 1.5 W 2 Power Supply Inrush Current ICC_P - - 1500 mA 4 LVDS Impedance ZLVDS 90 100 110 Ω 5
BACKLIGHT : ( with LED Driver)
LED Power Input Voltage VLED 7.0 12.0 20.0 V 6 LED Power Input Current ILED - 400 435 mA 7 LED Power Consumption PLED - 4.8 5.2 W 7 LED Power Inrush Current ILED_P - - 2000 mA 8 PWM Duty Ratio 6 - 100 % 9
Values
PWM Jitter
-
0 - 0.2 % 10
PWM Impedance ZPWM 20 40 60 PWM Frequency FPWM 200 - 1000 Hz 11 PWM High Level Voltage V
PWM Low Level Voltage V
PWM_H
PWM_L
3.0 - 3.6 V 0 - 0.3 V
LED_EN Impedance ZPWM 20 40 60 LED_EN High Voltage VLED_EN_H 3.0 - 3.6 V LED_EN Low Voltage VLED_EN_L 0 - 0.3 V Life Time 12,000 - - Hrs 12
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LP173WD1
Liquid Crystal Display
Product Specification
Note)
1. The measuring position is the connector of LCM and the test conditions are under 25, fv = 60Hz, Black pattern.
2. The specified Icc current and power consumption are under the Vcc = 3.3V , 25, fv = 60Hz condition and Mosaic pattern.
3. This Spec. is the max load condition for the cable impedance designing.
4. The below figures are the measuring Vcc condition and the Vcc control block LGD used. The Vcc condition is same as the minimum of T1 at Power on sequence.
Rising time Vcc
0V
10%
90%
3.3V
0.5ms
5. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.
6. The measuring position is the connector of LCM and the test conditions are under 25.
7. The current and power consumption with LED Driver are under the Vled = 12.0V , 25, Dimming of Max luminance and White pattern with the normal frame frequency operated(60Hz).
8. The below figures are the measuring Vled condition and the Vled control block LGD used. VLED control block is same with Vcc control block.
Rising time VLED
0V
10%
90%
12.0V
0.5ms
9. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
10. If Jitter of PWM is bigger than maximum, it may induce flickering.
11. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for more consistent brightness control at any specific level desired.
12. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user condition.
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LP173WD1
Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector is used for the module electronics interface and the other connector is used for the integral backlight system. .
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
Pin Symbol Description Notes
1 2 3 4 5 6 7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
34
35 36 37 38 39 40
NC No Connection VCC LCD Logic and driver power (3.3V Typ.) VCC LCD Logic and driver power (3.3V Typ.)
V EEDID DDC Power (3.3V)
NC No Connection
Clk EEDID DDC Clock
DATA EEDID DDC Data
ORX0- Negative LVDS differential data input
ORX0+ Positive LVDS differential data input
GND LCM Ground
ORX1- Negative LVDS differential data input
ORX1+ Positive LVDS differential data input
GND LCM Ground
ORX2- Negative LVDS differential data input
ORX2+ Positive LVDS differential data input
GND LCM Ground
ORXC- Negative LVDS differential clock input
ORXC+ Positive LVDS differential clock input
GND LCM Ground
ERX0- Negative LVDS differential data input
ERX0+ Positive LVDS differential data input
GND LCM Ground
ERX1- Negative LVDS differential data input
ERX1+ Positive LVDS differential data input
GND LCM Ground
ERX2- Negative LVDS differential data input
ERX2+ Positive LVDS differential data input
GND LCM Ground
ERXC- Negative LVDS differential clock input
ERXC+ Positive LVDS differential clock input
GND LCM Ground (LED Backlight Ground) GND LCM Ground (LED Backlight Ground) GND LCM Ground (LED Backlight Ground)
NC
No Connection
PWM System PWM Signal input for dimming
LED_EN LED Backlight On/Off
NC
No Connection
VLED LED Backlight Power VLED LED Backlight Power VLED LED Backlight Power
[Interface Chip]
1.1 LCD : SW, SW0656 (LCD Controller) including LVDS Receiver
1.2 System : SiW LVDSRx or equivalent
* Pin to Pin compatible with LVDS
[Connector]
Hirose KN38-40S-0.5H or equivalent
[Mating Connector]
Mating of IPEX 20455-040E or equivalent
[Connector pin arrangement]
40
[LCD Module Rear View]
1
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Product Specification
LVDS +
LVDS -
0V
V
CM
# |VID| = |(LVDS+) – (LVDS-)| # VCM = {(LVDS+) + (LVDS-)}/2
|VID|
V
IN_MAXVIN_MIN
LVDS Data
t
SKEW
LVDS Clock
T
clk
t
SKEW (Fclk
= 1/T
clk
)
1) 85MHz > Fclk 65MHz : -400 ~ +400
2) 65MHz > Fclk 25MHz : -600 ~ +600
3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
LP173WD1
Liquid Crystal Display
Description
Symb
ol
Min Max Unit Notes
LVDS Differential Voltage |VID| 100 600 mV ­LVDS Common mode Voltage V LVDS Input Voltage Range V
CM
IN
0.6 1.8 V -
0.3 2.1 V -
3-3-2. AC Specification
Description Symbol Min Max Unit Notes
85MHz > Fclk ≥
65MHz > Fclk ≥
LVDS Clock to Data Skew Margin
t
SKEW
t
SKEW
- 400 + 400 ps
- 600 + 600 ps
65MHz
25MHz
LVDS Clock to Clock Skew Margin (Even to Odd)
Maximum deviation of input clock frequency during SSC
Maximum modulation frequency of input clock during SSC
Ver. 1.0 Jun. 14, 2012
t
SKEW_EO
F
DEV
F
MOD
- 1/7 + 1/7 T
-
± 3
clk
% -
- 200 KHz -
-
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