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LP173WD1-TLA1
Specification
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LG Display LP173WD1-TLA1 Specification

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LP173WD1
Liquid Crystal Display
Product Specification
FOR
APPROVAL
)
( (
Preliminary Specification
●
)
Final Specification
17.3” HD+ TFT LCDTitle
LG Display Co., Ltd.SUPPLIER LP173WD1*MODEL TLA1Suffix
MODEL
APPROVED BY
/
/
QuantaBUYER
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY SIGNATURE
SIGNATURE
K. J. KWON / S.Manager
REVIEWED BY
G. J. Han / Manager
PREPARED BY
/
Please return 1 copy for your confirmation with your signature and comments.
Ver. 0.0 18. Nov, 2008
H. M. Yoon / Engineer
M. S. Yeom / Engineer
Product Engineering Dept.
LG Display Co., Ltd
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LP173WD1
Liquid Crystal Display
Product Specification
Contents
COVER CONTENTS RECORD OF REVISIONS GENERAL DESCRIPTION1 ABSOLUTE MAXIMUM RATINGS2
ELECTRICAL SPECIFICATIONS3 ELECTRICAL CHARACTREISTICS3-1
INTERFACE CONNECTIONS3-2 LVDS SIGNAL TIMING SPECIFICATIONS3-3
SIGNAL TIMING SPECIFICATIONS3-4 SIGNAL TIMING WAVEFORMS3-5
COLOR INPUT DATA REFERNECE3-6 POWER SEQUENCE3-7 OPTICAL SFECIFICATIONS4
ITEMNo
Page
1 2 3 4
5 6
8
10 10 11 12 12
MECHANICAL CHARACTERISTICS5 RELIABLITY6 INTERNATIONAL STANDARDS7 SAFETY7-1 EMC7-2 PACKING8 DESIGNATION OF LOT MARK8-1 PACKING FORM8-2 PRECAUTIONS9 APPENDIX A. Enhanced Extended Display Identification DataA
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16 23
24 24
25 25 26 28
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LP173WD1
Liquid Crystal Display
Product Specification
RECORD OF REVISIONS
DescriptionPageRevision DateRevision No
First Draft-Nov. 18, 20080.0
EDID
ver
0.0
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1. General Description
The LP173WD1 is a Color Active Matrix Liquid Cr ystal Display with an integra l LED backlight system. The matrix employs a-Si Thin Film Tran sis tor as the active element. It is a trans missi ve type d isplay ope rating in the normally white mode. This TFT-LCD has 17.3 inches diagonally measured active display area with WHD+ resolution(1600 horizontal by 900 vertical pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vert ical stripes. Gray s cale or the brightness of the sub-pixel color is determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144 colors.
The LP173WD1 has been designed to apply the in terface method that enables low power, high speed, low EMI.
The LP173WD1 is intended to support applications where thin th ickness, low power are critical factor s and graphic displays are important. In combination with the vertical arrangement of the sub-pixels, the LP173WD1 characteristics provide an exce llent flat display for office automa tion products such as Notebook PC.
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LP173WD1
Liquid Crystal Display
Product Specification
CN
1
User connector
40
Pin
General Features
LVDS & Timing
900
GIP(Gate In Panel)
Control
Block
TFT-LCD Panel
(1600 x 900)
POWER
BLOCK
1
(LOG_B type)
1
Source Driver Circuit
EDID
BLOCK
LED Backlight Ass’y
Control & Data Power EDID signal & Power
17.3 inches diagonal Active Screen Size
398.1(H, Typ.) × 232.8(V, Typ.) × 6.0(D, Max.) mmOutline Dimension
0.2388 X 0.2388 mmPixel Pitch 1600 horiz. by 900 vert. Pixels RGB strip arrangementPixel Format 6-bit, 262,144 colorsColor Depth 220 cd/m Total 6.5W(Typ.) Logic : 1.5 W (Typ.@Mosaic), B/L : 5.0W (Typ.)Power Consumption 570g (Max.)Weight Transmissive mode, normally whiteDisplay Operating Mode
Glare treatment of the front Polarizer Surface Treatment
2
(Typ., @I
LED
=TBD)Luminance, White
1600
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2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
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LP173WD1
Liquid Crystal Display
Product Specification
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Notes
Symbol
Values
MaxMin
Units
Power Input Voltage Operating Temperature Storage Temperature Operating Ambient Humidity
OP
Storage Humidity
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39
Wet Bulb Temperature [℃]
30
20
10
0
°C Max, and no condensation of water.
90% 80%
60
50
40
60%
Humidity[(%)RH]
40%
20%
10%
Storage
Operation
at 25 ± 5°CVdc4.0-0.3VCC
1°C500TOP 1°C60-20HST 1%RH9010H 1%RH9010HST
-20
10
20 30 40 50
60 70 800
Dry Bulb Temperature [℃]
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3. Electrical Specifications 3-1. Electrical Characteristics
The LP173WD1 requires two power inputs. The first logic is employed to power the LCD electronics and to drive the TFT array and liquid crystal. The second backlight is the input about LED BL.with LED Driver.
Parameter Symbol
LOGIC :
BACKLIGHT : ( with LED Driver)
PWM High Level Voltage PWM Low Level Voltage LED_EN High Voltage LED_EN Low Voltage
Note)
1. The specified Icc current and power consumption are under the Vcc = 3.3V , 25℃, fv = 60Hz condition whereas Mosaic pattern is displayed and fv is the frame frequency.
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Product Specification
Table 2. ELECTRICAL CHARACTERISTICS
Values
CCPower Supply Input Voltage
CCPower Supply Input Current
I
LEDLED Power Input Voltage
LEDLED Power Comsumption
LED_PLED Power Inrush Current
PWMPWM Impedance PWMPWM Frequency
PWM_H
PWM_L LED_EN_H LED_EN_L
Liquid Crystal Display
MaxTypMin
V3.63.33.0V
mA1800--ICC_PPower Supply Inrush Current
11010090ZLVDSLVDS Impedance
TBDTBDTBDZ
Ω
V20.0TBD7.0V
mATBD--I
Ω
V53.32.1V V0.8-0V V53.32.1V V0.8-0V
LP173WD1
NotesUnit
1mA515455­1W1.71.5-PCCPower Consumption
2
3mATBDTBD-ILEDLED Power Input Current 3W5.35.0-P
4%100-12.5-PWM Dimming (Duty) Ratio
5Hz1500200F
6Hrs--12,000Life Time
2. This impedance value is needed to proper display and measured form LVDS Tx to the mating connector.
3. The specified LED current and power consumption are under the Vled = 12.0V , 25℃, Dimming of Max
luminance whereas White pattern is displayed and fv is the frame frequency.
4. The operation of LED Driver below minimum dimming ratio may cause flikering or relaibility issue.
5. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for more consistent brightness control at any specific level desired.
6. The life time is determined as the time at which brightness of LCD is 50% compare to that of initial value at the typical LED current. These LED backlight has 6 strings on it and the typical current of LED’s string is base on 20mA.
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3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector is used for the module electronics interface and the other connector is used for the integral backlight system.
The electronics interface connector is a model UJU
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
No Connection.NC1 Power Supply (3.3V typ.)VDD2 Power Supply (3.3V typ.)VDD3
4
6 7
EDID
EDID
EDID
VSS
DDC 3.3V powerV No Connection.NC5 DDC clock / SMBus clockCLK DDC data / SMBus dataDATA
- LVDS differential data input (R0-R5,G0)Odd_Rin0-8 + LVDS differential data input (R0-R5,G0)Odd_Rin0+9 Ground10
- LVDS differential data input (G1-G5,B0-B1)Odd_Rin1-11 + LVDS differential data input (G1-G5,B0-B1)Odd_Rin1+12 GroundVSS13
- LVDS differential data input (B2-B5,HS,VS,DE)Odd_Rin2-14 + LVDS differential data input (B2-B5,HS,VS,DE)Odd_Rin2+15 GroundVSS16
- LVDS differential clock inputOdd_ClkIN-17 + LVDS differential clock inputOdd_ClkIN+18 No ConnectionNC19
- LVDS differential data input (R0-R5,G0)Even Rin0-20 + LVDS differential data input (R0-R5,G0)Even Rin0+21 GroundVSS22
- LVDS differential data input (G1-G5,B0-B1)Even Rin1-23 + LVDS differential data input (G1-G5,B0-B1)Even Rin1+24 GroundVSS25
- LVDS differential data input (B2-B5,HS,VS,DE)Even Rin2-26 + LVDS differential data input (B2-B5,HS,VS,DE)Even Rin2+27 GroundVSS28
- LVDS differential clock inputEven ClkIN-29 + LVDS differential clock inputEven ClkIN+30 LED power returnVBL-31 LED power returnVBL-32 LED power returnVBL-33 No Connection.NC34 PWM for luminance controlBLIM35 BL On/OffBL_EN36 No Connection.NC37 7V-20V LED powerVBL+38 7V-20V LED powerVBL+39 7V-20V LED powerVBL+40
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LP173WD1
Liquid Crystal Display
Product Specification
20455-040E manufactured by UJU.
NotesDescriptionSymbolPin
[Interface Chip]
1. LCD : SW, SW0617(LCD Controller) Including LVDS Receiver.
2. System : SiWLVDSRx or equivalent
* Pin to Pin compatible with LVDS
[Connector]
UJU 20455-040E
[Mating Connector]
20345-#40E-## series or equivalent
[Connector pin arrangement]
140
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3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
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LP173WD1
Liquid Crystal Display
Product Specification
Description
LVDS Common mode Voltage LVDS Input Voltage Range
3-3-2. AC Specification
LVDS Clock to Data Skew Margin
Symb
ol
ID
CM
IN
SKEW
SKEW
NotesUnitMaxMin
|LVDS Differential Voltage
-mV600100|V
-V1.80.6V
-V2.10.3V
NotesUnitMaxMinSymbolDescription
85MHz > Fclk ≥
65MHz
65MHz > Fclk ≥
25MHz
- 600
ps+ 400- 400t
ps+ 600t
LVDS Clock to Clock Skew Margin (Even to Odd)
SKEW_EO
Maximum deviation of input clock frequency during SSC
DEV
Maximum modulation frequency of input clock during SSC
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MOD
-1/7
+ 1/7t
T
clk
%± 3-F
KHz200-F
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Freq.
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LP173WD1
Liquid Crystal Display
Product Specification
< Clock skew margin between channel >
F
max
F
center
F
min
3-3-3. Data Format
1) LVDS 1 Port
RCLK+
RA+/-
RB+/-
R3 R2
G4 G3
R1 R0
G2 G1
1
F
MOD
< Spread Spectrum >
G0 R5 R4 R3 R2 R1 R0
B1 B0 G5 G4 G3 G2 G1
F
G0
B1
center
* F
DEV
Time
R5 R4
B0 G5
RC+/-
RD+/-
B5 B4
G7 G6
Previous (N-1 )th Cycle Next(N+1)th Cycle
B3 B2
R7 R6
DE VSYNC HSYNC B5 B4 B3 B2
X B7 B6 G7 G6 R7 R6
Current (Nth ) Cycle
DE
VSYNC HSYNC
X
B7 B6
< LVDS Data Format >
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3-4. Signal Timing Specifications
This is the signal timing required at the input of the User connector. All of the interface signal timing should be satisfied with the following specifications and specifications of LVDS Tx/Rx for its proper operation.
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LP173WD1
Liquid Crystal Display
Product Specification
Table 5. TIMING TABLE
NoteUnitMax.Typ.Min.SymbolITEM
FrequencyDCLK Period WidthHsync Width-Active Period
Vsync
Data
Enable
Width Width-Active Horizontal back porch Horizontal front porch Vertical back porch Vertical front porch
3-5. Signal Timing Waveforms
f
CLK
t
HP
t
WH
tw
HA
t
VP
t
WV
tw
VA
t
HBP
t
HFP
t
VBP
t
VFP
High: 0.7VCC
Low: 0.3VCC
-97.75-
179617601724
403224
160016001600
935926916
853
900900900
968064
MHz
tCLK
tHP
tCLK
604836 221811
tHP
532
Condition : VCC=3.3V
t
Hsync
t
WH
t
HBP
HP
tWHA
t
HFP
Date Enable
t
VP
t
WV
Vsync
t
VBP
tWVA
t
VFP
Date Enable
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