LG Display LD550WUD-SCA1 Specification
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LD550WUD
Product Specification
SPECIFICATION
FOR
APPROVAL
)
(
●
Preliminary Specification
)
(
Final Specification
Title 55.0” WUXGA TFT LCD
BUYER General
MODEL
APPROVED BY
/
/
SIGNATURE
DATE
SUPPLIER LG.Display Co., Ltd.
*MODEL LD550WUD
SUFFIX SCA1 (RoHS Verified)
*When you obtain standard approval,
please use the above model name without suffix.
APPROVED BY
Y.S. Park /Senior Manager
REVIEWED BY
B.Y. Park / Manager
SIGNATURE
DATE
PREPARED BY
/
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 0.0
Ver. 0.0
J.H. Kim / Engineer
PD Product Development Dept.
LG Display Co., Ltd
0 / 43
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LD550WUD
Product Specification
CONTENTS
Number ITEM
COVER
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS
3-1 ELECTRICAL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATIONS
3-4 LVDS SIGNAL SPECIFICATIONS
3-5 COLOR DATA REFERENCE
3-6 POWER SEQUENCE
4 OPTICAL SPECIFICATIONS
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY
Page
-
1
2
3
4
5
5
7
10
11
14
15
17
21
24
7 INTERNATIONAL STANDARDS
7-1 SAFETY
7-2 EMC
7-3 ENVIRONMENT
8 PACKING
8-1 INFORMATION OF LCM LABEL
8-2 PACKING FORM
9 PRECAUTIONS
9-1 MOUNTING PRECAUTIONS
9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
HANDLING PRECAUTIONS FOR PROTECTION FILM9-6
9-7 APPROPRIATE CONDITION FOR PUBLIC DISPLAY
Ver. 0.0
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Revision No. Revision Date Page Description
0.0 Jan. 22. 2010 - Preliminary Specification (First Draft)
LD550WUD
Product Specification
RECORD OF REVISIONS
Ver. 0.0
2 / 43
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1. General Description
The LD550WUD is a Color Active Matrix Liquid Crystal Display with an integral Cold Cathode Fluorescent
Lamp(CCFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 54.64 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilion colors.
It is intended to support Public Display where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
LD550WUD
Product Specification
Mini-LVDS(RGB)
SDA
3PinX1CN(High)
3PinX1CN(High)
Source Driver Circuit
Gate Driver Circuit
S1 S1920
G1
TFT - LCD Panel
(1920 × RGB × 1080 pixels)
G1080
Back light Assembly
LVDS
2Port
+12.0V
LVDS
2Port
LVDS Select
Bit Select
OPC Enable
ExtVBR-B
VBR-B out
+24.0V, GND,
VBR-A, ExtVBR-B,Status
CN2
(41pin)
CN1
(51pin)
+24.0V, GND
LVDS 3,4
LVDS 1,2
Option
signal
I2C
EEPROM
SCL
Timing Controller
[LVDS Rx + OPC + ODC
DGA+SSIC+SDRAM
integrated]
Power Circuit
Block
Inverter(Master)
Inverter(Slave)
General Features
Active Screen Size 54.64 inches(1387.80mm) diagonal
Outline Dimension 1286.0(H) x 745.0 (V) x 60.0 mm(D) (Typ.)
Pixel Pitch 0.630 mm x 0.630 mm
Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Color Depth 8-bit, 16.7 M colors (※ 1.06B colors @ 10 bit (D) System Output )
Luminance, White 700 cd/m2 (Center 1point ,Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Power Consumption Total 248W (Typ.) (Logic=8.0(TBD)W, Backlight=240W)
Weight 19.5Kg (Typ.)
Display Mode Transmissive mode, Normally black
Hard coating (3H), Anti-reflection treatment of the front polarizer (Reflectance : < 2%)Surface Treatment
Possible Display Mode Landscape and Portrait
Ver. 0.0
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2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the
LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
LD550WUD
Product Specification
Parameter Symbol
Power Input Voltage
Inverter Control Voltage
Brightness Control Voltage EXTVBR-B
T-Con Option Selection Voltage VLOGIC
Operating Temperature TOP
Storage Temperature TST
Panel Front Temperature TSUR - TBD °C 3
Operating Ambient Humidity HOP
Storage Humidity HST 10 90 %RH
1. Ambient temperature condition (Ta = 25 ± 2 °C )
Note
2. Temperature and relative humidity range are shown in the figure below.
LCD Circuit VLCD
Inverter VBL -0.3 + 27.0 VDC
ON/OFF VOFF / VON
Brightness VBR
Value
Min Max
-0.3 +14.0
-0.3 +5.5
0.0 +5.0
-0.3 +4.0
-0.3 +4.0
0 +50
-20 +60
10 90
Unit Note
VDC
VDC
VDC
VDC
VDC
°C
°C
%RH
Wet bulb temperature should be Max 39°C, and no condensation of water.
3. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 65°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65℃. The range of operating temperature may degraded in case of
improper thermal management in final product design.
90%
1
2
2
60
60%
Ver. 0.0
Wet Bulb
Temperature [°C]
20
10
0
10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [°C]
30
40
50
40%
Humidity [(%)RH]
10%
Storage
Operation
4 / 43
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3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the CCFL
backlight and inverter circuit.
Table 2. ELECTRICAL CHARACTERISTICS
LD550WUD
Product Specification
Parameter Symbol
Min Typ Max
Circuit :
Power Input Voltage VLCD 10.8 12.0 13.2 VDC
Power Input Current ILCD
Power Consumption PLCD TBD TBD Watt 1
Rush current IRUSH - - 5.0 A 3
Note
1. The specified current and power consumption are under the V
- TBD TBD mA 1
- TBD TBD mA 2
Value
Unit Note
=12.0V, Ta=25 ± 2°C, fV=120Hz
LCD
condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
White : 1023 Gray
Black : 0 Gray
Mosaic Pattern(8 x 6)
Ver. 0.0
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Table 3. ELECTRICAL CHARACTERISTICS (Continue)
LD550WUD
Product Specification
Parameter Symbol
Inverter :
Power Supply Input Voltage VBL 22.8 24.0 25.2 VDC 1
Power Supply
Input Current
Power Supply Input Current (In-Rush) IRUSH - - 15 A
Power Consumption PBL -
Input Voltage for
Control System
Signals
Lamp:
After Aging IBL_A - 10
Before Aging IBL_B - 12
On/Off
Brightness Adjust EXTVBR-B 30 - 100 %
PWM Frequency for
NTSC & PAL
Pulse Duty
Level (PWM)
(Burst mode)
On VON 2.5 - 5.0 VDC
Off VOFF -0.3 0.0 0.8 VDC
PAL 100 Hz 5
NTSC 120 Hz 5
High Level 2.5 - 5.0 VDC
Low Level 0.0 - 0.8 VDC
Min Typ Max
Discharge Stabilization Time Ts
Life Time 50,000 60,000 Hrs 4
Values
240 264
Unit Note
11
13.2
3 min 3
A 1
A 2
VBL = 22.8V
EXTVBR-B = 100%
W 1
High: Lamp on
Low : Lamp off
On Duty
6
7
Note
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 120
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (EXTVBR-B : 100%), it is total power consumption.
2. Electrical characteristics are determined within 30 minutes at 25±2°C.
The specified currents are under the typical supply Input voltage 24V.
3. The brightness of the lamp after lighted for 5minutes is defined as 100%.
TS is the time required for the brightness of the center of the lamp to be not less than 95% at typical current.
The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.
4. Specified Values are for a single lamp which is aligned horizontally.
The life time is determined as the time which luminance of the lamp is 50% compared to that of initial value
at the typical lamp current (EXTVBR-B :100%), on condition of continuous operating at 25± 2°C
5. LGD recommend that the PWM freq. is synchronized with One times harmonic of Vsync signal of system.
6. The duration of rush current is about 10ms.
7. EXTVBR-B is based on input PWM duty of the inverter.
Ver. 0.0
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Product Specification
3-2. Interface Connections
This LCD module employs three kinds of interface connection, 51-pin, 41-pin and 4-pin connector are used
for the module electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector : FI-R51S-HF(manufactured by JAE) or KN25-51P-0.5SH(manufactured by Hirose)
(CN1) Refer to below and next Page table
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION
No Symbol Description No Symbol Description
Reverse ‘H’ = Enable , ‘L’ or NC = Disable
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC No Connection
NC No Connection
NC No Connection (Reserved for LGD)
NC No Connection (Reserved for LGD)
NC No Connection (Reserved for LGD)
LVDS Select
EXTVBR-B External VBR (From System)
VBR-B out OPC output (From LCM)
OPC Enable ‘H’ = Enable , ‘L’ or NC = Disable
GND
R1AN
R1AP
R1BN
R1BP
R1CN
R1CP
GND
R1CLKN
R1CLKP
GND
R1DN
R1DP
R1EN
R1EP
NC
‘H’ =JEIDA , ‘L’ or NC = VESA
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)
Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)
Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
FIRST LVDS Receiver Signal (E-)
FIRST LVDS Receiver Signal (E+)
No Connection
27
Bit Select
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
- - -
R2AN
R2AP
R2BN
R2BP
R2CN
R2CP
GND
R2CLKN
R2CLKP
GND
R2DN
R2DP
R2EN
R2EP
NC
NC
GND Ground
GND Ground
GND Ground
NC No connection
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
‘H’ or NC= 10bit(D) , ‘L’ = 8bit
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)
Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)
Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+)
No Connection
No Connection
LD550WUD
Note
1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. Specific pins(pin No. #2~#6) are used for internal data process of the LCD module.
These pins should be no connection.
5. Specific pins(pin No. # 8~#10) are used for OPC function of the LCD module.
If not used, these pins are no connection. (Please see the Appendix III-4 for more information.)
6. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
7. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
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-LCD Connector : FI-RE41S-HF (manufactured by JAE) or KN25-41P-0.5SH (manufactured by Hirose)
(CN2)
- Mating Connector : FI-RE41HL
Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No Symbol Description No Symbol Description
1
2
3
4 NC
5
6
7
8
9
10
11
12
13 RB3P
14
15
16
17
18 RCLK3P
19
20
21
NC
NC
NC
NC
NC
NC
NC
GND
RA3N
RA3P
RB3N
RC3N
RC3P
GND
RCLK3N
GND
RD3N
RD3P
No connection(Reserved) 22
No connection 23
No connection 24 GND Ground
No connection
No connection
No connection 27
No connection 28
No connection 29 RB4P
Ground
THIRD LVDS Receiver Signal (A-)
THIRD LVDS Receiver Signal (A+)
THIRD LVDS Receiver Signal (B-)
THIRD LVDS Receiver Signal (B+)
THIRD LVDS Receiver Signal (C-)
THIRD LVDS Receiver Signal (C+)
Ground
THIRD LVDS Receiver Clock Signal(-)
THIRD LVDS Receiver Clock Signal(+)
Ground
THIRD LVDS Receiver Signal (D-)
THIRD LVDS Receiver Signal (D+)
Product Specification
25 GND Ground
26
30
31
32
33
34 RCLK4P
35
36
37
38
39
40 GND Ground
41 GND Ground
RCLK4N
-
RE3N
RE3P
RA4N
RA4P
RB4N
RC4N
RC4P
GND
GND
RD4N
RD4P
RE4N
RE4P
LD550WUD
THIRD LVDS Receiver Signal (E-)
THIRD LVDS Receiver Signal (E+)
FORTH LVDS Receiver Signal (A-)
FORTH LVDS Receiver Signal (A+)
FORTH LVDS Receiver Signal (B-)
FORTH LVDS Receiver Signal (B+)
FORTH LVDS Receiver Signal (C-)
FORTH LVDS Receiver Signal (C+)
Ground
FORTH LVDS Receiver Clock Signal(-)
FORTH LVDS Receiver Clock Signal(+)
Ground
FORTH LVDS Receiver Signal (D-)
FORTH LVDS Receiver Signal (D+)
FORTH LVDS Receiver Signal (E-)
FORTH LVDS Receiver Signal (E+)
Note : 1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. LVDS pin (pin No. #22,23,38,39) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
- Part/No. : FI-RE41S-HF(JAE)
- Mating connector : FI-RE41HL
(Manufactured by JAE) or compatible
1
51
1
41
CN1 CN2
[Figure 4-2]
Ver. 0.0
Rear view of LCM
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3-2-2. Backlight Module
LD550WUD
Product Specification
[ Master ]
-Inverter Connector : 20022WR-14B1(Yeonho)
or Equivalent
- Mating Connector : 20022HS-14 or Equivalent
[ Slave ]
-Inverter Connector : 20022WR-12B1(Yeonho)
or Equivalent
-Mating Connector : 20022HS-12 or Equivalent
Table 5. INVERTER CONNECTOR PIN CONFIGULATION
Pin No Symbol Description Master Slave Note
1
2
3
4
5
6
7
8
9
10
11
VBL Power Supply +24.0V VBL VBL
VBL Power Supply +24.0V VBL VBL
VBL Power Supply +24.0V VBL VBL
VBL Power Supply +24.0V VBL VBL
VBL Power Supply +24.0V VBL VBL
GND Backlight Ground GND GND
GND Backlight Ground GND GND
GND Backlight Ground GND GND
GND Backlight Ground GND GND
GND Backlight Ground GND GND
NC No Connection NC Don’t care 2
1
12
13
14
Note
1. GND should be connected to the LCD module’s metal frame.
2. Normal : Low (under 0.7V) / Abnormal : High (upper 3.0V)
Please see Appendix IV-1 for more information.
3. The impedance of pin #12 is over 50[KΩ]
◆◆◆◆ Rear view of LCM
◆◆◆◆ Rear view of LCM
Ver. 0.0
ON/OFF
V
NC No Connection NC -
Status Lamp Status Status - 3
14
14
1
1
Backlight ON/OFF control V
PCB
PCB
…
…
…
<Master>
<Master>
…
ON/OFF
…
…
1
1
12
12
Don’t care
PCB
PCB
<Slave>
<Slave>
…
…
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3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6-1. TIMING TABLE for NTSC (DE Only Mode)
ITEM Symbol Min Typ Max Unit Note
LD550WUD
Product Specification
Horizontal
Vertical
Frequency
Display
Period
Blank tHB 40 70 200 tCLK 1
Total tHP 520 550 680 tCLK
Display
Period
Blank tVB 16 45 86 Lines 1
Total tVP 1096 1125 1166 Lines
DCLK fCLK 66.97 74.25 78.00 MHz
Horizontal fH 121.8 135 140 KHz 2
Vertical fV 108 120 122 Hz 2
tHV 480 480 480 tCLK 1920 / 4
tVV 1080 1080 1080 Lines
Table 6-2 TIMING TABLE for DVB/PAL (DE Only Mode)
ITEM Symbol Min Typ Max Unit Note
Horizontal
Display
Period
Blank tHB 40 70 200 tCLK 1
tHV 480 480 480 tCLK 1920 / 4
Total tHP 520 550 680 tCLK
Vertical
Frequency
Display
Period
Blank tVB 228 270 300 Lines 1
Total tVP 1308 1350 1380 Lines
DCLK fCLK 66.97 74.25 78.00 MHz
Horizontal fH 121.8 135 140 KHz 2
Vertical fV 95 100 104 Hz 2
tVV 1080 1080 1080 Lines
Note 1. The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
If you use spread spectrum for EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency.
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3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
LD550WUD
Product Specification
DCLK
First data
Second data
Third data
Forth data
DE(Data Enable)
tCLK
0.5 VDD
Invalid data
Invalid data
Invalid data
Invalid data
DE, Data
Valid data
Pixel 0
Valid data
Pixel 1
Valid data
Pixel 2
Valid data
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
0.7VDD
0.3VDD
Invalid data
Invalid data
Invalid data
Invalid data
DE(Data Enable)
Ver. 0.0
* tHB = tHFP + tWH +tHBP
* tVB = tVFP + tWV +tVBP
1 1080
tVV
tVP
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3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS -
LVDS +
LD550WUD
Product Specification
# VCM= {(LVDS +) + ( LVDS - )}/ 2
0V
V
CM
V
IN _ MAXVIN _MIN
Description Symbol Min Max Unit Note
LVDS Common mode Voltage V
LVDS Input Voltage Range V
CM
IN
1.0 1.5 V -
0.7 1.8 V -
Change in common mode Voltage ΔVCM 250 mV -
2) AC Specification
T
clk
LVDS Clock
A
LVDS Data
(F
= 1 /T
)
clk
A
LVDS 1’st Clock
LVDS 2nd/ 3rd/ 4thClock
tSKEW
tSKEW
t
SKEW_mintSKEW_max
clk
T
clk
80%
20%
t
RF
Description Symbol Min Max Unit Note
LVDS Differential Voltage
High Threshold
Low Threshold
LVDS Clock to Data Skew Margin t
LVDS Clock/DATA Rising/Falling time t
Effective time of LVDS t
LVDS Clock to Clock Skew Margin (Even to Odd) t
1. All Input levels of LVDS signals are based on the EIA 644 Standard.
Note
2. If tRFisn’t enough, t
should be meet the range.
eff
V
TH
V
TL
SKEW
RF
eff
SKEW_EO
3. LVDS Differential Voltage is defined within t
Ver. 0.0
100 300 mV
-300 -100 mV
|(0.25*T
260 (0.3*T
)/7| ps -
clk
)/7 ps 2
clk
±360 ps -
1/7* T
clk
eff
T
clk
3
-
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LD550WUD
Product Specification
360ps
V+
data
Vcm
Vdata
V+
clk
Vcm
0.5tui
tui
VTH
VTL
360ps
teff
tui : Unit Interval
Vclk
Ver. 0.0
13 / 43
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