LG Display LD470WUN-SAA1 Specification

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LD470WUN

Product Specification

SPECIFICATION

FOR

APPROVAL

)

(

Preliminary Specification

●

)

(

Final Specification

BUYER

MODEL

APPROVED BY

/

/

SIGNATURE

DATE

47.0” WUXGA TFT LCDTitle

LG Display Co., Ltd.SUPPLIER

LD470WUN*MODEL

SAA1 (RoHS Verified)SUFFIX

*When you obtain standard approval,

please use the above model name without suffix

APPROVED BY

Y. S Park / S. Manager

REVIEWED BY

B. Y Park / Manager

SIGNATURE

DATE

PREPARED BY

/

Please return 1 copy for your confirmation with

your signature and comments.

Ver. 0.0

J. H Kim / Engineer

PD Products Development Dept.

LG Display Co., Ltd

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LD470WUN

Product Specification

CONTENTS

CONTENTS

RECORD OF REVISIONS

GENERAL DESCRIPTION1

ABSOLUTE MAXIMUM RATINGS2

ELECTRICAL SPECIFICATIONS3

ELECTRICAL CHARACTERISTICS3-1

INTERFACE CONNECTIONS3-2

SIGNAL TIMING SPECIFICATIONS3-3

SIGNAL TIMING WAVEFORMS3-4

COLOR DATA REFERENCE3-5

POWER SEQUENCE3-6

OPTICAL SPECIFICATIONS4

MECHANICAL CHARACTERISTICS5

ITEMNumber

Page

1COVER

2

3

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11

12

13

15

19

Ver. 0.0

RELIABILITY6

INTERNATIONAL STANDARDS7

SAFETY7-1

EMC7-2

PACKING8

DESIGNATION OF LOT MARK8-1

PACKING FORM8-2

PRECAUTIONS9

MOUNTING PRECAUTIONS9-1

OPERATING PRECAUTIONS9-2

ELECTROSTATIC DISCHARGE CONTROL9-3

PRECAUTIONS FOR STRONG LIGHT EXPOSURE9-4

STORAGE9-5

HANDLING PRECAUTIONS FOR PROTECTION FILM9-6

APPROPRIATE CONDITION FOR PUBLIC DISPLAY 9-7

22

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2 / 27

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LD470WUN

Product Specification

RECORD OF REVISIONS

DescriptionPageRevision DateRevision No.

First specification released-June, 02, 20080.0

Ver. 0.0

3 / 27

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1. General Description

The LD470WUN is a Color Active Matrix Liquid Crystal Display with an integral Cold Cathode Fluorescent
Lamp(CCFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 46.96 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.07 Billion colors.
It has been designed to apply the 10-bit 2-port LVDS interface.
It is intended to support Public Display where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.

LD470WUN

Product Specification

+12.0V

LVDS

2Port

DCR
Enable

VBR_OUT

Bit Selection

LVDS Selection

+24.0V, GND, VBR-A,VBR-B

CN1

(51pin)

Status

+24.0V, GND

General Features

EEPROM

SCL

Timing Controller

[LVDS Rx + ODC

integrated]

Power Circuit

Block

Inverter(Master)

Inverter(Slave)

46.96 inch (1192.87mm) diagonalActive Screen Size

1096.0(H) x 640.0 (V) x 51 mm(D) (Typ.)Outline Dimension

0.5415 mm x 0.5415 mmPixel Pitch

1920 horiz. by 1080 vert. Pixels, RGB stripe arrangementPixel Format

SDA

Mini-LVDS(RGB)

G1

Gate Driver Circuit

G1080

3PinX1CN(High)

3PinX1CN(High)

Source Driver Circuit

S1 S1920

TFT - LCD Panel

(1920 × RGB × 1080 pixels)

Back light Assembly

10Bit (D), 1.07 Billion colorsColor Depth

500 cd/m2 (Center 1point ,Typ.)Luminance, White

Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))Viewing Angle (CR>10)

Total 220.08 W (Typ.) [Logic=7.08W, Backlight=213W (V

BR-A

14.5 Kg (Typ.) Weight

Transmissive mode, Normally blackDisplay Mode

Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 13%)Surface Treatment

Landscape and Portrait EnabledPossible Display Type

Ver. 0.0

=1.65V)]Power Consumption

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2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or damage to the
LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

LD470WUN

Product Specification

Value

Parameter Remark

Symbol

Unit

MaxMin

Power Input

Voltage

LCM

VDC+27.0-0.3VBLBacklight inverter

VDC+5. 5-0.3VON/OFFON/OFF Control Voltage

VDC+5.00VBRBrightness Control Voltage

+500TOPOperating Temperature

+60-20TSTStorage Temperature

°C

°C

%RH9010HOPOperating Ambient Humidity

%RH9010HSTStorage Humidity

Notes : 1. Temperature and relative humidity range are shown in the figure below.

Wet bulb temperature should be 39 °C Max. and no condensation of water.

90%

60

60%

at 25 ± 2 °CVDC+14.0-0.3VLCD

Note 1,2

Ver. 0.0

Wet Bulb
Temperature [°C]

20

10

0

10 20 30 40 50 60 70 800-20

Dry Bulb Temperature [°C]

50

40

40%

30

Humidity [(%)RH]

10%

Storage

Operation

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3. Electrical Specifications

3-1. Electrical Characteristics

It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the CCFL
backlight and inverter circuit.

Table 2. ELECTRICAL CHARACTERISTICS

LD470WUN

Product Specification

Parameter Symbol

Value

Circuit :

Power Input Voltage

Power Input Current

Power Consumption

Rush current

LCD

I

LCD

LCD

RUSH

Notes: 1. The specified current and power consumption are under the V

condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.

2. The current is specified at maximum current pattern.

3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).

White : 1023Gray
Black : 0Gray

MaxTypMin

12.612.011.4V

=12.0V, 25 ± 2°C, fV=60Hz

LCD

V

DC

NoteUnit

1mA770590410

2mA1080830580

1Watt9.247.08-P

3A5--I

Mosaic Pattern(8 x 6)

Ver. 0.0

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Table 3. ELECTRICAL CHARACTERISTICS (Continue)

Parameter Symbol

Inverter :

LD470WUN

Product Specification

Values

NotesUnit

MaxTypMin

Power Supply
Input Current

Power Consumption

Input Voltage for

Control System

On/Off

Signals

Brightness Adjust

Lamp:

Discharge Stabilization Time

IBL_AAfter Aging

IBL_BBefore Aging

BR-ABrightness Adjust

On Vdc5.0-2.5V on

Off

Ts

Vdc25.224.022.8VBLPower Supply Input Voltage

1

1Vp-p0.5--Power Supply Input Voltage Ripple

8.9-

10.0-

11.0-

12.0-

10.3

11.0

12.0

13.0

VBR-A = 1.65V … 1A

VBR-A = 3.3V … 1A

V

BR-A = 1.65V … 2A

V

BR-A = 3.3V … 2A

VBL = 22.8V
VBR-B = 3.3V

A14.0--IrushPower Supply Input Current (In-Rush)

VBR-A = 1.65V

-PBL

250213

VBR-A = 1.65V … 1W

Vdc3.31.650.0V

Vdc0.80.0-0.3V off

V3.3-0VBR-B

3min3

Hrs50,000Life Time

4

Notes :

1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 30
minutes at 25± 2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (VBR-A : 1.65V & VBR-B :3.3V), it is total power consumption.

The ripple voltage of the power supply input voltage is under 0.5 Vp-p. LPL recommend Input Voltage is

24.0V ± 5%.

2. Electrical characteristics are determined within 30 minutes at 25± 2°C.
The specified currents are under the typical supply Input voltage 24V.

3. The brightness of the lamp after lighted for 5minutes is defined as 100%.
TS is the time required for the brightness of the center of the lamp to be not less than 95% at typical current.

The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.

4. Specified Values are for a single lamp which is aligned horizontally.
The life time is determined as the time which luminance of the lamp is 50% compared to that of initial value
at the typical lamp current (VBR-A : 1.65V & VBR-B :3.3V), on condition of continuous operating at 25± 2°C

5. The duration of rush current is about 10ms.

Ver. 0.0

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3-2. Interface Connections

This LCD module employs two kinds of interface connection, a 51-pin connector is used for the module
electronics and Master 14-pin and Slave 12-pin connectors are used for the integral backlight system.

3-2-1. LCD Module

- LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE) or Equivalent

- Mating Connector : FI-RE51HL(manufactured by JAE)

Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION

LD470WUN

Product Specification

10

11

12

13

14

15

16

17

18

19

20
21
22

23

24

25

26

DescriptionSymbolNo

1

2

3

4

5

6
7

8

9

GND

GND

RA1N

RA1P

RB1N
RB1P

RC1N

RC1P

GND

RCLK1N
RCLK1P

GND

RD1N

RD1P

RE1N

RE1P

GND

Ground

No ConnectionNC

No ConnectionNC

No ConnectionNC

No ConnectionNC

No ConnectionNC

‘H’ =JEIDA , ‘L’ = VESA LVDS Select

External VBRVBR_EXT

VBR outputVBR_OUT

‘H’ = Enable , ‘L’ = Disable DCR_Enable

Ground

FIRST CHANNEL A-

FIRST CHANNEL A+

FIRST CHANNEL B-

FIRST CHANNEL B+

FIRST CHANNEL C-

FIRST CHANNEL C+
Ground

FIRST CLOCK CHANNEL Clk-

FIRST CLOCK CHANNEL Clk+
Ground

FIRST CHANNEL D-

FIRST CHANNEL D+

FIRST CHANNEL E-

FIRST CHANNEL E+
Ground

No

27

28

29

30

31

32
33

34

35

36

37

38

39

40

41

42

43

44

45

46
47
48

49

50

51

-

Symbol

Bit Select

RA2N

RA2P

RB2N

RB2P

RC2N
RC2P

GND

RCLK2N

RCLK2P

GND

RD2N

RD2P

RE2N

RE2P

GND

GND

GND

GND

GND

NC
VLCD

VLCD

VLCD

VLCD

-

‘H’ = 10Bit (D)

SECOND CHANNEL A-

SECOND CHANNEL A+

SECOND CHANNEL B-

SECOND CHANNEL B+

SECOND CHANNEL C­SECOND CHANNEL C+
Ground

SECOND CLOCK CHANNEL Clk-

SECOND CLOCK CHANNEL Clk+
Ground

SECOND CHANNEL D-

SECOND CHANNEL D+

SECOND CHANNEL E-

SECOND CHANNEL E+
Ground

Ground

Ground

Ground

Ground
No connection
Power Supply +12.0V

Power Supply +12.0V

Power Supply +12.0V

Power Supply +12.0V

Description

-

Notes :

1. The pin no 44 is LCD Test option. “AGP” (Auto Generation LCM operates Pattern) or “NSB” (No Signal
Black) is case that LVDS signals are out of frequency or abnormal condition in spite of 12 volt power
supply. LPL recommends “NSB”. ( AGP : “VCC” or “OPEN” / NSB : “GND” )

2. All GND(ground) pins should be connected together to the LCD module’s metal frame.

3. All VLCD (power input) pins should be connected together.

4. All Input levels of LVDS signals are based on the EIA 664 Standard.

5. Specific pins(pin No. #1~#10) are used for internal data process of the LCD module.

If not used, these pins are no connection.

6. If DCR function should be enable(‘H’), 10th pin must be connected to serial resistor which value is under
1k ohm.

Ver. 0.0

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3-2-2. Backlight Inverter

Master

-Inverter Connector : S14B-PH-SMC (JST)
or Equivalent

- Mating Connector : PHR-14 or Equivalent

Table 5. INVERTER CONNECTOR PIN CONFIGURATION

Product Specification

Slave

-Inverter Connector : S12B-PH-SMC (JST)

-Mating Connector : PHR-12 or Equivalent

Master

or Equivalent

Slave

LD470WUN

NoteDescriptionSymbolPin No

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VBR-A

ON/OFF

BR-B

V

Status

Power Supply +24.0VVBL

Power Supply +24.0VVBL

Power Supply +24.0VVBL

Power Supply +24.0VVBL

Power Supply +24.0VVBL

Backlight GroundGND

Backlight GroundGND

Backlight GroundGND

Backlight GroundGND

Backlight GroundGND

Analog dimming voltage
DC 0.0V ~ 3.3V (Typ : 1.65V)

Burst dimming voltage
DC 0.0V ~ 3.3V

Normal : Upper 3.0V

Abnormal : Under 0.7V

VBL

VBL

VBL

VBL

VBL

GND

GND

GND

GND

GND

VBR-B

Notes : 1. GND should be connected to the LCD module’s metal frame.

2. If Pin #11 is open, VBR-A = 1.65V. When apply over 1.65V( ~ 3.3V) continuously,
its luminance is increasing however lamp’s life time is decreasing.
It could be usable for boost up luminance when using DCR (=Dynamic contrast ratio) function only.

3. Minimum Brightness : VBR-B =0V Maximum Brightness : VBR-B = 3.3V

4. Even though Pin #14 is open, there is no effect on inverter operating, The output terminal of inverter.

5. Each impedance of pin #11,12 and 13 is 140[KΩ], 41[KΩ],125[KΩ]

Don’t careOn/Off0.0V ~ 5.0VV

VBL

VBL

VBL

VBL

V

BL

GND

GND

GND

GND

GND

-

1

2, 3Don’t careVBR-A

3

4-Status

◆◆◆◆

Rear view of LCM

14

…

PCB

…

1

PCB

…

…

1

<Master>

Ver. 0.0

12

<Slave>

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3-3. Signal Timing Specifications

Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timing
should be satisfied with the following specification for normal operation.

Table 6. TIMING TABLE for NTSC (DE Only Mode)

LD470WUN

Product Specification

Horizontal

Vertical

Frequency

Display Period

Blank

Total

DCLK

Horizontal

Vertical

Symbol

tHV

tHB

tHP

Symbol

fCLK

fH

fV

tclk-960-

tclk32014072

Lines-1080-tVVDisplay Period

Lines864512tVBBlank

Lines116611251090tVPTotal

KHz70.967.564.1

Hz636057

NoteUnitMaxTypMinITEM

2200/2tclk128011001060

NoteUnitMaxTypMinITEM

148.5/2MHz7874.2570.5

Table 7 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timing
should be satisfied with the following specification for normal operation.

Table 7. TIMING TABLE for PAL (DE Only Mode)

Symbol

NoteUnitMaxTypMinITEM

Horizontal

Vertical

Frequency

Display Period

Blank

Total

DCLK

Horizontal

Vertical

tHV

tHB

tHP

Symbol

fCLK

fH

fV

tclk-960-

tclk32014072

2200/2tclk128011001060

Lines-1080-tVVDisplay Period

Lines300270228tVBBlank

Lines138013501308tVPTotal

NoteUnitMaxTypMinITEM

148.5/2MHz7874.2570.5

KHz70.967.564.1

Hz535047

Note : The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).

The performance of the electro-optical characteristics may be influenced by variance of the vertical refresh rate.

Ver. 0.0

10 / 27