LG TCC-9310 Service manual
WIRING DIAGRAM(DECK MECHANISM)
Shinwa DECK: CDS-802 STD
DECK P/N: 6720AN0001A
2-15 2-16
BLOCK DIAGRAM
TU101 Q101,CF101,102 IC101 IC102 IC103
VT FM Vcc FM Vcc FM Vcc FM Vcc FM Vcc
Vdd Q807
TU201 FM ON *OPTI
O
FM OSC
AM Vcc VT Q805
Q109,110 IC104
AM OSC PWR ON AM ON Q803,Q804
IC501 IC601
MUTE IC801
IC503 *OPTION
LEVEL DET
ACC DET
IC502
Motor ON
*OPTION
FM F/ E ND
IF F ilter &
Amp
IF IC
[LA1140]
NC I C
[KIA6010]
MPX I C
[LA3430M]
AM T UNER
LPF1
PLL I C
[KIC9256P]
Q112
Q203
9.4V Reg
Q802
PWR 1 4V
Q808,Q809
4.7V ZD102
LogicDeck
CDS-802
EQ IC
[KIA2025]
Sub D rive
[FAN8082]
M/Drive
Q502,Q503
AMS I C
[LA2000]
E/Vol IC
[PT2312L]
POWER I C
[TDA8571]
AF Am p
[Q601,Q602]
CDC
u-COM
IC401
[uPD780022]
B/UP
ACC
Q806
SPK
LINE O UTD601
5V Reg
LED Fl ash
RESET
DIODE M ATRIX
LCD DRI VER I C
IC901
[PT6523]
KEY I N1/2
LCD
Back Li ght
[LD901~925]
TAPE BLOCK
2-18 2-17
SCHEMATIC DIAGRAM
2-19 2-20
SECTION 3. CABINET MAIN CHASSIS & MECHANISM
281
A00-1
441
330
286
A47
260
301
A40
455
302
A42
A44
A46
A43
457
A41
320
441
447
441
A00-2
A00
■ EXPLODED VIEW
CAUTION
Exposed blade will cause
severe injury
3-1 3-2
- 2-7 -
INTERNAL BLOCK DIAGRAM of ICs
■ IC101 LA1140
■ IC102 KIA6010SN
■ IC103 LA3430M
- 2-8 -
NOTE: Mark terminals are not existence in KIC9256P, KIC9256F
Terminal name of KIC9256P, KIC9256F is shown in parentheses.
Others are common terminals.
■ IC104 KIC9256P
POWER ON
RESET
TRI-STATE
BUFFER
TRI-STATE
BUFFER
RESET
PHASE
COMPARATOR
OSC
CIRCUIT
24bit REGISTER
ADDRESS
DECODER
20bit BINARY COUNTER
UNIVERSAL COUNTER CONTROL
OUTPUT PORT
24bit REGISTER
4
FM
1mS
OSC
MODE LF
4
UNLOCK
1/0 PORT
8
TEST
24 22
5
5
10
12 bit PROGRAMMABLE COUNTER
MAX
12
15
4
OT4
DO1
DO2
(DO2/OT-4)
1/0-5/CLK
1/0-6
1/0-9 IF
IN2
(1/0-6 IF )
IN2
1/0-8 IF
IN1
1/0-7 SC
IN
(1/0-5 IF )
IN1
4
15
129
16
13
14
8
OT-4
OT-2
OT-3
OT-4
OT-1
XT 1mS
GATE
AMP
AMP
7
6
3
4
5
1
2
10
11
1/2
FM
FM
PSC
V
DD
GND
AMP
HF
FM
IN
AM
IN
XT
XT
DATA
CLOCK
PERIOD
S
L
2 MODULUS
PRESCALER
4 bit SWALLOW
COUNTER
REFERENCE COUNTER
24bit SHIFT REGISTER
■ IC201 DBL 1019
LOCAL
OSC
BUFFER
LOCAL
OSC
RF
AGC
ATTENUATOR
DRIVER
MIX
IF
AMP
IF
DETECTOR
RF
AMP2
RF
AMP2
IF
AGC
SIGNAL
METER
ALC
RF DETECTOR
20 19 18 17 16 15 14 13 12 11
12345678910
Local OSC
Butter Out
RFAGC
Out
RFAmp2InRF
AGC
GND MIX in &
RF AMP1 In
MIX
Out
IF AmpInIF Amp
Out
ANT Damping
Driver
Local
OSC2
Local
OSC1
Signal
Meter Out
Signal
Meter In
Detector
Out
Detector
InGND
V
CC
V
CC
IF
AGC
- 2-9 -
■ IC401 uPD780022
1) Overall block diagram
30
17
29
28
27
26
25
24
23
22
21
20
19
18
12 1413
1 32 4 5 6 8 9 107 11
15 16
37 3536
48 4647 45 44 43 41 40 3942 38
34 33
32
31
51
64
52
53
54
55
56
57
58
59
60
61
62
63
49
50
N.C
N.C
UNLOAD
LOAD
REEL PULSE
F/R SW
MAIN MTR ON
GND
VDD
AMS IN
TAPE IN
IF CNT Req
CDC D-OU T
STAND- BY SW
MODE SW
ENVOL- A
KEY IN2
LEVEL METER
KEY IN1
EJECT KEY IN
SD IN
STEREO IN
GND
VDD
PLL PERI
EV CLOCK
EV DATA
PLL CLK
PLL DATA
CDC ON
N.C
ENVOL- B
AVREF
AVDD
RESET
NC
NC
IC(VPP)
X2
X1
GND
N.C
N.C
CDC BUS
N.C
LCD DATA
LCD CE
N.C
LCD RESET
LCD CLK
BEEP OUT
DIODE OUTO
DIODE OUT1
DIODE OUT2
DIODE IN0
DIODE IN1
DIODE IN2
N.C
N.C
N.C
ACC IN
LED FLASHING
MUTE ON
POWER ON
uPD780022
- 2-10 -
2) Pin function
1 P50/A8 POWER ON O Power Supply Control H
2P51/A9 N.C - 3P52/A10 N.C - 4P53/A11 UNLOAD O SUB MOTOR UNLOAD Output (-) H
5P54/A12 LOAD O SUB MOTOR LOAD Output (+) H
LOAD UNLOAD STOP OFF
UNLOAD L H H L
LOAD H L H L
6P55/A13 REEL PULSE I TAPE REEL PULSE INPUT
7 P56/A14 HEAD F/R SW O TAPE HEAD DIRECTION SELLECTION
8 P57/A15 MAIN MOTOR O TAPE MAIN MOTOR Power Control H
9 VSS0 GND 10 VDD0 VDD 11 P30 AMS IN I TAPE! MUSIC LEVEL Perception H
12 P31 TAPE IN SW I TAPE INSERT PACK Perception H
13 P32 IF CNT Req O IF COUNT REQ. H
14 P33 CDC DATA OUT O CD CHANGER DATA Out 15 P34/SI31 STAND-BY SW I TAPE STAND-BY STATE Perception H
16 P35/SO31 MODE SW I TAPE PLAY MODE STATE Perception
17 P36/SCK31 N.C O 18 P20/SI30 CDC ON O CD CHANGER Power Control H
19 P21/SO30 PLL DATA O PLL IC(KIC9256P)" Serial Data Output 20 P22/SCK30 PLL CLK O PLL IC(KIC9256P) CLOCK Output 21 P23/RXD0 EV DATA O I.C(PT2313L) Serial Data Output 22 P24/TXD0 EV CLOCK O I.C(PT2313L) CLOCK Output 23 P25/ASCK0 PLL PERI O PLL I.C(KIC9256P) CHIP ENABLE
PLL PREI
H
L
24 VDD1 VDD
25 AVSS O GND
26 P17/ANI7 STEREO IN I Stereo Perception L
27 P16/ANI6 SD IN I Radio Mode: Perception of Receive Sensitivity
*TUNER BAND : SEEK STOP LEVEL
FM
MW(LW)
28 P15/ANI5 EJECT KEY I TAPE EJECT KEY INPUT Perception
29 P14/ANI4 KEY IN1 I KEY A/D VALUE INPUT
30 P13/ANI3 LEVEL R/L I AUDIO LEVEL INPUT
31 P12/ANI2 KEY IN2 - KEY A/D VALUE INPUT
32 P11/ANI1 ENVOL-A I ENCODER VOLUME Input
33 P10/ANI0 ENVOL-B I ENCODER VOLUME Input
34 AVREF A/D Convertor Reference Voltage
35 AVDD GND
36 RESET SYSTEM RESET Signal Input L
37 XT2 Sub Clock Connection
38 XT1 Sub Clock Connection
39 IC(VPP) GND
40 X2 X2 - Crystal Connection
41 X1 X1 - Ceramic Oscillator Connection
42 VSS1 - GND
43 P00/INTP0 N.C 44 P01/INTP1 N.C 45 P02/INTP2 CDC BUS I CD CHANGER DATA BUS INPUT
46 P03/INTP3/ADTRG N.C 47 P70/TI00/TO0 LCD DATA O FRT LCD DRIVER DATA OUTPUT
48 P71/TI01 LCD CE O FRT LCD DRIVER CHIP ENABLE OUTPUT
49 P72/TI50/TO50 N.C 50 P73/TI51/TO51 LCD RESET O FRT LCD DRIVER RESET OUTPUT
51 P74/PCL LCD CLK O FRT LCD DRIVER CLOCK OUTPUT
52 P75/BUZ BEEP OUT O BEEP(2KHZ) Output
53 P64/RD DIODE OUT0 I/O DIODE OPTION MATRIX DATA INPUT0
54 P65//WR DIODE OUT1 I/O DIODE OPTION MATRIX DATA INPUT1
55 P66/WAIT DIODE OUT2 I/O DIODE OPTION MATRIX DATA INPUT2
56 P67/ASTB DIODE IN0 I/O DIODE OPTION MATRIX DATA OUTPUT0
57 P40/AD0 DIODE IN1 I/O DIODE OPTION MATRIX DATA OUTPUT1
58 P41/AD1 DIODE IN2 I/O DIODE OPTION MATRIX DATA INPUT2
59 P42/AD2 N.C I
60 P43/AD3 N.C I
61 P44/AD4 N.C O
62 P45/AD5 ACC IN O ACC ON/OFF Perception L
63 P46/AD6 LEDOFRT LED FLASH H
64 P47/AD07 MUTE ON O H
1.5 VOLT (HIGH)
1.2 VOLT(LOW)
State
DATA Transmission
CHIP Address Transmission
SDIN(Volt)
FORWARD H
REVERSE L
DESCRIPTION ACTIVE
DIRECTION HEAD F/R SW
No PORT FUNCTION I/O
- 2-11 -
■ IC501 KIA2025
4
1
■ IC503 FAN8082
1GND
O1
V
CTL
V
O2
V
CC
PV
CC
SV
TSD
IN2
V
IN1
V
8
2 7
3 6
4 5
PRE DRIVER
LOGIC SWITCH
BIAS
DRIVER OUT
■ IC502 LA2000
- 2-12 -
■ IC601 PT2313L
RB
RB
TREB_RBIN_RBOUT_RLOUDRINROUTREFAGNDVDD
RIN1
RIN1
RIN2
RIN2
RIN3
RIN3
LIN3
LIN3
Input
Selector
& Gain
Control
LIN2
LIN2
LIN1
LOUT LIN LOUD_L BOUT_L BIN_L TREB_L
LFOUT
Mute
Mute
Mute
Mute
Speaker
ATT
Speaker
ATT
Speaker
ATT
Speaker
ATT
LROUT
CLK
DATA
DGND
RFOUT
RROUT
LIN1
2
11
10
9
13
14
15
17 16 12 19
18
4
25
23
28
27
26
24
22
31 7 6 8 21
20
5
Supply
Bass
Serial Bus Decoder & Latches
Bass
Treble
Treble
Voume
&
Loudness
Voume &
Loudness
- 2-13 -
■ IC801 TDA8571J
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
PGND1 PGND2 PGND3 PGND4
MGG153
OUT4
-
OUT4+
OUT3+
DIAGNOSTIC
OUT2+
V
OUT1+
OUT3
-
OUT2
-
OUT1
-
21
20
22
19
17
9
5
7
4
2
23 16
10
11
12
13
14
30 K•
30 K•
30 K•
30 K•
IN1
MODE
IN2
SGND
IN3
IN4
8 1 15
186
3
ref
V
P1
V
P2
V
P3
V
P4
V
ref
V
DIAG
■ IC901 PT6523
V
SS
V2
LCD
V1
LCD
V
V
LCD
OSC
Common
driver
Segment driver & latch
Shift register
Clock
generator
Address
detector
COM3
DI
CL
CE
COM2
COM1
S35
ZZ
ZZ ZZ ZZ
S34
S9
S8/P8
S2/P2
S1/P1
INH
DD
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