SPECIFICATION
()Preliminary Specification
(
) Final Specification
●
Title 17.3” HD+ TFT LCD
LP173WD1
Liquid Crystal Display
Product Specification
FOR
APPROVAL
BUYER Acer
MODEL
www.jxlcd.com
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APPROVED BY
/
/
/
SIGNATURE
SUPPLIER LG Display Co., Ltd.
*MODEL LP173WD1
Suffix TLA1
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY SIGNATURE
K. J. KWON / S.Manager
REVIEWED BY
G. J. Han / Manager
PREPARED BY
C. Y. Kim / Engineer
S. W. Kim / Engineer
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 1.0 2. Feb, 2009
Product Engineering Dept.
LG Display Co., Ltd
1/ 32
Product Specification
Contents
LP173WD1
Liquid Crystal Display
No ITEM
COVER
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS
3-1 ELECTRICAL CHARACTREISTICS
3-2 INTERFACE CONNECTIONS
3-3 LVDS SIGNAL TIMING SPECIFICATIONS
3-4 SIGNAL TIMING SPECIFICATIONS
3-5 SIGNAL TIMING WAVEFORMS
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3-6 COLOR INPUT DATA REFERNECE
3-7 POWER SEQUENCE
4 OPTICAL SFECIFICATIONS
Page
1
2
3
4
5
6
8
10
10
11
12
12
5 MECHANICAL CHARACTERISTICS
6 RELIABLITY
7 INTERNATIONAL STANDARDS
7-1 SAFETY
7-2 EMC
8 PACKING
8-1 DESIGNATION OF LOT MARK
8-2 PACKING FORM
9 PRECAUTIONS
A APPENDIX A. Enhanced Extended Display Identification Data
Ver. 1.0 2. Feb, 2009
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Product Specification
RECORD OF REVISIONS
LP173WD1
Liquid Crystal Display
Revision No Revision Date Page Description
0.0 Oct. 7, 2008 - First Draft 0.0
0.1 Oct.29.2008 6 Revise LED life time 10,000 Æ 12,000hr 0.0
7 Use UJU connector
- Delete LED connector pin configuration
18 Add pin#1 position at rear drawing
0.2 Nov.11.2008 4 Revise Power Consumption 0.0
6 Update Electrical Characteristics
10 Update Signal Timing Specifications
12 Update Power Sequence (include LED control signal)
13 Revise Luminance Variation / Add color gamut
16 Add Mother Glass Thickness
19 Add rear view drawing
21 Add Backlight Exploded View image
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0.3 Dec.22.2008 11 Revise Signal Timing Specifications 0.1
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30~32 Update EDID data
14 Update Gray scale specification
EDID
ver
18 Update 2D drawing(Label information)
30~32 Update EDID data (check sum 09 Æ 01)
0.4 Dec.30.2008 4 Revise Pixel Pitch 0.2
6 Update Elcrical Characteristics
13 Update Color Coordinates
30~32 Update EDID data (check sum 01 Æ 78)
1.0 Feb. 2, 2009 - Final Draft 1.0
Ver. 1.0 2. Feb, 2009
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LP173WD1
EMI
N
(
N
Control
(
G
P
Total 7.2W(T
B/L
)
Liquid Crystal Display
Product Specification
1. General Description
The LP173WD1 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally white mode. This TFT-LCD has 17.3 inches diagonally measured active display area with
WHD+ resolution(1600 horizontal by 900 vertical pixel array). Each pixel is divided into Red, Green and
Blue sub-pixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel
color is determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than
262,144 colors.
The LP173WD1 has been designed to apply the interface method that enables low power, high speed, low
.
The LP173WD1 is intended to support applications where thin thickness, low power are critical factors and
graphic displays are important. In combination with the vertical arrangement of the sub-pixels, the
LP173WD1 characteristics provide an excellent flat display for office automation products such as Notebook
PC.
900
GIP
Gate In Panel)
1
C
1
User connector
40
Pin
LVDS &
Timing
Block
POWER
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Control & Data Power EDID signal & Power
BLOCK
EDID
BLOCK
eneral Features
Active Screen Size 17.3 inches diagonal
Outline Dimension
Pixel Pitch 0.23868 X 0.23868 mm
Pixel Format 1600 horiz. by 900 vert. Pixels RGB strip arrangement
Color Depth 6-bit, 262,144 colors
Luminance, White 220 cd/m
ower Consumption
Weight 570g (Max.)
Display Operating Mode Transmissive mode, normally white
Surface Treatment Glare treatment of the front Polarizer
398.1(H, Typ.) × 232.8(V, Typ.) × 6.0(D, Max.) mm
2
(Typ., @I
yp.) Logic : 1.5 W (Typ.@Mosaic),
=21mA)
LED
TFT-LCD Panel
(1600 x 900)
(LOG_B type)
1
Source Driver Circuit
LED Backlight Ass’y
: 5.7W (Typ.
1600
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LP173WD1
10
%
Liquid Crystal Display
Product Specification
2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39
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Wet Bulb
Temperature [℃]
20
10
0
VCC -0.3 4.0 Vdc at 25 ± 5°C
TOP 050°C1
HST -20 60 °C1
HOP 10 90 %RH 1
HST 10 90 %RH 1
°C Max, and no condensation of water.
50
40
30
Values
Min Max
90% 80%
60
Units Notes
60%
Humidity[(%)RH]
Storage
40%
Operation
20%
-20
Ver. 1.0 2. Feb, 2009
10
20 30 40 50
Dry Bulb Temperature [℃]
60 70 800
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LP173WD1
Power Supply Input Voltage
VCC3.0
3.3
3.6
V
_
_g g
LED_EN_H
g
gy
Liquid Crystal Display
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
The LP173WD1 requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL.with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS
Parameter Symbol
LOGIC :
Power Supply Input Current ICC - 455 515 mA 1
Power Consumption P
Power Supply Inrush Current I
LVDS Impedance Z
BACKLIGHT : ( with LED Driver)
LED Power Input Voltage V
LED Power Input Current ILED -2125mA3
LED Power Comsumption PLED -5.76.0W3
LED Power Inrush Current I
PWM Dimming (Duty) Ratio - 12.5 - 100 % 4
PWM Frequency F
PWM High Level Voltage V
PWM Low Level Voltage V
LED
LED_EN Low Voltage V
Life Time 12,000 - - Hrs 6
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EN High VoltageV
CC -1.51.7W1
CC_P - - 1800 mA
LVDS 90 100 110 Ω 2
LED 7.0 12.0 20.0 V
LED_P - - 1800 mA
PWM 200 1500 Hz 5
PWM_H
PWM_L
LED_EN_L
Min Typ Max
2.1 3.3 5 V
0-0.8V
2.1 3.3 5 V
0-0.8V
Values
Unit Notes
Note)
1. The specified Icc current and power consumption are under the Vcc = 3.3V , 25℃, fv = 60Hz condition
whereas Mosaic pattern is displayed and fv is the frame frequency.
2. This impedance value is needed to proper display and measured form
LVDS Tx to the mating connector.
3. The specified LED current and power consumption are under the Vled = 12.0V , 25℃, Dimming of Max
luminance whereas White pattern is displayed and fv is the frame frequency.
4. The operation of LED Driver below minimum dimming ratio may cause flikering or relaibility issue.
5. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable ran
more consistent brightness control at any specific level desired.
6. The life time is determined as the time at which brightness of LCD is 50% compare to that of initial value
at the typical LED current. These LED backlight has 6 strings on it and the typical current of LED’s string
is base on 21mA.
Ver. 1.0 2. Feb, 2009
e as defined, the PWM Frequency should be fixed and stable for
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LP173WD1
SW, SW0617(LCD Controller)
3
VDD
P
)
20345
-
#40E
-
## series
11
Odd_Rin1
--LVDS differential data input (G1
-
G5,B0
-
B1)
19NCNo Connection
p
1
40
p
Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector is used for the module electronics interface
and the other connector is used for the integral backlight system.
The electronics interface connector is a model UJU
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
Pin Symbol Description Notes
1 NC No Connection.
2 VDD Power Supply (3.3V typ.)
ower Supply (3.3V typ.
4 V
5 NC No Connection.
6 CLK
7 DATA
8 Odd_Rin0- - LVDS differential data input (R0-R5,G0)
9 Odd_Rin0+ + LVDS differential data input (R0-R5,G0)
10 VSS Ground
EDID
EDID
EDID
DDC 3.3V power
DDC clock / SMBus clock
DDC data / SMBus data
20455-040E manufactured by UJU.
[Interface Chip]
1. LCD :
Including LVDS Receiver.
2. System : SiWLVDSRx or equivalent
* Pin to Pin compatible with LVDS
[Connector]
UJU 20455-040E or equivalent
[Mating Connector]
12 Odd_Rin1+ + LVDS differential data input (G1-G5,B0-B1)
13 VSS Ground
14 Odd_Rin2- - LVDS differential data input (B2-B5,HS,VS,DE)
15 Odd_Rin2+ + LVDS differential data input (B2-B5,HS,VS,DE)
16 VSS Ground
17 Odd_ClkIN- - LVDS differential clock input
18 Odd_ClkIN+ + LVDS differential clock input
20 Even Rin0- - LVDS differential data input (R0-R5,G0)
21 Even Rin0+ + LVDS differential data input (R0-R5,G0)
22 VSS Ground
23 Even Rin1- - LVDS differential data input (G1-G5,B0-B1)
24 Even Rin1+ + LVDS differential data input (G1-G5,B0-B1)
25 VSS Ground
26 Even Rin2- - LVDS differential data input (B2-B5,HS,VS,DE)
27 Even Rin2+ + LVDS differential data in
28 VSS Ground
29 Even ClkIN- - LVDS differential clock input
30 Even ClkIN+ + LVDS differential clock input
31 VBL- LED power return
32 VBL- LED power return
33 VBL- LED power return
34 NC No Connection.
35 BLIM PWM for luminance control
36 BL_EN BL On/Off
37 NC No Connection.
38 VBL+ 7V-20V LED power
39 VBL+ 7V-20V LED power
40 VBL+ 7V-20V LED power
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ut (B2-B5,HS,VS,DE)
or equivalent
[Connector pin arrangement]
Ver. 1.0 2. Feb, 2009
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Product Specification
3-3-1. DC S
ificati
F
DEV
±
3
%
3-3. LVDS Signal Timing Specifications
LP173WD1
Liquid Crystal Display
pec
Description
LVDS Differential Voltage |V
LVDS Common mode Voltage V
LVDS Input Voltage Range V
3-3-2. AC Specification
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on
Symb
ol
| 100 600 mV -
ID
CM
IN
Min Max Unit Notes
0.6 1.8 V -
0.3 2.1 V -
Description Symbol Min Max Unit Notes
LVDS Clock to Data Skew Margin
LVDS Clock to Clock Skew Margin (Even
to Odd)
Maximum deviation
of input clock frequency during SSC
Maximum modulation frequency
of input clock during SSC
Ver. 1.0 2. Feb, 2009
t
SKEW
t
SKEW
t
SKEW_EO
F
MOD
- 400 + 400 ps
- 600 + 600 ps
-1/7 + 1/7 T
-
- 200 KHz -
clk
85MHz > Fclk ≥
65MHz > Fclk ≥
65MHz
25MHz
-
-
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< Clock skew margin between channel >
Freq.
F
max
F
center
F
min
Product Specification
LP173WD1
Liquid Crystal Display
F
* F
center
DEV
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3-3-3. Data Format
1) LVDS 2 Port
1
F
MOD
< Spread Spectrum >
Time
Ver. 1.0 2. Feb, 2009
< LVDS Data Format >
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3-4. Signal Timing Specifications
This is the signal timing required at the input of the User connector
All of the interface signal timing should be
Horizontal back porch
t
324448
LP173WD1
Liquid Crystal Display
Product Specification
.
satisfied with the following specifications and specifications of LVDS Tx/Rx for its proper operation.
Table 5. TIMING TABLE
ITEM Symbol Min. Typ. Max. Unit Note
DCLK Frequency f
Period
Hsync tCLK 2 Port
Vsync
Data
Enable
Width
Width-Active
Period
Width
Width-Active
Horizontal front porch
Vertical back porch
Vertical front porch
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t
t
tw
t
t
tw
t
t
t
CLK
HP
WH
HA
VP
WV
VA
HBP
HFP
VBP
VFP
47.375 48.875 50.375
868 892 908
20 24 32
800 800 800
907 912 926
235
900 900 900
16 24 28
4715
126
MHz 2 Port
tHP
tCLK 2 Port
tHP
3-5. Signal Timing Waveforms
t
Hsync
Date Enable
Vsync
Ver. 1.0 2. Feb, 2009
t
WH
t
WV
Date Enable
t
t
VBP
HBP
HP
t
VP
High: 0.7VCC
Low: 0.3VCC
tWHA
tWVA
Condition : VCC=3.3V
t
HFP
t
VFP
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