MECHANICAL CHARACTERISTICS
RELIABLITY6
INTERNATIONAL STANDARDS7
SAFETY7-1
EMC7-2
PACKING8
DESIGNATION OF LOT MARK8-1
PACKING FORM8-2
PRECAUTIONS9
APPENDIX. Enhanced Extended Display Identification Data A
Update Electrical Characteristics6
Update Signal Specifications10
Update Rear View18
Update EDID
Final SpecificationAllJan. 21, 20101.0
ML1-, ML1+)
EDID
ver
-
X20EDID Updated28-30Dec. 5, 20090.3
A00
Ver. 1.0Jan.21, 2010
3 / 30
LP156WF1
Liquid Crystal Display
Product Specification
1. General Description
The LP156WF1 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally white mode. This TFT-LCD has 15.6 inches diagonally measured active display area with FHD
resolution(1080 vertical by 1920 horizontal pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors.
The LP156WF1 has been designed to apply the interface method that enables low power, high speed, low
EMI.
The LP156WF1 is intended to support applications where thin thickness, low power are critical factors and
graphic displays are important. In combination with the vertical arrangement of the sub-pixels, the
LP156WF1 characteristics provide an excellent flat display for office automation products such as Notebook
PC.
The LP156WF1 requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS
LOGIC :
Power Supply Input Voltage
Power Consumption
Power Supply Inrush Current
LVDS Impedance
BACKLIGHT : ( with LED Driver)
LED Power Input Voltage
LED Power Input Current
LED Power Consumption
LED Power Inrush Current
PWM Jitter
PWM Impedance
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SymbolParameter
CC
MosaicPower Supply Input Current
CC
CC
CC_P
LVDS
LED
LED
LED
LED_P
-
PWM
Values
MaxTypMin
11010090Z
Ω
kΩ604020Z
NotesUnit
1V3.63.33.0V
2mA700600-I
2W2.32.0-P
3mA1500--I
4
5V21.012.07.0V
6mA517487-I
6W6.25.85-P
7mA1500--I
8%100-5PWM Duty Ratio
9%0.2-0
PWM Frequency
PWM High Level Voltage
PWM Low Level Voltage
LED_EN Impedance
LED_EN High Voltage
LED_EN Low Voltage
Ver. 1.0Jan.21, 2010
PWM
PWM_H
PWM_L
PWM
LED_EN_H
LED_EN_L
10Hz1000-200F
V5.3-3.0V
V0.5-0V
kΩ604020Z
V5.3-3.0V
V0.5-0V
11Hrs--12000Life Time
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Liquid Crystal Display
Product Specification
Note)
1. The measuring position is the connector of LCM and the test conditions are under 25℃, fv = 60Hz,
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25℃, fv = 60Hz condition and Mosaic pattern.
3. This Spec. is the max load condition for the cable impedance designing.
4. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.
LP156WF1
Rising time
Vcc
0V
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5. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.
6. The measuring position is the connector of LCM and the test conditions are under 25℃.
7. The current and power consumption with LED Driver are under the Vled = 12.0V , 25℃, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).
8. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.
90%
10%
0.5ms
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3.3V
Rising time
V
LED
0V
10%
12.0V
90%
0.5ms
9. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
10. If Jitter of PWM is bigger than maximum, it may induce flickering.
11. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.
12. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user condition.
Ver. 1.0Jan.21, 2010
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LP156WF1
Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 30 pin connector is used for the module electronics interface
and the other connector is used for the integral backlight system.
The electronics interface connector is a model CABLINE-VS RECE ASS’Y manufactured by I-PEX.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
NotesDescriptionSymbolPin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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BL_GNDBL Ground
Conn. Continuity Test (Reserved)PAID
High Speed (Main Link) GroundH_GND
Complement Signal-Lane 1ML1True Signal-Main Lane 1ML1+
High Speed (Main Link) GroundH_GND
Complement Signal-Lane 0ML0True Signal-Main Lane 0ML0+
High Speed (Main Link) GroundH_GND
True Signal-Auxiliary ChannelAUX+
Complement Signal-Auxiliary ChannelAUXHigh Speed (Main Link) GroundH_GND
VCC for Module (3.3V)VCC
VCC for Module (3.3V)VCC
Built-In Self Test (active high)BIST
GroundGND
GroundGND
HPD signal pinHPD
BL GroundBL_GND
BL GroundBL_GND
BL GroundBL_GND
1, Interface chips
1.1 LCD : IDT, Becrux (LCD Controller)
including eDP Receiver
PWM for luminance control (200~1KHz, 3.3V, 6~100%,
0V=off) 5V tolerant
No Connection (Reserved)NC
No Connection (Reserved)NC
BL Power 7V-20VVBL
BL Power 7V-20VVBL
BL Power 7V-20VVBL
BL Power 7V-20VVBL
Conn. Continuity Test (Reserved)PAID
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LP156WF1
Liquid Crystal Display
Product Specification
3-3. eDP Signal Timing Specifications
3-3-1. DC Specification
The VESA Display Port related AC specification is compliant with the VESA Display Port Standard v1.1a.
NotesUnitMaxMinSymbolDescription
Differential peak-to-peak Input voltage
Rx DC common mode voltage
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VDIFF p-p
CM
-120
mV
For high bit rate
For reduced bit rate-40
-V2.00V
3-3-2. AC Specification
The VESA Display Port related AC specification is compliant with the VESA Display Port Standard v1.1a.
Unit Interval for high bit rate
(2.7Gbps/lane)
Unit Interval for high bit rate
(1.62Gbps/lane)
Lane-to-Lane skew
V Rx-SKEWINTER_PAIR
Typ
370
-
617
-
-
Range is nominal ±350ppm.
ps-UI_High_Rate
DisplayPort Link Rx does not
require local crystal for link
clock generation
ps-UI_Low_Rate
-
ps5200-
NotesUnitMaxMinSymbolDescription
Lane intra-pair skew
Ver. 1.0Jan.21, 2010
V Rx-SKEWINTRA_PAIR
-
For high bit rate
ps100-
For reduced bit rateps300--
9 / 30
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