INTERFACE CONNECTIONS3-2
SIGNAL TIMING SPECIFICATIONS3-3
SIGNAL TIMING WAVEFORMS3-4
COLOR INPUT DATA REFERNECE3-5
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POWER SEQUENCE3-6
OPTICAL SFECIFICATIONS4
MECHANICAL CHARACTERISTICS5
Page
1
2
3
4
5
6
7
9
9
10
11
12
16
RELIABLITY6
INTERNATIONAL STANDARDS7
SAFETY7-1
EMC7-2
PACKING8
DESIGNATION OF LOT MARK8-1
PACKING FORM8-2
PRECAUTIONS9
APPENDIX. Enhanced Extended Display Identification Data (EEDID
Ver. 0.0May. 7, 2007
TM
20
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21
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Product Specification
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RECORD OF REVISIONS
LP141WP1
Liquid Crystal Display
DescriptionPageRevision DateRevision No
First draft-May. 7. 20070.0
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EDID
ver
V0.0
Ver. 0.0May. 7, 2007
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LP141WP1
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Liquid Crystal Display
Product Specification
1. General Description
The LP141WP1 is a Color Active Matrix Liquid Crys tal Display with an integral Cold Cathode Fluo rescent
Lamp (CCFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active e lement. It is a
transmissive type display operating in the normally white mode. This TFT-LCD has 14.1 inches diagonally
measured active display area with WXGA+ resolution(900 vertical by 1440 horizontal pixel array). Each
pixel is divided into Red, Green and Blue sub -pixels or dots which are arranged in vertical st ripes. Gray
scale or the brightness of the sub-pixel color is determined with a 6-bit gray scale signal for each dot, thus,
presenting a palette of more than 262,144 colors.
The LP141WP1 has been designed to apply the interface me thod that enables low power, high speed, low
EMI.
The LP141WP1 is intended to support applications where thin thickness , low power are critica l factor s and
graphic displays are important. In combination with the vertical arrangement of the sub-pixels, the
LP141WP1 characteristics prov ide an excellent flat display for office automa t ion products such as Notebook
PC.
CN
1
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General Features
LVDS
&
Timing
Control
Block
Power
Block
:Control & Data:Power
14.1 inches diagonal Active Screen Size
320 (H) × 206(V) × 5.5(D) mm [Max.)Outline Dimension
0.2109 mm × 0.2109 mmPixel Pitch
1440 horiz. By 900 vert. Pixels RGB strip arrangementPixel Format
6-bit, 262,144 colorsColor Depth
220 cd/m2(Typ.5 point)Luminance, White
Total 6.0 Watt(Typ.) @ LCM circuit 1.9Watt(Typ.), B/L input 4.1Watt(Typ.)Power Consumption
435 g (Max.), 425g(Typ.)Weight
Transmissive mode, normally whiteDisplay Operating Mode
Anti-glare treatment of the front polarizer(Nitto Denko AG ARC 150T)Surface Treatment
YesRoHS Comply
Row Dirver Circuit
Column Driver Circuit
TFT-LCD
(1440 X 900)
J3
Backlight Ass'y
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LP141WP1
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Liquid Crystal Display
Product Specification
2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
Table 1. ABSOLUTE MAXIMUM RATINGS
60
Values
Units
MaxMin
90% 80%
60%
Humidity[(%)RH]
Storage
40%
Operation
20%
10%
ParameterNotes
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity
Note : 1. Temperature and relative humidity range are shown in the figure below.
The LP141WP1 requires two power inputs. One is employed to power the LCD electronic s and to drive the
TFT array and liquid crystal. The second input which powers the CCFL, is typically generated by an
inverter. The inverter is an external unit to t h e L CD.
Table 2. ELECTRICAL CHARACTERISTICS
ParameterSymbol
MODULE :
Power Supply Input Current
(Window Desk Top Pattern)
Power Consumption
(Window Desk Top Pattern)
Differential Impedance
LAMP :
Operating Voltage
Operating Current
Power Consumption
Operating Frequency
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I
CC
Zm
BL
BL
-
-Pc
BL
BL
-P
Values
560
(460)
1.9
(1.5)
880(2.0mA)675(6.0mA)640(7.0)V
MaxTypMin
3.63.33.0VCCPower Supply Input Voltage
645
(530)
2.2
(1.8)
11010090
7.06.02.0I
4.54.1
NotesUnit
V
DC
1Ma
1Watt
2Ohm
V
RMS
RMS
kHz806550f
3mA
4Min3--TsDischarge Stabilization Time
5Hrs--15,000Life Time
Established Starting Voltage
at 25℃
at 0 ℃
Ver. 0.0May. 7, 2007
Vs
1180
1400
V
RMS
V
RMS
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LP141WP1
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Liquid Crystal Display
Product Specification
Note)
1. The specified current and power consumption are under the Vcc = 3.3V , 25℃, fv = 60Hz condition
whereas full black pattern (Window Desk Top Pattern) is displayed and fv is the frame frequency.
2. This impedance value is needed to proper display and measured form LVDS Tx to the mating connector.
3. The typical operating current is for the typical surface luminance (L
4. Define the brightness of the lamp after being lighted for 5 minutes as 100%, Ts is the time required for
the brightness of the center of the lamp to be not less than 95%.
5. The life time is determined as the time at which brightness of lamp is 50% compare to that of initial value
at the typical lamp current.
6. The output of the inverter must have symmetrical(negative and positive) voltage waveform and
symmetrical current waveform.(Asymmetrical ratio is less than 10%) Please do not use the inverter
which has asymmetrical voltage and asymmetrical current and spike wave.
Lamp frequency may produce interface with horizontal synchronous frequency and as a result this may
cause beat on the display. Therefore lamp frequency shall be as away possible from the
horizontal synchronous frequency and from its harmonics in order to prevent interference.
7. It is defined the brightness of the lamp after being lighted for 5 minutes as 100%.
T
is the time required for the brightness of the center of the lamp to be not less than 95%.
S
8. The lamp power consumption shown above does not include loss of external inverter.
The applied lamp current is a typical one.
) in optical characteristics.
WH
9. Requirements for a system inverter design, which is intended to have a better display performance, a
better power efficiency and a more reliable lamp, are following.
It shall help increase the lamp lifetime and reduce leakage current.
a. The asymmetry rate of the inverter waveform should be less than 10%.
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b. The distortion rate of the waveform should be within √2 ±10%.
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* Inverter output waveform had better be more similar to ideal sine wave.
* Asymmetry rate:
I p
I -p
※ Do not attach a conducting tape to lamp connecting wire.
If the lamp wire attach to a conducting tape, TFT-LCD Module has a low luminance and the inverter
has abnormal action. Because leakage current is occurred between lamp wire and conducting tape.
| I
–I –p| / I
p
* Distortion rate
I
(or I –p) / I
p
rms
rms
* 100%
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Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 30 pin connector is used for the module electronics interface
and the other connector is used for the integral backlight system.
The electronics interface connector is a model
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
GroundGND1
Power Supply, 3.3V Typ.VCC2
Power Supply, 3.3V Typ.VCC3
DDC 3.3V powerV EEDID4
Requested for LCD supplier test pointBIST5
DDC ClockClk EEDID6
DDC DataDATA EEDID7
Negative LVDS differential data input, R0-R5, G0RA1-8
Positive LVDS differential data input, R0-R5, G0RA1+9
GroundGND10
Negative LVDS differential data input, G1-G5, B0-B1RB1-11
Positive LVDS differential data input, G1-G5, B0-B1RB1+12
GroundGND13
Negative LVDS differential data input, B2-B5, HS/VS/DERC1-14
Positive LVDS differential data input, B2-B5, HS/VS/DERC1+15
GroundGND16
Negative LVDS differential clock inputRCLK1-17
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RA2+Positive LVDS differential data input, R0-R5, G021
1Power supply for lamp (High voltage side)HV1
1Power supply for lamp (Low voltage side)LV2
Notes : 1. The high voltage side terminal is colored pink and the low voltage side terminal is Green.
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Liquid Crystal Display
Product Specification
3-3. Signal Timing Specifications
This is the signal timing required at the input of the User connector. All of the interface signal timing should be
satisfied with the following specifications and specifications of LVDS Tx/Rx for its proper operation.
Table 6. TIMING TABLE
NoteUnitMaxTypMinSymbolITEM
MHz10510299f
tCLK
tHP
tCLK
tHP
Vsync
Data
Enable
FrequencyDCLK
Width
Width-Active
Period
Width
Width-Active
Horizontal back porch
Horizontal front porch
Vertical back porch
Vertical front porch
CLK
WH
WHA
VP
WV
WVA
HBP
HFP
VBP
VFP
186418401800ThpPeriodHsync
887256t
144014401440t
939926920t
1063t
900900900t
256248240t
808064t
231712t
632t
Note)
1. In this documentation, all reliabilities are specified for timing spe cification bas ed on refresh rate of 60Hz.
However, LP141WP1 has a good actual performance even at lower refresh rate( eg. 40Hz or 50Hz) for
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power saving mode, whereas LP141WP1 is secured only for function under lower refresh rate.
60Hz at Normal mode, 50Hz ,40 Hz at Power save mode. Don’t care Flicker level (power save mode).
3-4. Signal Timing Waveforms
High: 0.7VCC
Condition : VCC =3.3V
Data Enable, Hsync, Vsy n c
Low: 0.3VCC
DCLK
Hsync
t
tCLK
WH
t
HBP
0.5 Vcc
t
HP
Data Enable
t
VP
t
WV
Vsync
t
VBP
Data Enable
Ver. 0.0May. 7, 2007
tWHA
tWVA
t
HFP
t
VFP
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