LG LDC-A310 BLOCK DIAGRAM

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1. OUTLINE OF CIRCUIT DESCRIPTION

1-1. CP1 CIRCUIT DESCRIPTION

1. IC Configuration

IC903 (ICX432JQ) CCD imager IC904 (CXD3440EN) V driver IC905 H driver, CDS, PGA and A/D converter (HD49335NP01)

2. IC903 (CCD imager)

[Structure]

Interline type CCD image sensor

Image size Diagonal 6.67 mm (1/2.7 type) Pixels in total 2140 (H) x 1560 (V) Recording pixels 2064 (H) x 1541 (V)

Pin No.

Symbol

Vø

Vertical register transfer clock

Pin Description

GND

OUT

Waveform

Vertical register

Horizontal register

GND

SUB

(Note) : Photo sensor

Fig. 1-1. CCD Block Diagram

Voltage

-7.5 V, 0 V

(Note)

2, 3

8, 7, 4

5, 6

9, 13

Vø

5A, Vø5B

Vø1, Vø2, Vø4

Vø3A, Vø3B

GND

OUT

VDD

øRG

øSUB

CSUB

Hø1

Hø

Vertical register transfer clock

GND

GND 0 V

Signal output

Circuit power

Reset gate clock

Substrate clock

Substrate bias

Protection transistor bias DC

Horizontal register transfer clock

Table 1-1. CCD Pin Description

-7.5 V, 0 V, 15 V

-7.5 V, 0 V

-7.5 V, 0 V, 15 V

Aprox. 10 V

15 V

13.0 V, 16 V

Approx. 9 V Approx. 9 V

(Different from every CCD)

0 V, 3.0 V

When sensor read-out

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3. IC904 (V Driver)

V driver is necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD. IC904 is V driver. In addition the XV1-XV4 signals which are output from IC101 are the vertical transfer clocks, and the XSG signal which is output from IC102 is superimposed onto XV1 and XV3 at IC904 in order to generate a ternary pulse. In addition, the XSUB signal which is output from IC101 is used as the sweep pulse for the electronic shutter.

4. IC905 (CDS, PGA, A/D Converter and H driver)

The video signal which is output from the CCD is input to Pin (51) of IC905. There are inside the CDS block, PGA block and A/D converter block. The setting of sampling phase and PGA is carried out by serial data at Pin (63) of IC935. The video signal is carried out A/D converter, and is output by 10-bit. A H driver is inside IC905, and H1, H2 and RG clock are generated at IC905.

HD_in

CLK_in

DRDV

Reset

D9 D8

D7 D6 D5 D4 D3 D2

Output latch circuit

D1 D0

ADC_in

CDS_in

BLKSH

BLKC

BLKFB

CDS

DC offset

compensation

ciruit

H2A

PBLK

CPDM

PGA

Serial

interface

H1A

ADCK

CPOB

SP1

SP2

Bias

genera-

tion

VD_in

TIMING

generator

10 bit

ADC

5. Lens drive block

5-1. Iris drive

When the drive signals (IIN+ and IIN–) which are output from the ASIC (IC101), it is driven by the driver (IC951), and are then used to drive the iris steps.

5-2. Focus drive

When the drive signals (FIN_A, FIN_-A, FIN_B and FIN_-B) which are output from the ASIC expansion I/O port (IC105), the focus stepping motor is driven by the driver (IC951). Detection of the standard focusing positions is carried out by means of the photointerruptor (FOCUS PI) inside the lens block.

5-3. Zoom drive

When the drive signals (ZIN+ and ZIN–) which are output from the ASIC (IC101), the zoom motor is driven by the driver (IC951). Detection of the standard zoom positions is carried out by means of photointerruptor (ZOOM PI and PI2) inside the lens block.

5-4. Shutter drive

When the drive signals (SIN+ and SIN–) which are output from the ASIC (IC101), it is driven regular current by the driver (IC951).

MON

DLL_C

SCK

SDATA

CDS_CS

BIAS

VRT

VRM

Fig. 1-2. IC905 Block Diagram

VRB

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6. Circuit Description

6-1. Digital clamp

The optical black section of the CCD extracts averaged values from the subsequent data to make the black level of the CCD output data uniform for each line. The optical black section of the CCD averaged value for each line is taken as the sum of the value for the previous line multiplied by the coefficient k and the value for the current line multiplied by the coefficient 1-k.

6-2. Signal processor

1. γ correction circuit

This circuit performs (gamma) correction in order to maintain a linear relationship between the light input to the camera and the light output from the picture screen.

2. Color generation circuit

This circuit converts the CCD data into RGB signals.

3. Matrix circuit

This circuit generates the Y signals, R-Y signals and B-Y signals from the RGB signals.

4. Horizontal and vertical aperture circuit

This circuit is used gemerate the aperture signal.

6-3. AE/AWB and AF computing circuit

The AE/AWB carries out computation based on a 64-segment screen, and the AF carries out computations based on a 6segment screen.

6-4. SDRAM controller

This circuit outputs address, RAS, CAS and AS data for controlling the SDRAM. It also refreshes the SDRAM.

6-5. Communication control

1. SIO

This is the interface for the 8-bit microprocessor.

7. Outline of Operation

When the shutter opens, the reset signals (ASIC and CPU) and the serial signals (“take a picture” commands) from the 8-bit microprocessor are input and operation starts. When the TG/SG drives the CCD, picture data passes through the A/D and CDS, and is then input to the ASIC as 10-bit data. The AF, AE, AWB, shutter, and AGC value are computed from this data, and three exposures are made to obtain the optimum picture. The data which has already been stored in the SDRAM is read by the CPU and color generation is carried out. Each pixel is interpolated from the surrounding data as being either Ye, Cy, Mg or B primary color data to produce R, G and B data. At this time, correction of the lens distortion which is a characteristic of wide-angle lenses is carried out. After AWB and γ processing are carried out, a matrix is generated and aperture correction is carried out for the Y signal, and the data is then compressed by JPEG and is then written to card memory (SD card). When the data is to be output to an external device, it is taken data from the memory and output via the USB I/F. When played back on the LCD and monitor, data is transferred from memery to the SDRAM, and the image is then elongated so that it is displayed over the SDRAM display area.

8. LCD Block

LCD block is in the CP1 board, and it is constructed by VCOM gerenated circuit etc. The video signal from the ASIC are input to LCD panel directly by 6-bit digital signal, and are converted into RGB signals by driver circuit in the LCD panel. Because the LCD closes more as the difference in potential between the VCOM (common polar voltage: AC) and the R, G and B signals becomes greater, the display becomes darker; if the difference inpotential is smaller, the element opens and the LCD becomes brighter. And also timing pulse except video signal are input at LCD panel directly from ASIC.

2. PIO/PWM/SIO for LCD

8-bit parallel input and output makes it possible to switch between individual input/output and PWM input/output.

6-6. TG/SG

Timing generated for 3 million pixel CCD control.

6-7. Digital encorder

It generates chroma signal from color difference signal.

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1-2. CP1 POWER CIRCUIT DESCRIPTION

1. Outline

This is the main power circuit, and is comprised of the following blocks. Switching power controller (IC501) Analog system power output (Q5001, T5001) Digital 1.8 V power output (Q5009, L5006) Digital 3.3 V power output (Q5002, L5004) LCD 15 V system power output (Q5010, L5007) LCD 5 V power output (IC502) LED backlight power output (Q5013, L5008)

3.6 V lens system power output (IC955, Q9551, L9551)

2. Switching Controller

This is the basic circuit which is necessary for controlling the power supply for a PWM-type switching regulator, and is provided with five built-in channels, only CH1 (analog system power output), CH2 (digital 3.3 V system power output), CH3 (digital 1.8 V system power output), CH4 (LCD 15 V system power output) and CH5 (LED back light power output) are used. Feedback from 15.0 V (A) (CH1), 3.3 V (D) (CH2), 1.8 V (D) (CH3), 15 V B (CH4) and LED backlight output (CH5) are received, and the PWM duty is varied so that each one is maintained at the correct voltage setting level.

3. Analog System Power Output

15.0 V (A), -7.6 V (A) and 3.05 V (A) are output. Feedback for the 15.0 V (A) is provided to the switching controller (Pin (40) of IC501) so that PWM control can be carried out.

4. Digital 1.8 V Power Output

1.8 V (D) is output. Feedback for the 1.8 V (D) is provided to the switching controller (Pins (45) of IC501) so that PWM control can be carried out.

5. Digital 3.3 V Power Output

3.3 V (D) is output. Feedback for the 3.3 V (D) is provided to the swiching controller (Pin (43) of IC501) so that PWM control can be carried out.

6. LCD 15 V System Power Output

LCD 15 V (L) and buzzer 15 V B are output. Feedback for the 15 V B is provided to the swiching controller (Pin (47) of IC501) so that PWM control can be carried out.

7. LCD 5 V Power Output

5 V (L) is output. 5 V (L) is output for regulated 15 V B at IC502.

2-1. Short-circuit Protection

If output is short-circuited for the length of time determined by the condenser which is connected to Pin (37) of IC501, all output is turned off. The control signal (P ON) are recontrolled to restore output.

8. LED Backlight Power Output

A constant current flows to the backlight LEDs. Feedback for the voltage of R5063 is provided to the power controller (Pin (2) of IC501) so that PWM control can be carried out.

9. 3.6 V Lens System Power Output

Lens power 3.6 V is output. Feedback for the lens 3.6 V is provided to the swiching controller (Pin (1) of IC955) so that PWM control can be carried out.

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