LG LDC-A310 BLOCK DIAGRAM
1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CP1 CIRCUIT DESCRIPTION
1. IC Configuration
IC903 (ICX432JQ) CCD imager
IC904 (CXD3440EN) V driver
IC905 H driver, CDS, PGA and A/D converter
(HD49335NP01)
2. IC903 (CCD imager)
[Structure]
Interline type CCD image sensor
Image size Diagonal 6.67 mm (1/2.7 type)
Pixels in total 2140 (H) x 1560 (V)
Recording pixels 2064 (H) x 1541 (V)
Pin No.
1
Symbol
6
Vø
Vertical register transfer clock
Pin Description
GND
8
9
10
11
DD
OUT
V
V
Waveform
7
6
Gb
R
Gb
R
Gb
R
Vertical register
Gb
R
Horizontal register
12
13
GND
5
B
Gr
B
Gr
B
Gr
B
Gr
14
3
4
Gb
R
Gb
R
Gb
R
Gb
R
15
16
L
V
SUB
C
(Note) : Photo sensor
Fig. 1-1. CCD Block Diagram
Voltage
-7.5 V, 0 V
Gr
Gr
Gr
Gr
B
B
B
B
2
(Note)
17
1
18
2, 3
8, 7, 4
5, 6
9, 13
10
11
12
14
15
16
17
18
Vø
5A, Vø5B
Vø1, Vø2, Vø4
Vø3A, Vø3B
GND
OUT
V
VDD
øRG
øSUB
CSUB
VL
Hø1
Hø
2
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
GND 0 V
Signal output
Circuit power
DC
Reset gate clock
Substrate clock
Substrate bias
DC
DC
Protection transistor bias DC
Horizontal register transfer clock
Horizontal register transfer clock
Table 1-1. CCD Pin Description
-7.5 V, 0 V, 15 V
-7.5 V, 0 V
-7.5 V, 0 V, 15 V
Aprox. 10 V
15 V
13.0 V, 16 V
Approx. 9 V
Approx. 9 V
(Different from every CCD)
0 V, 3.0 V
0 V, 3.0 V
When sensor read-out
– 2 –
3. IC904 (V Driver)
V driver is necessary in order to generate the clocks (vertical
transfer clock, horizontal transfer clock and electronic shutter
clock) which driver the CCD.
IC904 is V driver. In addition the XV1-XV4 signals which are
output from IC101 are the vertical transfer clocks, and the
XSG signal which is output from IC102 is superimposed onto
XV1 and XV3 at IC904 in order to generate a ternary pulse.
In addition, the XSUB signal which is output from IC101 is
used as the sweep pulse for the electronic shutter.
4. IC905 (CDS, PGA, A/D Converter and H driver)
The video signal which is output from the CCD is input to Pin
(51) of IC905. There are inside the CDS block, PGA block
and A/D converter block.
The setting of sampling phase and PGA is carried out by serial data at Pin (63) of IC935. The video signal is carried out
A/D converter, and is output by 10-bit. A H driver is inside
IC905, and H1, H2 and RG clock are generated at IC905.
DD
DD
HD_in
CLK_in
DD
AV
DRDV
DV
AV
SS
DV
SS
Reset
D9
D8
D7
D6
D5
D4
D3
D2
Output latch circuit
D1
D0
ADC_in
CDS_in
BLKSH
BLKC
BLKFB
CDS
DC offset
compensation
ciruit
H2A
PBLK
CPDM
PGA
Serial
interface
H1A
ADCK
CPOB
RG
SP1
SP2
Bias
genera-
tion
VD_in
TIMING
generator
10 bit
ADC
5. Lens drive block
5-1. Iris drive
When the drive signals (IIN+ and IIN–) which are output from
the ASIC (IC101), it is driven by the driver (IC951), and are
then used to drive the iris steps.
5-2. Focus drive
When the drive signals (FIN_A, FIN_-A, FIN_B and FIN_-B)
which are output from the ASIC expansion I/O port (IC105),
the focus stepping motor is driven by the driver (IC951). Detection of the standard focusing positions is carried out by
means of the photointerruptor (FOCUS PI) inside the lens block.
5-3. Zoom drive
When the drive signals (ZIN+ and ZIN–) which are output from
the ASIC (IC101), the zoom motor is driven by the driver
(IC951). Detection of the standard zoom positions is carried
out by means of photointerruptor (ZOOM PI and PI2) inside
the lens block.
5-4. Shutter drive
When the drive signals (SIN+ and SIN–) which are output from
the ASIC (IC101), it is driven regular current by the driver
(IC951).
ID
MON
DLL_C
SCK
SDATA
CDS_CS
BIAS
VRT
VRM
Fig. 1-2. IC905 Block Diagram
VRB
– 3 –
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