LG GX500 User Manual

Service Manual Model : GX500

Internal Use Only

Service Manual

GX500

Date: March, 2010 / Issue 1.0

Table Of Contents

1. INTRODUCTION ................................................. 5

1.1 Purpose ............................................................................................... 5

1.2 Regulatory Information ............................................................... 5

1.3 Abbreviations ................................................................................... 7

2. PERFORMANCE ..................................................9

2.1 H/W Features .................................................................................... 9

2.2 Technical Speciﬁcation ...............................................................10

3. TECHNICAL BRIEF ............................................17

3.1 GX500 Functional Block diagram...........................................17

3.2 Dual Baseband Processor (BBP) Introduction ...................18

3.3 Power management IC ..............................................................38

3.4 Power ON/OFF ...............................................................................46

3.5 Dual SIM & u-SD Interface .........................................................48

3.6 Memory ............................................................................................50

3.7 LCD Display .....................................................................................53

3.8 Keypad Switching & Scanning ................................................54

3.9 LCD back-light illumination ......................................................55

3.10 JTAG & ETM interface connector .........................................56

3.11 Audio ...............................................................................................57

3.12 Charging circuit ..........................................................................59

3.13 WI-FI & BLUETOOTH & FMradio ............................................60

3.14 5pin Micro USB Interface connector ..................................63

3.15 Triaxial, digital acceleration sensor .....................................64

3.16 General Description ..................................................................66

3.17 Receiver part ................................................................................68

3.18 Transmitter part ..........................................................................69

3.19 RF synthesizer ..............................................................................70

3.20 DCXO ...............................................................................................70

3.21 Front End Module control ......................................................71

3.22 Power Ampliﬁer Module .........................................................72

3.23 PAM Schematic ...........................................................................73

4.4 LCD display trouble .....................................................................80

4.5 Camera Trouble .............................................................................82

4.6 Receiver & Speaker trouble ......................................................84

4.7 Microphone trouble ....................................................................86

4.8 Vibrator trouble .............................................................................87

4.9 SIM & uSD trouble ........................................................................89

4.10 Touch trouble...............................................................................92

4.11 LCD LED trouble .........................................................................93

4.12 Trouble shooting of Receiver part .......................................94

4.13 Trouble shooting of Transmitter part .............................. 100

4.14 Trouble shooting of WI-FI/BT/FM part ............................ 109

5. DOWNLOAD & S/W UPGRADE......................112

6. BLOCK DIAGRAM ...........................................120

7. CIRCUIT DIAGRAM ........................................121

8. BGA Pin Map ..................................................129

9. PCB LAYOUT ...................................................139

10. RF CALIBRATION .........................................147

10.1 Test Equipment Setup ........................................................... 147

10.2 Calibration Step ....................................................................... 147

11. STAND ALONE TEST ....................................152

11.1 SIM1 TEST ...................................................................................152

11.2 SIM2 TEST ...................................................................................159

12. ENGINEERING MODE ..................................161

13. EXPLODED VIEW & REPLACEMENT

PART LIST ....................................................163

13.1 EXPLODED VIEW ......................................................................163

13.2 Replacement Parts..................................................................165

13.3 Accessory ...................................................................................189

4. TROUBLE SHOOTING ......................................74

4.1 Trouble shooting test setup .....................................................74

4.2 Power on Trouble ..........................................................................75

4.3 Charging trouble ..........................................................................78

- 3 -

LGE Internal Use Only

- 4 -

Only for training and service purposes

1. INTRODUCTION

GX500 Operational Description Revision A

I. Introduction

1.1 Purpose

This manual provides the information necessary to repair, calibration, description and download the features of the GX500.

1.2 Regulatory Information

1.2.1 Security

Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges you’re your telecommunications services. System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. LGE does not warrant that this product is immune from the above case but will prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it. LGE will not be responsible for any charges that result from such unauthorized use.

1.2.2 Incidence of Harm

If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done.

1.2.3 Changes in Service

A local telephone company may make changes in its communications facilities or procedure. If these changes could reasonably be expected to affect the use of the GX500 or compatibility with the network, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service.

1.2.4 Maintenance Limitations

Maintenance limitations on the GX500 must be performed only at the LGE or its authorized agents. The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty.

1.2.5 Notice of Radiated Emissions

The GX500 complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies. In accordance with these agencies, you may be required to provide information such as the following to the end user.

1. INTRODUCTION

- 5 -

LGE Internal Use Only

1. INTRODUCTION

GX500 Operational Description Revision A

1.2.6 Pictures

The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.

1.2.7 Interference and Attenuation

An GX500 may interfere with sensitive laboratory equipment, medical equipment, etc. Interference from unsuppressed engines or electric motors may cause problems.

1.2.8 Electrostatic Sensitive Devices

ATTENTION

Boards, which contains Electrostatic Sensitive Device(ESD), are indicated by the sign. Following information is ESD handling: Service personnel should ground themselves by using a wrist strap when exchange system boards. When repairs are made to a system board, they should spread the floor with anti-static mat which is also grounded. Use a suitable, grounded soldering iron. Keep sensitive parts in these protective packages until these are used. When returning system boards or parts such as EEPROM to the factory, use the protective package as described.

- 6 -

Only for training and service purposes

1. INTRODUCTION

GX500 Operational Description Revision A

1.3 ABBREVIATION

For the purposes of this manual, following abbreviations apply:

୛ APC Automatic Power Control ୛ BB Baseband ୛ BER Bit Error Ratio ୛ CC-CV Constant Current – Constant Voltage ୛ CLA Cigar Lighter Adapter ୛ DAC Digital to Analog Converter ୛ DCS Digital Communication System ୛ dBm dB relative to 1 milli-watt ୛ DSP Digital Signal Processing ୛ EEPROM Electrical Erasable Programmable Read-Only Memory ୛ EGPRS Enhanced General Packet Radio Service ୛ EL Electroluminescence ୛ ESD Electrostatic Discharge ୛ FPCB Flexible Printed Circuit Board ୛ GMSK Gaussian Minimum Shift Keying ୛ GPIB General Purpose Interface Bus ୛ GPRS General Packet Radio Service ୛ GSM Global System for Mobile Communications ୛ IPUI International Portable User Identity ୛ IF Intermediate Frequency ୛ LCD Liquid Crystal Display ୛ LDO Low Drop Output ୛ LED Light Emitting Diode ୛ LGE LG Electronics ୛ OPLL Offset Phase Locked Loop ୛ PAM Power Amplifier Module ୛ PCB Printed Circuit Board ୛ PGA Programmable Gain Amplifier ୛ PLL Phase Locked Loop ୛ PSTN Public Switched Telephone Network ୛ RF Radio Frequency ୛ RLR Receiving Loudness Rating ୛ RMS

Root Mean Square

୛ RTC Real Time Clock ୛ SAW Surface Acoustic Wave ୛ SIM Subscriber Identity Module ୛ SLR Sending Loudness Rating ୛ SRAM Static Random Access Memory ୛ STMR Side Tone Masking Rating ୛ TA Travel Adapter ୛ TDD Time Division Duplex ୛ TDMA Time Division Multiple Access ୛ UART Universal Asynchronous Receiver/Transmitter

- 7 -

LGE Internal Use Only

1. INTRODUCTION

GX500 Operational Description Revision A

୛ VCO Voltage Controlled Oscillator ୛ DCXO Digitally Controled Crystal Oscillator ୛ WAP Wireless Application Protocol

ଝ 8PSK 8 Phase Shift Keying

- 8 -

Only for training and service purposes

2. PERFORMANCE

GX500 Operational Description Revision A

II. General Performance

2.1 H/W Feature

Item Feature Comment

Standard Battery Lithium-Ion Polymer, 15000mAh

AVG TCVR Current 265mA typ @PL5

Standby Current 3.7 mA typ @PP5

Talk time 7 hours (GSM TX Level 7)

Standby time Over 390 hours (Paging Period:5, RSSI: -85dBm)

Charging time Under 3.5 hours

RX Sensitivity EGSM/GSM850:-105dBm˨ ,DCS/PCS:-105dBm˨

TX output power

EGSM/GSM850 : 33dBm (@PL 5) DCS/PCS: 30dBm (@PL 0)

GPRS compatibility Class 12

SIM card type 3V Small

Display

Main 240 u 400 pixels, 3” WQVGA, 262K color

Status Indicator

Send Key, Shortcut Key, Volume Up/Down Key, PWR Key, Camera Key, Lock Key

ANT Built in antenna

EAR Phone Jack 5pin Micro USB

PC Synchronization Yes

Speech coding HR/EFR/FR/AMR

Data and Fax Yes

Vibrator Yes

Buzzer No

Voice Recoding Yes

C-Mic Yes

Receiver Yes

Travel Adapter Yes

Options Bluetooth hands-free kit, Data Kit

2. PERFORMANCE

- 9 -

LGE Internal Use Only

2. PERFORMANCE

GX500 Operational Description Revision A

2.2 Technical specification

Item Description Specification

1

Frequency Band

GSM850

TX: 824 + 0.2 x n MHz

RX: 869 + 0.2 x n MHz ( n = 128 ~ 251 )

EGSM

TX: 890 + 0.2 x (n-1024) MHz RX: 935 + 0.2 x (n-1024) MHz ( n = 975 ~ 1023 /1 ~ 124)

DCS1800

TX: 1710 + ( n-511 ) u 0.2 MHz (n = 512 a 885)

RX: TX + 95 MHz

PCS1900

TX: 1850.2 + ( n-512 ) u 0.2 MHz (n = 512 a 810) RX: TX + 80MHz

2

Phase Error

RMS < 5 degrees Peak < 20 degrees

3

Frequency Error < 0.1ppm

GSM850/EGSM

Level Power Toler. Level Power Toler.

5 33 dBm ±2dB 13 17 dBm ±3dB

6 31 dBm ±3dB 14 15 dBm ±3dB

7 29 dBm ±3dB 15 13 dBm ±3dB

8 27 dBm ±3dB 16 11 dBm ±5dB

9 25 dBm ±3dB 17 9 dBm ±5dB

10 23 dBm ±3dB 18 7 dBm ±5dB

11 21 dBm ±3dB 19 5 dBm ±5dB 12 19 dBm ±3dB

DCS1800/PCS1900

Level Power Toler. Level Power Toler. 0 30 dBm ±2dB 8 14 dBm ±3dB 1 28 dBm ±3dB 9 12 dBm ±4dB 2 26 dBm ±3dB 10 10 dBm ±4dB 3 24 dBm ±3dB 11 8 dBm ±4dB 4 22 dBm ±3dB 12 6 dBm ±4dB 5 20 dBm ±3dB 13 4 dBm ±4dB 6 18 dBm ±3dB 14 2 dBm ±5dB

4

Power Level

7 16 dBm ±3dB 15 0 dBm ±5dB

- 10 -

Only for training and service purposes

2. PERFORMANCE

GX500 Operational Description Revision A

GSM850/EGSM

Offset from Carrier (kHz). Max. dBc

100 +0.5

200 -30

250 -33

400 -60

600 ~ 1,200 -60

1,200 ~ 1,800 -60

1,800 ~ 3,000 -63

3,000 ~ 6,000 -65

6,000 -71

DCS1800/PCS1900

Offset from Carrier (kHz). Max. dBc

100 +0.5

200 -30

250 -33

400 -60

600 ~ 1,200 -60

1,200 ~ 1,800 -60

1,800 ~ 3,000 -65

3,000 ~ 6,000 -65

5

Output RF Spectrum (due to modulation)

6,000 -73

GSM850/EGSM

Offset from Carrier (kHz) Max. (dBm)

400 -19

600 -21

1,200 -21

1,800 -24

DCS1800/PCS1900

Offset from Carrier (kHz) Max. (dBm) 400 -22 600 -24

1,200 -24

6

Output RF Spectrum (due to switching transient)

1,800 -27

- 11 -

LGE Internal Use Only

2. PERFORMANCE

GX500 Operational Description Revision A

7 Spurious Emissions

Conduction, Emission Status Conduction, Emission Status

8

Bit Error Ratio

EGSM/GSM850

BER (Class II) < 2.439% @-102dBm

DCS1800/PCS1900

BER (Class II) < 2.439% @-102dBm

9

Rx Level Report accuracy

r 3 dB

10 SLR

8 r 3 dB

Frequency (Hz) Max.(dB) Min.(dB) 100 -12 / 200 0 / 300 0 -12 1,000 0 -6 2,000 4 -6 3,000 4 -6 3,400 4 -9

11

Sending Response

4,000 0 /

12 RLR 2 r 3 dB

Frequency (Hz) Max.(dB) Min.(dB) 100 -12 /

200 0 / 300 2 -7 500 * -5 1,000 0 -5 3,000 2 -5 3,400 2 -10 4,000 2

13 Receiving Response

* Mean that Adopt a straight line in between 300 Hz and 1,000 Hz to be Max. level in the range.

14 STMR

13 r 5 dB

15 Stability Margin > 6 dB

dB to ARL (dB) Level Ratio (dB)

-35 17.5

-30 22.5

-20 30.7

-10 33.3 0 33.7 7 31.7

16

Distortion

10 25.5

- 12 -

Only for training and service purposes

2. PERFORMANCE

GX500 Operational Description Revision A

17

Side tone Distortion Three stage distortion < 10%

18

<Change> System frequency (26 MHz) tolerance

d 2.5 ppm

19

<Change>32.768KHz tolerance

d 30ppm

20

Power consumption

Standby

- Normalஆd 3.8 mA(@PP5)

21

Talk Time

EGSM/Lvl 7(Battery Capacity 1500mA):450 min

EGSM/Lvl12(Battery Capacity 1500 mA):630min

22

Standby Time

Under conditions, at least 390 hours:

1. Brand new and full 1500mAh battery

2. Full charge, no receive/send and keep GSM in idle mode.

3. Broadcast set off.

4. Signal strength display set at 3 level above.

5. Backlight of phone set off.

23

Ringer Volume

At least 65 dB under below conditions:

1. Ringer set as ringer.

2. Test distance set as 50 cm

24

Charge Current Normal charging : 680 mA

Antenna Bar Number

Power

7

>-92 dBm a

5

-97dBm a –93dBm

4

-100dBm a –98dBm

2

-103dBm a –101dBm

1

-105dBm a –104dBm

0 < –106 dBm

25

Antenna Display

Off No Service

Battery Bar Number Voltage (±0.05V)

3 3.69V~4.2V

2 3.53V~3.69V

1 3.43V~3.53V

26 Battery Indicator

0 3.35V~3.43V

3.53VĻ±0.05V (Call)

27 Low Voltage Warning

3.43VĻ±0.05V (Standby)

- 13 -

LGE Internal Use Only

2. PERFORMANCE

GX500 Operational Description Revision A

28 Forced shut down Voltage

3.3 r 0.05 V

29

Battery Type

Li-Polymer Battery Standard Voltage = 3.7 V Battery full charge voltage = 4.2 V Capacity: 1500mAh

30

Travel Charger

Switching-mode charger Input: 150 a 240 V, 50/60Hz Out put: 5.1, 0.7A

- 14 -

Only for training and service purposes

2. PERFORMANCE

GX500 Operational Description Revision A

* EDGE RF Specification (Option: is not serviced for ”EDGE mode”)

Item Description

Specification

1 RMS EVM

≤9%

2 Peak EVM

≤30%

3 95th Percentile EVM

≤15%

4 Origin Offset Suppression

≥30dB

GSM850/EGSM

Level Power Toler. Level Power Toler. 5 27dBm ±3dB 13 17dBm ±3dB 6 27dBm ±3dB 14 15dBm ±3dB 7 27dBm ±3dB 15 13dBm ±3dB 8 27dBm ±3dB 16 11dBm ±5dB 9 25dBm ±3dB 17 9dBm ±5dB 10 23dBm ±3dB 18 7dBm ±5dB 11 21dBm ±3dB 19 5dBm ±5dB 12 19dBm ±3dB DCS1800, PCS1900 Level Power Toler. Level Power Toler. 0 26/25dBm ±3dB 8 14dBm ±3dB 1 26/25dBm ±3dB 9 12dBm ±4dB 2 26/25dBm ±3dB 10 10dBm ±4dB 3 24dBm ±3dB 11 8dBm ±4dB 4 22dBm ±3dB 12 6dBm ±4dB 5 20dBm ±3dB 13 4dBm ±4dB 6 18dBm ±3dB 14 2dBm ±5dB

5 Power Level

7 16dBm ±3dB 15 0dBm ±5dB

GSM850/EGSM

Offset from carrier(kHz) Max. dBc 100 +0.5 200 -30 250 -33 400 -54 600~<1,200 -60 1,200~<1,800 -60 1,800~<3,000 -63 3,000~<6,000 -65

6

Output RF Spectrum (due to modulation)

6,000 -71

- 15 -

LGE Internal Use Only

2. PERFORMANCE

GX500 Operational Description Revision A

DCS1800, PCS1900

Offset from carrier(kHz) Max. dBc 100 +0.5 200 -30 250 -33 400 -54 600~<1,200 -60 1,200~<1,800 -60 1,800~<3,000 -63 3,000~<6,000 -65 6,000 -71

GSM850/EGSM

Offset from carrier(kHz) Max. dBm 400 -23 600 -26 1,200 -27 1,800 -30 DCS1800, PCS1900 Offset from carrier(kHz) Max. dBm 400 -23 600 -26 1,200 -27

7

Output RF Spectrum (due to switching transient)

1,800 -30

6

- 16 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

III. Technical brief

III-1 Baseband circuit

3.1 GX500 Functional Block diagram

The functional component arrangement is mentioned below diagram.

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3. TECHNICAL BRIEF

- 17 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.2 Dual Baseband Processor (BBP) Introduction

GX500 is composed of dual Baseband Processor. (S-Gold3 & S-Gold Radio)

3.2.1 S-Gold3 Part

Figure3- 2. Top level block diagram of the S-GOLD3

TM

(PMB8877)

- 18 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.2.1.1 General Description

S-GOLD3

TM

is a GSM/EDGE single chip mixed signal Baseband IC containing all analog and digital functionality

of a cellular radio. Additionally S-GOLD3

TM

Provides multimedia extensions such as camera, software MIDI, MP3 sound. It is designed as a single chip solution, integrating the digital and mixed signal portions of the base band in 0.09um, 1.2V technology. The chip will fully support the FR, EFR, HR and AMR-NB vocoding. S-GOLD3TM support multi-slot operation modes HSCSD (up to class 10), GPRS for high speed data application (up to class 12) and EGPRS (up to class 12) without additional external hardware.

3.2.1.2 Block Description

z Processing core

ARM926EJ-S 32 bit processor core for controller functions. The ARM926EJ-S includes an MMU, and the Jazelle Java extension for Java acceleration.

- TEAKLite DSP core

z ARM-Memory

- 32k Byte Boot ROM on the AHB

- 96k Byte SRAM on the AHB, flexibly usable as program or data RAM

- 16k Byte Cache for Program (internal)

- 8k Byte tightly coupled memory for Program(internal)

- 8k Byte Cache for Data(internal)

- 8k Byte tightly coupled memory for Data(internal)

z DSP-Memory

- 104K x 16bit Program ROM

- 8k x 16bit Program RAM

- 60k x 16bit Data ROM

- 37k x 16bit Data RAM

- Incremental Redundancy(IR) Memory of 35904 words of 16bit

z Shared Memory Block

1.5K x 32bit Shared RAM(dual ported) between controller system and TEAKLite.

z Controller Bus system

The processor cores and their peripherals are connected by powerful buses. Multi-layer AHB for connecting the ARM and the other master capable building blocks with the internal and external memories and with the peripheral buses.

z Clock system

The clock system allows widely independent selection of frequencies for the essential parts of the S-GOLD3. Thus power consumption and performance can be optimized for each application.

- 19 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

z Functional Hardware block

- CPU and DSP Timers

- MOVE coprocessor performing motion estimation for video encoding algorithms (H.263, MPEG-4)

- Programmable PLL with additional phase shifters for system clock generation

- GSM Timer Module that off-loads the CPU from radio channel timing

- GMSK / 8-PSK Modulator according to GSM-standard 05.04 (5/2000)

- GMSK Modulator: gauss-filter with B*T=0.3

- EDGE Modulator: 8PSK-modulation with linearized GMSK-Pulse-Filter

- Hardware accelerators for equalizer and channel decoding.

- Incremental Redundancy memory for EDGE class 12 support

- A5/1, A5/2, A5/3 Cipher unit

- GEA1, GEA2, GEA3 Cipher Unit to support GPRS data transmission

- Advanced static and dynamic power management features including TDMA-Frame

synchronous low power mode and enhanced CPU modes(idle and sleep modes)

- Pulse Number Modulation output for Automatic Frequency Correction(AFC)

- Serial RF Control interface: support of direct conversion RF

- A Universal Serial Interface(USIF) enabling asynchronous (UART) of synchronous (SPI) serial data transmission

- 3 USIF with autobaud detection, hardware flow control and integrated

- A dedicated Fas IfDA Controller supporting IrDA’s SIR,MIR and FIR standards

(up to 4Mbps)

- I2C-bus interface (e.g. connection to S/M power)

- A fast display interface supporting serial and parallel interconnection

- An ITU-R BT.656 compatible Camera interface.

- Programmable clock output for a camera

- An multimedia/Secure Digital Card Interface (MMCI/SD:SDIO capable)

3.2.1.3 External Devices connected to memory interface

Table 3-1. Memory interface

Device Name Maker Remark

NAND FLASH H8ACS0SJ0MCP-56M Hynix SDR H8ACS0SJ0MCP-56M Hynix

LCD DPRAM

- 20 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.2.1.4 RF Interface (T_OUT)

S-Gold3 uses this interface to control RF IC and Peripherals. 13 signals are provided switch on/off RF ICs Periodically each TDMA frame.

Table 3-2. RF Interface Spec.

T_OUT Resource Interconnection Description

T_OUT0 TXON_PA PAM Power on T_OUT1 FE2 FEM Control T_OUT2 PA_BAND TX RF band select T_OUT3 FE1 FEM control T_OUT6 PA_MODE PAM Mode select

3.2.1.5 USIF Interface

GX500 have three USIF Drivers as follow :

- USIF1 : Hardware Flow Control / SW upgrade / Calibration

- USIF2 : Not used Rx, Tx and CTS, RTS use BT Interface

- USIF3 : BT Interface

Table 3-3. USIF Interface Spec.

3.2.1.6 ADC channel

BBP ADC block is composed of 10 external ADC channel. This block operates charging process and other related process by reading battery voltage and other analog values.

Table 3-4. S-Gold3 ADC channel usage

ADC channel Resource Interconnection Description

M0 BAT_ID Battery temperature measure M1 RF_TEMP RF block temperature measure M8 VSUPPLY Battery supply voltage measure

Resource Name Remark USIF1

USIF1_TXD SIM1_UART_TX Transmit Data USIF1_RXD SIM1_UART_RX Receive Data USIF1_CTS USB_SE0_VM USB USIF1_RTS USB_DAT_VP USB

USIF2 USIF2_CTS SIM1_BT_CTS BlueTooth

USIF2_RTS SIM1_BT_RTS. BlueTooth USIF3 USIF3_TXD SIM1_BT_TX BT Transmit tx

USIF3_RXD SIM!_BT_RX BT Receive rx

- 21 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.2.1.7 GPIO map

Over a hundred allowable resources, GX500 is using as follows except dedicated to SIM and Memory. GX500 GPIO(General Purpose Input/Output) Map, describing application, I/O state, and enable level, is shown in below table

Table 3-5 S-Gold3 GPIO pin Map

Port function Signal Name Reset Value Description

#Keypad G G G KP_IN0 KEY_ROW0 T/PU G KP_IN1 KEY_ROW1 T/PU G KP_IN4 KEY_ROW4 T/PU G GPIO_03 HSMIC_BIAS_EN T/PU G CC0CC4IO CHG_DET T/PU "Falling Edge" INT on TA CC1CC0IO MMC_DET T/PU "Falling Edge" INT CC1CC4IO ACCEL_INT T/PU For Accel Sensor KP_OUT0 KEY_COL0 T/PU G KP_OUT1 KEY_COL1 T/PU G KP_OUT2 KEY_COL2 T/PU G KP_OUT3 KEY_COL3 T/PU G

#USIF1: Universal Serial IF #USB

G G G

USIF1_RXD_MRST SIM1_UART_RX T/PD G USIF1_TXD_MTSR SIM1_UART_RX T/PD G USIF1_RTS_N USB_DAT_VP T/PU G USIF1_CTS_N USB_SE0_VM T/PD G

G G G G GPIO_15 BT_SEL T/PU G

GPIO_16 USB_SEL T/PD G USIF2_RTS_N SIM1_BT_RTS T/PD G USIF2_CTS_N SIM1_BT_CTS T/PD G

G G G G USIF3_RXD_MRST SIM1_BT_RX T/PD G

USIF3_TXD_MTSR SIM1_BT_TX T/PD G GPIO_21 SGR_PWR_ON T/PD "High" Enable

G G G G MMCI2_CMD MMC_CMD T/PD G

MMCI2_DAT[0] MMC_D0 T/PD MMCI2_CLK MMC_CLK T/PD

G G G G CIF_D0 CIF_D0 T/PD G

CIF_D1 CIF_D1 T/PD G CIF_D2 CIF_D2 T/PD G

- 22 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

CIF_D3 CIF_D3 T/PD G CIF_D4 CIF_D4 T/PD G CIF_D5 CIF_D5 T/PD G CIF_D6 CIF_D6 T/PD G CIF_D7 CIF_D7 T/PD G CIF_PCLK CIF_PCLK

T/PD G

CIF_HSYNC CIF_HSYNC

T/PD G

CIF_VSYNC CIF_VSYNC

T/PD G

CLKOUT2 CIF_MCLK

T/PD G

CIF_PD CIF_PD

T/PD

CIF_RESET

T/PD G #Display_Interface G G G DIF_D0

DIF_D0

T/PD G DIF_D1

DIF_D1

T/PD G DIF_D2

DIF_D2

T/PD G DIF_D3

DIF_D3

T/PD G DIF_D4

DIF_D4

T/PD G DIF_D5

DIF_D5

T/PD G DIF_D6

DIF_D6

T/PD G DIF_D7

DIF_D7

T/PD G GPIO_109 MIC_BIAS_EN T/PD "High" Enable DIF_CS1 DIF_CS T/PU G GPIO_96 TOUCH_EN T/PU G DIF_CD DIF_CD

T/PU G DIF_WR DIF_WR

T/PU G DIF_RD DIF_RD

T/PU G EINT7

USW_INT

T/PD G DIF_VD

DIF_VSYNC

T/PD GPIO_27

DIF_RESET

T/PD G GPIO_101 LCD_BL_CTRL

T/PD G #I2C1 G G G I2C1_SCL SCL T G I2C1_SDA SDA T G PM_INT PM_INT # G #I2C2 G G G I2C2_SCL CODEC_SCL T G I2C2_SDA CODEC_SDA T G #Chip Card (USIM1) G G G

CC_IO SG3_SIM1_IO L G

CC_CLK SG3_SIM1_CLK L G CC_RST SG3_SIM1_RST L G

G G G G GPIO_110 USB_OEn T/PD G EINT3 BT_HOST_WAKEUP

T/PU

- 23 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

G G G G SWIF_TXRX G T/PU Not Used

G G G G MMCI1_CMD

WLAN_CMD

T/PD G

MMCI1_DAT[0]

WLAN_SDIO[0]

T/PD G

MMCI1_CLK

WLAN_CLK

T/PD G G G G G MMCI1_DAT[1]

WLAN_SDIO[1]

T/PD G MMCI1_DAT[2]

WLAN_SDIO[2]

T/PD G MMCI1_DAT[3]

WLAN_SDIO[3]

T/PD G G G G G I2S1_CLK0

SIM1_I2S1_CLK

T/PD G GPIO_112

RPWRON

T/PD G I2S1_RX

SIM1_I2S1_RX

T/PD G I2S1_TX

SIM1_I2S1_TX

T/PD G I2S1_WA0

SIM1_I2S1_WA0

T/PD G G G G G EINT4 _EOC

T/PD End Of Charge GPIO_102 LCD_ID

T/PD G CC0CC1IO _PPR

T/PD USB/TA Charger Insert GPIO_33

SG3_INT

T/PD

To SGR

CC0CC3IO VIB_PWM

T/PD

T0 timer (PWM)

GPIO_103 NA

T/PD G G G G EPN1 EAR_N G G EPP1 EAR_P G G EPPA1 BB_SND_L G G EPREF G G G EPPA2 BB_SND_R G G MICN1 SIM1_MIC_N G G MICP1 SIM1_MIC_P G G MICN2 SIM1_HSMIC_N G G MICP2 SIM1_HSMIC_P G G AUXN1 GND G Connected to GND AUXP1 GND G Connected to GND AUXN2 GND G Connected to GND AUXP2 GND G Connected to GND AUXGND G G G VMICP TP 116 G Not Used VMICN GND G Connected to GND

#I/Q-Signale: Analog Interface, Baseband

G G G

PAOUT1 PA_LEVEL G G BB_I I G G

- 24 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

BB_IX IX G G BB_Q Q G G BB_QX QX G G #Measurement G G G M_0

BAT_ID

G G

M_1 S1_RF_TEMP

G G

M_2

ʳ

G

M_3 TP 101

G Not Used

M_4

ʳ

G Not Used

M_5 ʳ

G G

M_6

ʳ

G G

M_7 TP 105

G Not Used

M_8

VSUPPLY

G G

M_9 ʳ

G G

M_10

ʳ

G G

G G G G

G VREFN G G G G G G

#JTAG G G G TDO S1_TDO T G TDI S1_TDI PU G TMS S1_TMS PU G TCK S1_TCK PD G TRST_n S1_TRSTn PD G RTCK S1_RTCK L G #Debug G G G TRIG_IN S1_TRIG_IN PD/Latched

MON1 2V62_VIO PD/Latched

MON2 G PD/Latched

config pins (MON1, MON2, TRIG_IN) according to memory types => NAND 8-bit

TRACESYNC TRACESYNC L G TRACECLK TRACECLK L G PIPESTAT[2] PIPESTAT2 H G PIPESTAT[1] PIPESTAT1 H G PIPESTAT[0] PIPESTAT0 H G TRACEPKT[0] TRACEPKT0

L G TRACEPKT[1] TRACEPKT1 L G TRACEPKT[2] TRACEPKT2 L G TRACEPKT[3] TRACEPKT3 L G TRACEPKT[4] TRACEPKT4 L G TRACEPKT[5] TRACEPKT5 L G TRACEPKT[6] TRACEPKT6 L G TRACEPKT[7] TRACEPKT7 L G

- 25 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

G G # TP 106 G S1_ADD(31) H G G _RD_S1 H G G S1_DATA(0) T/PD G G S1_DATA(1) T/PD G G S1_DATA(2) T/PD G G S1_DATA(3) T/PD G G S1_DATA(4) T/PD G G S1_DATA(5) T/PD G G S1_DATA(6) T/PD G G S1_DATA(7) T/PD G G S1_DATA(8) T/PD G G S1_DATA(9) T/PD G G S1_DATA(10) T/PD G G S1_DATA(11) T/PD G G S1_DATA(12) T/PD G

G S1_DATA(13) T/PD G

G S1_DATA(14) T/PD G

G S1_DATA(15) T/PD G

G _NAND_CS_S1 H G

G _RAM_CS_S1 H G

G _DPRAM_CS_S1 H G

G G H G G _WR_S1 H G

G S1_ADD(16) L G

G S1_ADD(17) L G

G S1_ADD(18) L G G S1_ADD(19) L G G S1_ADD(20) L G G S1_ADD(21) L G G S1_ADD(22) L G G S1_ADD(23) L G G S1_ADD(24) L G G S1_ADD(25) L G G S1_ADD(26) L G G S1_ADD(27) H G

- 26 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

G S1_ADD(28) H G G S1_ADD(29) H G G S1_ADD(30) H G G G L G G S1_SDCLKI T G G S1_SDCLKO H G G _BC0_S1 H G G _BC1_S1 H G G _BC2_S1 H G G _BC3_S1 H G G S1_ADD(0) T/PD G G S1_ADD(1) T/PD G G S1_ADD(2) T/PD G G S1_ADD(3) T/PD G G S1_ADD(4) T/PD G G S1_ADD(5) T/PD G G S1_ADD(6) T/PD G G S1_ADD(7) T/PD G G S1_ADD(8) T/PD G G S1_ADD(9) T/PD G

G S1_ADD(10) T/PD G

G S1_ADD(11) T/PD G

G S1_ADD(12) T/PD G

G S1_ADD(13) T/PD G

G S1_ADD(14) T/PD G

G S1_ADD(15) T/PD G

G _RAS_S1 H G G _CAS_S1 H G G S1_CKE L G G G G G FCDP_RBn S1_FCDP T/PU G G G G G FWP _DPRAM_SEM_S1 T/PU G G G G G

T_OUT0 TXON_PA

T/PD/Latched

ʳ

GPIO_44 WLAN_WAKEUP

T/PD/Latched

WIFI

T_OUT2 S1_PA_BAND

T/PD/Latched

ʳ

GPIO_46 WLAN_ENABLE

T/PD

WIFI

GPIO_47 ʳ

T/PU

NA

- 27 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

CC1CC1IO SGR_INT

T/PD

from SGR

T_OUT6 PA_MODE

T/PD

ʳ

GPIO_50 SGR_Resetn

T/PD/Latched

SGR RESET 洢歾穞処穳旇 HIGH 決檺檂穮

GPIO_51 UART_SEL

T/PD/Latched

ʳ

GPIO_52 LIN_MOTOR_EN

T/PD/Latched

MOTOR DRIVER IC CONTROL

CC1CC7IO

WLAN_HOST_WAKE UP

T/PU/Latched

WIFI

GPIO_54 SIM_SWITCH

T/PD

ʳ

GPIO_55 _CHG_EN

T/PD

Charging IC Enable & control #SPCU G G G GPIO_117 SIM1_SIM2_SEL

T/PD

ʳ GPIO_118

BT_ENABLE

T/PD

WIFI SPCU_RC_OUT0 VCXO_EN

H

ʳ SPCU_RQ_IN2

RESOURCE_CTRL

T/PD

ʳ #RF Control Unit G G G RF_STR0 RF_EN T/PD G GPIO_57 _DPRAM_BUSY_S1 T/PD/Latched  RF_DATA RF_DA L G RF_CLK RF_CLK L G

#Other Functional Pins: Clocks and control

G G G

AFC AFC T G EINT1 _DPRAM_INT_S1 T/PD 1.8V Power Domain F26M 26MHZ_MCLK # G F32K G # Connected to 32KHz OSC32K G # Connected to 32KHz RESET_n _RESET # G GPIO_59 SIM1_DSR T G RTC_OUT RTC_OUT # TP 110

G G G G CLK32K CLK32K

T/PD

WIFI DSPOUT1 WDOG

T/PD

ʳ GPIO_63 BT_WAKEUP

T/PU

WIFI

- 28 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.2.2 S-Gold Radio Part

Figure 3-3. S-Gold Radio Circuit Diagram of GX500

- 29 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.2.2.1 Block Description

Connectivity

TM offers a variety of connectivity options common in today’s feature phone applications:

• USB 2.0 Full Speed (12 Mbps)

• IrDA Controller Supports Infrared SIR Mode Transceivers

• RS-232 over a 16C550 compliant UART

• MMC/SD Memory Card Interface – Low Voltage Capable – SDIO expandable (using external components)

• Ready to connect to the Infineon’s Bluemoon Family Bluetooth Transceivers – HCI (H5) optimized USIF (Universal Serial Interface) – Dedicated PCM-style digital audio interface (I2S) – Dedicated power supply

• Microcontroller-Like Extension Interface For multimedia companions (for example, complex display/camera modules or graphic accelerators)

• External Memory Interface Supporting: – SDRAM – Cellular RAM – Burst Flash – SRAM – NAND flashes (error correction capability in HW)

• User Interface (Keypad) Supporting up to 74 keys with multiple key-press capability

• SIM Card interface (USIM) ISO 7816 compatible

• Analogue Measurement Unit For various general purpose measurements such as battery voltage, battery, VCXO and environmental temperature, battery technology, transmission power, offset, on-chip temperature, etc.

Security

TM has the following security features:

• Secure Boot and Flash Update

• SHA1 HW acceleration

• Secure Debug

• 128-bit customer defined efuse key

• Anti-intrusion logic.

- 30 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Audio

Besides the telephony voice CODECs supplied by the Firmware running on the TEAKLite® DSP core, the ARM926 core enables running high-quality audio CODECs such as MPEG-1/2 Layer-3 Decode (MP3), AAC+ or AAC++. Audio streaming is supported according to the 3GPP PSS Release 4 standard. The output of audio and voice codecs can be mixed and routed to the integrated Hi-Fi Stereo voiceband supporting CD-Quality. Alternatively, the audio can also be sinked to a mono loudspeaker using the integrated hands-free amplifier.

Video and Imaging

TM allows connecting an external camera module over an ITU-R BT656 compliant interface and a

TM also enables video down-streaming because of its DSP and ARM performances.

Supported "still pictures" multimedia scenarios are:

• View Finding for a Picture Snapshot: Captured frames are transferred from the camera IF to the display IF at up to15 fps (depending on the camera used) in QCIF resolution (depending on the display used). Downscaling and color conversion is done by the camera and display interface logic. Therefore, view finding for a snapshot is possible without burdening the CPU. However, picture rotation and/or overlay are performed by SW if required.

• Shooting: The captured picture, with up to 1.31 MPixel resolution (SXGA 1280 x 1024), is transferred within 1/15 sec to external memory.

1) Then, JPEG compression is done by SW, while the viewfinder is

frozen so that the user can immediately see the snapshot on the display.

• Photo Flash: Under low light conditions usually a photo flash is required. To activate the flash at the right time, a general purpose timer unit (GTPU) can be used that is triggered by the frame synchronization signal (VSYNC) from the camera interface.

• Processing: JPEG thumbnail generation, picture overlay, picture rotation and other picture processing tasks are performed by SW.

• Viewing: A JPEG picture is decoded, down-scaled and format converted by SW and then transferred to the display interface. JPEG thumbnails can also be transferred directly to the display interface after decoding by SW without additional downscaling.

• Storage: JPEG pictures can be stored on an MMC/SD card, a Flash or a PC.

• Sending/Receiving: JPEG thumbnails can be sent/received as MMS (E-GPRS). Full resolution JPEG pictures can be sent/received as e-mail or downloaded from the internet. Supported "video sequence" multimedia scenarios:

• Record Video Sequences: Captured frames in QCIF resolution are transferred to internal memory at 15 fps. H.263 or MPEG-4 encoding is performed on-the-fly by SW with the support of the MOVE coprocessor.

- 31 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

The audio recording is performed on the DSP (GSM AMR CODEC). Multiplexing of audio and video streams is performed by the ARM.

• View Finding during Video Encoding: During video recording the user needs to see what is being recorded. Therefore, the captured frames are not only encoded but also transferred to the display interface. If only every second frame from the camera is used for encoding, viewfinding is possible without burdening the CPU. However, if each frame from the camera has to be encoded, due to low camera frame rate, the YCbCr4:2:2 to YCbCr4:4:4 color conversion and further downscaling is performed by SW. Picture rotation and overlay has to be done in SW in any case.

• Storage: Compressed H.263 or MPEG-4 videos can be stored on an MMC/SD, a Flash or a PC.

• Viewing: De-multiplexing of audio and video streams is performed by the ARM. The H.263 or MPEG-4 decoding is also done by SW on the ARM and then the frames are transferred to the display interface. Audio decoding (GSM-AMR) is done on the DSP. The audio/video synchronization is done by time stamp feedback from the DSP to the ARM.

• Sending/Receiving: H.263 or MPEG-4 videos can be sent/received as MMS (E-GPRS), as e-mail or downloaded from the internet.

Higher Multimedia Performance

TM because it contains a multimedia IC interface module. The camera and display interface

3.2.2.2 External Devices connected to memory interface

Table 3-6 Memory interface

Device Name Maker Remark

NAND FLASH K5D1H12ACC-A075 SAMSUNG 1G(64Mx16) NAND SDRAM K5D1H12ACC-A075 SAMSUNG 512M(16Mx16) SDRAM

- 32 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.2.2.3 RF Interface

Table 3-7 RF Interface Spec.

T_OUT

Resource Interconnection Description

PABS S2_PA_BAND TX RF band select T_OUT6 PA_MODE_2 PAM Mode select FE1 VC1 FEM control FE2 VC2 FEM control PAEN PA_EN PAM Power on VRAMP TX_RAMP APC

3.2.2.4 USART Interface

GX500(SGold Radio Part) has a UART Driver as follow :

- USART1 : Hardware Flow Control / SW upgrade / Calibration

Table 3-8 USART Interface Spec.

USART_0(USART1)

Resource Name Remark

USART0_TXD SIM2_UART_TX Transmit Data USART0_RXD SIM2_UART_RX Receive Data

3.2.2.5 ADC channel

SGold Radio ADC block is composed of 7 external ADC channel. This block operates charging process and other related process by reading battery voltage and other analog values.

ADC channel

Resource Interconnection Description

M0 BAT_ID Battery IC check M1 RF_TEMP RF block temperature measure M8 VSUPPLY Battery supply voltage measure

3.2.2.3 RF Interface

- 33 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.2.2.6 GPIO map

Over a hundred allowable resources, GX500 is using as follows except dedicated to SIM and Memory. GX500 GPIO(General Purpose Input/Output) Map, describing application, I/O state, and enable level, is shown in below table.

Port function Signal Name Reset Value Description

#Keypad G G G KP_IN0 G T/PU Not Used

KP_IN1 G T/PU Not Used KP_IN2 G T/PU Not Used KP_IN3 G T/PU Not Used KP_IN4 G T/PU Not Used KP_IN5 G T/PU Not Used KP_IN6 G T/PU Not Used KP_OUT0 G T/PU Not Used KP_OUT1 G T/PU Deleted KP_OUT2 G T/PU Not Used KP_OUT3 G T/PU Not Used #USART0 G G G USART0_RXD SIM2_UART_RX T/PD G USART0_TXD SIM2_UART_TX T/PU G USART0_RTS_N G T/PU Not Used USART0_CTS_N G T/PU Not Used DSPOUT0 G T/PU Not Used #USB G G G USB_DPLUS SIM2_USB_DP T G USB_DMINUS SIM2_USB_DM T G #CIF:Camera Interface G G G CIF_D0 G T/PD Not Used CIF_D1 G T/PD Not Used CIF_D2 G T/PD Not Used CIF_D3 G T/PD Not Used CIF_D4 G T/PD Not Used CIF_D5 G T/PD Not Used CIF_D6 G T/PD Not Used CIF_D7 G T/PD Not Used CIF_PCLK G T/PD Not Used CIF_HSYNC T/PD Not Used CIF_VSYNC G T/PD Not Used CLKOUT2 G T/PD Not Used CIF_PD_GPIO G T/PD Not Used

- 34 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

CIF_RESET_GPIO G T/PD Not Used #Display_Interface G G G DIF_D0 G T/PD Not Used DIF_D1 G T/PD Not Used DIF_D2 G T/PD Not Used DIF_D3 G T/PD Not Used DIF_D4 G T/PD Not Used DIF_D5 G T/PD Not Used DIF_D6 G T/PD Not Used DIF_D7 G T/PD Not Used DIF_CS1 G T/PU Not Used DIF_CS2 G T/PU Not Used DIF_CD G T/PU Not Used GPIO_41 SIM2_RPWRON T/PU G DIF_RD G T/PU Not Used GPIO_43 SGR_INT T/PD G DIF_VD G T/PD Not Used EINT3 SG3_INT T/PD G #I2C G G G I2C_SCL S2_I2C_SCL T G I2C_SDA S2_I2C_SDA T G PM_INT NONE # G #Chip Card (USIM1) G G G CC_IO SGR_SIM2_IO OD/L G CC_CLK SGR_SIM2_CLK L G

CC_RST SGR_SIM2_RST L G #MMCI: Multimedia Card IF G G G

MMCI_CMD G T/PD Not Used MMCI_DAT0 G T/PD Not Used

MMCI_CLK G T/PD Not Used #USIF: Universal Serial IF G G G

USIF_TXD_MTSR G T/PD Not Used USIF_RXD_MRST G T/PD Not Used USIF_SCLK G T/PD Not Used #I2S1: DAI-PCM G G G I2S1_CLK0 SIM2_I2S1_CLK T/PD G I2S1_RX SIM2_I2S1_RX T/PD G I2S1_TX SIM2_I2S1_TX T/PD G I2S1_WA0 SIM2_I2S1_WA0 T/PD G

#MMCI: SD-Extension

G G G

MMCI_DAT1 _DPRAM_INT_S2 T/PD Power Change MMCI_DAT2 _DPRAM_BUSY_S2 T/PD G

MMCI_DAT3 _DPRAM_SEM_S2 T/PD G

- 35 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

#Voiceband: Analog Interface G G G EP_N SKP_N G G EP_P SPK_P G G HS_N RCV_N G G EP_CM G G Not Used HS_P RCV_P G G MIC1_N SIM2_MIC_N G G MIC1_P SIM2_MIC_P G G MIC2_N SIM2_HSMIC_N G G MIC2_P SIM2_HSMIC_P G G VMIC TP 515 G Not Used #Measurement G G G M0 BAT_ID G G M1 S2_RF_TEMP G G M2 G G G M7 GND G G M8 VBAT G G M9 G G G M10 G G G #Bandgap reference: Analog

Interface

G G G

VREF2 GND G G IREF2 GND G G #JTAG G G G TDO S2_TDO T G TDI S2_TDI PU G TMS S2_TMS PU G TCK S2_TCK PD G TRST_n S2_TRSTn PD G RTCK S2_RTCK L G #Debug G G G TRIG_IN 0 PD/Latched G MON1 1 PD/Latched G MON2 0 PD/Latched G #External Bus Interface (EBU) G G G #FCDP:

Flash Controller DMA Port

G G G

FCDP_RBN S2_FCDP T/PU G

#GSM TDMA Timer: GSM Control G G G

T_OUT1 NONE T/PD/Latched G T_OUT2 NONE T/PD/Latched G T_OUT3 G T/PD G T_OUT4 G T/PU G T_OUT5 G T/PD G

- 36 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

T_OUT6 PA_MODE_2 T/PD G T_OUT7 G T/PD G T_OUT8 G T/PD G #Other Functional Pins: Clocks and

control

G G G

CLKOUT0 G T/PD Not Used F26M NONE # G F32K F32K # G

OSC32K OSC32K # G RESET_N nRESET G G

VDD_FUSE_FS GND G G RTC_OUT NONE # G PMU_SCMODE_OUT NONE G G VCXO_EN NONE H G #Extra I/Os & Interrupt Inputs G G G DSPIN0 G T/PD Not Used DSPIN1 G T/PU Not Used

- 37 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.3 Power management IC

GX500 is composed of dual Power Management Part. (S-Gold3 & S-Gold Radio)

3.3.1 S-Gold3 Part

3.3.1.1 General Description

SM-POWER is a highly integrated Power and Battery Management IC for mobile handsets. It has been specially designed for usage with S-Gold3. Although optimized for usage with the Infineon S-GOLD baseband device it is suitable for the S-GOLDlite and the E-GOLD+ baseband devices as well. It also supports the cellular RF devices like SMARTi-DC, SMARTi-DC+, SMARTi-SD and the Bluemoon Single, Infineon’s single chip solution for Bluetooth. If used with S-GOLD3 it provides all power supply functions (except for the RF PA) for a complete advanced GSM Edge smart phone minimizing external device count.

Block Description

• Highly efficient step-down converter for main digital baseband supply including Core, DSP and memory interface (External Bus Unit).

• Support of S-GOLD standby power-down concept

• Low-drop-out (LDO) regulators for Flash and mobile RAM memory devices

• Voltage independent switching of two SIM cards

• LDO regulators for baseband I/O supply

• LDO regulator for analog mixed-signal section of S-GOLD

• Low-noise LDO regulators for RF devices

• Supply for Bluemoon Single, Infineon’s single chip solution for Bluetooth

• Audio amplifier 8 Ohms for handsfree operation and ringing

• Charge Control for charging Li-Ion/Polymer batteries under software control

• Pre-charge current generator with selectable current level

• RTC regulator with ultra-low quiescent current

• USB interface support for peripheral and mini-host mode

• Backlight LEDs driver with current selection and PWM dimming function

• Two single LED driver outputs for signaling

• Vibrator driver with adjustable voltage

• Fully controlable by software via I2C – Bus

• Temperature and battery voltage sensors

• Interrupt channels for peripherals

• System debug mode

• VQFN 48 package with heat sink and non-protruding leads

• Compatible with the Infineon E-GOLD+ V2 and V3

SM-POWER is a further step on the successful E-Power product line with enhanced and optimized functionality.

SM-POWER features a baseband supply concept with a DC/DC step-down converter cascaded by two linear regulators

–SM-POWER’s DC/DC converter makes up to 40 % reduction of battery current for smart phone functions (e.g. organizer functions, games, MP3 decoding) possible.

- 38 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

– SDBB has high efficiency up to 95% and also a power save mode. – Memory Interface is directly supported by the SDBB – SDBB can also act as main supply voltage for E-GOLD+ or S-GOLDlite baseband devices. – For S-GOLD two linear regulators for DSP and Core are cascaded after the SDBB.

SM-POWER supports the standby power-down concept of S-GOLD by temporarily switching off the linear regulator for the DSP during mobile standby whenever this subsystem is not used. In this phase the ARM controller and most peripherals including parts of the on-chip SRAM are kept powered-up with power being supplied by the other linear regulator.

SM-POWER includes a fully differential audio amplifier able to drive loads down to a nominal value of 8 Ohm for usage in hands-free phones and for ringing

– 450 mW maximum output power

– adjustable gain

– mute switch SM-POWER also integrates a charging function for Li-Ion, Li-Polymer batteries

– click and pop -protection SM-POWER also integrates a charging function for Li-Ion, Li-Polymer batteries – Precharge current source with two current levels – Constant current / constant voltage charging with 3 different termination voltages – Programable charge current limitation for use with different batteries – Freely programable pulse charging to reduce the thermal power dissipation in the constant voltage charging phase – Top-off charge current sensing SM-POWER completes the USB interface of S-GOLD – Regulated voltage for S-GOLD USB interface including reverse current and overvoltage protection – Switch to supply USB pull-up resistor – Mini-host pull down resistor functionality – Charge pump with internal switching capacitor for USB host VBUS supply voltage SM-POWER fully supports LED and Vibra Motor functionality – no external components needed – driver for backlight LEDs adjustable in steps up to 140mA and with soft turn on and off by PWM dimming – two driver outputs for single LEDs for precharge indication and signaling with i.e. change of colour

–driver for Vibra Motor with adjustable voltages, soft startup / shutdown and current limitation

SM-POWER offers several control functions – Power-on Reset Generator with logic state machine – I2C bus interface

– I2C bus configurable mode control logic with ON (push-button or RTC), VCXOEN and LRF3EN

(wake-up by Bluetooth) inputs – Programable interrupt channels to handle peripherals like SIM, MMC and USB – Monitoring of charging functions – Undervoltage Shut-Down – Errorflags (volatile or non-volatile) from many power-supply functions and thermal sensor in order to debug system – Overtemperature Shut-Down – Overtemperature Warning – Support of S-GOLD standby power-down concept – Support of S-GOLD Power-Down Pad Tristate Function

- 39 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Table 3-11. LDO Output Table of SM-Power

LDO Net name

Output Voltage

Output Current Usage

SD1 1V35_Core 1.35V 600mA Core & for LDO SD2 1V8_SD 1.8V 300mA Memory VAUX 2V85_VFM 2.9V 100mA LCD VIO 2V62_VIO 2.62V 100mA Peripherals VSIM 2V9_SIM 2.9V 70mA SIM card VMME 2V8_VMME 2.9V 150mA u-SD VUMTS 1V5_VBT 2.85V 110mA Not used VUSB VUSB 3.1V 40mA Not used VLED VLED 2.9V 10mA Not used VAUDIOa 2V5_VAUDA 2.5V 200mA Stereo headset, Mono earpiece VAUDIOb 2V5_VAUDB 2.5V 50mA Analog parts of S-Gold

VRF1 2V85_VRF 2.85V 150mA

2.85 V supply for SMARTi-PM RF transceiver

VRF2 1V5_VRF 1,53V 100mA

1.5 V supply for SMARTi-PM

RF transceiver VRF3 2V65_VBT 2.7V 150mA Bluetooth VPLL 1V35_VPLL 1.35V 30mA S-GOLD3 PLL VRTC 2V11_RTC 2.11V 4mA Real Time Clock VAFC VAFC 2.65V 5mA Not used VVIB 2V8_VVIB 2.8V 140mA Vibrator

- 40 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Figure 3-4. SM-Power Circuit Diagram of GX500

Figure 3-5 SM-Power Circuit Diagram with charging part

u01102C

2.2u

C203

220

102BF

K7.450

2 R

2V11_RTC

IND

602R

K7.4702R

10u

C204

2V9_VMME

K7.4802R

1V35_CORE

0.1u C205

702Cu1

C208

10u

C209

2.2u

102L

u01

C210

2.2u

C213

22u

0.1u

C214

VBAT

1u

C212

2V85_VRF

1V8_SD2V85_VFM

1V35_VPLL

2V62_VIO

2V5_VAUDA

2.2u

C216

2.2u

C217

2V9_SIM

u01812C

2V8_VVIB

VBAT

212R

K001

u1 122C

222Cu2.2

322Cu2.2

2V65_VBT

VBAT

C224

0.1u 1u

C244

TP202

C226

10u

1u

C227 C228

2.2u

C229

2.2u

C230

2.2u

10u

L202

VBAT

2.2u

C232

TP203

2.2u

C233

102D

VBAT

2V5_VAUDB

202D

1u

C234

FB202

022

U201

4H8H9D6J7H6H5H9G8G7G6G

5 G

4G

3G9F

8 F

7F

6F5F

4 F

3F9E8E7E6E5E4E8D7D6D5D4D6C

L2

L10K2

J10K1

K11

J3

J11H3

H9J2

J1

H10

H1

H11H2

G10G1

G2

G11

F11F1

F10F2

E11E1

E10E2

D1

D11E3

D10

D2

C10C1

C11D3

C2

B1

11L

8A

9J

01K

9L

9K8L8K7L8J

7K6L7J

6K5K5J

5L4L4K3L3K4J1A

4B

11B1L11A

9B

01A

01B

9C9A8C8B6A7C7A5A7B5C6B5B4A4C3A3B3C2A2B

MV_

0ES

PV_TAD

CA

+CA

DNEPSUS

N_EO

BSUV

BSU_DDV

PNI_ONOM

N N I_O

N OM

O NOM_

D DV

M_XEFERV

PTUO_ONOM

ONO

M _SSV

N T UO_

O NOM

FE R

R

FE RV

KNIHS_HSALF

NO_

HSA

L F

AP N

OXT

LLPV

OILLPDDV

OIV

2DSV

3SMUP

2SMUP

1SMUP

TROPTUO

NO_REWOP

GODW

1FFO_NO

2FFO_NO

TUO_FFO_NO

LTRC_ECRUOSER

TNI_C2I

TAD_C2I

KLC_C2I

MWP_1LB

MWP_2LB

MWP_3LB

LRTNC_HC

ECRUOS_HC

CU_EGRAHC

EGRAHC_DDV

1NI_ESNES

2NI_ESNES

FER_DDV

DELV

1DSV

RCV

VPIN

VMIN VMME

D+ VDDMME

D-

VDDRF2

RESET_N VRF2

RESET2_N

SLEEP1_N VRF3

SLEEP2_N VDDRF13_AFC

VAUDIOA VRF1

VDDAUDIOA VVIB

VDDSIMVIB

VDDAUDIOB

VAUDIOB VSIM

VAUX VAFC

VDDAUX

VRTC

SU1_GATE

SU1_GND VDDUMTS

SU1_FB VUMTS

SU1_ISENSE

VDDSD1

VDDSD2 SD1_FB

SD2_FB SD1_FBL

SD2_FBL

1SSV

2SSV

3SSV

4SSV

5SSV

6SSV

7SSV

8SSV

9SSV

01SSV

1 1SSV21SSV

31SSV

41SSV

5 1SSV61SSV

71SSV

81SSV

9 1SSV

02SSV

12SSV

22SSV

32SSV

42SSV

52SSV

62SSV

72SSV

82SSV

92SSV

03SSV

FERV_SSV

1DS_SSV

2DS_SSV

C236 1u

2.2u

C237

1V5_VRF

R216

27K

u01832C

1V8_SD

K0 01

712R

0.1u

C240

2V62_VIO

2V7_VRF

2.2u

C242

K2.2812R

1u

C243

100u

C206

K2.2912R

2.2u

C247

2.2u

C245

642Cu1.0

1V5_VBT

VBAT

VUSB

10u

C241

LRTC_ECRUOSER

USB_DAT_VP

RTC_OUT

TXON_PA

VCXO_EN

USB_OEN

GODW

USB_SE0_VM

SIM1_BT_VCXO_EN

NORWP

2FFO_NO

ON_OFF2

SIM1_USB_DM

SIM1_USB_DP

PMRSTN

TNI_REWOPS

SG3_RPWRON_EN

LCS_1C2I

ADS_1C2I

PMIC

C202 47p

C211 10p

2.2u

C215

100p

C220

1K

R214

C235 27p

CN201

3

2

4

1

VBAT

BAT_ID

BATTERY CONNECTOR

K3.3

2 23

R

057

523R

1uF

C336

123R

IND

2V62_VIO

C337 1uF

V_BUS

smhoK001

323R

2V62_VIO

423R

smhoK001

VBAT

1uF

C338

BQ25040

U310

5

6

74

83

92

101

11

PGND

IN BAT

ISET _PG

VSS1 CHG

LDO VSS2

EN_SETIFULL

2V62_VIO

_EOC

_PPR

RPWRON_EN

_CHG_EN

560 ohm->(910mA)

) %

1 (

)%1(

SINGLE CHARGING IC

820 ohm->(646mA)

2K(10%)->91mA

780 ohm->(680mA)

- 41 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.3.2 S-Gold Radio Part

3.3.2.1 General Description

provides stand-by voltages and supports different low power modes. See Figure 4.

TM PMU Block Diagram

- 42 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

General Features

• Software controlled charging of Lithium-Ion batteries

• Different low power modes for very low power consumption

• Temperature monitoring with built-in over-temperature warning.

Switched Power Supplies

• Two fully integrated step-down converters with PFM low power modes: – 400 mA high efficiency step-down converter (SD1) with 1.5 V output voltage – 300 mA high efficiency step-down converter (SD2) with 1.8 V output voltage

• One step-up converter: – 5.6 V ... 25 V, 120 mA step-up converter (SU1) for the main LCD backlight, keypad backlight and photo

flash.

Linear Low Dropout (LDO) Regulators

• General Purpose LDOs: – 2.9 V, 150 mA, ultra low drop (VAUX) – 2.62 V, 100 mA (VIO) – 1.8 V / 2.9 V, 22 mA, ultra low drop (VSIM) – 1.8 V / 2.9 V, 150 mA, ultra low drop (VMME) – 2.8 V, 140 mA, ultra low drop (VVIB) – 3.1 V, 40 mA, ultra low drop (VUSB)

• Low Noise LDOs: – 2.5V, 220 mA (VAUDIOa) – 2.85 V, 20 mA (VRF1) – 1.5 V, 80 mA (VRF2) – 2.85 V, 150 mA (VRF3)

Low Power LDOs

• 1.5 V, 20 mA (VPLL)

• 2.0 V, 4 mA (VRTC).

LED Control

• 3x PWM modulated control signal

• Current Sink Support for photo flash LED driver

• Support for serial connected LEDs

• Support for Trickle and Indicator LED.

Audio Amplifier

• Battery driven 400 mW differential audio amplifier for driving 8 ohm loudspeaker

• Three gain stages including overdrive for ringing tones

• >90 dB PSRR (4 kHz).

- 43 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Interfaces

• I2C control interface for device configuration

• PMU is configured in software via registers

• Power-on reset generation

• Interrupt (event) line to indicate status change.

Control Unit

• Device ON/OFF switching

• Over-temperature warning

• System start-up state machine

• Under-voltage shut down with defined system behavior

• Independent LDO switch on

• Software and hardware programmable voltages

• System watchdog timer with on-chip oscillator.

10n

C535

2.2u

C521

10n

C514

S2_VBAT

0.1u

C503

2.2u

C504

VAUDIO_2V5VRF3_2V85

100n

C505

VRF3_2V85

VRF2_1V5

VUSB_3V1

VRF1_2V85

C508 10n

VPLL_1V5

2.2u

C509

1u

C510

C511

100n

C512

0.1u

C513 1u

0V2_CTRV

VIO_2V62

220n

C515

615C

u1

1u

C517

C518

1u

VRF3_2V85

S2_VBAT

VRTC_2V0

u1

225C

n001

525C

2.2u

C527

C528 1u

C529 10n

VRF3_2V85

C530 1u

2.2u

C531

8V2_BIVV

C532

1u

VRF3_2V85

C533

100n

V

SD1_1V5

VBT_2V9

C534

0.1u

S2_VBAT

VSIM_2V9

0.1u

C538

0.47u

C539

VMMC_1V8

VRF2_1V5

V

SD2_1V8

VRF3_2V85

VRF1_2V85

C542

100p

81D

81E

91W

91A

1A

4M

8C

5A

7D

4C5D5C

4A

1W

6V

5V4V2V

6U3U2U2T2R2P3N

2N

2M

3C

2B1B2A3B4B

3A

6D

8B

8A

7C

6C

7B

7A

11E

21E

21D

1 1D

0 1C

3E2E1E

1L

6W

7V

4P

6T3

T

5W

4W

4K

1K

2H

3F

9 1V

8 L

8J

0 1M

0 1L

21 L

9M

9L

1 1M

1 1L

1_NIAM_DDV

2_NIA

M _DDV

3 _NIAM_DDV

4_NIAM_DDV

1 _ N

IAM

_SSV

2_NIAM_SSV

3_NIAM_SSV

4_NIA

M _SSV

5 _ N

IAM

_SSV

1_UBE_PDDV

SM_SSV

PE_SSV

1SM_

D NGA

2S

M_DN

GA

XTDDV

OCVDDV

XRTDDV

GI D D DV

SMDDV

OXDDV

LLPDDV

XRDDV

OIDUAV

OIDUA_TABV

OI D UA_SSV

DELV

XUAV

B

IVV

1ODL_TABV

1ODL_SSV

CMMV

BS UV

CMM_BSU_WSB_TABV

OIV

MISV

2ODL_TABV

2ODL_SSV

LLPV

2FRV

LLP2FR_DDV

1FRV

3FRV

31FR_TABV

3ODL_SSV

1FRSSV

2FRSSV

3FRSSV

4FRSSV

5 FRSSV

6FRSSV

7FRSSV

8FRSSV

9FRSSV

01FRSSV

11FRSSV

21FRSSV

31FRSSV

4 1 F RSSV

ECRUOS_HC

ETAG

_ H C

1NI_ESNES

2NI_ESNES

FER_DDV

EGRAHCDDV

1NI_NACS_CU_EGRAHC

SF_ESUF_DDV

1CN

2CN

3CN

CTR_SSV

CTR_DDV

SGR_RPWRON_EN

- 44 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.3.3 Charging

SM-POWER provides together with an external p-channel FET Siliconix Si3455 an external AC-adapter a

complete charge control function for charging of Li-Ion or Li-Ion-Polymer batteries. Either a 1-cell Li-Ion or

Li-Ion-Polymer battery with 4.1, 4.2 or 4.4 Volts may be used.

4.2V~3.75V 3.75V~3.65V 3.65V~3.58V 3.58V~3.30V

Figure 3-8 Battery Block Indication

1. Charging method : CC-CV

2. Charger detect voltage : 4.0 V

3. Charging time : 3h 15m

4. Charging current : 680 mA

5. CV voltage : 4.2 V

6. Cutoff current : 120 mA

7. Full charge indication current (icon stop current) : 120 mA

8. Recharge voltage : 4.16 V

9. Low battery alarm a. Idle : 3.58 V ~ 3.3 V b. Dedicated : 3.58 V ~ 3.3 V

10. Low battery alarm interval

a. Idle : 3 min b. Dedicated : 1 min

11. Switch-off voltage : 3.3 V

12. Charging temperature adc range

a. ~ -5୅ : low charging voltage operation (3.6 V ~ 3.9 V) . b. -5୅ ~ 50୅ : standard charging (up to 4.2 V)

c. 50୅~ : low charging voltage operation (3.6V ~ 3.9V)

- 45 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.4 Power ON/OFF

GX500 Power State : Defined 3cases as follow ඖ Power-ON : Power key detect (SM-Power’s ON port) ඖ Power-ON-charging : Charger detect.

Figure 3-9 Power on application.

- 46 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Input ON is a power-on input for SM-POWER with 2 active high levels (see Figure 6). It might be triggered by a push button or by the RTCOUT output of the S-GOLD device as well. To detect if the push-button is pressed during system operation the logical level at pin ON or its change (if Bit 1 EION in INTCTRL2 is asserted) is recorded in bit LON of the ISF register. If the high level of voltage at pin ON does not reach VIHdet (Vbat-0.8 ~ Vbat-0.3) the above-mentioned bit won’t be set.

To support Remote power on function for factory mass production, applied an analog switch as following figure. As monitoring the RPWRON and Key matrix KP_OUT(2) & KP_IN (0), GX500 system recognize whether remote power on or End-key pushed

Figure 3-10 Remote power on and End-key power on circuit

I ND

402R

I ND

112R

K2

302R

R209

10K

312R

K001

Q201

321

456

2V11_RTC

VA204

KEY_COL2

RPWRON_EN

END_KEY

PWRO

N

RPWRON

KEY_ROW4

Remote Power On

- 47 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.5 Dual SIM & u-SD Interface

3.5.1 Dual SIM Interface

GX500 supports dual SIM mode and each SIM supports 1.8V & 2.9V plug in SIM, SIM interface scheme is shown in (Figure 8). SIM_IO, SIM_CLK, SIM_RST ports are used to communicate with BBP(S-Gold3) and the SIM power supply enabled by PMIC.

SIM Interface

SIM_CLK : SIM card reference clock SIM_RST : SIM card Async /sync reset SIM_IO : SIM card bidirectional reset

Figure 3-11 Dual

SIM Interface

S102

C6

C14

C7

C15

C1

C13C9

C5

C2

C4

C10

C8

C3

C12

C11

C16

RESERVED4

CLK2

RESERVED3

CLK1

RESERVED2

RST2

RESERVED1

RST1

GND1

VCC2 GND2

VCC1

I/O_2

I/O_1

VPP2

VPP1

1u

C109

2V9_SIM

K7. 4

211R

0.1u

C110 C111

22p

K

7. 4

311R

VSIM_2V9

22p

C106

22p

C112

22p

C105

SG3_SIM1_RST

SG3_SIM1_CLK

SGR_SIM2_RST

SGR_SIM2_CLK

SGR_SIM2_IO

SG3_SIM1_IO

DUAL SIM SOCKET

- 48 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.5.2 u-SD Card Interface

The MicroSD Memory Module has eight exposed contacts on one side. The S-Gold3 is connected to the module using a dedicated eight-pin connector

Figure 3-12 Micro SD Memory Card Detection Scheme

Table 3-12 Micro SD memory pad assign.

GX500 Operational Description Revision A

3.5.2 u-SD Card Interface

The MicroSD Memory Module has eight exposed contacts on one side. The S-Gold3 is connected to the module using a dedicated eight-pin connector

Figure 3-12 Micro SD Memory Card Detection Scheme

Table 3-12 Micro SD memory pad assign.

SD mode

Pin No. Name Type Description

1 DAT2 I/O Data bit [2]

2 CD/DAT3 I/O Data bit [3]

3 CMD I/O Command response

4 VDD Power Power supply

5 CLK I Clock

6 VSS Ground Power ground

7 DAT0 I/O Data bit [0]

8 DAT1 I/O Data bit [1]

- 49 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.6 Memory

GX500 is composed of 3 memories. 2 MCPs(NAND+SDR) are connected each BBP(SG3 / SGR). And 1 DPRAM is used to communicate between 2 MCPs.(SG3 and SGR).

Figure 3-13 SGold3 Part Flash memory & SDR RAM MCP circuit diagram

1

01

R

003

3

0.1U

C102

0.1U

C103

1V8_SD

0.1U

C104C107

0.1U 0.1U

C110C113

0.1U

22R107

801R

K0

1

TP102

C116

0.1U

TP103

0.1U

C117

0.1U

C118

TP104

0.1U

C120

C125

0.1U0.1U

C126 C127

0.1U

TP105

R113 100K

TP106

1V8_SD

TP107

1V8_SD

TP108

TP109

0.1U

C133

0.1U

C135

C136

0.1U

C138

0.1U

TP111

0.1U

C143

K001911R

H8ACS0SJ0BCR-46M

U102

01P1P4M3M5G1G3F5E01B2B1B8H7H7J

R10G10

R9F9

R2E10

R1D9

A10C10

A9N10

A2M9

L10

E7K10

F8J9

G6

J8G9

H2F10

G2E9

K1D10

E3C9

G8N9

J2M10

L9

C7K9

C8J10

D7

D8M2

D6P9

E8J1

D5H9

F6C1

F7B9

E6

H4M1

H3P8

F5H10

E4H1

F4D1

G4B8

G3

J4P6

H5C5

H6

J5N5

J6B5

G7

K6C6

K5C3

K7C4

L8B4

K8B7

L7B3

L6B6

L5

L4N8

M7

K2N7

J3P5

F1P4

F2N4

K3P3

D4P2

E2M8

D3N6

E1M6

D2P7

C2M5

L3N3

L2N2

L1N1

K4

A0 IO0 A1 IO1 A2 IO2 A3 IO3 A4 IO4 A5 IO5 A6 IO6 A7 IO7 A8 IO8 A9 IO9 A10 IO10 A11 IO11 A12 IO12 BA0 IO13 BA1 IO14 IO15 DQ0

DQ1 _CE DQ2 _RE DQ3 _WEN DQ4 CLE DQ5 ALE DQ6 _WP DQ7 R_B DQ8

DQ9 VCCN0 DQ10 VCCN1 DQ11

DQ12 VSSN0 DQ13 VSSN1 DQ14

DQ15 VDD0 DQ16 VDD1 DQ17 VDD2 DQ18 VDD3 DQ19 VDD4 DQ20 VDD5 DQ21

DQ22 VSS0 DQ23 VSS1 DQ24 VSS2 DQ25 VSS3 DQ26 VSS4 DQ27 VSS5 DQ28

DQ29 VDDQ0 DQ30 VDDQ1 DQ31 VDDQ2 VDDQ3 _CS VDDQ4 CK VDDQ5 CKE VDDQ6 _WED VDDQ7 _RAS VDDQ8 _CAS VDDQ9 DQM0

DQM1 VSSQ0 DQM2 VSSQ1 DQM3 VSSQ2 VSSQ3 DNU0

VSSQ4 DNU1 VSSQ5 DNU2 VSSQ6 DNU3 VSSQ7 DNU4 VSSQ8 DNU5 VSSQ9 DNU6

1 C N2CN

3CN

4 C N

5 C N

6CN7CN

8CN

9 C N

01CN11

C N

21CN

3 1 C N

41CN

_RAS_S1

S1_ADD[0] S1_ADD[1]

S1_ADD[10]

S1_ADD[5]

S1_ADD[11]

S1_ADD[6]

S1_ADD[12]

S1_ADD[7]

S1_ADD[13]

S1_ADD[8]

S1_ADD[14]

S1_ADD[9]

S1_ADD[15]

S1_ADD[16]

S1_ADD[17]

S1_ADD[18] S1_ADD[19]

S1_ADD[2]

S1_ADD[20] S1_ADD[21] S1_ADD[22] S1_ADD[23] S1_ADD[24]

S1_ADD[3] S1_ADD[4]

S1_DATA[0]

S1_DATA[0] S1_DATA[1]

S1_DATA[1]

S1_DATA[3]

S1_DATA[4]

S1_DATA[5]

S1_DATA[6]

S1_DATA[7]

S1_DATA[2]

S1_ADD[25]

_NAND_CS_S1

_BC0_S1 _BC1_S1

S1_FCDP

_CAS_S1

S1_CKE

_RAM_CS_S1

_RD_S1 _WR_S1

_WR_S1

S1_SDCLKI

S1_ADD[26]

S1_ADD[27] S1_ADD[28] S1_ADD[29] S1_ADD[30]

_BC2_S1 _BC3_S1

S1_DATA[8]

S1_DATA[9]

S1_DATA[11]

S1_DATA[12]

S1_DATA[13]

S1_DATA[14]

S1_DATA[15]

S1_DATA[10]

S1_SDCLKO

2G NAND(LB/128Mx16bit) +1G SDR SDRAM(8Mx4x32bit)

EUSY0347505, Hynix

- 50 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Figure 3-14 SGold Radio Part Flash memory & SDR RAM MCP circuit diagram

U502

9 N

2 N

3J

6H5

H

6G

5G

4G

6F

3F

8E

9B

7B

2B

N8F5

N5D6

B5E6

E5

C5

N6D5

C6

N7

B6G7

H9

D9

L2H8

J2H7

E2J9

K9

L9

N4M9

G2B8

F9C9

C2C8

C7

K2H3

F2G3

D2F7

E7

D8

M2D7

H2F8

G9G8

B4H4

E9

M8N3

K8M4

M7M3

K7L4

M6L3

K6K4

M5K3

K5J4

L8F4

J8E3

L7E4

J7D3

L6D4

J6C3

L5C4

J5B3

01P

9P

2P

1P

01N 1 N

01B

1B

01A

9A

2A

1UND

2UND

3 U N

D

4UND

5UND

6 U N D

7 U N D

8UND

9UND

01 U

N D

11UND

DQ0 IO0

DQ1 IO1

DQ2 IO2

DQ3 IO3

DQ4 IO4

DQ5 IO5

DQ6 IO6

DQ7 IO7

DQ8 IO8

DQ9 IO9

DQ10 IO10

DQ11 IO11

DQ12 IO12

DQ13 IO13

DQ14 IO14

DQ15 IO15

_CS

CLK VDD1

CKE VDD2

_WED VDD3

BA0 VDD4

BA1

_RAS

_CAS VDDQ1

LDQM VDDQ2

UDQM VDDQ3

A0

A1 VSS1

A2 VSS2

A3 VSS3

A4 VSS4

A5

A6

A7 VSSQ1

A8 VSSQ2

A9 VSSQ3

A10

A11

A12 VCC1

VCC2

_CE

ALE VCCQ

CLE

_RE

R__B VSS5

_WE VSS6

_WP VSS7

1 C N

2CN

3CN

4 C N

5 C N

6CN

7CN

8 C N

9 C N

01CN

11CN

2 1 C N

31CN

41CN

K001

325R

VSD2_1V8

22R524

52

5

R

K

001

VSD2_1V8

15p

C543

15p

C544

100R526

725R

K3.3

VSD2_1V8

K3

.3

825R

C545 470n

C546 220n

VSD2_1V8

470n

C547

S2_DATA[15]S2_DATA[15]

S2_DATA[14]S2_DATA[14]

S2_DATA[13]S2_DATA[13]

S2_DATA[12]S2_DATA[12]

S2_DATA[11]S2_DATA[11]

S2_DATA[10]S2_DATA[10]

S2_DATA[9]S2_DATA[9]

S2_DATA[8]S2_DATA[8]

S2_DATA[7]S2_DATA[7]

S2_DATA[6]S2_DATA[6]

S2_DATA[5]S2_DATA[5]

S2_DATA[4]S2_DATA[4]

S2_DATA[3]S2_DATA[3]

S2_DATA[2]S2_DATA[2]

S2_DATA[1]S2_DATA[1]

S2_DATA[0]S2_DATA[0]

_WR_S2

_RD_S2

_BC1_S2

_BC0_S2

_RAS_S2

_RAM_CS_S2

_NAND_CS_S2

_CAS_S2

S2_FCDP

S2_SDCLKI

S2_CKE

S2_ADD[9]

S2_ADD[8]

S2_ADD[7]

S2_ADD[6]

S2_ADD[5]

S2_ADD[4]

S2_ADD[3]

S2_ADD[2]

S2_ADD[17]

S2_ADD[16]

S2_ADD[14]

S2_ADD[13]

S2_ADD[12]

S2_ADD[11]

S2_ADD[10]

S2_ADD[1]

S2_ADD[0]

M_RESET

S2_SDCLKO

1G NAND(LB/64Mx16bit) +512M SDR SDRAM(8Mx4x16bit)

EUSY0389001, SS

- 51 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Figure 3-15 DPRAM for communication Between SGold3 and SGold Radio

R703 47K

R704 47K

R705 47K

VSD2_1V8

47KR706

1V8_SD

TP701 TP702

817C U1

R707 47K

U1

917C

02

7

C U1

CYDM128B16-55BVXI

U702

J6

F6

E8E10

B8E6

F10E5

H7E1

J5C10

F5A10

E2A5

F1D1

H9E3

H8D2

C6F2

J4G1

D4E4

A6K5

D3F3

B7G5

B5H5

C5H4

A4K4

B6K6

D6G4

A3K3

D5J3

B4H3

A2K2

B3J2

C4K1

A1G3

B2H2

B1J1

C3G2

C2F4

C1H1

A7F9

C7G9

D7G10

A8G8

C8G7

A9H10

B9J10

D8J9

C9K10

B10J8

D9K9

E7J7

F7G6

D10K8

E9H6

F8K7

IO0L

IO0R

IO1L IO1R

IO2L IO2R

IO3L IO3R

IO4L IO4R

IO5L IO5R

IO6L IO6R

IO7L IO7R

IO8L IO8R

IO9L IO9R

IO10L IO10R

IO11L IO11R

IO12L IO12R

IO13L IO13R

IO14L IO14R

IO15L IO15R

A0L A0R

A1L A1R

A2L A2R

A3L A3R

A4L A4R

A5L A5R

A6L A6R

A7L A7R

A8L A8R

A9L A9R

A10L A10R

A11L A11R

A12L A12R

R__WL R__WR

_UBL _UBR

_LBL _LBR

_CEL _CER

_OEL _OER

_BUSYL _BUSYR

_SEML _SEMR

_INTL _INTR

0DR0 IRR0

0DR1 IRR1

0DR2 NC1

0DR3 NC2

0DR4 _SFEN

VSS1 M__S

VSS2 VCC1

VSS3 VCC2

VSS4 VDDIOL1

VSS5 VDDIOL2

VSS6 VDDIOR1

VSS7 VDDIOR2

VSS8

VSS9

47KR708

VSD2_1V8

47KR709

47KR711

S1_ADD[0] S1_ADD[1]

S1_ADD[10]

S1_ADD[5]

S1_ADD[11]

S1_ADD[6]

S1_ADD[12]

S1_ADD[7] S1_ADD[8] S1_ADD[9]

S1_ADD[2] S1_ADD[3] S1_ADD[4]

S1_DATA[0] S1_DATA[1]

S1_DATA[3] S1_DATA[4] S1_DATA[5] S1_DATA[6] S1_DATA[7]

S1_DATA[2]

_BC0_S1

_BC1_S1

_DPRAM_CS_S1

_RD_S1

_WR_S1

S1_DATA[8] S1_DATA[9]

S1_DATA[11] S1_DATA[12] S1_DATA[13] S1_DATA[14] S1_DATA[15]

S1_DATA[10]

_DPRAM_SEM_S1

_DPRAM_INT_S1

_DPRAM_BUSY_S1

S2_DATA[15]

S2_DATA[14]

S2_DATA[13]

S2_DATA[12]

S2_DATA[11]

S2_DATA[10]

S2_DATA[9]

S2_DATA[8]

S2_DATA[7]

S2_DATA[6]

S2_DATA[5]

S2_DATA[4]

S2_DATA[3]

S2_DATA[2]

S2_DATA[1]

S2_DATA[0]

_WR_S2

_RD_S2

_BC1_S2 _BC0_S2 _DPRAM_CS_S2

S2_ADD[9]

S2_ADD[8]

S2_ADD[7]

S2_ADD[6]

S2_ADD[5]

S2_ADD[4]

S2_ADD[3]

S2_ADD[2]

S2_ADD[12]

S2_ADD[11]

S2_ADD[10]

S2_ADD[1]

S2_ADD[0]

_DPRAM_BUSY_S2

_DPRAM_INT_S2

EUSY0285602, CYPRESS

128K DUAL PORT STATIC RAM

- 52 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.7 LCD Display

LCD module include:

- Main LCD: 3.0” 240x400 WQVGA, 262K color TFT

- Backlight : 6 piece of white LED

LCD FPC Interface Spec:

Table 3-13. LCD FPC Interface Spec.

- 53 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.8 Keypad Switching & Scanning

The keypad interface is a peripheral which can be used for scanning keypads up to 3 rows (outputs from Port Control Logic) and 2columns (inputs to PCL). The number of rows and columns depend on settings of the PCL.

VA803VA801VA802

SIDEKEY_3P_Contact

CN801

3

2

1

KEY_ROW0

KEY_COL0

KEY_COL1

VOLUME SIDEKEY

VA806 VA807VA805

CN803

4

3

2

1

KEY_ROW1

KEY_COL3

KEY_COL2

CAMERA KEY LOCK KEY

SEND MENU

KEY_ROW1

KEY_COL0

KEY_COL1

VBAT

END

SEND MENU

KEY_ROW1

KEY_COL0

KEY_COL1

END_KEY

GX500 Operational Description Revision A

3.8 Keypad Switching & Scanning

The keypad interface is a peripheral which can be used for scanning keypads up to 3 rows (outputs from Port Control Logic) and 2columns (inputs to PCL). The number of rows and columns depend on settings of the PCL.

Figure 3-16 Key pad part key matrix

- 54 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.9 LCD back-light illumination

The SC654 is a high efficiency charge pump LED driver using Analogic-tech’s proprietary charge pump technology. Performance is optimized for use in single-cell Li-ion battery applications.

Figure 3-17 LCD Back light unit and Flash LED charge pump IC

The LED current magnitude is controlled by the EN/SET pin using the S2Cwire interface. The interface records rising edges of the EN/SET pin and decodes them into 32 individual current level settings. Code 1 is full scale (31mA), and Code 32 is 0.5mA. The modulo 32 interface wraps states back to state 1 after the 32nd clock. The counter can be clocked at speeds up to 1MHz, so intermediate states are not visible. The first rising edge of EN/SET enables the IC and initially sets the output LED current to full scale, the lowest setting equal to 0.5mA. Once the final clock cycle is input for the desired brightness level, the EN/SET pin should be held high to maintain the device output current at the programmed level.

Figure 3-18 control method

VA205

EVLC18S02015

VA203

AAT3369IDT-1-T1U205

19

5

15 14 13

7

6

17

4

3

2

18

98

16

10

11

1

12

D3

OUTCP1

D2 D1

EN_SET

PWM FCAP

OUTCP2

C1C1+

C2C2+

IN

GND

D4

D5

D6

NC

EP

C253

1u

VBAT

10K

R224

47n

C256

0

522R

C255

1u

1uC252

C254 1u

LCD_BL_CTRL

MLED5 MLED4 MLED3

MLED

MLED2 MLED1

MLED6

LCD_PWM

LCD BACKLIGHT LED DRIVER

- 55 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.10 JTAG & ETM interface connector

Figure 3-19 JTAG & ETM(Embedded Trace Module) interface connector

In case of GX500 mass production, the JTAG & ETM interface connector will not be mount on board. That is only for developing and software debugging purpose.( It will not be mounted on mass production PCB)

- 56 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.11 Audio

GX500 Audio signal flow diagram as following diagram.

wti

__^^

OzptXP

wti

____

OzptYP

yj}Gz~p{jo

ozGyj}Gz~p{jo

tpjGz~p{jo

ozGtpjGz~p{jo

stG[`X\X{s

zwr

oz

tpj

ozGtpj

t|pj

zptXzptYzls

wti

__^^

OzptXP

wti

____

OzptYP

yj}Gz~p{jo

ozGyj}Gz~p{jo

tpjGz~p{jo

ozGtpjGz~p{jo

stG[`X\X{s

zwr

oz

tpj

ozGtpj

t|pj

zptXzptYzls

Figure 3-20 Audio signal flow diagram

- 57 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.11.1 Audio amplifier

The LM49151 is a fully integrated audio subsystem designed for portable handheld applications such as cellular phones. The LM49151 combines a 1.25W mono E2S class D amplifier, 125mW Class AB earpiece driver, 42mW/channel stereo ground referenced headphone drivers, volume control, input mixer/multiplexer, and speaker protection into a single device..

Figure 3-21 Audio amplifier

3.11.2. Microphone circuit

Figure 3-22 Microphone circuit

C712

0.1u

VBAT

C702

0.1uF

10u

C701

C704

2.2uF

1uC705

1uC706

1 07L

Hu1.0

207L

H u

1.0

C708

0.1uF

C709

2.2uF

U701

LM49151TL

4E

4D

3D

4C

2A

E2B3

B2

A1

C3

E3

C2

D2C1

A3D1

A4E1

4B

1B

DDV

D D V S L

INM+ LSOUT+

INM- LSOUT-

INL SET

INR

HPL

BYPASS

I2CVDD SDA SCL HPR

DNG

SSVPC

N 1 C

P1C

DN

GP C

27pF

C710C711

27pF

FB701

2V62_VIO

2.2u

C713

smh

oK0

0 1

20 7 R

220nC703

220nC707

SPK_N

SPK_P

RCV_N

RCV_P

HSO_L

HSO_RI2C1_SCL

I2C1_SDA

AMP_IN_L

A

MP_IN_R

AUDIO AMP SUB SYSTEM

VA301

VA302

MIC301

SPU0410HR5H-PB

4

3

2

1

P

G1

G2

O

0

623R

47p

C307

47P

C311

1V8_MIC_BIAS

100NH

L303

403L

HN001

2.2u

C318

47p

C316

MAIN_MIC_P

MAIN_MIC_N

MAIN MIC

- 58 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.12 Charging circuit

The bq25040 has a single power output that charges the battery. A system load can be placed in parallel with the battery. The charge current is programmed using the ISET and EN/SET inputs. The input current limit is programmable to USB100, USB500 or a user programmed current limit up to 1.1A. Additionally, a 4.9V ±3% 50mA LDO is integrated into the IC for supplying low power external circuitry. The single-input interface (EN/SET) is used to select the charge current and to place the bq25040 into Production Test Mode. In Production Test Mode, the bq25040 operates as a linear regulator without a battery connected, where the output is regulated at 4.2V and supplies up to 2.3A to calibrate GSM transceivers.

Figure 3-23 Charging circuit

K3.3

2 23

R

057

523R

1uF

C336

123R

IND

2V62_VIO

C337 1uF

V_BUS

smhoK001

323R

2V62_VIO

423R

smhoK001

VBAT

1uF

C338

BQ25040

U310

5

6

74

83

92

101

11

PGND

IN BAT

ISET _PG

VSS1 CHG

LDO VSS2

EN_SETIFULL

2V62_VIO

_EOC

_PPR

RPWRON_EN

_CHG_EN

560 ohm->(910mA)

) %

1 (

)%1(

SINGLE CHARGING IC

820 ohm->(646mA)

2K(10%)->91mA

780 ohm->(680mA)

- 59 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

8*'*#-6&5005)'.SBEJP

 (FOFSBM%FTDSJQUJPO 

5IF(9EFWJDFQSPWJEFTUIFIJHIFTUMFWFMPGJOUFHSBUJPOGPSBNPCJMFXJSFMFTTTZTUFNXJUI JOUFHSBUFE*&&&CH."$CBTFCBOESBEJP#MVFUPPUIBOE'.SFWFJWFS5IF8:4%/#(9UIBUJT JODMVEFEPG#$.TPMVUJPOJTTVQQPSUFEUISFFLJOETPGGVODUJPOT*UJTUIFPOFBOUFOOBTUSVDUVSFXIJDIJT TVQQPSUFE

PG8-"/#MVFUPPUIJO()[BOE

 'JHVSF8-"/#MVFUPPUI'.3BEJP4ZTUFN"SDIJUFDUVSF

 

- 60 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.13.1 WLAN

The GX500 supports single-band 2.4GHz IEEE802.11b/g standardization. The WLAN module which is consisted of the BCM4325 single chip device provides for the highest level of integration for a mobile or handheld wireless system, with integrated IEEE802.11TM b/g (MAC/baseband/radio). The BCM4325’s integrated CMOS WLAN 2.4GHz power amplifier provide sufficient output power to meet the need of most WLAN devices. The interface between PMB8877 and WLAN module is the standard interfaces SDIO v1.2 (4-bit and 1-bit).

3.13.2 Bluetooth

The GX500 provides the Bluetooth 2.0 specification. The Bluetooth module is the optimal solution for any voice or data application that requires the Bluetooth SIG standard Host Controller Interface (HCI) using a high-speed UART and PCM. The Bluetooth solution has an integrated radio transceiver that has been optimized for 2.4GHz Bluetooth wireless systems. It has been designed to provided low power,low-cost, robust communications for applications operating in the globally available 2.4GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and meets or exceeds the requirements to provide the highest communication link quality of service

3.13.3 FM Radio

This FM is a function of WYSDNBGX6 module, electronically tuned, FM stereo radio with RDS/RBDS demodulator and decoder for low voltage applications, with fully integrated IF selectivity and demodulation. This equipment supports the European Radio Data System (RDS) and the North American Radio Broadcast Data System (RBDS) modulations. The FM unit supports I2C for communications, stereo analog output, as well as I2S and PCM interfaces.

- 61 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Figure 3-25. WI-FI / Bluetooth / FM Radio Circuit Diagram

0.1u

C698

0.1u

C695

4.7u

L699

U601

03

92

82

72

625242

3222120291817

161

31

3215

14

33

3413

3512

3611

3710

389

398

407

6

415

4

42

433

442

45

1

64

7484940515

25

3 5

4 5

4DNG

3 D N G

2DNG

1DNG

B_EKAW

_ TSOH_LW

DXT_TRAU_TB

N_STC_TRAU_TB

N_ST

R _ T RA

U _ TB

DXR

_ TRAU

_ TB

ANT

BT_PCM_CLK

GND5 BT_PCM_OUT

VDD_WL_PA BT_PCM_SYNC

BT_PCM_IN

SDIO_CMD

SDIO_CLK VDD_BT_PA

SDIO_DATA_3

SDIO_DATA_2 32KHZ

SDIO_DATA_1 GND7

SDIO_DATA_0 FM_ANT

WL_RST_N BT_WAKE_B

WL_WAKE_B BT_HOST_WAKE

REG_ON BT_GPIO_3

VBAT_IN BT_GPIO_4

BT_GPIO_7

SR_VLX1

SR_VLX1BB XTALP

XTALN

BB 2X LV _RS

BBTUOV_RS

OIDDV

UP_LATX

DS_OIDDV

21_GID_DDV

21_ANA_DDV

ODL_NIV

MF_

D DV

ADS_TB

LCS

_ TB

LFAV

RFAV

TSR_TB

6DNG

0.1u

C692

C693

2.2uF

OIV_26V2

TP692

TP693

TP695

TP694

TP699

TP698

TP697

TP696

0

R699

1uF

C689

3.3UH L607

10uF

C697

TABV

FB601

1uF

C691

2.2uF

C699

0.1u

C687

4.7uF

C619

FB602

C688 10uF

0.1u

C696

C694

4.7uF

TBV_56V2

OIV_26V2

TP601

CN601

1

1p

C606

C607 DNI

CN602

1

0

C608

1.5nL602

FM_ANT

FM_L

FM_R

XT_TRAU_TB

XR_TRAU_TB

WLAN_SDIO[3]

BT_PCM_CLK

BT_HOST_WAKEUP

CLK32K

QER_KLC_TB

CLK_IN

PUEKAW_TSOH_NALW

WLAN_CMD WLAN_CLK

WLAN_SDIO[0]

WLAN_SDIO[1]

WLAN_SDIO[2]

BT_WAKEUP

WLAN_WAKEUP

BT_PCM_TX

BT_PCM_RX BT_PCM_SYNC

BT_ENABLE

WLAN_ENABLE

STR

_ TRAU_TB

ST C

_ T RAU_TB

REG_ON

close to 17

close to 3

WLAN+BT+FM

606R

K0

01

2V7_VTOUCH

VBAT

C643

1u

C646

1u

C647

100K

R607

VDD_TCXO

U604

9

54

63

72

81

VIN

VOUT1

EN1 VOUT2

P2 GND

P1 EN2

DNGP

VDD_TCXO

1uF

C644

Fu100.0

5 4 6C

X601

26MHZ

TG-5010LH-87N

4 2

3 1

NC

OUT

GNDVCC

BT_CLK_REQ

CLK_IN

TOUCH_EN

26MHz TCXOLDO for TCXO

- 62 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.14 5pin Micro USB Interface connector

Table 3-14. Multi media interface pin assign

GX500 MMI Pin Function Description

1 V_BUS USB V_BUS 2 USB_DM USB_DM 3 USB_DP USB_DP 4 ID Detect ID PIN 5 GND GND

Figure 3-26 5Pin u-USB Connector circuit

103C

Fu100.0

CN301

15

13

11

9

7

5

4

3

2

1

14

12

10

8

6

100n

L306

C333 22pF

10pF

C334

103LF

3

A

1

B5

01

CP

12

MFN

4

3

2 1

N

IT

U

O

1

G

2

G

V_BUS

USW_ID

USW_DP

USW_DM

FM_ANT

1005 coil

5PIN uUSB

- 63 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.15 Triaxial, digital acceleration sensor

General description

The BMA020 is a tri-axial, low-g acceleration sensor IC with digital output for consumer market applications. It allows measurements of acceleration in perpendicular axes as well as absolute temperature measurement. An evaluation circuitry converts the output of a three-channel micromechanical acceleration sensing structure that works according to the differential capacitance principle. Package and interface have been defined to match a multitude of hardware requirements. Since the sensor IC has small footprint and flat package it is attractive for mobile applications. The sensor IC can be programmed to optimize functionality, performance and power consumption in customer specific applications. The BMA150 senses tilt, motion and shock vibration in cell phones, handhelds, computer peripherals, man-machine interfaces, virtual reality features and game controllers. The BMA150 is the LGA package version of the SMB380 triaxial acceleration sensor which is available in a 3mm x 3mm x 0.9mm QFN package.

Axes orientation of the BMA150

Figure 3-27 Axes orientation of the BMA150

Figure 3- 28 Accel sensor circuit

BMA020U203

2 1

11

65

74

83

92

101

NC1 NC2

VDD VDDIO

GND SDI

INT SDO

CSB SCK

1DNGP2D

NGP

22n

C248

TP205

2V85_VFM

2V62_VIO

0.1u

C249

I2C2_SCL

I2C2_SDA

A

CCEL_INT

ACCEL SENSOR

- 64 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

III-2. RF circuit

*RF Block Diagram

Figure 3-29 GX500 RF part Block Diagram

FEM

Mobile Switch

PAM(TQM7M5005H)

ANT

- 65 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.16 General Description

The RF transceiver (PMB 6272 SMARTi-PM) is an integrated single chip, quad-band transceiver for GSM850/GSM900/GSM1800/GSM1900 designed for voice and data transfer applications. The transceiver provides an analog I/Q baseband interface and consists of a direct conversion receiver and a quad-band polar transmitter for GSM and EDGE with integrated PGA functionality. Further on a completely integrated SD-synthesizer with HSCSD and GPRS/EDGE capability, a digitally controlled reference oscillator with three outputs, a fully integrated quad-band RF oscillator and a three wire bus interface with all necessary control circuits complete the transceiver.

Figure 3-30 RF transceiver PMB6272 SMARTi-PM functional block diagram

- 66 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

Figure 3-31 RF PAM TQM7M5005H schematic

3.3p

C421

n51

104L

2.7p

C431

2.7p

C427

TP401

TP402

FRV

_ 5V1

2 7 26BMP

1 04

U

20

19

18

17

16

15

14

13

1221

2211

3201

429

528

627

726

825

924

033

132

231

33

34

35

36

37

38

39

40

41

GND4

GND3

VDDMIX2V8

VDDTX2V8

TX2

TX1

VDDTX1V5

VBIAS

FE2

A 1EF

XA 8V2SAIB

D DV

B X

1X R

XB 1XR

8V2G

I DDDV X2XR

A D

2X R

KL C

2 D N G

5V1GID

D DV X3XR

3SYSF 3X

R

2SYSF X4X

R

OX 4XR

XOX 5V1A

N LDDV

GND1

FSYS1

VDDXO2V8

EN

VDDVCO2V8

VCO_RC

VDDRX1V5

VDDRX2V8

C407

0.1U

F

R

V

_

5

V

1

C408

2.2P4.7P

C409

FRV_5V1

3.3p

C426

0.1U

C411

C412

4.7P

220N

C413

R401

10

R402

820

C416

0.1U

26MHz

DSX321SG-26M

X401

21

34

FRV_58V2

9 14

C

N 7 4

4.7N

C423

FRV_58V2

FRV_

58

V

2

0.1U

C430

F RV_

5 8V2

0.22U

C432

FRV_58V2

2.2P

C435

HN1.5

804L

R405

10

504L

HN51

n7.4

204L

C438

0.1U

C442

I

IX

Q

QX

FE2

FE1

RF_DA

RF_CLK

LBAND_PAM_IN

HBAND_PAM_IN

GSM900 PCS1900GSM850

DCS1800

- 67 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.17 Receiver part

Figure 3-32 Receiver part block diagram

The constant gain direct conversion receiver contains all active circuits for a complete receiver chain for GSM/GPRS/EDGE (see Figure 39). The GSM850/900/DCS1800/ PCS1900 LNAs with balanced inputs are fully integrated. No inter-stage filtering is needed. The orthogonal LO signals are generated by a divider-by-four for GSM850/900 band and a divider-by-two for the DCS1800/PCS1900 band. Down conversion to baseband domain is performed by low/high band quadrature direct down conversion mixers. The baseband chain contains a LNB (low noise buffer), channel filter, output buffer and DC-offset compensation. The 3rd order low pass filter is fully integrated and provides sufficient suppression of blocking signals as well as adjacent channel interferers and avoids anti-aliasing through the baseband ADC. The receive path is fully differential to suppress on-chip interferences. Several gain steps are implemented to cope with the dynamic range of the input signals. Depending on the baseband ADC dynamic range, single- or multiple gain step switching schemes are applicable. Furthermore an automatic DC-offset compensation can be used (depending on the gain setting) to reduce the DC-offset at baseband-output. A programmable gain correction can be applied to correct for front end- and receiver gain tolerances.

- 68 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.18 Transmitter part

The GMSK transmitter supports power class 4 for GSM850 and GSM900 as well as power class 1 for DCS1800 and PCS1900. The digital transmitter architecture is based on a very low power fractional-N Sigma-Delta synthesizer without any external components (see Figure39). The analog I/Q modulation data from the baseband is converted to digital, filtered and transformed to polar coordinates. The phase/frequency signal is further on processed by the Sigma-Delta modulation loop. The output of its associated VCO is divided by four or two, respectively, and connected via an output buffer to the appropriate single ended output pin. This configuration ensures minimum noise level. The 8PSK transmitter supports power class E2 for GSM850 and GSM900 as well as for DCS1800 and PCS1900. The digital transmitter architecture is based on a polar modulation architecture, where the analog modulation data (rectangular I/Q coordinates) is converted to digital data stream and is subsequently transformed to polar coordinates by means of a CORDIC algorithm. The resulting amplitude information is fed into a digital multiplier for power ramping and level control. The ready processed amplitude signal is applied to a DAC followed by a low pass filter which reconstructs the analog amplitude information. The phase signal from the CORDIC is applied to the Sigma-Delta fractional-N modulation loop. The divided output of its associated VCO is fed to a highly linear amplitude modulator, recombining amplitude and phase information. The output of the amplitude modulator is connected to a single ended output RF PGA for digitally setting the wanted transmit power. The PA interface of SMARTi-PM supports direct control of standard dual mode power amplifiers (PA’s) which usually have a power control input VAPC and an optional bias

Figure 3-33 Transmitter part block diagram

control pin VBIAS for efficiency enhancement. In GMSK mode, the PA is in saturated high efficiency mode and is controlled via its VAPC pin directly by the baseband ramping DAC. In this way both up- / down-ramping and output power level are set. In 8PSK mode, the ramping functionality is assured by an on-chip ramping generator, whereas output power is controlled by the PGA’s as described above.

- 69 -

LGE Internal Use Only

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.19 RF synthesizer

The transceiver contains a fractional-N sigma-delta synthesizer for the frequency synthesis in the RX operation mode. For TX operation mode the fractional-N sigma-delta synthesizer is used as Sigma-Delta modulation loop to process the phase/frequency signal. The 26MHz reference signal is provided by the internal crystal oscillator. This frequency serves as comparison frequency of the phase detector and as clock frequency for all digital circuitry.The divider in the feedback path of the synthesizer is carried out as a multi-modulus divider (MMD). The loop filter is fully integrated and the loop bandwidth is about 100 kHz to allow the transfer of the phase modulation. The loop bandwidth is automatically adjusted prior to each slot (OLGA). To overcome the statistical spread of the loop filter element values an automatic loop filter adjustment (ALFA) is performed before each synthesizer startup. The fully integrated quad-band VCO is designed for the four GSM bands (850, 900, 1800, 1900 MHz) and operates at double or four times transmit or receive frequency. To cover the wide frequency range the VCO is automatically aligned by a binary automatic band selection (BABS) before each synthesizer startup.

3.20 DCXO

The SMARTiPM contains a fully integrated 26MHz digitally controlled crystal oscillator (DCXO) with three outputs for the system clock, one output for the GSM baseband and two additional for other subsystems (GPS, Bluetooth, etc.).The only external part of the oscillator is the crystal itself. The frequency tuning is performed along the selected subrange by programming the frequency control word (XO_TUNE) via the three wire bus (“3Wbus”)

Figure 3-34 DCXO Schematic

14

13

21

11

01

3SYSF

2SYS

F

OX

XOX

GND1

26MHz

DSX321SG-26M

X401

21

34

- 70 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.21 Front End Module control

Implemented in the S-Gold3 (FL600) are two outputs which are FE1, FE2 for direct control of front end modules with two logic input pins to select RX and TX mode as well as low and high band operation. FEM need 2V85_VRF supply.

Table 3-15 FEM Control Logic

MODE Tx 1GHz

Tx 2GHz Rx 1GHz Rx 2GHz

VDD ON

ON ON ON

VC1 OFF ON OFF ON VC2 ON ON OFF OFF

Figure 3-35 FEM schematic

18n

C436

104LF

287-AN34PSML

02

9131

11

81

518

417

216

95

4

013

612

1

17

ANT

1XR058MSG

2X R0 58 MS G 1CV

1X R

009

MS G 2CV

2XR009MSG

1XR0081MSG 1DNG

2X R

00 81 MS G

2 D N G

1XR

0 091

MS G

3 D N G

2XR0091MSG 4DNG

5DNG

X T 009

1 _00

8 1MS

G

XT009_058MSG 1CN

2 C N

SW401

43

2

1

ANT COMMON

G3 G4

1p

C440

GND402

C418

100P

C424

100P

C428

0.5p

L404

4.7p

C433

8.2n

2.2n

C405

ANT401

C439

100P

100NH

L407

20pL403

FE2

FE1

GSM900 PCS1900GSM850 DCS1800

LGE Internal Use Only

- 71 -

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.22 Power Amplifier Module

The TQM7M5005H Power Amplifier Module(PAM) is designed in a compact from fact for quad-band cellular handsets comprising GSM850/900,DCS1800,PCS1900,supporting GMSK and linear EDGE modulation. Class12 General Packet Radio Service(GPRS) multi-slot operation is also supported. The module consists of a GSM850/900 PA block and a DCS1800/PCS1900 PA block,impedance matching circuitry for 50ohm input and output impedances, and a Multi-function Power Amplifier Control(MFC) block. A custom CMOS integrated circuit provides the internal MFC function and interface circuitry. Two separate Heterojunction Bipolar Transistor(HBT) PA blocks are fabricated onto InGaP die; one supports the GSM850/900 bands, the other supports the DCS1800 and PCS1900 bands. Both PA blocks share common power supply pins to distribute current. The InGaP die, the silicon die, nad the passive components are mounted on a multi layer laminate substrate. The assembly is encapsulated with plastic overmold. RF input and output ports are internally matched to 50ohm to reduce the number of external components Extremely low leakage current(2.5uA) maximizes handset standby time. Band select(BS) circuitry select GSM transmit frequency band(logic0) and DCS/PCS transmit frequency(logic1). MODE circuitry selects GMSK modulation (logic0) or EDGE modulation(logic1). VRAMP controls the output power for GMSK modulation and provides bias optimization for EDGE modulation depending on the state of MODE control. The integrated multi-function(MFC) provides envelope amplitude control in GMSK mode, reducing sensitivity to input drive, temp, power supply, and process variation. In EDGE mode, the MFC configures the PA for fixed gain, and provides the ability to optimize the PA bias operation at different power levels, This circuitry regulates PA bias conditions, reducing sensitivity to temp., power supply, and process variation. The Enable input signal(pin8) provides a standby state to minimize battery drain..

.Table 3-16 PAM pin description

- 72 -

Only for training and service purposes

3. TECHNICAL BRIEF

GX500 Operational Description Revision A

3.23 PAM Schematic

Figure 3-36 PAM schematic

1u

C414

TABV

100P

C415

12n

C410

C417

22n

R403

10K

47P

C420

C422

0.01U0.01U

C425

C428

0.5p

100P

C429

L404

4.7p

C433

8.2n

27P

C434

100P

R404

C437

33u

OK

L406

3.9p

TQM7M5005H

U402

OK

15 7

8 6

11

14 5

9 4

13 3

10 2

12 1

DCS_PCS_INDCS_PCS_OUT

MODE_SELECTGSM850_900_OUT

BSBY_CAP1

VBATTBY_CAP2

VRAMPGND1

GND2

TX_ENGND3

GSM850_900_INPGND

C441 100P

R407

100P

TXON_PA

S1_PA_BAND

PA_MODE

PA_LEVEL

LBAND_PAM_IN

HBAND_PAM_IN

LGE Internal Use Only

- 73 -

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

IV. Trouble shooting

4.1 Trouble shooting test setup

Equipment setup

Power on all of test equipment

-Connect PIF-UNION JIG or dummy battery to the DUT for power up.

-Connect mobile switch cable between Communication test set and DUT when you need to make a phone call.

-Follow trouble shooting procedure

4. TROUBLE SHOOTING

- 74 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.2 Power on Trouble

Check Points

-Battery Voltage( Need to over 3.35V)

-Power-On Key detection (PWRON signal)

-Outputs of LDOs from PMIC

Figure 4-1. Remote Power On Circuit

Figure 4-2. PMIC Circuit

TP1

I ND

402R

I ND

112R

K2

302R

R209

10K

312R

K001

Q201

321

456

2V11_RTC

VA204

KEY_COL2

RPWRON_EN

END_KEY

PWRO

N

RPWRON

KEY_ROW4

Remote Power On

u01102C

2.2u

C203

220

102BF

K7.450

2 R

2V11_RTC

IND

602R

K7.4702R

10u

C204

2V9_VMME

K7.4802R

1V35_CORE

0.1u C205

702Cu1

C208

10u

C209

2.2u

102L

u01

C210

2.2u

C213

22u

0.1u

C214

VBAT

1u

C212

2V85_VRF

1V8_SD2V85_VFM

1V35_VPLL

2V62_VIO

2V5_VAUDA

2.2u

C216

2.2u

C217

2V9_SIM

u01812C

2V8_VVIB

VBAT

212R

K001

u1 122C

222Cu2.2

322Cu2.2

2V65_VBT

VBAT

C224

0.1u 1u

C244

TP202

C226

10u

1u

C227 C228

2.2u

C229

2.2u

C230

2.2u

10u

L202

VBAT

2.2u

C232

TP203

2.2u

C233

102D

VBAT

2V5_VAUDB

202D

1u

C234

FB202

022

U201

4H8H9D6J7H6H5H9G8G7G6G

5 G

4G

3G9F

8 F

7F

6F5F

4 F

3F9E8E7E6E5E4E8D7D6D5D4D6C

L2

L10K2

J10K1

K11

J3

J11H3

H9J2

J1

H10

H1

H11H2

G10G1

G2

G11

F11F1

F10F2

E11E1

E10E2

D1

D11E3

D10

D2

C10C1

C11D3

C2

B1

11L

8A

9J

01K

9L

9K8L8K7L8J

7K6L7J

6K5K5J

5L4L4K3L3K4J1A

4B

11B1L11A

9B

01A

01B

9C9A8C8B6A7C7A5A7B5C6B5B4A4C3A3B3C2A2B

MV_

0ES

PV_TAD

CA

+CA

DNEPSUS

N_EO

BSUV

BSU_DDV

PNI_ONOM

N N I_O

N OM

O NOM_

D DV

M_XEFERV

PTUO_ONOM

ONO

M _SSV

N T UO_

O NOM

FE R

R

FE RV

KNIHS_HSALF

NO_

HSA

L F

AP N

OXT

LLPV

OILLPDDV

OIV

2DSV

3SMUP

2SMUP

1SMUP

TROPTUO

NO_REWOP

GODW

1FFO_NO

2FFO_NO

TUO_FFO_NO

LTRC_ECRUOSER

TNI_C2I

TAD_C2I

KLC_C2I

MWP_1LB

MWP_2LB

MWP_3LB

LRTNC_HC

ECRUOS_HC

CU_EGRAHC

EGRAHC_DDV

1NI_ESNES

2NI_ESNES

FER_DDV

DELV

1DSV

RCV

VPIN

VMIN VMME

D+ VDDMME

D-

VDDRF2

RESET_N VRF2

RESET2_N

SLEEP1_N VRF3

SLEEP2_N VDDRF13_AFC

VAUDIOA VRF1

VDDAUDIOA VVIB

VDDSIMVIB

VDDAUDIOB

VAUDIOB VSIM

VAUX VAFC

VDDAUX

VRTC

SU1_GATE

SU1_GND VDDUMTS

SU1_FB VUMTS

SU1_ISENSE

VDDSD1

VDDSD2 SD1_FB

SD2_FB SD1_FBL

SD2_FBL

1SSV

2SSV

3SSV

4SSV

5SSV

6SSV

7SSV

8SSV

9SSV

01SSV

1 1SSV21SSV

31SSV

41SSV

5 1SSV61SSV

71SSV

81SSV

9 1SSV

02SSV

12SSV

22SSV

32SSV

42SSV

52SSV

62SSV

72SSV

82SSV

92SSV

03SSV

FERV_SSV

1DS_SSV

2DS_SSV

C236 1u

2.2u

C237

1V5_VRF

R216

27K

u01832C

1V8_SD

K0 01

712R

0.1u

C240

2V62_VIO

2V7_VRF

2.2u

C242

K2.2812R

1u

C243

100u

C206

K2.2912R

2.2u

C247

2.2u

C245

642Cu1.0

1V5_VBT

VBAT

VUSB

10u

C241

LRTC_ECRUOSER

USB_DAT_VP

RTC_OUT

TXON_PA

VCXO_EN

USB_OEN

GODW

USB_SE0_VM

SIM1_BT_VCXO_EN

NORWP

2FFO_NO

ON_OFF2

SIM1_USB_DM

SIM1_USB_DP

PMRSTN

TNI_REWOPS

SG3_RPWRON_EN

LCS_1C2I

ADS_1C2I

PMIC

TP1

- 75 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Table 4-1. PMIC GPIO PIN MAP

LDO Net name

Output Voltage

Output Current

Usage

SD1 1V35_Core 1.35V 600mA Core & for LDO SD2 1V8_SD 1.8V 300mA Memory VAUX 2V85_VFM 2.9V 100mA LCD VIO 2V62_VIO 2.62V 100mA Peripherals VSIM 2V9_SIM 2.9V 70mA SIM card VMME 2V8_VMME 2.9V 150mA u-SD VUMTS 1V5_VBT 2.85V 110mA Not used VUSB VUSB 3.1V 40mA Not used VLED VLED 2.9V 10mA Not used VAUDIOa 2V5_VAUDA 2.5V 200mA Stereo headset, Mono earpiece VAUDIOb 2V5_VAUDB 2.5V 50mA Analog parts of S-Gold

VRF1 2V85_VRF 2.85V 150mA

2.85 V supply for SMARTi-PM RF transceiver

VRF2 1V5_VRF 1,53V 100mA

1.5 V supply for SMARTi-PM

RF transceiver VRF3 2V65_VBT 2.7V 150mA Bluetooth VPLL 1V35_VPLL 1.35V 30mA S-GOLD3 PLL VRTC 2V11_RTC 2.11V 4mA Real Time Clock VAFC VAFC 2.65V 5mA Not used VVIB 2V8_VVIB 2.8V 140mA Vibrator

- 76 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Checking Flow

START

“PWRON” signal

Check 3 pin of U203

Check the all LDO’s

output

Replace main PCB

Check the RPWRON,

replace Q201

Check solder

U201 or replace it

Check solder X401

or replace it

Check 3 pin of X401

Or Check 11 pin of U401

Yes

No

Connect power

supply to the DUT

Vbat = over 3.35V

Q201

TP1

U201

Is the 26MHz

clock From X401

signal correct?

Figure 4-3. RPWRON

GX500 Operational Description Revision A

14pin of U401

Checking Flow

START

“PWRON” signal

Check 3 pin of U203

Check the all LDO’s

output

Replace main PCB

Check the RPWRON,

replace Q201

Check solder

U201 or replace it

Check solder X401

or replace it

Check 3 pin of X401

Or Check 11 pin of U401

Yes

No

Connect power

supply to the DUT

Vbat = over 3.35V

Q201

TP1

X401

U201

1pin of X401

U401

Is the 26MHz

clock From X401

signal correct?

Figure 4-3. RPWRON

Figure 4-5. X-TAL & Transceiver

- 77 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.3 Charging trouble

Check Points

-Connection of TA (check TA voltage 4.8V)

-Charging Current Path component voltage drop

-Battery voltage

1 Charging method : CC-CV 2 Charger detect voltage : 4.8 V 3 Charging time : 3h 15m 4 Charging current : 680 mA 5 CV voltage : 4.2 V 6 Cutoff current : 120 mA 7 Full charge indication current (icon stop current) : 120 mA 8 Recharge voltage : 4.16 V

4.2V~3.75V 3.75V~3.65V 3.65V~3.58V 3.58V~3.30V

TP1

TP2

Figure 4-6. Charging circuit

K3.3

2 23

R

057

523R

1uF

C336

123R

IND

2V62_VIO

C337 1uF

V_BUS

smhoK001

323R

2V62_VIO

423R

smhoK001

VBAT

1uF

C338

BQ25040

U310

5

6

74

83

92

101

11

PGND

IN BAT

ISET _PG

VSS1 CHG

LDO VSS2

EN_SETIFULL

2V62_VIO

_EOC

_PPR

RPWRON_EN

_CHG_EN

560 ohm->(910mA)

) %

1 (

)%1(

SINGLE CHARGING IC

820 ohm->(646mA)

2K(10%)->91mA

780 ohm->(680mA)

- 78 -

TP2TP1

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

START

18pin IO(CN401)

Is soldered ?

Source pin

of U401 = 4.8V ?

Output pin

of U310 =4.2V?

Resolder the CN301

Battery voltage is

over 3.4V?

Charge is operating properly

T

he TA can be

broken

Change other TA

then retest

Check solder

U310 or replace it

Waiting until

battery

Voltage goes up to

3.4V

Yes

No

Battery thermistor

value

is about 10K?

Change the Battery

retest

No

5pin IO(CN301)

U310

TP1: Source pin

U310

TP2: Output pin

Figure 4-7. IO Connector

Figure 4-8. USB SWITCH

5pin IO(CN301)

U310

TP1: Source pin

U310

TP2: Output pin

Figure 4-7. IO Connector

Figure 4-8. USB SWITCH

- 79 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.4 LCD display trouble

Check Points

-LCD assembly status ( LCD FPCB, Connector on FPCB)

-EMI filter soldering

-Connector combination

Figure 4-9. LCD Connector circuit

Charge Pump

Check signal flow via EMI filter

Check the connection LCD FPCB Connector

Figure 4-10. LCD FPCB Connector

Figure 4-11. Charge Pump

DNIR817

TP801

C817 1U

CN804

21 20

22 19

23 18

24 17

25 16

26 15

27 14

28 13

29 12

30 11

31 10

32 9

33 8

34 7

35 6

36 5

37 4

38 3

39 2

40 1

2V85_VFM

VA804 EVLC14S02050

EVRC14S03Q030100R FL803

01

5

6 4

7 3

8 2

9 1

INOUT_A1

INOUT_B1

INOUT_A2INOUT_B2

INOUT_A3INOUT_B3

INOUT_A4INOUT_B4

1G

2

G

FL804

EVRC14S03Q030100R

0

1

5

64

73

82

91

INOUT_A1 INOUT_B1

INOUT_A2 INOUT_B2

INOUT_A3 INOUT_B3

INOUT_A4 INOUT_B4

1G

2G

FL805 EVRC14S03Q030100R

0 1

5

64

73

82

91

INOUT_A1

INOUT_B1

INOUT_A2 INOUT_B2

INOUT_A3 INOUT_B3

INOUT_A4 INOUT_B4

1G2G

LCD_ID DIF_D0 DIF_D1 DIF_D2 DIF_D3

DIF_D4 DIF_D5 DIF_D6 DIF_D7

DIF_CS DIF_RD DIF_WR

MLED5

MLED4

MLED3

DIF_RESET

MLED

MLED2

MLED1

DIF_CD

MLED6

IF_MODE0

IF_MODE1

DIF_VSYNC

LCD_PWM

LCD CONNECTOR

GB042-40S-H10-E3000

ENBY0036001

- 80 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Checking Flow

START

Is LCD

normal?

Signal is normal on

DIF Signal

FL803, FL804, FL805

Assemble

Replace LCD

Check solder and repair

Damaged filter

Yes

No

Check LCD connector

combination then LCD test

with New LCD

FL803, FL804, FL805

Figure 4-11. EMI Filter

- 81 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.5 Camera Trouble

Check Points

-Connectors combination

-FPCB status

Check the Socket combination

Figure 4-13. SUB FPCB Assy

Figure 4-12. Camera

1V8_CAM

2V8_CAM

S101

61

4 1

31

7 1

6

1 2

51

8

75

94

103

112

121

1824

1923

2022

52

6272

8292

0313

2 3

1DNGP

2DNGP

3 DNGP

4 DN

GP

5DNGP

6DNGP

7 DNGP8DN

GP

D0 PCLK D1 VSYNC D2 HSYNC D3 STANDBY D4 SCK D5 SDA D6 RESETB D7 MCLK

1DNGD

2DNGD

3DNGD

1D NGA

2DNGA

DDVD

OIDDV

DDVA

I2C2_SCL I2C2_SDA

CIF_MCLK

CIF_VSYNC

CIF_PCLK

CIF_HSYNC CIF_PD

CIF_D0 CIF_D1 CIF_D2 CIF_D3 CIF_D4 CIF_D5 CIF_D6 CIF_D7

CIF_RESET

- 82 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Checking Flow

START

Replace New Camera

module

Working properly?

Assemble

Yes

No

Check camera socket, 34pin combination then Camera test with equipped camera module

Replace Camera module

Yes

Replace

SUB PCB

- 83 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.6 Receiver & Speaker trouble

Check Points

-Speaker contact

-Audio amp soldering

C712

0.1u

VBAT

C702

0.1uF

10u

C701

C704

2.2uF

1uC705

1uC706

1 07L

Hu1.0

207L

H u

1.0

C708

0.1uF

C709

2.2uF

U701

LM49151TL

4E

4D

3D

4C

2A

E2B3

B2

A1

C3

E3

C2

D2C1

A3D1

A4E1

4B

1B

DDV

D D V S L

INM+ LSOUT+

INM- LSOUT-

INL SET

INR

HPL

BYPASS

I2CVDD SDA SCL HPR

DNG

SSVPC

N 1 C

P1C

DN

GP C

27pF

C710C711

27pF

FB701

2V62_VIO

2.2u

C713

smh

oK0

0 1

20 7 R

220nC703

220nC707

SPK_N

SPK_P

RCV_N

RCV_P

HSO_L

HSO_RI2C1_SCL

I2C1_SDA

AMP_IN_L

A

MP_IN_R

AUDIO AMP SUB SYSTEM

CN701

2

1

C715 47pF

47pF

C716

C717 100pF

VA701

L703 47n

VA702

L704 47n

SPK_N

SPK_P

SPK

U701

C705 C706

L704L703

Figure 4-16. Audio Amp

GX500 Operational Description Revision A

4.6 Receiver & Speaker trouble

Check Points

-Speaker contact

-Audio amp soldering

Figure 4-14. Audio Amp Circuit

- 84 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Figure 4-17. Speaker

Checking Flow

START

Input Signal is

High(C705,C706)

Output Signal is

High(L703,L704)

Replace Audio

Check Speaker ‘s

Contacts are clear.

Yes

Resolder/Replace

Speaker

No

Yes

No

Yes

Assemble

Speaker contact

- 85 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.7 Microphone trouble

Check Points

-Microphone hole

-Mic. Bias & signal line

Figure 4-18. Microphone

Checking Flow

START

Mic bias ON

(2.5V)when

Assemble

Check mic. Bias line

Yes

No

Check microphone sound

hole

Check Signal

Replace microphone

(MIC301)

No

L303 C307 C316

MIC301

- 86 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.8 Vibrator trouble

Check Points

-Vibrator soldering

-IC is working correct

Figure 4-19. LINEAR MOTOR DRIVER Circuit

Figure 4-20. Vibrator Driver

Check the driver IC(U204) of sub boarad

100nL204

100nL203

K0 65

122R

TP206

U204

9

54

63

72

81

EN

V1

SIN VSS

TYPE VCC

OCT V2

DN

GP

VB201

2

1

VA201VA202

R220

10K

2V8_VVIB

1u

C250C251

3.9n

R223

10K

LIN_MOTOR_EN

Rev.B

CLOSE TO CONN

1%

EUSY0200803

LINEAR MOTOR DRIVER

- 87 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Figure 4-21. Vibrator

Checking Flow

Check the vibrator soldering

START

Pin1 of

Check FPCB_LCD or

replace it

No

Check Vibrator sodering

Yes

Pin3 of U204(VIB)

Yes

No

Replace Main Board

Replace Vibrator

Yes

No

Replace U204

Assemble

- 88 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.9 SIM & uSD trouble

SIM Check Points

-Power is working

-Socket soldering

-Proper SIM is used

Figure 4-23. SIM CLK

Pin 13 /

2V9_SIM

Pin 12 /

SIM_CLK

Pin 11 / SIM_IO

Check

soldering

all pin of

socket

Figure 4-22. SUB FPCB Assy

- 89 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Checking Flow

uSD Check Points

-Power is working

-Socket soldering

-Card detect is working

START

16 pins are

Check Proper SIM

Assemble

Resolder pin

Replace SUB Board

Yes

No

Check All of SIM card voltage

GX500 support

2.9V SIM onl

y

TP1

Figure 4-24. uSD

MMC-DETECT PIN

MMC_DETECT SIGNAL

- 90 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Figure 4-25. MMC_DETECT SIGNAL

Checking Flow

Card insert Card Deject

START

T

F socket pins

Check proper

Assemble

Resolder it

(check data line

TP 1 is 2.9V Signal)

Replace Main Board

Yes

No

Check Micro SD card voltage

(2V9_VMME)

- 91 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.10 Touch trouble

Check Points

- Touch driver IC soldering`

- FPCB_Folder Crack

Figure 4-26. Touch driver IC Circuit

Checking Flow

START

Pin6 of U802 is

FPCB_Key is

Resolder U802

Check and Replace

Fpcb_Key

Yes

No

Pin1 of Touch driver IC(U802)

is high(2.9v)?

Yes

No

Check Fpcb_Key and

re

p

lace

Yes

Replace FPCB_Folder and

Assemble

DNI

C821

DNI

C822 DNI

C823

DNI

C824

TP802

2V7_VTOUCH

IN D

81 8

R

0

918R

IND

518R

10U

C819

0.1UF

C820

2V62_VIO

TSC2007IYZGRU802

D3B3

D2B2

D1B1

C3A3

C2A2

C1A1

AUX

SDA

VDD_REF A1

X+ X-

PENIRQ- SCL

A0 GND

Y+ Y-

2V62_VIO

IND

318R

I2C2_SCL

I2C2_SD

A

TS_XP TS_XM

TS_YP TS_YM

TS_IRQ

TOUCH IC

- 92 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.11 LCD LED trouble

Check Points

-Signal path is connected well

Figure 4-27. LCD BACKLIGHT LED DRIVER Circuit

Checking Flow

START

Check TP1 is

hl

g

h ?

Check TP2 is

hi

g

h?

Assemble

Check R224 and

Replace

Check and Replace

charge pump.

(U205)

Yes

No

Check All of LEDs solder

Yes

TP1

TP2

VA205

EVLC18S02015

VA203

AAT3369IDT-1-T1U205

19

5

15 14 13

7

6

17

4

3

2

18

98

16

10

11

1

12

D3

OUTCP1

D2 D1

EN_SET

PWM FCAP

OUTCP2

C1C1+

C2C2+

IN

GND

D4

D5

D6

NC

EP

C253

1u

VBAT

10K

R224

47n

C256

0

522R

C255

1u

1uC252

C254 1u

LCD_BL_CTRL

MLED5 MLED4 MLED3

MLED

MLED2 MLED1

MLED6

LCD_PWM

LCD BACKLIGHT LED DRIVER

TP2

- 93 -

TP1

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.12 Trouble shooting of Receiver part

Checking Flow

START

Check point ྙ

Check point ྚ

Setup Test Equipment

Cell Power : –74dBm

EGSM CH30

DCS CH699

Re-Download S/W & CAL

Check point ྜ

Check point ྛ

Mobile SW & FEM

Fi

g

ure 4-28. Main PCB SIM1

Figure 4-29. Main PCB SIM2

ྙ

ྚ

ྛ

ྜ

ྙ

ྚ

ྛ

ྜ

Checkin

g

Points

- 94 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

Figure 4-30. DCXO (SIM1)

Waveform

Figure 4-33. DCXO Waveform

Replace

X406/X502

N0

X-T

AL Circuit is OK.

See next page to check

PLL Circuit.

Is the waveform

of TP similar to Fig.7?

TP1(C406) : 26MHz

X401

X502

Fi

g

ure 4-31. DCXO (SIM2)

TP1

TP1 (C406)

Fi

g

ure 4-32. DCXO Cicuit(SIM1)

*SIM2-> Transceiver is embeded in BB chi

p

.

4.12.1 Checking DCXO Circuit

Checking Points

DCXO Circuit Diagram

Checking Flow

P 0 001

604C

20

19

18

17

16

15

14

13

1221

2211

3201

3SYSF 3X

R

2SYS

F X

4X R

OX

4X R

XOX 5V1A

N LD

DV

GND1

FSYS1

VDDXO2V8

EN

VDDVCO2V8

VCO_RC

VDDRX1V5

VDDRX2V8

R402

820

26MHz

DSX321SG-26M

X401

21

34

9 14

C

N74

0.1U

26MHZ_MCLK

RF_EN

TP1

- 95 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.12.2 Checking PLL Control signals

Check U401

Yes

No

Yes

Control Signal is OK.

See next page to check

Mobile SW & FEM.

No

Yes

Checking Flow

Check U401

Figure 4-34. Transceiver

Waveform

Figure 4-36. PLL Control Waveform

EN Si

g

nal(TP1) is OK ?

DA

(

Data,TP2) is Normal ?

CLK

(

Clock,TP3) is Normal ?

RF_EN(TP1)

RF_CLK(TP2)

RF_DATA(TP3)

TP3 (RF_CLK)

TP1 (RF_EN)

TP2 (RF_DATA)

TP2

TP3

TP1

*SIM2-> Transceiver is embeded in BB chip.

Checking Points

RF Transceiver Circuit Diagram

Figure 4-35. Transceiver Circuit

TP401

TP402

P 0 0 0 1

6 0 4C

2 72

6BMP

1 04

U

20

19

18

17

16

15

14

13

1221

2211

3201

429

52

8

627

726

825

924

033

132

231

33

34

35

36

37

38

39

40

41

GND4

GND3

VDDMIX2V8

VDDTX2V8

TX2

TX1

VDDTX1V5

VBIAS

FE2

A 1EF

XA

8V 2SA

IB DDV

B X

1X R

XB

1X R

8V2G

I DD

DV X

2XR

A D

2XR

K L C 2D

N G

5V 1

GID

DDV

X3XR

3SYS

F 3X

R

2SYSF X4X

R

OX 4XRXOX 5V1A

N

LDDV

GND1

FSYS1

VDDXO2V8

EN

VDDVCO2V8

VCO_RC

VDDRX1V5

VDDRX2V8

0.1U

C411

R402

820

C416

0.1U

26MHz

DSX321SG-26M

X401

21

34

9 14

C

N 7 4

0.1U

C430

0.1U

C442

I

IX

Q

QX

26MHZ_MCLK

RF_DA

RF_CLK

RF_EN

TP1

TP3

TP2

- 96 -

Only for training and service purposes

GX500 Operational Description Revision A

4.12.3 Checking Mobile SW & FEM

SIM2 Circuit

Figure 4-37 Mobile SW & FEM Circuit

EGSM/GSM850 DCS/PCS FE1 OFF ON FE2 OFF OFF

SIM2 Circuit

TP2

TP3

TP4

SIM2

TP5~8

Table 4-2. FEM RX Control Logic

SIM2 Circuit

TP2

TP3

TP4

Figure 4-38. Mobile SW & FEM

SIM1

SIM2

TP5~8

Figure 4-37 Mobile SW & FEM Circuit

SW602

43

2

1

ANT COMMON

G3 G4

100NH

L601

1 LF

2 8 7

-A N

34PSM

L

029131

1 1

81518417

216

95

4

013

612

1

17

ANT

1X R0 5

8MS

G

2X

R0 5

8MS

G

1 CV

1XR

0 09MSG

2 CV

2XR

0 09MSG

1XR

0 0 81MSG

1 D N G

2XR0081MSG 2DNG

1XR0091MSG 3DNG

2XR

0 091MSG 4D

N G

5 D N G

X T 009

1 _00

8 1MS

G

XT0

0 9_

0 58MSG 1CN

2 CN

P001

6

1

6C

0.75p

C641

C636 47P47P

C637

VC2

VC1

5pL611

SW602

43

2

1

ANT COMMON

G3 G4

100NH

L601

1L F

28 7

-AN34PSML

02

913

1

11

81

518

417

2 16

95

4

013

6 12

1

17

ANT

1X R

058

MS

G

2X R

05 8MS

G 1CV

1X R0 0

9MS

G

2 CV

2X R

0 0 9MS

G

1X R0 0

8 1MS

G

1 D N G

2XR

0 0 81MSG

2D N

G

1XR

0 09

1MS

G 3D

N G

2XR009

1MS

G 4DNG

5D N

G

X T 0 0 91

_ 0 08

1MS

G

X T 0 0 9 _0

5 8MS

G 1CN

2CN

P0

0

1

6

1

6

C

0.75p

C641

C636 47P47P

C637

18n

C632

VC2

VC1

L

GSM 1800 / 1900_ RX

GSM 1800 / 1900_ TX

VC2 (FE2)

L

GSM850 / 900_RX

L

VC1 (FE1)

L

GSM850 / 900_TX

H

TP1 TP2

4. TROUBLE SHOOTING

TP3 TP4

SIM1 Circult

SIM2 Circult

- 97 -

LGE Internal Use Only

4. TROUBLE SHOOTING

Check TP1 of (SW401/SW602)

with RF Cable and TP2 of (C418/C616

)

TP1 Signal same as

T

P2?

Replace Mobile SW

(SW401/SW602)

Yes

No

Yes

Mobile SW & FEM is OK.

Check Antenna.

Replace U101 / U503

Control Signal is

O

K

?

No

Yes

Check TP3, TP4 of FL401/FL1 ?

Replace

FEM (FL401/FL1)

T

P5~8 Signal is

No

Yes

Checking Flow

Figure 4-39 Mobile SW (R403)

Figure 4-40 FEM Control Signals

FE1

FE2

- 98 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.12.4 Checking RX I/Q Signals

Figure 4-42. RX I/Q

Figure 4-43. RX I/Q Waveform

I

Q

RX

TP402(I

)

TP2(QX

TP1(IX)

TP401

(Q)

U401G

*SIM2-> Transceiver is embeded in BB chip.

Check RX I/Q signals TP

Signals are

Normal?

Replace Transceiver

PMB6272(U401)

Yes

No

RX Part is OK.

Check Base Band Circuit

or

-

Checking Flow

TP402(I)

TP1

(IX)

TP2

(Q

X

TP401

(Q)

Figure 4-41. RX I/Q Circuit

Checking Points

3.3p

C421

n51

104L

2.7p

C431

2.7p

C427

TP401

TP402

FRV

_ 5V1

2 7 26BMP

1 04

U

20

19

18

17

16

15

14

13

1221

2211

3201

429

528

627

726

825

924

033

132

231

33

34

35

36

37

38

39

40

41

GND4

GND3

VDDMIX2V8

VDDTX2V8

TX2

TX1

VDDTX1V5

VBIAS

FE2

A 1EF

XA 8V2SAIB

D DV

B X

1X R

XB 1XR

8V2G

I DDDV X2XR

A D

2X R

KL C

2 D N G

5V1GID

D DV X3XR

3SYSF 3X

R

2SYSF X4X

R

OX 4XR

XOX 5V1A

N LDDV

GND1

FSYS1

VDDXO2V8

EN

VDDVCO2V8

VCO_RC

VDDRX1V5

VDDRX2V8

C408

2.2P4.7P

C409

3.3p

C426

0.1U

C411

C412

4.7P

R402

820

C416

0.1U

26MHz

DSX321SG-26M

X401

21

34

9 14

C

N 7 4

4.7N

C423

FRV_58V2

FRV_

58

V

2

0.1U

C430

FRV_58V2

2.2P

C435

HN1.5

804L

504L

HN51

n7.4

204L

0.1U

C442

I

IX

Q

QX

RF_DA

RF_CLK

GSM900 PCS1900GSM850

DCS1800

TP2(QX)TP1(IX)

TP401(Q)

TP402(I)

- 99 -

LGE Internal Use Only

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.13 Trouble shooting of Transmitter part

Checking Points

Check point ྙ

Check point ྚ

Setup Test Equipment

Cell Power : –74dBm

EGSM CH30

Check point ྛ

Re-Download S/W & RF CAL

Check point ྜ

Check point ྜྷ

Check ྞ

FEM & Mobile

-

Checking Points

Figure 4-45. Main PCB SIM2

ྙ

ྚ

ྛ

ྜ

ྙ

ྚ

ྜྷ

ྞ

ྜྷ

ྞ

- 100 -

Only for training and service purposes

4. TROUBLE SHOOTING

GX500 Operational Description Revision A

4.13.1 Checking VCTCXO Circuit

See RX Part “1. Checking DCXO Circuit”

4.13.2 Checking PLL Control Signal

See RX Part “2. Checking PLL Control Signal”

- 101 -

LGE Internal Use Only

LG GX500 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual