LG 72LM9500 Schematic

Internal Use Only

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LED LCD TV

SERVICE MANUAL

CHASSIS : LT23J

MODEL : 72LM9500 72LM9500-DA

CAUTION

BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL67443404 (1206-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ....................................................................................... 4

ADJUSTMENT INSTRUCTION ................................................................ 9

TROUBLE SHOOTING ............................................................................ 19

EXPLODED VIEW .................................................................................. 26

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks.

It will also protect the receiver and it's components from being damaged by accidental shorts of th e cir cuitry that may be inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exp ose d metallic par t. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This spec sheet is applied to the LCD TV used LT23J chassis.

2. Test condition

Each part is tested as below without special notice.

1) Temperature : 25 ºC ± 5 ºC (77 ºF ± 9 ºF), CST : 40 ºC±5 ºC

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage : S ta ndard i nput voltage (100~240V@ 50/60Hz)

4) Specification and performance of each parts are followed

ea ch drawing and s pe cificatio n b y p art number in accordance with BOM.

5) The receiver must be operated for about 5 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

.

Only for training and service purposes

- 4 -

4. General Specification

No Item Specication Remark

1. Display Screen Device 54.64” Color Active Matrix LCD Module

46.96” Color Active Matrix LCD Module

72.07” Color Active Matrix LCD Module

2. Aspect Ratio 16:9 All

3. LCD Module 54.64” WUXGA diagonal LCD

46.96” WUXGA diagonal LCD

72.07” WUXGA diagonal LCD

4. Operating Environment TFT 1) Temp. : 0 ~ 40 deg

2) Humidity : 0 ~ 85%

ALEF Temp. : 0 ~ 50 deg

Humidity : 20 ~ 90%

5. Storage Environment TFT Temp. : -20 ~ 60 deg Humidity : 10 ~ 90%

ALEF Temp. : -20 ~ 60 deg

Humidity : 10 ~ 90%

6. Input Voltage AC100 ~ 240V, 50/60Hz

7. Power Consumption(Max) =

LCD(Module) + Backlight(LED)

8. LCD Module Size Maker Inch (H) × (V) × (D)

Pixel Pitch Maker Inch (H) × (V) × (D)

T480 54.64” 190 W LC550DUT-SEF1(55LM9600-DA)

46.96” 81 W LC470DUT-SEF1(47LM9600-DA)

72.07” 385 W LC720DUC-SDF1(72LM9500-DA)

T240 46.96” 129 W LC470EUH-KEF1(47LM8600-DA)

LGD 54.64” 1217 x 689.9 x 1.5 LC550DUT-SEF1(55LM9600-DA)

46.96” 1046.68 x 594.02 x1.5 LC470DUT-SEF1(47LM9600-DA)

46.96” 1059.5 x 616.2 x 20.7 LC470EUH-KEF1(47LM8600-DA)

72.07” 1666.0 x 968.0 x 54.0

LGD 47” 0.5415 x 0.5415 LC470DUT-SEF1(47LM9600-DA)

55” 0.630 x 0.630

47” 0.5415 x 0.5415

LC550DUT-SEF1(55LM9600-DA) LC470DUT-SEF1(47LM9600-DA) LC470EUH-KEF1(47LM8600-DA) LC720DUC-SDF1(72LM9500-DA)

LGE SPEC

LC720DUC-SDF1(72LM9500-DA)

LC550DUT-SEF1(55LM9600) ALEF 3D-PG T480

LC470EUH-KEF1(47LM8600-DA)

Back Light LGD 54.64” ALEF

Only for training and service purposes

72.07” 0.831 x 0.831

46.96” ALEF LC470DUT-SEF1(47LM9600-DA)

46.96” EDG-LED LC470EUH-KEF1(47LM8600-DA)

72.07” EDG-LED LC720DUC-SDF1(72LM9500-DA)

- 5 -

LC720DUC-SDF1(72LM9500-DA)

LC550DUT-SEF1(55LM9600) ALEF 3D-PG T480

5. External Input Support Format

5.1. Component(Y, Pb, Pr)

No. Resolution H-freq(kHz) V-freq(Hz) Remark

1. 720*480i 15.73 59.94 13.500 SDTV, DVD 480I(525I)

2 720*480i 15.73 60.00 13.514 SDTV, DVD 480I(525I)

3. 720*576i 15.625 50.00 13.500 SDTV, DVD 576I(625I) 50Hz

4 720*480p 31.47 59.94 27.000 SDTV 480P

5 720*480p 31.50 60.00 27.027 SDTV 480P

6 720*576p 31.25 50.00 27.000 SDTV 576P 50Hz

7 1280*720 44.96 59.94 74.176 HDTV 720P

8 1280*720 45.00 60.00 74.250 HDTV 720P

9 1280*720 37.50 50.00 74.25 HDTV 720P 50Hz

10 1920*1080 28.125 50.00 74.250 HDTV 1080I 50Hz,

11 1920*1080 33.72 59.94 74.176 HDTV 1080I

12 1920*1080 33.75 60.00 74.25 HDTV 1080I

13 1920*1080 26.97 23.976 63.296 HDTV 1080P

14 1920*1080 27.00 24.000 63.36 HDTV 1080P

15 1920*1080 33.71 29.97 79.120 HDTV 1080P

16 1920*1080 33.75 30.00 79.20 HDTV 1080P

17 1920*1080 56.25 50 148.5 HDTV 1080P

18 1920*1080 67.432 59.94 148.350 HDTV 1080P

19 1920*1080 67.5 60.00 148.5 HDTV 1080P

5.2. RGB Input ( PC )

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock (MHz) Proposed Remark

1 640*350 31.468 70.09 25.174 EGA For only DOS mode

2 720*400 31.469 70.08 28.321 DOS For only DOS mode

3

640*480 31.469 59.94 25.17 VESA(VGA)

4 800*600 37.879 60.31 40.00 VESA(SVGA)

5. 1024*768 48.363 60.00 65.00 VESA(XGA)

6. 1152*864 54.348 60.053 80.00 VESA(XGA Plus)

7. 1360*768 47.712 60.015 85.50 VESA(WXGA) FHD Only

8. 1920*1080 67.5 60.00 148.5 VESA(WUXGA)

Input 848*480 60Hz, 852*480 60Hz => 640*480 60Hz Display

Only for training and service purposes

- 6 -

5.3. HDMI input

5.3.1. DTV mode

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remarks

1 720*480 15.73 59.94 13.500 SDTV, DVD 480I(525I)

Spec. out but display2 720*480 15.75 60.00 13.514 SDTV, DVD 480I(525I)

3 720*576 15.625 50.00 13.500 SDTV, DVD 576I(625I) 50Hz

4 720*480 31.47 59.94 27 SDTV 480P

5 720*480 31.5 60.00 27.027 SDTV 480P

6 720*576 31.25 50.00 27 SDTV 576P

7 1280*720 44.96 59.94 74.176 HDTV 720P

8 1280*720 45 60.00 74.25 HDTV 720P

9 1280*720 37.5 50.00 74.25 HDTV 720P

10 1920*1080 28.125 50.00 74.25 HDTV 1080I

11 1920*1080 33.72 59.94 74.176 HDTV 1080I

12 1920*1080 33.75 60.00 74.25 HDTV 1080I

13 1920*1080 26.97 23.976 63.296 HDTV 1080P

14 1920*1080 27.00 24.000 63.36 HDTV 1080P

15 1920*1080 33.71 29.97 79.120 HDTV 1080P

16 1920*1080 33.75 30.00 79.20 HDTV 1080P

17 1920*1080 56.25 50.00 148.5 HDTV 1080P

18 1920*1080 67.432 59.94 148.350 HDTV 1080P

19 1920*1080 67.5 60.00 148.5 HDTV 1080P

5.3.2. PC mode

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remarks

1 640*350 31.468 70.09 25.17 EGA

2 720*400 31.469 70.08 28.32 DOS

3 640*480 31.469 59.94 25.17 VESA(VGA)

4 800*600 37.879 60.31 40 VESA(SVGA)

5 1024*768 48.363 60.00 65 VESA(XGA)

6 1152*864 54.348 60.053 80.00 VESA

7 1280*1024 63.981 60.020 108.00 SXGA

8 1360*768 47.712 60.015 84.75 VESA(WXGA)

9

1920*1080 67.5 60.00 148.5 WUXGA

Only for training and service purposes

- 7 -

5.3.3. 3D mode

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks

*** HDMI 1.4

1 1280*720 75 50 148.5 HDTV 720P Frame packing

2 1280*720 37.5 50 74.25 HDTV 720P Side by Side(half), Top and Bottom

3. 1280*720 89.9 59.94 148.35 HDTV 720P Frame packing

90 60 148.5

4 1280*720 45 60 74.25 HDTV 720P Side by Side(half), Top and Bottom

5 1920*1080 53.95 23.95 148.35 HDTV 1080P Frame packing

54 24 148.5

6 1920*1080 27 24 74.25 HDTV 108 0P Side by Side(half), Top and Bottom

7 1920*1080 33.7 30 89.1 HDTV 1080P Side by Side(half), Top and Bottom

8 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side(half), Top and bottom

9 1920*1080 56.25 50 148.5 HDTV 1080P Side by Side(half), Top and bottom,

10 1920*1080 33.7 60 74.25 HDTV 1080i Side by Side(half), Top and Bottom

11 1920*1080 28.1 50 74.25 HDTV 1080i Side by Side(half), Top and Bottom

*** HDMI 1.3

1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom

2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom

3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom

4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom

5 1920*1080 27.00 24.00 74.25 HDTV 1080P

6 1920*1080 33.75 30.00 74.25 HDTV 1080P

7 1920*1080 67.50 60.00 148.5 HDTV 1080P

8 1920*1080 56.25 50 148.5 HDTV 1080P

Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

Only for training and service purposes

- 8 -

ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet is applied all of 72” LCD TV, LT23J chassis by manufacturing LG TV Plant all over the world

2. Specification

(1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation

transformer will help protect test instrument.. (2) Adjustment must be done in the correct order (3) The adjustment must be performed in the circumstance of

25 ºC ±5 ºC of temperature and 65±10% of relative

humidity if there is no specific designation. (4) The input voltage of the receiver must keep 100~220V,

50/60Hz (5) Before adjustment, execute Heat-Run for 5 minutes at RF

no signal.

3. Adjustment items

3.1. PCB assembly adjustment items

(1) MAC Address, ESN Key and Wide-vine Key D/L (2) LAN Test( Ping-Test ) (3) Main S/W program download : Using USB Memory stick (4) Input Tool - Option (5) Download EDID : EDID data are automatically downloaded

when adjusting the Tool Option. (6) ADC Calibration – RGB & Component (7) Check SW Version

4. PCB assembly adjustment method

4.1. MAC Address, ESN Key and Wide-vine Key Download

■ D/L Program : keydownload.exe

4.1.1. Equipment & Condition

1) Play file: keydownload.exe

2) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

3) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

4.1.2. Download Process

(12Y LCD TV + MAC + WIDEVINE + ESN)

1) Execute “keydownload.exe” on PC

2) Select the download items.

3) Mode check: Online only

4) Check the test process

- DETECT -> MAC_WRITE -> ESN_WRITE -> WIDEVINE_ WRITE

5) Play: START

6) Check of result: Ready, Test, OK or NG

3.2. SET assembly adjustment items

(1) Input Area option. (2) Adjustment of White Balance : Auto (3) Adjustment of White Balance : Manual (4) Intelligent Sensor Inspection Guide (5) LAN Inspection Guide (6) Widevine Key Inspection Guide (7) Model name & Serial number D/L (8) Wi-Fi MAC Address Check (9) Local Dimming Inspection Guide (10) Preset CH information (11) Internal Press Test (12) Motion Remote controller Inspection (13) 3D Function test

(14) Outgoing Condition Conguration

(15) Sound spec (16) Factoring Option Data input.

4.1.3. Inspection

INSTART menu, check these keys.

Only for training and service purposes

- 9 -

4.2. PING Test(LAN Operating Test)

4.2.1. Check PCBA

1) Connect LAN to PCBA& Power On.(Default IP can be set to automatic setting. When power ON, IP can be Automatically be achieved from the router)

2) Push ADJ key on Adjust remote-controller.

3) Enter “13. ACAP PING TEST” & check Network

4.2.2. Check Set

1) Co nnect TV-Set & PC with Cross LAN cable.(PC IP :

12.12.2.3)

2) Execute “PINT Test program ”, Ch eck sett ing data of program. (TV-Set IP : 12.12.2.2)

3) Push Power Only key on Adjust remote-controlle.

4) Click “RUN”, Check “OK” or “NG”

4.3. Main S/W program download

4.3.1. Using the Memory Stick

** USB DOWNLOAD : Service Mode

1) Insert the USB memory Stick to the USB port

2) Automatically detect the SW Version.

-> S/W download process is executed automatically.

3) Show the message “Copy the file from the Memory”

4) After Finished the Download, Automatically DC Off -> On

5) If the TV IS Turn On, Check the updated SW Version and Tool Option.

Only for training and service purposes

- 10 -

4.4. Input tool option.

Adjust tool option refer to the BOM.

▪ Tool Option Input : PCBA Check Process ▪ Area Option Input : Set Assembly Process

*** Tool Option table

MODEL 55LM9600 47LM9600 47LM8600 72LM9500

Tool Option1 33001 32999 32983 33148

Tool Option2 46421 46421 42325 50517

Tool Option3 21325 21325 21357 21325

Tool Option4 21039 21039 12845 21039

Tool Option5 23063 23063 23063 6677

Tool Option6 1321 1321 1321 1321

Tool Option7 63019 63019 62763 63019

After Input Tool Option and AC off Before PCBA check, you have to change the Tool option and have to AC off/on (Plug out and in) (If missing this process, set can operate abnormally)

4.4.1. Profile

Must be changed the option value because being different with some setting value depend on module maker, inch and market

4.4.2. Equipment

Adjustment remote control

4.5. EDID D/L method

Recommend that don’t connect HDMI and RGB(D-SUB) cable when downloading the EDID. If not possible, recommend that connect the MSPG equipment. There are two methods of downloading the edid data

It is a VESA regulation. A PC or a MNT will display an optimal resolution through information Sharing without any necessity of user input. It is a realization of “Plug and Play”

4.5.1. 1st Method

EDID datas are automatically downloaded when adjusting the Tool Options. Automatically downloaded when pushing the enter key after adjusting the tool option5. It takes about 2seconds

4.5.2. 2nd Method

● Caution : Must be checked that the tool option is right or not.

If tool option is wrong, hdmi edid data could not be

downloaded well.

1) Press the ADJ key

2) Move to the 10. EDID D/L and Press the right direction

key(►)

3) Press the right direction key(►) at Start.

4) After about a few seconds, appear “Waiting..” => “OK”, then

compele.

4.4.3. Adjustment method

The input methods are same as other chassis.(Use ADJ Key on the Adjust Remocon.) (If not changed the option, the input menu can differ the model spec.) Re fe r to Job Expre ss ion of each main ch assis ass’ y (EBTxxxxxxxx) for Option value Caution : Don’t Press “IN-STOP” key after completing the

function inspection.

4.5.3. RS-232C command Method

1) Command : AE 00 10

● Caution : Don’t connect HDMI and RGB(D-SUB) cable when

downloading the EDID.

If the cables are connected, Downloading of edid

could be failed

Only for training and service purposes

- 11 -

4.5.4. EDID data

4.5.4.1. HDMI(FHD 3D_Deep color support)

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 02 03 37 F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 26 15 07 50 09 57 07 78 03 0C 00 10 00

20 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16

30 10 28 10 E3 05 03 01 02 3A 80 18 71 38 2D 40 58

40 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18 71 1C 16

50 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 72 51

60 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11

(1) HDMI 1 Check sum : 0x43, 0X11 (CEA Block 0x1E :10) (2) HDMI 2 Check sum : 0x43, 0X01 (CEA Block 0x1E :20) (3) HDMI 3 Check sum : 0x43, 0XF1 (CEA Block 0x1E :30) (4) HDMI 4 Check sum : 0x43, 0XE1 (CEA Block 0x1E :40)

4.5.4.2. RGB(Check sum : 5C)

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 5C

4.6. ADC Calibration : Comp 480i/Comp 1080p/RGB

4.6.1. ADC Calibration : Internal Auto ADC

※ If Adjust ADC is “OTP”, It doesn’t need ADC adjustment.

(GP3-BCM)

4.6.2. Automatic ADC Calibration

4.6.2.1. Process ADC adjustment is needed to find the optimum black level and gain in Analog to Digital device and to compensate RGB deviation

4.6.2.2. Equipment & Condition

1) Jig(RS-232C protocol)

2) Inner Pattern

- Resolution : 1080P(inner pattern)

- Resolution : 1024 * 768 RGB(Inner pattern)

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level : 0.7± 0.1 Vp-p

4.6.2.3. Adjustment Process

4.6.2.3.1. Adj protocol

Protocol Command Set ACK

Enter adj. mode aa 00 00 a 00 OK00x

Source change xb 00 40

xb 00 60

Begin adj. ad 00 10

Return adj. result OKx (Case of Success)

Read adj. data (main)

ad 00 20

(sub ) ad 00 21

Conrm adj. ad 00 99 NG 03 00x (Fail)

End adj. aa 00 90 a 00 OK90x

4.6.2.3.2. Adj order (1) aa 00 00 [Enter ADC adj. model] (2) xb 00 40 [Change input source to Component(480i)] (3) ad 00 10 [Adjust 480i Component1] (4) xb 00 60 [Change input source to RGB(1024*768)] (5) ad 00 10 [Adjust 1024*768 RGB] (6) ad 00 90 [End adj] (Ref) ADC adj RS232C Protocol_Ver1.0

b 00 OK40x (Adjust 480i Comp1 ) b 00 OK60x (Adjust 1024*768 RGB)

NGx (Case of Fail)

(main) 000000000000000000000000007c007b006dx

(Sub) 000000070000000000000000007c00830077x

NG 03 01x (Fail) NG 03 02x (Fail) OK 03 03x (Success)

Only for training and service purposes

- 12 -

4.7. Check SW Version

4.7.1. Method

1) Push In-star key on Adjust remote-controller.

2) SW Version check(ex. 47LW9500-DA)

5. SET assembly adjustment method

5.1. Input Area-Option

(1) Prole : Must be changed the Area option value because

being different of each Country’s Language and

signal Condition. (2) Equipment : adjustment remote control. (3) Adjustment method

- The input methods are same as other chassis.(Use IN-START

Key on the Adjust Remocon.)

Refer to Job Expression of each main chassis ass’y

(EBTxxxxxxxx) for Option value

※ Required Equipment

▪ Remote controller for adjustment ▪ Color Analyzer : CA100+ or CA-210 or same product (should

be used in the calibrated ch by CS-1000)

- LCD TV : CH-9

- PDP TV : CH-10

- White LED TV : CH-14

- RGB LED(MNT) : CH-16

▪ Auto W/B adjustment instrument(only for Auto adjustment)

5.2.1. Adjustment of White Balance : (For Automatic Adjustment)

Co nnectin g diag ram of equipme nt for measu ring (Fo r Automatic Adjustment)

1) Set TV in adj. mode using POWER ON key

2) Zero calibrate probe then place it on the center of the Display

3) Connect Cable(RS-232C)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sing), check adj. status pre mode(Warm, Medium, Cool)

6) Remove probe and RS-232C cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need

※ Luminance min value is 150cd in the Cool/Medium/Warm

mode( For LCD)

5.2. Adjustment of White Balance

● In case of keeping module is in the circumstance of 0°C, it should be placed in the circumstance of above 15°C for 2

hours

● In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above 15°C

for 3 hours.

▪ Purpose : Adjust the color temperature to reduce the deviation

of the module color temperature.

▪ Principle : To adjust the white balance without the saturation,

Fix the one of R/G/B gain to 192 (default data) and decrease the others.

▪ Adjustment mode : Three modes – Cool / Medium / Warm

Only for training and service purposes

- 13 -

5.2.2. Adjustment of White Balance (for Manual adjustment)

▪ Co lor analyzer(CA100+, CA210) should be used in the

calibrated ch by CS-1000

▪ Operate the zero-calibration of the CA100+ or CA-210, then

stick sensor to the module when adjusting.

▪ For manual adjustment, it is also possible by the following

sequence.

1) Select white pattern of heat-run by pressing “POWER ON”

key on remote control for adjustment then operate heat run longer than 15 minutes.

(If not executed this step, the condition for W/B may be

different.)

2) Push “Exit” key.

3) Change to the AV mode by remote control.

4) Input external pattern (80% white pattern)

5) Push the ADJ key => Enter “0000” (Password)

6) Select “3. W/B ADJUST”

7) Enter the W/B ADJUST Mode

8) Stick the sensor to the center of the screen and select each

items (Red/Green/Blue Gain and Offset) using ▲/▼(CH +/-)

key on R/C..

9) Adjust R/ G/ B Gain using ◄/►(VOL +/-) key on R/C.

10) Adjust three modes all (Cool / Medium / Warm) : Fix the

one of R/G/B gain and change the others

11) When adjustment is completed, Enter “COPY ALL”

12) Exit adjustment mode using EXIT key on R/C.

※ CASE First adjust the coordinate far away from the target value(x, y). (1) x, y >target i) Decrease the R, G. (2) x, y < target i) First decrease the B gain, ii) Decrease the one of the others. (3) x >target , y< target i) First decrease B, so make y a little more than the target. ii) Adjust x value by decreasing the R (4) x < target , y >target i) First decrease B, so make x a little more than the target. ii) Adjust x value by decreasing the G

● Standard color coordinate and temperature when using the

CA100+ or CA210 equipment

Color coordinate

Mode

Temp

△uv

X Y

Cool

0.269±0.002 0.273±0.002 13000K

0.0000

Medium 0.285±0.002 0.293±0.002 9,300 K 0.000

Warm 0.313±0.002 0.329±0.002 6,500K 0.003

Change reason : When vivid mode, more detail than other

company set.

GP3 Aging

● In case of Edge LED module, the color coordinates is changing

by aging, so you have to use the below table.

The Time Table of color coordinates by SET Aging Time

(1) Edge LED Models(47LM8600-DA)

time

(Min)

1 0 ~ 2 293 305 309 323 330 348

2 3 ~ 5 292 303 308 321 330 347

3 6 ~ 9 291 302 307 320 329 346

4 10 ~19 288 298 304 316 326 342

5 20 ~ 35 286 295 302 313 324 339

6 36 ~ 49 285 293 301 311 322 337

7 50 ~ 79 283 291 299 309 321 335

8 80 ~ 149 282 289 298 308 320 334

9 Over 150 281 287 298 306 319 332

Cool Medium Warm

x y x y x y

269 273 285 293 313 329

(2) ALEF (47LM9600-DA)

time

(Min)

1 0 ~ 2 283 293 299 313 320 339

2 3 ~ 5 282 291 298 311 319 337

3 6 ~ 9 281 290 297 310 318 336

4 10 ~19 279 289 295 309 316 335

5 20 ~ 35 277 284 293 304 314 330

6 36 ~ 49 274 279 290 299 311 325

7 50 ~ 79 271 277 287 297 308 323

8 80 ~ 119 270 274 286 294 307 320

9 Over 120 269 273 285 293 306 319

Cool Medium Warm

x y x y x y

269 273 285 293 313 329

(3) ALEF (55LM9600-DA)

time

(Min)

1 20 282 298 298 318 319 344

2 21 ~ 25 280 296 296 316 317 342

3 26 ~ 30 279 294 295 314 316 340

4 31 ~ 35 277 292 293 312 314 338

5 36 ~ 40 276 290 292 310 313 336

6 41 ~ 50 275 288 291 308 312 334

7 51 ~ 80 272 284 288 304 309 330

8 81 ~ 119 271 282 287 302 308 328

9 Over 120 270 281 286 301 307 327

Cool Medium Warm

x y x y x y

269 273 285 293 313 329

Only for training and service purposes

- 14 -

(4) IOL (72LM9500-DA)

GP3 Aging

time

(Min)

1 0 ~ 2 280 287 296 307 320 337

2 3 ~ 5 279 285 295 305 319 335

3 6 ~ 9 277 284 293 304 317 334

4 10 ~19 276 283 292 303 316 333

5 20 ~ 35 274 280 290 300 314 330

6 36 ~ 49 272 277 288 297 312 327

7 50 ~ 79 271 275 287 295 311 325

8 80 ~ 119 270 274 286 294 310 324

9 Over 120 269 283 285 293 309 323

Cool Medium Warm

x y x y x y

269 273 285 293 313 329

■ In the SET applied LED module (LS5700/LM6200/LM6600/

LM7600 Series), cause of the physical characteristics of LED Module, sets are taken a 120 minutes by aging time to stabilize a color coordinates. So White Balance Control equipments have to get the SET Aging Time from the SET and then going to control the W/B by revise color coordinates at each time

5.3. Intelligent Sensor Inspection Guide

Step 1. Turn on the TV set. Step 2. Press “EYE” button on the Adjustment remote controller.

Step 3. Block the Intelligent Sensor module on the front C/A about 6 seconds. When the “Sensor Data” is lower than 20, you can see the “OK” message -> If it doesn’t show “OK” message, the Sensor Module is defected one. You have to replace that with a good one.

Green Eye-Check

Sensor Data : 492 BackLight : 100

OK

- To check the Coordinates of White Balance, you have to measure at the below conditions.

Picture Mode : select Vivid and change Dynamic Contrast : Off , Dynamic Colour : Off, Clear White : Off

->Picture Mode change : Vidid -> Vivid(User)

(If you miss the upper condition, the coordinates of W/B can be lower than the spec.)

Step 4. After check the “OK” message come out, take out your hand from the Sensor module.

-> Check “Sensor Data” value change from “0” to “300” or not. If it doesn’t change the value, the sensor is also defected

one. You have to replace it.

5.4. LAN Inspection

1) LAN Port connection with PCB

2) Network setting at MENU Mode of TV

3) Setting automatic IP

4) Setting state conrmation

5) If automatic setting is nished, you conrm IP and MAC

Address

Only for training and service purposes

- 15 -

5.5. WIDEVINE Key Inspection

1) Conrm Key input Data at the “IN START” MENU Mode

5.6. Model name & Serial number D/L

5.6.1. Notice

1) Serial number D/L is using of scan equipment.

2) Setting of scan equipment operated by Manufacturing

Technology Group.

3) Serial number D/L must be conformed when it is produced in

production line, because serial number D/L is mandatory by D-book 4.0

4) Check the model name In-start menu -> Factory name

displayed (ex 32LS5700-DA)

5) Check the Diagnostics (DTV country only) -> Buyer model

displayed (ex 32LS5700-DA)

5.7. Wi-Fi MAC ADDRESS CHECK

5.7.1. Notice

1) Using RS232

Command Set ACK

Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]

2) Check the menu on in-start

5.6.2. Method : Auto

1) Press “Power on” key of service remocon.(Baud rate : 115200

bps)

2) Connect RS232 Signal Cable to RS-232 Jack

3) Write Serial number by use RS-232.

4) Must check the serial number at Instart menu

5.6.3. Method : Manual

* If the TV set is downloaded By OTA or Service man, Sometimes model name or serial number is initialized. ( Not always) It is impossible to download by bar code scan, so It need Manual download.

1) Press the ‘instart’ key of ADJ remote controller.

2) Go to the menu ‘6.Model Number D/L’ like below photo.

3) Input the Factory model name or Serial number like photo.

5.8. Local Dimming Inspection (Optional)

5.8.1. Edge LED models with local dimming

1) Press ‘TILT” key of the Adj. R/C and check moving patterns. The black bar patterns moves from left to right. If local dimming function does not work, a whole screen shows full white.

5.9. GND and Hi-Pot test

No Item Vallue Unit Remark

1. Dielectric Voltage(AC<->FG)

2. Dielectric Voltage(Without FG)

1.5 kV At 100mA for 1sec(Line)

1.5 At 100mA for 1min(OQC)

3 kV At 100mA for

1sec(Line)

3 At 100mA for

1min(OQC)

Only for training and service purposes

- 16 -

5.10. Motion Remote controller Inspection

5.10.1. Equipment

Motion remote controller for test, IR-KEY-CODE remote controller for test Check battery before test. (Recommend : Change battery for every Lot.)

5.10.2. Process

1) Push “Mute” or “ START” key for pairing between TV-set and motion remote controller.

2) Push “OK” or “Enter” key, you can see the Cursor on screen.

3) Push “Vol+” or “STOP” key, Disconnect Pairing.

5.11. Audio

No Item Min Typ Max Unit Remark

1 Audio practical

max Output, L/R (Distortion=10% max Output)

2 Speaker (8Ω

Impedance)

▪ Measurement condition:

(1) RF input: Mono, 1 KHz sine wave signal, 100% Modulation (2) CVBS, Component: 1 KHz sine wave signal 0.4Vrms (3) RGB PC: 1 KHz sine wave signal 0.7Vrms

9.0 10.0 12.0 W Measure-

8.5 8.9 9.8 Vrms

10.0 15.0 W Measure-

ment condition (TBD)

47/55LM9600

5.12. 3D Function test

5.12.1. Equipment

Pattern Generator MSPG-3233, HDMI mode 37, pattern No. 81

5.12.2. Equipment

1) Connect HDMI (HDMI mode 371, Pattern No. 81)

2) Insert 3D Mode, Select side by side mode.

3) Without 3D-glasses, Like below gure.

4) With 3D left-glass, Like below gure. (Center is RED)

Only for training and service purposes

- 17 -

5) With 3Dright-glass, Like below gure.(Center is Blue)

5.13. HDMI ARC Function Inspection

5.13.1. Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

5.13.2. Test method

(1) Insert the HDMI Cable to the HDMI ARC port from the

master equipment (HDMI1)

(2) Check the sound from the TV Set

(3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

* Remark: Inspect in Power Only Mode and check SW version

in a master equipment

.

Only for training and service purposes

- 18 -

TROUBLE SHOOTING

No power

Check 24V, 12V, 3.5V

of Power B/D

Check short of Main B/D

or Change Power B/D

Pass

Check Output of

Q2305, IC2300, IC2301, IC2302

IC2304, IC2305, IC2306

Check P2301 Connector

Change LED Assy

: [A] PROCESS

Fail

Pass

Check LED Assy

Check short of

IC2303, IC6501

Pass

Check short of

Q2305, IC2300, IC2301, IC2302

IC2304, IC2305, IC2306

Fail

Re-soldering or Change defect

part of Q2305, IC2300, IC2301,

IC2302IC2304, IC2305, IC2306

Fail

Re-soldering or Change defect

part of IC2303, IC6501

Fail

Only for training and service purposes

- 19 -

No Raster

: [B] Process

Check LED status

On Display Unit

Repeat A PROCESS

Fail

Check Output of IC9301

Change IC9301

Fail

Change Inverter Connector

Or Inverter

Fail

Pass

Fail

Pass

Change LVDS Cable

Fail

Check LVDS Cable

Pass

Check Panel Link Cable

Or Module

Change Panel Link Cable

Or Module

Check Inverter Connector

Or Inverter

Pass

Check Output of IC3000(Micom)

Change IC3000

Fail

Pass

Only for training and service purposes

- 20 -

No Raster on USB Signal

Check Input source Cable And Jack

Re-soldering or

Change the defect part

Repeat [A], & [B] Process

Pass

Check the Input/Output

Of JK4300, JK4302, JK4303

Fail

Pass

Check the Input/Output

Of IC101

Fail

Re-soldering or

Change the defect part

Pass

Check the Input/Output

Of IC4200, IC4305, IC4306

Fail

Re-soldering or

Change the defect part

Pass

Only for training and service purposes

- 21 -

No Raster on PC Signal

Check Input source Cable And Jack

Re-soldering or

Change the defect part

Repeat [A], & [B] Process

Pass

Check the Input/Output

Of JK3603

Fail

Pass

Check the Input/Output

Of IC101

Fail

Re-soldering or

Change the defect part

Pass

Only for training and service purposes

- 22 -

No Raster on COMPONENT Signal

Check Input source

Cable And Jack

Re-soldering or

Change the defect part

Pass

Check the Input/Output

Of IC101

Fail

Re-soldering or

Change the defect part

Repeat [A], & [B] Process

Check The Input/Output

Of JK3801

Fail

Pass

No Raster on HDMI Signal

Check Input source

Cable And Jack

Check the Input/Output

Of JK3200, , JK3201, JK3202, JK3203

Fail

Re-soldering or

Change the defect part

Pass

Check the Input/Output

Of IC101

Fail

Re-soldering or

Change the defect part

Repeat [A], & [B] Process

Pass

Check the Input/Output

Of IC3201

Fail

Re-soldering or

Change the defect part

Pass

Check the Instart Menu

EDID D/L Status

Fail

Re-download EDID Data]

(Adjust Menu  EDID D/L)

Only for training and service purposes

- 23 -

No Raster On AV Video Signal

No Signal On TV(RF) Signal

Check Input source

Cable And Jack

Check Input source

Cable And Jack

Pass

Check The Input/Output

Of JK3800

Pass

Re-soldering or

Change the defect part

Pass

Fail

Repeat [A], & [B] Process

Check the Input/Output

Of IC101

Fail

Re-soldering or

Change the defect part

Pass

Check The Input/Output

Of TU6504

Pass

Re-soldering or

Change the defect part

Pass

Fail

Check the Input/Output

Of IC101

Fail

Re-soldering or

Change the defect part

Repeat [A], & [B] Process

Only for training and service purposes

- 24 -

No Sound

Check The Input Source

Check The Input/Output

Of IC5400

Re-soldering or

Change the defect part

Fail

Pass

Check The Speaker

Change Speaker

Fail

Check The Speaker Wire

Pass

Change The Source Input

Fail

No Sound of SPDIF

Check output source

Cable And Jack

Check The Input/Output

Of IC101

Pass

Check The Speaker Wire

Fail

Re-soldering or

Change the defect part

Only for training and service purposes

- 25 -

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essenti al that these special safet y parts shoul d be replac ed with the same compo nents as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

400

920

521

810

540

121

510

830

541

800

530

531

820

910

900

550

LV1

750

740

AM1

AG2

AG1

Dual Play

200

840

850

300

Only for training and service purposes

A10

A9

570

560

860

120

A5

122

500

A22

501

A21

A2

870

- 26 -

System Configuration

LGE Internal Use Only

NVRAM

Clock for LG1152

MAIN Clock(24Mhz)

C100

8pF

50V

X-TAL_1

GND_1

1

2

X101

24MHz

4

3

C101

8pF

50V

GND_2

X-TAL_2

PLL SET[1:0] ==> Internal Pull-UP. N.C is high 00 : CPU clock(1056Mhz), Main0,1/2 DDR (792/792 Mhz) 01 : CPU clock(792Mhz), Main0,1/2 DDR (672/792 Mhz) 10 : CPU clock(1152Mhz), Main0,1/2 DDR (792/672 Mhz) 11 : CPU clock(984Mhz), Main0,1/2 DDR (792/792 Mhz)

BOOT MODE "11" or "01" : NOR "10" : eMMC "00" : NAND

OPT

R102 22

R103 22

OPT

PLLSET1

PLLSET0

R112

XIN_MAIN

1M

XO_MAIN

JTAG I/F FOR MAIN

+3.3V_NORMAL

4.7K

R187

R185

OPT

BOOT_MODE1

+3.3V_NORMAL

R188

OPT

R186

4.7K

BOOT_MODE1

BOOT_MODE0

TRST_N0

TDI0 TDO0 TMS0 TCK0

SOC_RESET

OPT

R131 10K

R132 10K

OPT

R133 10K

R134 10K

BOOT_MODE0

+3.3V_NORMAL

HW_OPT_0

HW_OPT_1

HW_OPT_2

HW_OPT_3

HW_OPT_4

HW_OPT_5

HW_OPT_6

HW_OPT_7

HW_OPT_8

HW_OPT_9

HW_OPT_10

HP_AMP_MUTE

BackEnd 1

BackEnd 2

Pannel Resol

OPTIC I/F

3D Depth IC

DDR Size

CP BOX

FrontEnd 1

FrontEnd 2

OPT

R117

22

10K

URSA5

R110

FRC_EXTERNAL

R100 10K

10K

FRC3

FRC_INTERNAL

R107 10K

R111

FHD

R124 10K

UD

R125 10K

OPTIC

R138 10K

NON_OPTIC

R139 10K

OPT

3D_DEPTH

R140 10K

R145 10K

1GByte

R141 10K

R146 10K

NON_3D DEPTH

CP_BOX

R147 10K

DVB_T2_TUNER

NON_CP_BOX

R148 10K

NON_DVB_T2_TUNER

DVB_S_TUNER

R154 10K

R152 10K

R153 10K

R155 10K

NON_DVB_S_TUNER

ZORAN_FRC

R121 10K

R156 10K

DVB_C2_TUNER

NOT_ZORAN_FRC

R126 10K

R158 10K

NON_DVB_C2_TUNER

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6

MODEL_OPT_7

MODEL_OPT_8

MODEL_OPT_9

MODEL_OPT_10

Zoran FRC (For UD)

MODEL OPTION 8 is just for CP Box It should not be appiled at MP

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

IC102

R1EX24256BSAS0A

A0

1

A1

A2

VSS

8

2

7

A0’h

3

6

4

5

Place to LVDS Wafer

FRC_RESET

I2C_SCL1

SoC internal

NO_FRC

FRC

0

0 1

1

HIGH

FHD

OPTIC

3D DEPTH

3D_Depth_IC

DDR Reserved

CP BOX

Enable

T2 Tuner

Support

S Tuner

Support

C2 Tuner

Support

C111

0.1uF

VCC

WP

SCL

SDA

R151 22

4.7K

R113

R160 22

R162 22

MHL_DET

HDMI_INT

LG FRC3

10

0

LOW

UD

NON_OPTIC

NON_3D_Depth_IC

DDR_Default

Disable

Not Support

+3.3V_NORMAL

Write Protection

- Low : Normal Operation

- High : Write Protection

OPT

R143

OPT

22

10K

FRC3

R170

SOC_RX

SOC_TX

2N7002K

URSA5

1

R142

22

FRC3_RESET

3D_DEPTH_RESET

I2C_BE_SDA1I2C_SDA1

I2C_BE_SCL1

LOCAL_DIM_EN

+5V_NORMAL

G

D

Q100

2N7002K

+5V_NORMAL

G

S

D

Q105

OPT

+3.3V_NORMAL

R178

2.2K

I2C_SCL5

I2C_SDA5

I2C_SCL3 I2C_SDA3

+3.3V_NORMAL

S

+3.3V_NORMAL

R203

100K

R180

3.3K

R179

2.2K

OPT

R181

100K

2N7002K

3.3K

R202

G

S

D

Q103

I2C PULL UP

R182

2.2K

R195

2.2K

SOC_RESET

BOOT_MODE1 BOOT_MODE0

ERROR_OUT

/USB_OCD2 /USB_OCD3

M_REMOTE_RX M_REMOTE_TX

IRB_SPI_MISO IRB_SPI_MOSI

IRB_SPI_CK IRB_SPI_SS

AV1_CVBS_DET

DTV_ATV_SELECT

R196

3.3K

R197

3.3K

XIN_MAIN

XO_MAIN

TRST_N0

TMS0 TCK0 TDI0 TDO0

PLLSET1 PLLSET0

EPHY_INT

UART1_RX UART1_TX

R198

3.3K

I2C_SCL1 I2C_SDA1 I2C_SCL2 I2C_SDA2 I2C_SCL3 I2C_SDA3 I2C_SCL4 I2C_SDA4 I2C_SCL5 I2C_SDA5 I2C_SCL6 I2C_SDA6

R199

3.3K

R150 22

R101 22

R184

R183

1.2K

R104 560

1%

BOOT_MODE1 BOOT_MODE0

1.2K I2C_SDA1 I2C_SCL1 I2C_SDA2 I2C_SCL2 I2C_SDA3 I2C_SCL3 I2C_SDA4 I2C_SCL4

I2C_SDA5 I2C_SCL5

I2C_SDA6 I2C_SCL6

A22

XIN_MAIN

B22

XO_MAIN

AB16

OPM1

AB17

OPM0

AE3

PORES_N

V23

TRST_N0

U25

TMS0

V25

TCK0

V24

TDI0

U24

TDO0

Y22

TRST_N1

AA22

TMS1

AB20

TCK1

AB21

TDI1

W22

TDO1

AB9

PLLSET1

AB8

PLLSET0

AB15

BOOT_MODE1

AB14

BOOT_MODE0

Y23

EXT_INTR3/GPIO48

W25

EXT_INTR2/GPIO63

W24

EXT_INTR1/GPIO62

W23

EXT_INTR0/GPIO61

Y5

UART0_RX/GPIO49

W6

UART0_TX/GPIO50

AA6

UART1_RX

Y6

UART1_TX

AB5

UART2_RX

AA5

UART2_TX

AB23

SPI_DI0/GPIO39

AB24

SPI_DO0/GPIO38

AA25

SPI_SCLK0/GPIO37

AB25

SPI_CS0/GPIO36

Y25

SPI_DI1/GPIO35

AA23

SPI_DO1/GPIO34

Y24

SPI_SCLK1/GPIO33

AA24

SPI_CS1/GPIO32

AB6

SCL0/GPIO60

AB4

SDA0/GPIO59

AC5

SCL1/GPIO58

AC4

SDA1/GPIO57

AD4

SCL2/GPIO56

AE4

SDA2/GPIO71

AE5

SCL3/GPIO70

AD5

SDA3/GPIO69

AE6

SCL4/GPIO68

AD6

SDA4/GPIO67

AC6

SCL5/GPIO66

AC7

SDA5/GPIO65

FPGA_LVDS_INFO

USB_CTL3

DiiVA_POD_CTL

M25

M24

M23

N23

T27

EB_CS3/GPIO64

EB_CS2/GPIO79

EB_CS1/GPIO78

EB_CS0/GPIO77

RMII_REF_CLK

RMII_CRS_DV

RMII_MDIO

RMII_MDC

AD2

AB1

AB2

AB3

AC2

R105 22

EPHY_MDC

EPHY_MDIO

EPHY_REFCLK

EPHY_CRS_DV

for DiiVA(China)

SEL_USB3

SEL_USB2

SEL_USB1

EB_ADDR[0-14]

EB_OE_N

EB_BE_N1

EB_BE_N0

EB_WE_N

T28

U27

EB_OE_N

EB_WE_N

U26

U28

EB_WAIT

EB_BE_N1

J22

K22

J23

EB_BE_N0

EB_ADDR17/GPIO84

EB_ADDR16/GPIO83

EB_ADDR15/GPIO82

EB_ADDR[11]

EB_ADDR[12]

EB_ADDR[13]

EB_ADDR[14]

L26

L27

L25

N26

EB_ADDR14

EB_ADDR13

EB_ADDR12

EB_ADDR[9]

EB_ADDR[8]

EB_ADDR[10]

N27

M26

L28

EB_ADDR9

EB_ADDR11

EB_ADDR10

IC100

LG1152D-B1

LG1152_NON_RM

RMII_TXEN

RMII_TXD1

RMII_TXD0

RMII_RXD1

RMII_RXD0

CAM_CE1_N

CAM_CE2_N

CAM_CD1_N

CAM_CD2_N

CAM_VS1_N

CAM_VS2_N

CAM_IREQ_N

CAM_RESET

CAM_INPACK_N

AC3

AE1

AD3

AD1

W26

V28

Y27

Y26

W28

W27

AA28

AB26

AA27

AA26

R108 22

R106 22

EPHY_EN

EPHY_TXD1

EPHY_RXD0

EPHY_TXD0

EPHY_RXD1

+3.3V_NORMAL

/PCM_CE2

/PCM_CE1

CAM_CD2_N

CAM_CD1_N

CI

10K

R166

CAM_IREQ_N

CI

R167 10K

PCM_RST

CAM_INPACK_N

EPHY_INT

EB_ADDR[5]

EB_ADDR[7]

EB_ADDR[6]

L24

L23

K28

EB_ADDR8

EB_ADDR7

EB_ADDR6

EB_ADDR5

CAM_VCCEN_N

CAM_WAIT_N

CAM_REG_N

CAM_IOIS16_N

Y28

V27

V26

CAM_REG_N

CAM_WAIT_N

CI

10K

R168

PCM_5V_CTL

HP_DET

EB_ADDR[3]

EB_ADDR[2]

EB_ADDR[4]

K27

K26

K25

K24

EB_ADDR4

EB_ADDR3

EB_ADDR2

SC_CLK/GPIO90

SC_DETECT/GPIO93

R25

U23

T25

SMARTCARD_DET

SMARTCARD_CLK

SEL_USB1 SEL_USB2 SEL_USB3 /RST_PHY

SC_DET DiiVA_POD_CTL

+3.3V_NORMAL

EB_ADDR[1]

EB_ADDR[0]

10K

R109

K23

V22

U22

EB_ADDR1

EB_ADDR0

EB_DATA15

EB_DATA14

SC_VCCEN/GPIO89

SC_VCC_SEL/GPIO88

SC_RST/GPIO91

SC_DATA/GPIO92

T24

T23

R24

SMARTCARD_RST

SMARTCARD_VCC

SMARTCARD_DATA

SMARTCARD_PWR_SEL

T22

R22

P22

N22

M22

EB_DATA9

EB_DATA13

EB_DATA12

EB_DATA11

EB_DATA10

SD_CLK/GPIO76

SD_CMD/GPIO73

SD_CD_N/GPIO75

SD_WP_N/GPIO74

SD_DATA3/GPIO72

C22

C23

A23

B23

A24

MOTOR_CCW

MOTOR_CLOSE_SW

MO_SENS_TO_MAIN_UP

MO_SENS_TO_MAIN_DOWN

EB_DATA[0-7]

EB_DATA[0]

EB_DATA[1]

EB_DATA[3]

EB_DATA[2]

EB_DATA[4]

EB_DATA[5]

EB_DATA[6]

EB_DATA[7]

L22

T26

R28

R27

R26

P28

P27

P26

N28

EB_DATA8

EB_DATA7

EB_DATA6

EB_DATA5

EB_DATA4

EB_DATA3

EB_DATA2

EB_DATA1

EB_DATA0

EMMC_RST EMMC_CLK

EMMC_CMD EMMC_DATA7 EMMC_DATA6 EMMC_DATA5 EMMC_DATA4 EMMC_DATA3 EMMC_DATA2 EMMC_DATA1 EMMC_DATA0

NAND_CS1

NAND_CS0

NAND_ALE

NAND_CLE

NAND_REN

NAND_WEN

SD_DATA2/GPIO87

SD_DATA1/GPIO86

SD_DATA0/GPIO85

USB_DP1

USB_DM1

USB_DP2

USB_DM2

USB_TXR_RKL

USB_ANALOGTEST

BT_USB_DP

BT_USB_DM

BT_TXR_RKL

BT_ANALOGTEST

R173

Y4

C25

B25

AA1

AA2

AA4

22

OPT

R175

R176

R174

B24

C24

A25

MOTOR_CW

IR_B_RESET

MOTOR_OPEN_SW

B27

A27

A26

B26

USB_DM3

USB_DP3

USB_HUB_IC_IN_DM

USB_HUB_IC_IN_DP

Place near Jack side

E28 F27 F26 C26

EMMC_DATA[7]

E27

EMMC_DATA[6]

E26

EMMC_DATA[5]

D27

EMMC_DATA[4]

D28

EMMC_DATA[3]

C27

EMMC_DATA[2]

C28

EMMC_DATA[1]

D26

EMMC_DATA[0]

R23 P24 N25 P23 N24 P25

AC1

GPIO31

V7

GPIO30

W5

GPIO29

W4

GPIO28

V6

GPIO27

V5

GPIO26

V4

GPIO25

U6

GPIO24

U5

GPIO23

U4

GPIO22

T6

GPIO21

T5

GPIO20

T4

GPIO19

R6

GPIO18

R5

GPIO17

R4

GPIO16

P6

GPIO15

P5

GPIO14

P4

GPIO13

N6

GPIO12

N5

GPIO11

N4

GPIO10

N3

GPIO9

M6

GPIO8

AC23

GPIO7

AC24

GPIO6

AE24

GPIO5

AD23

GPIO4

AE23

GPIO3

AC22

GPIO2

AD22

GPIO1

AE22

GPIO0

OPT

WIFI_DP

LG1152 B1

MAIN & GPIO

RCLAMP0502BA

WIFI_DM

M25

M24

M23

N23

T27

T28

U27

U26

U28

J22

K22

J23

EB_OE_N

EB_WE_N

EB_WAIT

EB_BE_N1

EB_BE_N0

A22

XIN_MAIN

B22

EB_CS3/GPIO64

EB_CS2/GPIO79

EB_CS1/GPIO78

EB_CS0/GPIO77

XO_MAIN

AB16

OPM1

EB_ADDR17/GPIO84

EB_ADDR16/GPIO83

AB17

OPM0

AE3

PORES_N

V23

TRST_N0

U25

TMS0

V25

TCK0

V24

TDI0

U24

TDO0

Y22

TRST_N1

AA22

TMS1

AB20

TCK1

AB21

TDI1

W22

TDO1

AB9

PLLSET1

AB8

PLLSET0

AB15

BOOT_MODE1

AB14

BOOT_MODE0

Y23

EXT_INTR3/GPIO48

W25

EXT_INTR2/GPIO63

W24

EXT_INTR1/GPIO62

W23

EXT_INTR0/GPIO61

Y5

UART0_RX/GPIO49

W6

UART0_TX/GPIO50

AA6

UART1_RX

Y6

UART1_TX

AB5

UART2_RX

AA5

UART2_TX

AB23

SPI_DI0/GPIO39

AB24

SPI_DO0/GPIO38

AA25

SPI_SCLK0/GPIO37

AB25

SPI_CS0/GPIO36

Y25

SPI_DI1/GPIO35

AA23

SPI_DO1/GPIO34

Y24

SPI_SCLK1/GPIO33

AA24

SPI_CS1/GPIO32

AB6

SCL0/GPIO60

AB4

SDA0/GPIO59

AC5

SCL1/GPIO58

AC4

SDA1/GPIO57

AD4

SCL2/GPIO56

AE4

SDA2/GPIO71

AE5

SCL3/GPIO70

AD5

SDA3/GPIO69

AE6

SCL4/GPIO68

AD6

SDA4/GPIO67

AC6

SCL5/GPIO66

AC7

SDA5/GPIO65

RMII_REF_CLK

RMII_CRS_DV

RMII_MDIO

RMII_MDC

RMII_TXEN

RMII_TXD1

RMII_TXD0

RMII_RXD1

RMII_RXD0

CAM_CE1_N

CAM_CE2_N

AD2

AB1

AB2

AB3

AC2

AC3

AE1

AD3

AD1

W26

V28

Y27

LG1152_RM IC100-*1

OPTIC_FPGA_RESET

OPTIC_SERDES_RESET

3D_DEPTH_RESET /RST_PHY

OLED_TCON_RESET

HW_OPT_9

HW_OPT_7 HW_OPT_8

DSUB_DET

SC_DET COMP1_DET HW_OPT_5 HW_OPT_6

M_RFModule_ISP

HW_OPT_10

M_RFModule_RESET

FRC_RESET HW_OPT_2 HW_OPT_1 HW_OPT_0

HW_OPT_4

FLASH_WP /RST_HUB

HW_OPT_3

HP_DET

RF_SWITCH_CTL

/TU_RESET

/S2_RESET

OPT

D100

I2C_SDA2 I2C_SCL2

SMARTCARD_DATA SMARTCARD_RST SMARTCARD_PWR_SEL SMARTCARD_VCC SMARTCARD_DET

L26

L27

L25

N26

N27

M26

L28

L24

L23

K28

K27

K26

K25

K24

K23

V22

U22

T22

R22

P22

N22

M22

L22

T26

R28

R27

R26

P28

P27

P26

N28

EB_ADDR9

EB_ADDR8

EB_ADDR7

EB_ADDR6

EB_ADDR5

EB_ADDR4

EB_ADDR3

EB_ADDR2

EB_ADDR1

EB_ADDR0

EB_DATA9

EB_DATA8

EB_DATA7

EB_DATA6

EB_DATA5

EB_DATA4

EB_DATA3

EB_DATA2

EB_DATA1

EB_ADDR14

EB_ADDR13

EB_ADDR12

EB_ADDR11

EB_ADDR15/GPIO82

CAM_CD1_N

CAM_CD2_N

CAM_VS1_N

CAM_VS2_N

CAM_IREQ_N

Y26

W28

W27

AA28

AB26

EB_DATA0

EB_ADDR10

EB_DATA15

EB_DATA14

EB_DATA13

EB_DATA12

EB_DATA11

EB_DATA10

E28

EMMC_RST

F27

EMMC_CLK

F26

EMMC_CMD

C26

EMMC_DATA7

E27

EMMC_DATA6

E26

EMMC_DATA5

D27

EMMC_DATA4

D28

EMMC_DATA3

C27

EMMC_DATA2

C28

EMMC_DATA1

D26

EMMC_DATA0

R23

NAND_CS1

P24

NAND_CS0

N25

NAND_ALE

P23

NAND_CLE

N24

NAND_REN

P25

NAND_WEN

AC1

GPIO31

V7

GPIO30

W5

GPIO29

W4

GPIO28

V6

GPIO27

V5

GPIO26

V4

GPIO25

U6

GPIO24

U5

GPIO23

U4

GPIO22

T6

GPIO21

T5

GPIO20

T4

GPIO19

R6

GPIO18

R5

GPIO17

R4

GPIO16

P6

GPIO15

P5

GPIO14

P4

GPIO13

N6

GPIO12

N5

GPIO11

N4

GPIO10

N3

GPIO9

M6

GPIO8

AC23

GPIO7

AC24

GPIO6

AE24

GPIO5

AD23

GPIO4

AE23

GPIO3

AC22

GPIO2

AD22

GPIO1

AE22

CAM_RESET

CAM_INPACK_N

CAM_VCCEN_N

CAM_WAIT_N

CAM_REG_N

CAM_IOIS16_N

Y28

V27

V26

AA27

AA26

GPIO0

SC_CLK/GPIO90

SC_DETECT/GPIO93

SC_VCCEN/GPIO89

SC_VCC_SEL/GPIO88

SC_RST/GPIO91

SC_DATA/GPIO92

SD_CLK/GPIO76

SD_CMD/GPIO73

SD_CD_N/GPIO75

SD_WP_N/GPIO74

SD_DATA3/GPIO72

SD_DATA2/GPIO87

SD_DATA1/GPIO86

SD_DATA0/GPIO85

USB_DP1

USB_DM1

USB_DP2

USB_DM2

USB_TXR_RKL

USB_ANALOGTEST

BT_USB_DP

BT_USB_DM

BT_TXR_RKL

BT_ANALOGTEST

Y4 R25

U23

T25

T24

T23

R24

C22

C23

A23

B23

A24

B24

C24

A25

B27

A27

A26

B26

C25

B25

AA1

AA2

AA4

SMARTCARD_CLK MOTOR_CLOSE_SW

MOTOR_OPEN_SW MOTOR_CW MOTOR_CCW

MO_SENS_TO_MAIN_UP

MO_SENS_TO_MAIN_DOWN

OPTIC_FPGA_RESET OPTIC_SERDES_RESET

OLED_TCON_RESET

FPGA_LVDS_INFO

IRB_SPI_MISO IRB_SPI_MOSI

IRB_SPI_CK IRB_SPI_SS

IR_B_RESET

EMMC_RST EMMC_CLK EMMC_CMD EMMC_DATA[0-7]

+3.3V_NORMAL

SW1

JTP-1127WEM

12

2.7K

R201

DEBUG

For ISP

Delete PV

4 3

1/16W

5%

+5V_NORMAL

G

D

HDMI_S/W_RESET

S

Q104 2N7002K

Debug

+3.3V_NORMAL

UART1_RX

UART1_TX

1

P100

12507WS-04L

1

DEBUG

2

3

4

5

+1.0V_VDD

LGE Internal Use Only

Max 360mA

AVDD10_DEMOD

L304

BLM18PG121SN1D

10uFC312

C318 0.1uF

C321 0.1uF

+1.0V_VDD

L302

BLM18PG121SN1D

LG1152A

IC101

VDD33

VDD33_CVBS

VDD33_HDMI

VDD33_XTAL

VDD25_VSB

VDD25_CVBS

VDD25_REF

VDD25_COMP

VDD25_AUD

VDD25_LVTX

VDD18_A

AVDD10_DEMOD

AVDD10_VSB

AVDD10_LVTX

VDDC_XTAL

+2.5V_NORMAL

For HDCP OTP Will be change to LOW for MP

For HeatSinK, AL Block / SMD Top

MDS62110218

M300

M303

M306

M307

MDS62110218

AVSS25_REF

M301

MDS62110218

M302

MDS62110218

M321

MDS62110218

P1

P2 P14 R14 F18 H16 M16

L15 R13 R12 V13 P10 R10

P9

R9

V7 J16

P6

P7

V6 B18 G12 G13

N1

N2

G6

G7 R15 K15 D17 D18

N7 L16

G4

N10 K16 D16

G5

G8

G9 G10 G11 G14 G15

H4

H5

H6

H7

H8

H9 H10 H11 H12 H13 H14 H15

J4

J5

J6

J7

OPT

VDD33_1 VDD33_2 AVDD33_CVBS_1 AVDD33_CVBS_2 AVDD33_HDMI_1 AVDD33_HDMI_2 VDD33_XTAL

VDD25_VSB VDD25_CVBS_2 VDD25_CVBS_1 VDD25_CVBS_3 AVDD25_REF VDD25_COMP_3 VDD25_COMP_1 VDD25_COMP_2 VDD25_COMP_4 VDD25_AAD VDD25_AUD_1 VDD25_AUD_2 VDD25_AUD_3 VDD25_LVTX_1 VDD25_LVTX_2 VDD25_LVTX_3

VDD18_1 VDD18_2

VDDC10_1 VDDC10_2 AVDD10_CVBS AVDD10_VSB AVDD10_LVTX_1 AVDD10_LVTX_2 AVDD10_LLPLL VDDC_XTAL

VQPS

AVSS25_REF GND_XTAL GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24

M304

MDS62110218

M305

MDS62110218

M324

MDS62110218

M323

MDS62110218

GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90

J8 J9 J10 J11 J12 J13 J14 J15 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M17 N4 N5 N6 N8 N9 N11 N12 N13 N14 N15 N16 P3 P4 P5 P13 P15 P16 R3 R16 R17 R18 T13 U13

SMD Bottom

M315

MDS62110204

M312

MDS62110204

M313

MDS62110204

M314

MDS62110204

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

LG1152AN-B2

+1.8V_NORMAL

10uFC421

+2.5V_NORMAL

L326

BLM18PG121SN1D

VDD18_A

10uFC422

Max 100mA

VDD25_CVBS

L324 BLM18PG121SN1D

10uFC414

C417 0.1uF

On Package Decap : 0.1uF *1ea

Max 50mA

L322

BLM18PG121SN1D

10uFC401

VDD25_AUD

+2.5V_NORMAL

On Package Decap : 0.1uF *1ea

+3.3V_NORMAL

Max 35mA

L319 BLM18PG121SN1D

10uFC398

VDD33_CVBS

C403 0.1uF

C408 0.1uF

On Package Decap : 0.1uF *1ea

For Tuner Sensitivity / Under DDR

M318

MDS62110204

M317

MDS62110204

M308

MDS62110204

M309

MDS62110208

M322

MDS62110208

For Tuner Sensitivity / Under TUNER

M310

MDS62110204

M311

MDS62110204

C423 0.1uF

C419 0.1uF

C409 0.1uF

GASKET_8.0X6.0X5.5H

GASKET_8.0X6.0X4.5H

10uFC305

Max 1mA

VDDC_XTAL

C313 0.1uF

+2.5V_NORMAL

+1.0V_VDD

10uFC359

L313

BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

+2.5V_NORMAL

L315 BLM18PG121SN1D

10uFC379

On Package Decap : 0.1uF *1ea

+3.3V_NORMAL

L323 BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

SMD TOP FOR ESD

For ATSC

L308 BLM18PG121SN1D

Max 250mA

VDD25_LVTX

10uFC375

C385 0.1uF

C386 0.1uF

Max 256mA

VDD33_HDMI

10uFC413

OPT

C405 0.1uF

M316

MDS62110217

M320

MDS62110217

M319

MDS62110217

Max 250mA

C416 0.1uF

OPT

10uFC366

C368 0.1uF

C390 0.1uF

VDD25_COMP

C407 0.1uF

Max 12mA

AVDD10_VSB

10uFC369

C393 0.1uF

C370 0.1uF

Max 10mA

VDD25_REF

L321 BLM15BD121SN1

L320

BLM15BD121SN1

AVSS25_REF

+3.3V_NORMAL

L309

BLM18PG121SN1D

+1.0V_VDD

L305

BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

+2.5V_NORMAL

L325

BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

C400 0.1uF

Max 1mA

VDD33_XTAL

10uFC371

C381 0.1uF

Max 35mA

AVDD10_LVTX

10uFC332

C333 0.1uF

Max 28mA

VDD25_VSB

10uFC415

C338 0.1uF

C418 0.1uF

+1.5V_Bypass Cap

+1.5V_DDR

L300

BLM18PG121SN1D

5V

ZD301

ESD_LG1152

VCC1.5V_MAIN

Max 40mA

VREF_M0

R300

1K 1%

0.1uF

R301

1K 1%

On Package Decap : 0.1uF *1ea

+1.5V_DDR

BLM18PG121SN1D

On Package Decap : 0.1uF *2ea

+0.9V_VDD

10uFC301

5V

ZD300

ESD_LG1152

On Package Decap : 0.1uF *6ea

+0.9V_VDD

On Package Decap : 0.1uF *1ea

+1.8V_NORMAL

L312

BLM18PG121SN1D

On Package Decap:0.1uF *1ea

+1.8V_NORMAL

On Package Decap:0.1uF *1ea

+3.3V_NORMAL

L310

BLM18PG121SN1D

On Package Decap : 0.1uF *1ea

C308

C300

L301

10uFC303

10uFC307

Max 20mA

10uFC347

Max 120mA

VDD18_LVTX

10uFC374

Max 93mA

VDD18_LVRX

L318

BLM18PG121SN1D

10uFC397

10uFC372

1000pF

C306 0.1uF

C314 0.1uF

C353 0.1uF

C382 0.1uF

C404 0.1uF

C377 0.1uF

10uFC326

C316 0.1uF

C310 0.1uF

Max 5900mA

C322 0.1uF

C319 0.1uF

C388 0.1uF

C383 0.1uF

(18)

10uFC302

C317 0.1uF

C311 0.1uF

C323 0.1uF

C320 0.1uF

On Package Decap : 0.1uF *3ea

Max 340mA

VCC1.5V_DE

C336 0.1uF

C340 0.1uF

C327 0.1uF

C325 0.1uF

VDD33

C392 0.1uF

C394 0.1uF

C399 0.1uF

C391 0.1uF

Max 680mA

VCC1.5V_MAIN

C329 0.1uF

C334 0.1uF

C337 0.1uF

VCC1.5V_MAIN

C342 0.1uF

R302

R303

C343 0.1uF

1K 1%

C346 0.1uF

Max 40mA

VREF_M1

0.1uF

C350

C362

On Package Decap : 0.1uF *1ea

Max 40mA

VCC1.5V_DE

R304

R305

VREF_M2

1K 1%

0.1uF

1K 1%

C363

C351

On Package Decap : 0.1uF *1ea

10uFC309

10uFC341

Max 6mA

C315 0.1uF

Max 1320mA

C345 0.1uF

MAIN_XTAL

C324 0.1uF

AVDD10_OSPREY

C348 0.33uF

+0.9V_VDD

+1.0V_VDD

L303 BLM18PG121SN1D

L306

BLM18PG121SN1D

On Package Decap : 0.1uF *3ea

+1.8V_NORMAL

L316

BLM18PG121SN1D

10uFC395

On Package Decap:0.1uF *1ea

+1.8V_NORMAL

+3.3V_NORMAL

BLM18PG121SN1D

L314

BLM18PG121SN1D

L317

10uFC396

VDD18_MAIN_XTAL

10uFC378

Max 48.8mA

VDD33_USB

C402 0.1uF

1000pF

C349 0.33uF

Max 49mA

VDD18

C410 0.1uF

Max 31mA

C384 0.1uF

C389 0.1uF

C406 0.1uF

C411 0.1uF

C304 0.1uF

For secure BOOT OTP

Will be change to LOW for MP

LG1152

MAIN POWER

VDD33_USB

VDD18_LVTX

VDD18_LVRX

VDD18_MAIN_XTAL

VCC1.5V_DE

VCC1.5V_MAIN

VREF_M1

VREF_M0

AVDD10_OSPREY

+0.9V_VDD

MAIN_XTAL

VDD18

LG1152D

VDD33

U8 U9

U10

V8

V9 V10 J21 K21

AA10 AA11

VDD18

W18 W19 Y18 Y19

AG28 AH27

AA7 AA8 AA9 AG1

AA12 AA13 AB12

J28 B28 G22

F9

G8

G9 G10 G11

H8

H9 H10 H11 F22 G13 G14 G16 G17 G18 G19 G20 G21 H13 H14 H16 H17 H18 H19 H20 H21

VREF_M2

L4 F13 G12 F14 G15

L20 M20 M21 M27 M28 N20 N21 P20 P21 R20 R21

K8

K9 K10 K11

L8

L9 L10 L11

M8

M9 M10 M11

N8

N9 N10 N11

P8

P9 P10 P11

R8

R9 R10 R11

Y7

Y8 AF1 F28

H22

AA19

G23

G7

H7 H12 H15

J7

J8

J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20

K7 K12

IC100

LG1152D-B1

VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 AVDD33_USB_1 AVDD33_USB_2 AVDD33_BT_USB_1 AVDD33_BT_USB_2

VDD18_1 VDD18_2 VDD18_3 VDD18_4 VDD18_5 VDD18_6 VDD18_LTX_1 VDD18_LTX_2 VDD18_LTX_3 VDD18_LTX_4 VDD18_LVRX_1 VDD18_LVRX_2 VDD18_LVRX_3 VDD18_DISPPLL VDD18_DR3PLL VDD18_MAIN_XTAL

VDD15_M2_1 VDD15_M2_2 VDD15_M2_3 VDD15_M2_4 VDD15_M2_5 VDD15_M2_6 VDD15_M2_7 VDD15_M2_8 VDD15_M2_9 VDD15_M0_1 VDD15_M0_2 VDD15_M0_3 VDD15_M0_4 VDD15_M0_5 VDD15_M0_6 VDD15_M0_7 VDD15_M0_8 VDD15_M0_9 VDD15_M0_10 VDD15_M0_11 VDD15_M0_12 VDD15_M0_13 VDD15_M0_14 VDD15_M0_15 VDD15_M0_16 VDD15_M0_17

VREF_M2_0 VREF_M1_0 VREF_M1_1 VREF_M0_0 VREF_M0_1

VDDC10_OSPREY_1 VDDC10_OSPREY_2 VDDC10_OSPREY_3 VDDC10_OSPREY_4 VDDC10_OSPREY_5 VDDC10_OSPREY_6 VDDC10_OSPREY_7 VDDC10_OSPREY_8 VDDC10_OSPREY_9 VDDC10_OSPREY_10 VDDC10_OSPREY_11

VDDC09_1 VDDC09_2 VDDC09_3 VDDC09_4 VDDC09_5 VDDC09_6 VDDC09_7 VDDC09_8 VDDC09_9 VDDC09_10 VDDC09_11 VDDC09_12 VDDC09_13 VDDC09_14 VDDC09_15 VDDC09_16 VDDC09_17 VDDC09_18 VDDC09_19 VDDC09_20 VDDC09_21 VDDC09_22 VDDC09_23 VDDC09_24 VDD09_LTX_1 VDD09_LTX_2 VDD09_LTX_3 AVDD09_DR3PLL

VDDC_MAIN_XTAL

SP_VQPS

GND_MAIN_XTAL

GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20

3

GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98

GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148

K13 K14 K15 K16 K17 K18 K19 K20 L7 L12 L13 L14 L15 L16 L17 L18 L19 L21 M7 M12 M13 M14 M15 M16 M17 M18 M19 N7 N12 N13 N14 N15 N16 N17 N18 N19 P7 P12 P13 P14 P15 P16 P17 P18 P19 R7 R12 R13 R14 R15 R16 R17 R18 R19 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 U7 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W20 W21 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y20 Y21 AA14 AA15 AA16 AA17 AA18 AA20 AA21 AB7 AB10 AB11 AB13 AB22

Place these close to tuner

LGE Internal Use Only

TU_CVBS

680pF C506

OPT

L503

SC_CVBS_IN

AV1_CVBS_IN

DSUB_B+

DSUB_G+

DSUB_R+

SC_B SC_G

SC_R

COMP1_Pb

COMP1_Y

COMP1_Pr

OPT

R3634

SCART_Lout

SCART_Rout

PC_L_IN

PC_R_IN

SC_L_IN

SC_R_IN

AV1_L_IN

AV1_R_IN

CHB_CVBS

2K

SC_FB

SC_ID

5.5V

C3625

470K

D503

5pF 50V

OPT

R601 470K

R607

EU R602

R603 470K

R617

L501

L500

L502

D504

5.5V

75 OPT

NON SCART

R525-*1

0

D506

D505

5.5V

OPT

R3633

+12V

2K

100K

Q505

CHB

5.5V

C528

R552

R554

OPT

C573 560pF 50V

C574 560pF 50V

OPT

220

D500

EU

R618 CHB

B

OPT

10pF

C572 330pF 50V

+5V_TU

EU

R525

75

D501

D502

5.5V

5.5V OPT

OPT

C546

10pF

C580

10pF

EU

R538

100K

EU

C525

2.2uF

10V

EU

R549

100K

L506

L509

C581 560pF 50V

OPT

EU

OPT

L508

E

C

R522

OPT

C579

C3626

1uH

C508

EU 150pF 50V

EU

L504

1uH

50V 150pF C511

R616

220

CHB

680pF C517 OPT

R521 100

10K

EU

C524

10pF

5pF 50V OPT

2.2uF

L507

OPT

10pF

10V

NON SCART

0

C605

10pF

C578

EU

C522

R524

R524-*1

2.7K

OPT

C606

10pF

C607

10pF

75

R595

R600

DSUB_VSYNC

DSUB_HSYNC

Near Place Scart AMP

SCART_Lout_SOC

SCART_Rout_SOC

C575 100pF 50V

C587 100pF 50V

C576 330pF 50V

EU

EU R608

470K

C577 100pF 50V

R609

470K

75

R594

C6006

1uF 25V C6001

Place JACK Side

C514 150pF 50V

EU

1uF25V

EU

C509 150pF

EU

75

R52 8

75

1%

R606

C586 560pF 50V

OPT

75

R52 9

EU

10K

R60 06

EU

10K R6005

C582 330pF 50V

OPT

75

1%

R605

L511

R53 0

75

EU L510

75 1%

R604

R614 75 1%

R615 75 1%

SCART_AMP_R_FB

SCART_AMP_L_FB

EU

C588 330pF 50V

C589 100pF 50V

DTV/MNT_V_OUT

R613 75

OPT

1%

SC_SOG_IN

10K

R555

DSUB_HSYNC DSUB_VSYNC

SC_SOG_IN

R553

Main clock for LG1152A

8pF

C513

8pF

C512

C500

R508 22K

2.2uF

C501

R509 22K

2.2uF

EU

2.2uF

R510

EU

R511

EU

R512 22K

R513 22K

22K

C502

C503

C504

C505

Place SOC Side

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+5V_NORMAL

EU

C510

0.1uF 16V

SOC_RESET

DTV/MNT_VOUT

Close to LG1152A

R536 68 R539 33 R541 68 R546 33 R547 0 R548 68 R550 33 R568 33 R569 33

R570 33 R564 150 R565 150 R566 0 R567 150

R514 75K

R515 100K

EU

R516 75K

EU

R517 100K

R518 75K

R519 100K

EU

R527

10K

SELECT

XIN_SUB

XO_SUB

R571 33 R572 33 R573 100

R559 68

R574 100 R551 33 R557 33 R575 33

R558 68

C516 0.047uF C518 0.047uF C523 0.047uF C526 0.047uF C527 1000pF C531 0.047uF C532 0.047uF C542 0.047uF C543 0.047uF C544 1000pF C545 0.047uF C538 0.047uF C539 0.047uF C540 1000pF C541 0.047uF

X-TAL_1

GND_1

1

2

X500

24MHz

4

3

GND_2

X-TAL_2

AUAD_L_CH5_IN

AUAD_R_CH5_IN

AUAD_L_CH4_IN

AUAD_R_CH4_IN

AUAD_L_CH3_IN

AUAD_R_CH3_IN

Q506

MMBT3904(NXP)

IC500

NLASB3157DFT2G

EU

R560 R561

0.047uF

R563 0

EU

22 22

1M

1

2

3

330

33

XIN_SUB

XO_SUB

6

VCC

5

A

4

Selece = High ==> A = B1 Selece = Low ==> A = B0

C549 C550 C551 C552 C553 C554 C555 C556 C557

C515

100pF

50V

EU

R579 R580

R535

C

E

B1

GND

B0

L17 L18 P17 K17 K18

M2 M1

R4

N3 M3

U14 T14 V15 U15 T15 U16 V14 T16 V16 V17 U17

P8

R8 P11 R11

U8

V8 V10

T8

V9 T11

U9

T9 U10 T10 V11 U11 V12 U12 T12

EU

XIN_SUB XO_SUB VSB_AUX_XIN XTLIN_AAD XTLOUT_AAD OPM1 OPM0

PORES_N

L9A_SCL L9A_SDA

CVBS_IN1 CVBS_IN2 CVBS_IN3 CVBS_VCM CVBS_IN4 CVBS_IN5 CVBS_IN6 CB_IN CB_VCM BUF_OUT1 BUF_OUT2

HSYNC VSYNC SC1_FB SC1_SID BINCOM_IN B_IN GINCOM_IN G_IN SOG_IN RINCOM_IN R_IN PB1_IN Y1_IN SOY1_IN PR1_IN PB2_IN Y2_IN SOY2_IN PR2_IN

B

EU

R507

10K

IC101

LG1152AN-B2

AAD_ADC_SIFM

AAD_ADC_SIF

AUDA_BGR_OUT

AUD_SCART0_OUTLN AUD_SCART0_OUTLP AUD_SCART0_OUTRN AUD_SCART0_OUTRP

AUAD_L_CH5_IN AUAD_R_CH5_IN AUAD_L_CH4_IN AUAD_R_CH4_IN AUAD_L_CH3_IN AUAD_R_CH3_IN AUAD_L_CH2_IN AUAD_R_CH2_IN AUAD_L_CH1_IN AUAD_R_CH1_IN

AUAD_VR_OUT

PHY0_RXCN_0 PHY0_RXCP_0 PHY0_RX0N_0 PHY0_RX0P_0 PHY0_RX1N_0 PHY0_RX1P_0 PHY0_RX2N_0 PHY0_RX2P_0

PHY0_ARC_OUT_0

ADC_I_INCOM

AUDA_OUTR

DTV_ATV_SELECT

AUDA_OUTL AUDA_OUTR

AUAD_REFN AUAD_REFP

AUMI_BIAS

AUMI_IN

AUMI_COM

DDCD0_DA DDCD0_CK

HPD0

ANTCON

RFAGC IFAGC

ADC_I_INP ADC_I_INN

AUDA_OUTL

+5V_NORMAL

R592

220

EU

Q504

MMBT3906(NXP)

N17 N18

U1 R1 R2 T1 V2 U2 T2

U3 V3 V4 T3 U5 T5 U6 T6 U7 T7

T4

10K U4 V5

R7 R5 R6

E18 E17 E16

J18 J17 H17 H18 G17 G18 G16 F16 F17

P12 M18 P18

T17 U18 T18

R624 100

R625 100

R593

220 EU

E

B

C

DTV/MNT_VOUT

C533 0.1uF C534 0.1uF

10uFC535

C536 2.2uF

AUDA_OUTL AUDA_OUTR

EU

AUAD_L_CH5_IN AUAD_R_CH5_IN AUAD_L_CH4_IN AUAD_R_CH4_IN AUAD_L_CH3_IN AUAD_R_CH3_IN

R534

R52010K

R577 4.7K R578 4.7K

0.1uF

C115

0.1uF

C116

0.1uF

C117

H/NIM&CHB

R626

22K

C604

0.01uF

R627

22K

R599

75

R501100

R502100

+3.3V_NORMAL

HDMI_CLKHDMI_CLK+ HDMI_RX0HDMI_RX0+ HDMI_RX1HDMI_RX1+ HDMI_RX2HDMI_RX2+

SPDIF_OUT_ARC

IF_AGC

C603

0.01uF

EU

OPT

C558

1000pF

OPT

22K

EU

R531

R532 22K

C5372.2uF C5472.2uF C5482.2uF

IF_N IF_P

HP_LOUT_MAIN

HP_ROUT_MAIN

IC101

LG1152AN-B2

L1

INTR_GBB

BB_TP_VAL BB_TP_SOP BB_TP_ERR BB_TP_CLK

BB_SDA_I BB_SDA_O

BB_SCL

L9DA_SCL

CHB_DN

CHB_UP CHB_START CHB_DATA0 CHB_DATA1 CHB_DATA2 CHB_DATA3 CHB_DATA4

CLK_F54M CVBS_GC2 CVBS_GC1 CVBS_GC0

CVBS_UP CVBS_DN

FS00CLK

DAC_DATA0 DAC_DATA1 DAC_DATA2 DAC_DATA3 DAC_DATA4 DAC_START

AAD_GC0 AAD_GC1 AAD_GC2 AAD_GC3 AAD_GC4

AAD_DATA0 AAD_DATA1 AAD_DATA2 AAD_DATA3 AAD_DATA4 AAD_DATA5 AAD_DATA6 AAD_DATA7 AAD_DATA8 AAD_DATA9

HSR_AM0 HSR_AP0 HSR_BM0 HSR_BP0 HSR_CM0

HSR_CP0 HSR_CLKM0 HSR_CLKP0

HSR_DM0

HSR_DP0

HSR_EM0

HSR_EP0

HSR_AM1

HSR_AP1

HSR_BM1

HSR_BP1

HSR_CM1

HSR_CP1 HSR_CLKM1 HSR_CLKP1

HSR_DM1

HSR_DP1

HSR_EM1

HSR_EP1

L2 L3

K1 K2 J2 J3 K3 H1 H2 H3 J1

G1 G2 G3 B1 C1 A4 B4 C4 A2 D1 D2 E2 E1 F1 F2 B2 A3 C2

B3 C3 D3 E3 F3 D4 E4 F4 D5 E5 F5 D6

A5 B5 C5 A6 B6 C6

E6 F6 D7 B7 C7 A8 B8 C8

Close to LG1152A

A7

R581 33

D8 F7 E7 E8 F8

Close to LG1152A

A9

R582 33

B9

R583 33

C9 D9 E9 F9 C10 D10

E10 F10 D11 E11 F11 D12 E12 F12 D13 E13 F13 D14 E14 F14 D15 E15

F15

B10 A10 A11 B11 C12 C11 B12 A12 A13 B13 C14 C13 B14 A14 A15 B15 C16 C15 B16 A16 A17 B17 C18 C17

C529

220pF

OPT

50V

INTR_HDMI1

R576100

ATV_OUT

TUNER_SIF

SCART_Lout_SOC

SCART_Rout_SOC

EU

C520 0.01uF

C521 0.01uF

TPI_SOP TPI_CLK TPO_ERR TPO_VAL TPO_SOP TPO_CLK

CHB_DATA JDVR_SCLK

CHB_VAL CHB_ERR

TU_CVBS

SCART_Lout SCART_Rout

SC_R

CHB_CVBS

SC_CVBS_IN SC_B SC_G SC_FB SC_ID ATV_OUT

SC_L_IN

SC_R_IN TUNER_SIF TUNER_SIF

DTV/MNT_V_OUT

JDVR_SCLK

IF_N IF_P IF_AGC

FE_TS_CLK

FE_TS_SYNC

FE_TS_VAL

TPI_DVB_ERR

FE_TS_DATA[0-7]

TPO_DATA[0-7]

TPI_DATA[0-7]

TPI_ERR

TPI_VAL

OPTIC_GPIO1 OPTIC_BACK_CHANNEL

INTR_AFE3CH

AUD_HMR00ARC AUD_HMR0AMUTE AUD_HMR0ALRCK

AUD_HMR0ABCK

AUD_HMR0ASD4

AUD_HMR0ASD3

AUD_HMR0ASD2

AUD_HMR0ASD1

AUD_HMR0ASD0

AUD_DAC1_LRCH

AUD_DAC1_SCK AUD_DAC1_LRCK

AUD_FS25CLK AUD_FS24CLK AUD_FS23CLK AUD_FS21CLK AUD_FS20CLK

AUDCLK_OUT_SUB

AUD_DAC0_LRCK AUD_DAC0_LRCH

AUD_DAC0_SCK

AUD_ADC_LRCH

AUD_ADC_SCK AUD_ADC_LRCK AUD_MIC_LRCH

AUD_MIC_SCK AUD_MIC_LRCK

BB_TP_DATA0

BB_TP_DATA1

BB_TP_DATA2

BB_TP_DATA3

BB_TP_DATA4

BB_TP_DATA5

BB_TP_DATA6

BB_TP_DATA7

L9DA_SDA_I L9DA_SDA_O

AUDCLK_OUT

AAD_DATAEN

DCO_OUT_CLK

R9112 33

AH2

INTR_GBB

AG2

INTR_HDMI1

AF2

INTR_AFE3CH

AH3

AUD_HMR0ARC

AG3

AUD_HMR0AMUTE

AG4

AUD_HMR0ALRCK

AF4

AUD_HMR0ABCK

AF3

AUD_HMR0ASD4

AH5

AUD_HMR0ASD3

AG5

AUD_HMR0ASD2

AF5

AUD_HMR0ASD1

AH4

AUD_HMR0ASD0

AH6

AUD_DAC1_LRCH

AG6

AUD_DAC1_SCK

AF6

AUD_DAC1_LRCK

AH7

AUD_FS25CLK

AG7

AUD_FS24CLK

AH10

AUD_FS23CLK

AG10

AUD_FS21CLK

AF10

AUD_FS20CLK

AH8

AUDCLK_OUT_SUB

AF7

AUD_DAC0_LRCK

AE8

AUD_DAC0_LRCH

AD8

AUD_DAC0_SCK

AE7

AUD_ADC_LRCH

AD7

AUD_ADC_SCK

AC8

AUD_ADC_LRCK

AG8

AUD_MIC_LRCH

AH9

AUD_MIC_SCK

AF8

AUD_MIC_LRCK

AG9

BB_TPI_DATA0

AF9

BB_TPI_DATA1

AE9

BB_TPI_DATA2

AD9

BB_TPI_DATA3

AC9

BB_TPI_DATA4

AE10

BB_TPI_DATA5

AD10

BB_TPI_DATA6

AC10

BB_TPI_DATA7

AE11

BB_TPI_VAL

AD11

BB_TPI_SOP

AC11

BB_TPI_ERR

AE12

BB_TPI_CLK

AH11

BB_SDA_I

AG11

BB_SDA_O

AF11

BB_SCL

AH12

HS_SCL

AG12

HS_SDA_I

AF12

HS_SDA_O

AD12

CHB_DN

AC12

CHB_UP

AE13

CHB_START

AG13

CHB_DATA0

AF13

CHB_DATA1

AH14

CHB_DATA2

AG14

CHB_DATA3

AF14

CHB_DATA4

AH13

CLK_54

AE14

CVBS_GC2

AC13

CVBS_GC1

AD13

CVBS_GC0

AD14

CVBS_UP

AC14

CVBS_DN

AH15

FS00CLK

AG15

AUDCLK_TO_DIGITAL

AF15

DAC_DATA0

AE15

DAC_DATA1

AD15

DAC_DATA2

AC15

DAC_DATA3

AF16

DAC_DATA4

AE16

DAC_START

AD16

AAD_GC0

AC16

AAD_GC1

AE17

AAD_GC2

AD17

AAD_GC3

AC17

AAD_GC4

AE18

AAD_DATAEN

AD18

AAD_DATA0

AC18

AAD_DATA1

AE19

AAD_DATA2

AD19

AAD_DATA3

AC19

AAD_DATA4

AE20

AAD_DATA5

AD20

AAD_DATA6

AC20

AAD_DATA7

AE21

AAD_DATA8

AD21

AAD_DATA9

AC21

AUPLL_CLK

AG16

HS_RX1_AM

AH16

HS_RX1_AP

AH17

HS_RX1_BM

AG17

HS_RX1_BP

AF18

HS_RX1_CM

AF17

HS_RX1_CP

AG18

HS_RX1_CLKM

AH18

HS_RX1_CLKP

AH19

HS_RX1_DM

AG19

HS_RX1_DP

AF20

HS_RX1_EM

AF19

HS_RX1_EP

AG20

HS_RX2_AM

AH20

HS_RX2_AP

AH21

HS_RX2_BM

AG21

HS_RX2_BP

AF22

HS_RX2_CM

AF21

HS_RX2_CP

AG22

HS_RX2_CLKM

AH22

HS_RX2_CLKP

AH23

HS_RX2_DM

AG23

HS_RX2_DP

AF24

HS_RX2_EM

AF23

HS_RX2_EP

IC100

LG1152D-B1

STPIO_SOP/GPIO43 STPIO_VAL/GPIO42 STPIO_ERR/GPIO41

STPIO_DATA/GPIO40

TPI_DVB_CLK/GPIO47 TPI_DVB_SOP/GPIO46 TPI_DVB_VAL/GPIO45

TPI_DVB_DATA0/GPIO44

PCMI3LRCK/GPIO81

AUD_SUBSCK/GPIO51

AUD_SUBLRCK/GPIO52

STPI_CLK STPI_SOP STPI_VAL

STPI_ERR STPI_DATA STPIO_CLK

TPI_DVB_ERR

TPI_DVB_DATA1 TPI_DVB_DATA2 TPI_DVB_DATA3 TPI_DVB_DATA4 TPI_DVB_DATA5 TPI_DVB_DATA6 TPI_DVB_DATA7

TPI_CLK TPI_SOP TPI_VAL

TPI_ERR TPI_DATA0 TPI_DATA1 TPI_DATA2 TPI_DATA3 TPI_DATA4 TPI_DATA5 TPI_DATA6 TPI_DATA7

TPO_CLK

TPO_SOP

TPO_VAL

TPO_ERR TPO_DATA0 TPO_DATA1 TPO_DATA2 TPO_DATA3 TPO_DATA4 TPO_DATA5 TPO_DATA6 TPO_DATA7

AUDCLK_OUT

DACLRCH

DACSLRCH/GPIO95 DACCLFCH/GPIO94

DACSCK

DACLRCK

PCMI3LRCH

PCMI3SCK/GPIO80

IEC958OUT

AUD_SUBMCK

AUD_SUBLRCH

BTSCSEL

DTS_EN

TXA0N TXA0P TXA1N TXA1P TXA2N

TXA2P TXACLKN TXACLKP

TXA3N

TXA3P

TXA4N

TXA4P

TXB0N

TXB0P

TXB1N

TXB1P

TXB2N

TXB2P TXBCLKN TXBCLKP

TXB3N

TXB3P

TXB4N

TXB4P

PWM0/GPIO55 PWM1/GPIO54 PWM2/GPIO53

PWM_IN

AR102

CHB

AE27 AE26 AD28 AD27 AD26 AC28 AC26 AB28 AC27 AB27

AF27 AE28 AG27 AF28 AG26 AF26 AF25 AH26 AH25 AG25 AH24 AG24

H24 J25 J24 H25 J27 J26 H28 H27 H26 G28 G27 G26

D24 E23 D25 D23 H23 G25 G24 F25 F24 F23 E25 E24

C1 C2 A3 A2 B2 B1

B3 C3 A4

AE2

AD25 AC25 AD24 AE25

AB18 AB19

DTS_EN: ENABLE(’1’) (for development)

BTSC_EN: ENABLE(’1’) (for development)

N1 N2 P2 P1 P3 R3 R1 R2 T2 T1 T3 U3 U1 U2 V2 V1 V3 W3 W1 W2 Y2 Y1 Y3 AA3

L6 L5 M4 M5

47

R200

47

FE_TS_DATA[0] FE_TS_DATA[1] FE_TS_DATA[2] FE_TS_DATA[3] FE_TS_DATA[4] FE_TS_DATA[5] FE_TS_DATA[6] FE_TS_DATA[7]

R542100

100

100 100

OPTIC_BACK_CHANNEL

R598 47

OPT

R619 47

OPT

R628 22

OPT

R629 47

+3.3V_NORMAL

R59622 R59722

SOC_TXA0N SOC_TXA0P SOC_TXA1N SOC_TXA1P SOC_TXA2N SOC_TXA2P SOC_TXACLKN SOC_TXACLKP SOC_TXA3N SOC_TXA3P SOC_TXA4N SOC_TXA4P SOC_TXB0N SOC_TXB0P SOC_TXB1N SOC_TXB1P SOC_TXB2N SOC_TXB2P SOC_TXBCLKN SOC_TXBCLKP SOC_TXB3N SOC_TXB3P SOC_TXB4N SOC_TXB4P

OPT EDGE_LED

BPL_IN

CHB

33

R556

TPI_DATA[0] TPI_DATA[1] TPI_DATA[2] TPI_DATA[3] TPI_DATA[4] TPI_DATA[5] TPI_DATA[6] TPI_DATA[7]

TPO_DATA[0] TPO_DATA[1] TPO_DATA[2] TPO_DATA[3] TPO_DATA[4] TPO_DATA[5] TPO_DATA[6] TPO_DATA[7]

R543

R544 R545

OPTIC_GPIO1

R631 R632

R633

R630 100

10K

100

CHB_CLK CHB_SYNC CHB_VAL CHB_ERR CHB_DATA

USB_CTL2

FE_TS_CLK FE_TS_SYNC FE_TS_VAL TPI_DVB_ERR FE_TS_DATA[0-7]

TPI_CLK TPI_SOP TPI_VAL TPI_ERR TPI_DATA[0-7]

TPO_CLK TPO_SOP TPO_VAL TPO_ERR TPO_DATA[0-7]

AUD_MASTER_CLK AUD_LRCH

FRC3_FLASH_WP AUD_SCK AUD_LRCK

C559

OPT

2.2uF

C630 82pF 50V

AMP_RESET_N

A_DIM PWM_DIM2 PWM_DIM

SPDIF_OUT

LG1152A LG1152D

LG1152 B0

MAIN AUDIO/VIDEO

3

IC100

LGE Internal Use Only

LG1152D-B1

M0_DDR_RESET_N

M0_DDR_DQSL_P M0_DDR_DQSL_N

M0_DDR_DQSU_P M0_DDR_DQSU_N

M0_DDR_ZQCAL

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_DML M0_DDR_DMU

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ2 M0_DDR_DQ3 M0_DDR_DQ4 M0_DDR_DQ5 M0_DDR_DQ6 M0_DDR_DQ7 M0_DDR_DQ8 M0_DDR_DQ9

M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15

D18 E17 E18 E20 E16 D20 F16 F19 E15 D19 D14 E14 D17 F18 D16

F20 D15 F17

A17 A18 F15

F21 D22 E21 D21

E19

B20 A20

B16 C16

C19 C15

C20 B19 C21 B18 A21 C18 B21 A19 B17 C14 A16 B14 B15 A14 C17 A15 E22

R700 0 R701 0

SIGN50005

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8 M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_DDR_CKE

M0_DDR_ODT M0_DDR_RASN M0_DDR_CASN M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSL_P M0_DDR_DQSL_N

M0_DDR_DQSU_P M0_DDR_DQSU_N

M0_DDR_DML M0_DDR_DMU

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ2 M0_DDR_DQ3 M0_DDR_DQ4 M0_DDR_DQ5 M0_DDR_DQ6 M0_DDR_DQ7 M0_DDR_DQ8 M0_DDR_DQ9 M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15

240

1%

M0_DDR_CLK M0_DDR_CLKN

R704

VCC1.5V_MAIN

R709 10K

R705 200

R706 200

M0_DDR_CKE

M0_DDR_RESET_N

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CLK

M0_DDR_CLKN

IC700

H5TQ2G83BFR-PBC

DDR3

K4

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSL_P M0_DDR_DQSL_N

R742 10K

M0_DDR_DML

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ6

M0_DDR_DQ4 M0_DDR_DQ3 M0_DDR_DQ2 M0_DDR_DQ5

2Gbit

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

VREFCA

VREFDQ

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

NC_S1 NC_S2 NC_S3 NC_S4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9

M0_DDR_VREFCA

M0_DDR_VREFDQ

J9

E2

VCC1.5V_MAIN

R720

H9

ZQ

240

1% A3 A10 D8 G3 G9 K2 K10 M2 M10

B10 C2 E3 E10

A1 A11 N1 N11

A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10

B3 B9 C10 D2 D10

C706 0.1uF C707 C708 C709

C710

C711

C712

0.1uF

VCC1.5V_MAIN

R722

R723

1K 1%

VCC1.5V_MAIN

R724

R725

1K 1%

C724

1K 1%

C725

M0_DDR_VREFCA

0.1uF

C728

M0_DDR_VREFDQ

0.1uF

C729

1000pF

VCC1.5V_MAIN

R730

R731

1K 1%

VCC1.5V_MAIN

R732

R733

1K 1%

M0_1_DDR_VREFCA

1K 1%

C732

M0_1_DDR_VREFDQ

1K 1%

C733

0.1uF

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7

1000pF

M0_DDR_A8

1000pF

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_DDR_CLK

M0_DDR_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQSU_P M0_DDR_DQSU_N

M0_DDR_DMU

M0_DDR_DQ10 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ11M0_DDR_DQ7 M0_DDR_DQ15

M0_DDR_DQ9 M0_DDR_DQ8

M0_DDR_DQ12

C747

C748

H5TQ2G83BFR-PBC

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

IC703

DDR3 2Gbit

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

NC_S1 NC_S2 NC_S3 NC_S4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

M0_1_DDR_VREFCA

J9

E2

H9

ZQ

A3 A10 D8 G3 G9 K2 K10 M2 M10

B10 C2 E3 E10

A1 A11 N1 N11

A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10

B3 B9 C10 D2 D10

M0_1_DDR_VREFDQ

R739

240 1%

VCC1.5V_MAIN

C758

C746

C723

C760

C751

C756

0.1uF

C761

0.1uF

IC100

LG1152D-B1

C9 E9 F10 F12 F8 D11 E8 E11 E7 D10 C4 C5 D8 E10 C7

E12 F7 D9

A9 B9 D7

D13 C13 E13 D12

F11

C12 C11

A7 B7

A11 C6

A12 B11 A13 C10 B12 A10 B13 B10 A8 B4 C8 B5 B6 A5 B8 A6

R702 0 R703 0

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8 M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_DDR_CLK M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT M1_DDR_RASN M1_DDR_CASN M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSL_P M1_DDR_DQSL_N

M1_DDR_DQSU_P M1_DDR_DQSU_N

M1_DDR_DML M1_DDR_DMU

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7 M1_DDR_DQ8 M1_DDR_DQ9 M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15

VCC1.5V_MAIN

M1_DDR_CKE

R710 10K

M1_DDR_RESET_N

M1_DDR_CLK

R707 200

M1_DDR_CLKN

M1_DDR_CLK

R708 200

M1_DDR_CLKN

IC100

LG1152D-B1

R741 10K

M2_DDR_A0 M2_DDR_A1 M2_DDR_A2 M2_DDR_A3 M2_DDR_A4 M2_DDR_A5 M2_DDR_A6 M2_DDR_A7 M2_DDR_A8

M2_DDR_A9 M2_DDR_A10 M2_DDR_A11 M2_DDR_A12 M2_DDR_A13

M2_DDR_BA0 M2_DDR_BA1 M2_DDR_BA2

M2_DDR_CLK

M2_DDR_CLKN

M2_DDR_CKE

M2_DDR_ODT

M2_DDR_RASN M2_DDR_CASN

M2_DDR_WEN

M2_DDR_RESET_N

M2_DDR_DQSU_P M2_DDR_DQSU_N

M2_DDR_DQSL_P M2_DDR_DQSL_N

M2_DDR_DML M2_DDR_DMU

M2_DDR_DQ0 M2_DDR_DQ1 M2_DDR_DQ2 M2_DDR_DQ3 M2_DDR_DQ4 M2_DDR_DQ5 M2_DDR_DQ6 M2_DDR_DQ7 M2_DDR_DQ8 M2_DDR_DQ9

M2_DDR_DQ10 M2_DDR_DQ11 M2_DDR_DQ12 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15

M2_DDR_ZQCAL

M1_DDR_RESET_N

M1_DDR_DQSL_P M1_DDR_DQSL_N

D1 K4 D2 E5 H6 E4 J4 D6 J5 D3 H4 J6 K5 D4

E6 H5 F4

M2 M3 G6

F6 G5 G4 F5

D5

H3 J1

H1 H2

K3 F2

F1 L1 E3 L2 E1 M1 E2 L3 J3 G1 K2 F3 J2 G2 K1 G3 K6

M2_DDR_A0 M2_DDR_A1 M2_DDR_A2 M2_DDR_A3 M2_DDR_A4 M2_DDR_A5 M2_DDR_A6 M2_DDR_A7 M2_DDR_A8 M2_DDR_A9 M2_DDR_A10 M2_DDR_A11 M2_DDR_A12 M2_DDR_A13

M2_DDR_BA0 M2_DDR_BA1 M2_DDR_BA2

M2_DDR_CKE

M2_DDR_ODT M2_DDR_RASN M2_DDR_CASN M2_DDR_WEN

M2_DDR_RESET_N

M2_DDR_DQSU_P M2_DDR_DQSU_N

M2_DDR_DQSL_P M2_DDR_DQSL_N

M2_DDR_DML M2_DDR_DMU

M2_DDR_DQ0 M2_DDR_DQ1 M2_DDR_DQ2 M2_DDR_DQ3 M2_DDR_DQ4 M2_DDR_DQ5 M2_DDR_DQ6 M2_DDR_DQ7 M2_DDR_DQ8 M2_DDR_DQ9 M2_DDR_DQ10 M2_DDR_DQ11 M2_DDR_DQ12 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15

240

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8

M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSL_P M1_DDR_DQSL_N

M1_DDR_DQSU_P M1_DDR_DQSU_N

M1_DDR_DML M1_DDR_DMU

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7 M1_DDR_DQ8 M1_DDR_DQ9

M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8

M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DML

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ6 M1_DDR_DQ7 M1_DDR_DQ4 M1_DDR_DQ3 M1_DDR_DQ2 M1_DDR_DQ5

R711

1%

M2_DDR_CLK M2_DDR_CLKN

H5TQ2G83BFR-PBC

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8

J3 K9 J4

F8 G8

G10

H3 G2 F4 G4 H4

N3

C4 D4

B8 A8

B4 C8 C3 C9 E4 E9 D3 E8

A4 F2

F10

H2

H10

J8

M2_DDR_CLK

M2_DDR_CLKN

VCC1.5V_DE

R712

1K 1%

R713

1K 1%

IC701

DDR3 2Gbit

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQS DQS

DM/TDQS NF/TDQS

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6

VCC1.5V_DE

M2_DDR_VREFCA

C700

VREFCA

VREFDQ

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

R714 10K

M2_DDR_RESET_N M2_CLK

M2_CLK

R715 150

M2_CLKN

R716 0 R717 0

0.1uF 1000pF

C701

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

NC_S1 NC_S2 NC_S3 NC_S4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9

ZQ

VCC1.5V_DE

R718

R719

J9

E2

H9

A3 A10 D8 G3 G9 K2 K10 M2 M10

B10 C2 E3 E10

A1 A11 N1 N11

A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10

B3 B9 C10 D2 D10

M2_DDR_CKE

M2_CLK M2_CLKN

1K 1%

M1_DDR_VREFCA

R721

240 1%

M2_DDR_VREFDQ

0.1uF

C702

C703

M1_DDR_VREFDQ

VCC1.5V_MAIN

C713 C714 C715 C716 C717 C718 C719

R743 10K

1000pF

0.1uF

M2_DDR_RESET_N

M2_DDR_A0 M2_DDR_A1 M2_DDR_A2 M2_DDR_A3 M2_DDR_A4 M2_DDR_A5 M2_DDR_A6 M2_DDR_A7 M2_DDR_A8

M2_DDR_A9 M2_DDR_A10 M2_DDR_A11 M2_DDR_A12 M2_DDR_A13

M2_DDR_BA0 M2_DDR_BA1 M2_DDR_BA2

M2_CLKN

M2_DDR_CKE

M2_DDR_ODT

M2_DDR_RASN M2_DDR_CASN

M2_DDR_WEN

M2_DDR_DQSL_P M2_DDR_DQSL_N

M2_DDR_DQSU_P M2_DDR_DQSU_N

M2_DDR_DML M2_DDR_DMU

M2_DDR_DQ0 M2_DDR_DQ1 M2_DDR_DQ2 M2_DDR_DQ3 M2_DDR_DQ4 M2_DDR_DQ5 M2_DDR_DQ6 M2_DDR_DQ7

M2_DDR_DQ8 M2_DDR_DQ9

M2_DDR_DQ10 M2_DDR_DQ11 M2_DDR_DQ12 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15

VCC1.5V_MAIN

R726

R727

1K 1%

VCC1.5V_MAIN

R728

R729

1K 1%

M1_DDR_VREFCA

1K 1%

C726

M1_DDR_VREFDQ

1K 1%

C727

0.1uF 1000pF

C730

0.1uF 1000pF

C731

IC702

H5TQ1G63DFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9

NC_1 NC_2 NC_3 NC_4 NC_6

ZQ

VCC1.5V_MAIN

R734

R735

VCC1.5V_MAIN

R736

R737

M2_DDR_VREFCA

M8

H1

L8

VCC1.5V_DE

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1 J9 L1 L9 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M1_1_DDR_VREFCA

1K 1%

C734

M1_1_DDR_VREFDQ

1K 1%

C735

M2_DDR_VREFDQ

SIGN50000

C736 C737 C738 C739 C740 C741 C742 C743

C744

IC704

H5TQ2G83BFR-PBC

DDR3

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5

0.1uF

C749

0.1uF

C750

R738

C722

0.1uF

C704

0.1uF

C705

0.1uF

C720

0.1uF

C721

0.1uF

0.1uF 10uF

M1_DDR_A6 M1_DDR_A7

1000pF

M1_DDR_A8

M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_DDR_CLK

M1_DDR_CLKN

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN

1000pF

M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQSU_P M1_DDR_DQSU_N

M1_DDR_DMU

M1_DDR_DQ10 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ11 M1_DDR_DQ15

M1_DDR_DQ9 M1_DDR_DQ8

M1_DDR_DQ12

240

10V

DDR3 1.5V bypass Cap - Place these caps near Memory

K4

A0

2Gbit

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC

N4

A13

N8

A14

J3

BA0

K9

BA1

J4

BA2

F8

CK

G8

CK

G10

CKE

H3

CS

G2

ODT

F4

RAS

G4

CAS

H4

WE

N3

RESET

C4

DQS

D4

DQS

B8

DM/TDQS

A8

NF/TDQS

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A4

NC_1

F2

NC_2

F10

NC_3

H2

NC_4

H10

NC_5

J8

NC_6

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

NC_S1 NC_S2 NC_S3 NC_S4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

M1_1_DDR_VREFCA

J9

E2

H9

ZQ

A3 A10 D8 G3 G9 K2 K10 M2 M10

B10 C2 E3 E10

A1 A11 N1 N11

A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10

B3 B9 C10 D2 D10

M1_1_DDR_VREFDQ

R740

240 1%

VCC1.5V_MAIN

C757

C752

C753

C754

C755

C745

C759

0.1uF

LG1152 B0

4MAIN DDR 50

+5V_CI_ON

LGE Internal Use Only

CI HOST I/F

PCM_RST

/PCM_WAIT

PCM_INPACK

/PCM_IORD /PCM_IOWR

R6202 R6203 R6200

CI_IN_TS_DATA[0-7]

R6211

10K

OPT

CI

22

CI

22

OPT

22

+5V_CI_ON

R6204

10K

OPT

R6205

10K

OPT

CI_VS1

PCM_INPACK

/PCM_CE2

R6206 10K

+5V_CI_ON

OPT

R6207 10K

CI

C6200

0.1uF CI

/CI_CD1

CI_TS_DATA[3]

CI_TS_DATA[4] CI_TS_DATA[5] CI_TS_DATA[6] CI_TS_DATA[7]

/PCM_CE2

CI_VS1

CI_IN_TS_DATA[0] CI_IN_TS_DATA[1] CI_IN_TS_DATA[2] CI_IN_TS_DATA[3]

CI_IN_TS_DATA[4] CI_IN_TS_DATA[5] CI_IN_TS_DATA[6] CI_IN_TS_DATA[7]

CI_TS_CLK

/PCM_REG

CI_TS_VAL

CI_TS_SYNC CI_TS_DATA[0] CI_TS_DATA[1] CI_TS_DATA[2]

/CI_CD2

C6201 10uF 10V

CI

R6249

R6208

10K

OPT

0 OPT

R6210

R6209

10K

OPT

5V <=> 3.3V

IC904

74LVC245A

DIR

1

A0

2

A1

3

A2

4

A3

5

A4

CI

6

A5

7

A6

8

A7

9

GND

10

IC905

74LVC1G00GW

1B 5 VCC

2A

3GND

CI

AND GATE => NAND GATE

20

19

18

17

16

15

14

13

12

11

4 Y

+3.3V_NORMAL

VCC

OE

B0

B1

B2

B3

B4

B5

B6

B7

CI

+3.3V_NORMAL

CI

C903

0.1uF

16V

C904

0

0.1uF R913

16V

OPT

EB_DATA[0]

EB_DATA[1]

EB_DATA[2]

EB_DATA[3]

EB_DATA[4]

EB_DATA[5]

EB_DATA[6]

EB_DATA[7]

DIR

/PCM_CE1

EB_DATA[0-7]

CI_ADDR[11] CI_ADDR[9]

CI_ADDR[13]

R6243 22

C6206

0.1uF

16V

CI_ADDR[12]

CI_ADDR[7] CI_ADDR[6] CI_ADDR[5]

CI_ADDR[4]

CI_ADDR[3]

CI_ADDR[2] CI_ADDR[1] CI_ADDR[0]

CI_DATA[0-7]

OPT

+5V_CI_ON

CI_ADDR[10]

CI_ADDR[11] CI_ADDR[9] CI_ADDR[8] CI_ADDR[13] CI_ADDR[14]

CI_ADDR[12] CI_ADDR[7] CI_ADDR[6] CI_ADDR[5] CI_ADDR[4] CI_ADDR[3] CI_ADDR[2] CI_ADDR[1] CI_ADDR[0]

/PCM_CE1

+5V_CI_ON

R6245

10K

OPT

+5V_CI_ON

R6244

10K

CI

R6246

10K

/PCM_OE

OPT

/PCM_WE /PCM_IRQA

CI_DATA[0-7]

CI_DATA[0] CI_DATA[1] CI_DATA[2] CI_DATA[3]

CI_DATA[0-7]

CI_DATA[4] CI_DATA[5] CI_DATA[6] CI_DATA[7]

DIR

CI

AR909

33

CI

AR910

33

WE=>OE

IOWE=>IORD

/PCM_OE

/PCM_IORD

P6200

10067972-000LF CI

GND

/CI_DET1

TS_OUT3 TS_OUT4 TS_OUT5 TS_OUT6 TS_OUT7

CARD_EN2

IORD IOWR

TS_IN_SYN

TS_IN0 TS_IN1 TS_IN2 TS_IN3

TS_IN4 TS_IN5 TS_IN6 TS_IN7

TS_OUT_CLK

CI_RESET

CI_WAIT

INPACK

TS_OUT_VAL TS_OUT_SYN

TS_OUT0 TS_OUT1 TS_OUT2

/CI_DET2

35 36 37 38 39 40 41 42

VS1

43 44 45 46 47 48 49 50

VCC

51

VPP

52 53 54 55 56 57 58 59 60

REG

61 62 63 64 65 66 67

GND

68

69

100

R6214

CI

0

R6213

OPT

CI

R6212 0

CI

R6215 100

0

OPT

GND

1

DAT3

2

DAT4

3

DAT5

4

DAT6

5

DAT6

6

/CARD_EN1

7

ADDR10

8

/O_EN

9

ADDR11

10

ADDR10

11

ADDR8

12

ADDR13

13

ADDR14

14

/WR_EN

15

/IRQA

16

VCC

17

VPP

18

TS_IN_VAL

19

TS_IN_CLK

20

ADDR12

21

ADDR7

22

ADDR6

23

ADDR5

24

ADDR4

25

ADDR3

26

ADDR2

27

ADDR1

28

ADDR0

29

DAT0

30

DAT1

31

DAT2

32

/IO_BIT

33

GND

34

G1G2

R6216

R6217

R6219

10K

OPT

CI_DATA[3] CI_DATA[4] CI_DATA[5] CI_DATA[6] CI_DATA[7]

CI

R6224 22

C6205 0.1uF

0

OPT

10K

OPT

CI

CI_DATA[0] CI_DATA[1] CI_DATA[2]

CI_IN_TS_VAL CI_IN_TS_CLK

CI_IN_TS_SYNC

CI_ADDR[10]

CI_ADDR[8]

CI_ADDR[14]

CI

TPO_DATA[0-7]

TPO_CLK TPO_SOP TPO_VAL TPO_ERR

TPO_DATA[0] TPO_DATA[1] TPO_DATA[2] TPO_DATA[3] TPO_DATA[4] TPO_DATA[5] TPO_DATA[6] TPO_DATA[7]

CI

AR904

33

AR905

CI

AR903

33

CI 33

CI_IN_TS_DATA[0] CI_IN_TS_DATA[1] CI_IN_TS_DATA[2] CI_IN_TS_DATA[3] CI_IN_TS_DATA[4] CI_IN_TS_DATA[5] CI_IN_TS_DATA[6] CI_IN_TS_DATA[7]

CI_IN_TS_CLK CI_IN_TS_SYNC CI_IN_TS_VAL

CI_ADDR[0] CI_ADDR[1] CI_ADDR[2] CI_ADDR[3]

CI_ADDR[4] CI_ADDR[5] CI_ADDR[6] CI_ADDR[7]

CI_ADDR[8]

CI_ADDR[9] CI_ADDR[10] CI_ADDR[11]

BUFFER FOR 5V => 3.3V

/CI_CD2

/CI_CD1

+5V_NORMAL

CI

10K

R915

CI C905

0.1uF 16V

CI

10K

R916

CI C906

0.1uF 16V

CI_TS_DATA[7] CI_TS_DATA[6] CI_TS_DATA[5] CI_TS_DATA[4]

CI_TS_DATA[3] CI_TS_DATA[2] CI_TS_DATA[1] CI_TS_DATA[0]

PCM_INPACK

CI_TS_CLK

CI_TS_VAL

CI_TS_SYNC

/PCM_WAIT

/PCM_IRQA

AR921

AR920

AR919

CI

100

CI

100

CI

100

GND_8

VCC_4

GND_7

GND_6

VCC_3

GND_5

2OE

48

1A0

47

1A1

46

45

1A2

44

1A3

43

42

2A0

41

2A1

40

39

2A2

38

2A3

37

3A0

36

3A1

35

34

3A2

33

3A3

32

31

4A0

30

4A1

29

28

4A2

27

4A3

26

3OE

25

CI

AR911

33

CI

AR912

33

CI

AR913

33

IC903

74LVC16244ADGG

CI

EB_ADDR[0] EB_ADDR[1] EB_ADDR[2] EB_ADDR[3]

EB_ADDR[4] EB_ADDR[5] EB_ADDR[6] EB_ADDR[7]

EB_ADDR[8] EB_ADDR[9] EB_ADDR[10] EB_ADDR[11]

+3.3V_NORMAL

1OE

1

1Y0

2

1Y1

3

GND_1

4

1Y2

5

1Y3

6

VCC_1

7

2Y0

8

2Y1

9

GND_2

10

2Y2

11

2Y3

12

3Y0

13

3Y1

14

GND_3

15

3Y2

16

3Y4

17

VCC_2

18

4Y0

19

4Y1

20

GND_4

21

4Y2

22

4Y3

23

4OE

24

CI_ADDR[12] CI_ADDR[13] CI_ADDR[14]

/PCM_REG

/PCM_OE

/PCM_WE /PCM_IORD /PCM_IOWR

C900

0.1uF

16V

CI

CAM_WAIT_N CAM_IREQ_N

CAM_CD2_N

CAM_CD1_N

CAM_INPACK_N

75

AR916

CI

33

AR915

AR914

CI

AR918 75

75

TPI_DATA[3]

TPI_DATA[2]

TPI_DATA[1]

TPI_DATA[0]

EB_ADDR[12] EB_ADDR[13] EB_ADDR[14] CAM_REG_N

EB_OE_N EB_WE_N EB_BE_N1 EB_BE_N0

CI

AR917

TPI_CLK

TPI_VAL

TPI_SOP

TPI_DATA[7]

TPI_DATA[6]

TPI_DATA[5]

TPI_DATA[4]

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

RL_ON

LGE Internal Use Only

+3.5V_ST

eMMC POWER

+3.3V_NORMAL

L2319

BLM18PG121SN1D

C2371

0.1uF 16V

1

+3.5V_ST

L2301 BLM18PG121SN1D

C2301

4.7uF 10V

POWER_ON/OFF1

+12V

R2305 10K

C2306

0.1uF 50V

3.3V_EMMC

R2300 10K

+3.5V_ST

10K

1

R2306

2

3

L2303

BLM18SG121TN1D

C2307

0.1uF 16V

CIS21J121

L2302

+1.8V_NORMAL

C2372

0.1uF 16V

+1.8V

AP7173-SPG-13 HF(DIODES)

IN

1

PG

2

VCC

3

EN

4

1.5A

Q2301 MMBT3906(NXP)

GND/P.DIM2

PWM_DIM2

EMMC_VCCQ

L2306 BLM18PG121SN1D

IC2300

9

THERMAL

OPT P2301 FW20020-24S

PWR ON

24V GND GND

3.5V

3.5V GND GND 12V 12V 12V

SMAW200-H24S2

1

1 3

3 5

5 7

7 9

9 11

11 13

13 15

15 17

17 19

19 21

21 22 23

23 24

25

P2300

2

2 4

4 6

6 8

8

10

10 12

12 14

14 16

16 18

18 20

20 22 24

24V 24V GND GND

3.5V

3.5V GND GND/V-sync INV ON A.DIM P.DIM1 Err OUT

LPB

R2302 100

CIS21J121

Tuner 1.25V REG Input

+3.3V_TU

293 mA

[EP]

OUT

8

FB

7

SS

6

GND

5

C2308 2200pF 50V

1/16W

R2314 3K 1%

R2315 100 1%

3.9K R2321

R2

1%

+1.8V_NORMAL

R1

L2305

C2317

0.1uF

C2313 10uF 10V

50V

L/DIM0_VS

A_DIM

L2314

BLM18PG121SN1D

C2315

0.1uF 16V

+24V

R2312 100

PWM_DIM

+3.3V_NORMAL

R2330 1K

0

R2304

+3.3V_TU_IN

ERROR_OUT

INV_CTL

3. soft start

POWER_ON/OFF2_2

+12V

L2311

CIS21J121

1

+12V

L2310

BLM18PG121SN1D

C2322 10uF 16V

Switching freq: 700K

+3.3V_NORMAL

+5V_NORMAL

R2334 10K

PANEL_POWER

PANEL_CTL

+5V_Normal

R2301 10KPOWER_ON/OFF1

POWER_ON/OFF2_1

R1

C2334 100pF

50V

R2

1%

R2308

R2311

OPT

R2348

10K

56K

10K 1%

+2.5V

AP7173-SPG-13 HF(DIODES)

IN

1

PG

2

VCC

C2324

10uF

10V

3

EN

4

0.01uF

R2341

C2336 1uF 10V

IC2303

THERMAL

1.5A

10K

C2326 50V

9

C2328

0.1uF 50V

C2332 10uF

9

THERMAL

C2335

0.1uF 50V

16V

[EP]GND

VIN

8

VBST

7

SW

6

GND

5

VREG5

C2342 2200pF 50V

VFB

R2343

33K

R2344

5.6K

C

Q2304

B

MMBT3904(NXP)

E

IC2304

TPS54327DDAR

EN

1

2

3

SS

4

3A

Vout=0.765*(1+R1/R2)

[EP]

OUT

8

FB

7

SS

6

GND

5

C2331 2200pF 50V

R2346 2K 1%

R2347

4.3K 1%

AO3407A

OPT

R2

Q2305

R1

S

G

MAX 1A

C2345

0.1uF 16V

D

700 mA

1uF

C2339

OPT

L2313

6.8uH

NR8040T4R7N

C2340 10uF 10V

25V

+2.5V_NORMAL

TYP 1450mA

+5V_NORMAL

C2343 22uF 10V

C2344

0.1uF 16V

PANEL_VCC

C2346

0.1uF 50V

Power_DET

+12V

4

+12V

L2309

BLM18PG121SN1D

C2354

10uF 16V

C2303

0.1uF 50V

4

+3.5V_ST

+24V

PD_24V R2364

8.2K 1%

PD_24V R2365

1.5K 1%

PD_+3.5V R2366 0 5%

C2359

0.1uF 16V

C2360

0.1uF 16V

VCC

PD_24V

PD_+12V R2362

2.7K 1%

PD_+12V R2363

1.2K 1%

+1.0V_VDD

VIN2

VIN1

VBST

SW2

SW1

IC2306

TPS54425PWPR

14

13

12

4A

11

10

9

8

THERMAL

15

1

2

3

4

5

6

7

[EP]PGND

PGND2

PGND1

Vout=0.765*(1+R1/R2)

R2373 100K

IC2307

NCP803SN293

3

1

GND

PD_24V

R2372 100K

PD_24V

IC2308

NCP803SN293

3

1

GND

VO

VFB

VREG5

SS

GND

PG

EN

RESET

2

RESET

2

R2309 100K

R2310 10K

C2305

0.1uF OPT

C2318 1uF 10V

+3.5V_ST

R2376 10K

OPT

not to RESET at 8kV ESD

LG1152 Max: 1728 mA LG1132 Max: 2000 mA

R1

R2313

9.1K

C2368 22uF 10V

1%

C2369 22uF 10V

C2319 3300pF 50V

POWER_ON/OFF2_3

L2316

2uH

POWER_DET

C2365

0.1uF 16V

24V-->3.48V 12V-->3.58V

ST_3.5V-->3.5V

URSA5 R2322-*1 24K

1%

R2

R2322 22K

1%

FRC3

OPT

C2321 22pF 50V

+1.0VDC

Vout=0.8*(1+R1/R2)

2

C2353 3300pF 50V OPT

OPT

MAX 4.7 A

+3.3V_NORMAL

L2318

CIS21J121

R2319

1.5K

R2382

30K

1/16W

1%

R2320

10K

L2307

CIS21J121

R1

1%

R2

L2300

BLM18PG121SN1D

Placed on SMD-TOP

C2300

C2304

10uF

16V

+12V

+3.3V_NORMAL

IC2301

[EP]LX

AOZ1038PI

C2309

0.1uF 16V OPT

PGND

VIN

AGND

FB

NC_2

1

8

NC_1

9

2

7

THERMAL

EN

3

6

COMP

4

5

6A

D2350

ADUC 20S 02 010L

*NOTE 17

OPT

R23160

R2317

20K

C2310

0.1uF 16V

C2311

2200pF

50V

R2318

L2304

2uH

10K

C2312 10uF 10V

POWER_ON/OFF2_1

C2314 10uF 10V

C2316 10uF 10V

C2352 10uF 10V

Vout=0.8*(1+R1/R2)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

C2302

4.7uF 16V

RT/CLK

GND_1

GND_2

PVIN_1

PVIN_2

VIN

VSENSE

IC2305

EAN62348501

1

15

2

THERMAL

3

4

5

6

7

[EP]GND

PWRGD

14

C2349

BOOT

13

0.1uF 16V

PH_2

12

PH_1

11

EN

10

SS/TR

9

COMP

8

1.3K R2307

C2348

4700pF 50V

47pF 50V

22000pF 50V

C2373

R2381 0

Max 5926 mA

L2317

1uH

R2357 1K

C2374

1/16W

5%

Switching freq: 400 ~ 580 Khz

+0.9V_VDD

C2363

C2350

22uF

10V

POWER_ON/OFF2_3

OPT C2370 10uF 10V

Vout=0.8*(1+R1/R2)

4

+3.5V_ST

DDR MAIN 1.5V

L2308

C2320 10uF 10V

VIN_1

VIN_2

GND_1

GND_2

EP[GND]

1

2

3

4

AGND

10K

R2339

C2325

0.1uF 16V

THERMAL

17

IC2302

TPS54319TRE

3A

7

5

6

COMP

VSENSE

3A

BOOT14PWRGD15EN16VIN_3

13

12

11

10

9

8

RT/CLK

1/16W 5%

$ 0.145

PH_3

PH_2

PH_1

SS/TR

R2340 15K

C2327

0.1uF

16V

R2342

C2329

0.01uF 50V

330K1/16W 5%

C2330

4700pF

50V

NR8040T3R6N

POWER_ON/OFF2_3

L2312

3.6uH

C2333 22uF 10V

C2337 22uF 10V

1074 mA

+1.5V_DDR

C2341

0.1uF 16V

C2338 100pF 50V

R2349

R1

47K 1%

R2

R2350 56K 1/16W 1%

C2375 180pF 50V

R2378-*1

8.2K

1/16W

R2379-*1

15K

+0.9V_VDD

R2378

6.8K

R2379

12K

URSA5

1%

URSA5

1/16W

1%

Vout=0.6*(1+R1/R2)

1/16W

+12V

R2377 100K

C2347 10uF 16V

1/16W 5%

L2315

R1

1%

FRC3

R2

1%

FRC3

Vout=0.827*(1+R1/R2)=1.521V

LG1152

POWER

Renesas MICOM

LGE Internal Use Only

For Debug

+3.5V_ST

MICOM_DEBUG

P3000

12507WS-12L

1

2

3

4

5

6

7

8

9

10

11

12

13

GP4 High/MID Power SEQUENCE

POWER_ON/OFF!

POWER_ON/OFF2_1

POWER_ON/OFF2_2

POWER_ON/OFF2_3

POWER_ON/OFF2_4

SOC_RESET

MICOM MODEL OPTION

MICOM_MHL

MICOM_GED

R3016 10K

R3020 10K

MICOM_GP4_10PIN

R3030 10K

Don’t remove R3014, Not making P40 floated

R3014 1K

R3011 10K

MICOM_DEBUG

+3.5V_ST

MICOM_PDP

R3007 10K

R3005 10K

MICOM_TOUCH_KEY

R3009 10K

MICOM_JAPAN

MICOM_DEBUG

MICOM_RESET

R3005-*1

R3012 10K

MICOM_OLED_MAIN

MICOM_LOGO_LIGHT

R3005-*2

22K

56K

MICOM_OLED_FRC

MODEL1_OPT_0 MODEL1_OPT_1 MODEL1_OPT_2 MODEL1_OPT_3 MODEL1_OPT_4

MODEL1_OPT_5 MODEL1_OPT_6

MICOM MODEL OPTION

10

/ OLED

LOGO_LIGHT

JAPAN

TOUCH_KEY

PDP

IR Wafer

10Pin

(GP4_TOOL)

MHLMODEL_OPT_5

GEDMODEL_OPT_6

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

NON LOGO_LIGHT

NON JAPAN

TACT_KEY

LCD

IR Wafer 12/15Pin

(GP3_Soft touch)

NON_MHL

NON_GED

POWER_ON/OFF2_3

For LM86

For JAPAN

For Sample Set

GP4_HIGH

I2C_SCL3

I2C_SDA3

AMP_RESET_N

PANEL_CTL

MODEL1_OPT_5

HDMI_CEC

POWER_ON/OFF2_2

POWER_ON/OFF2_3

EEPROM_SDA

EEPROM_SCL

MODEL1_OPT_6

AMP_RESET_BY_MICOM

IR

+3.5V_ST

R3018

3.3K

+3.3V_NORMAL

R3032

10K

R3033

10K

R3003 22

AMP_RESET_BY_MICOM

P31/TI03/TO03/INTP4

P75/KR5/INTP9/SCK01/SCL01

P74/KR4/INTP8/SI01/SDA01

P71/KR1/SI21/SDA21

P70/KR0/SCK21/SCL21

P30/INTP3/RTC1HZ/SCK11/SCL11

R3019

3.3K

FLG_POD_DR

POD_WAKEUP_N

/RST_DIIVA

POD_WAKEUP_N

FLG_POD_DR

for DiiVA

+3.5V_ST

C3000

0.1uF

P60/SCLA0 P61/SDAA0

P62 P63

P73/KR3/SO01 P72/KR2/SO21

+3.3V_NORMAL

R3035

4.7K OPT

8pF

C3002

X3000

32.768KHz R3023

R3002 22

MICOM_DIIVA

R3001 22

MICOM_DIIVA

GND

C3001 0.47uF

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

VSS

VDD

43

44

45

46

47

48

1 2 3 4 5 6 7 8

IC3000

R5F100GEAFB

MICOM

9 10 11 12

13

14

15

16

17

18

P17/TI02/TO02

P51/INTP2/SO11

P16/TI01/TO01/INTP5

P50/INTP1/SI11/SDA11

P14/RXD2/SI20/SDA20

P15/PCLBUZ1/SCK20/SCL20

R30 22 1 0K

10K

R3000

C3003 8pF

4.7M OPT

MICOM_RESET

R3024 22

RESET

P124/XT2/EXCLKS

P123/XT1

40

41

42

19

20

21

LOGO_LIGHT

MICOM_DEBUG

LOGO_LIGHT

R3025 22

MICOM_DIIVA

C3004

0.1uF 16V

P120/ANI19

P41/TI07/TO07

P40/TOOL0

37

38

39

36 35 34 33 32 31 30 29 28 27 26 25

22

23

24

+3.5V_ST

10K

R3026

R3027

P140/PCLBUZ0/INTP6 P00/TI00/TXD1 P01/TO00/RXD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7

P146

P147/ANI18

P13/TXD2/SO20

P10/SCK00/SCL00

P12/SO00/TXD0/TOOLTXD

P11/SI00/RXD0/TOOLRXD/SDA00

12V_EXT_PWR_DET

HDMI_WAUP:HDMI_INIT

MICOM_RESET_SW

SW3000

JTP-1127WEM

12

4 3

270K

OPT

POWER_ON/OFF2_4

RL_ON



SCART_MUTE

POWER_ON/OFF2_4

KEY2

KEY1

MODEL1_OPT_2

MODEL1_OPT_1

MODEL1_OPT_0

MODEL1_OPT_4

MODEL1_OPT_3

For Japan:LNB_INIT

EXT_AMP_MUTE

EXT_AMP_RESET

COMMERCIAL_12V_CTL

12V_EXT_PWR_DET

SCART_MUTE

+3.3V_NORMAL

R3036

10K

OPT

R3037

10K

OPT

POWER_ON/OFF2_1

SIDE_HP_MUTE

R3006 10K

R3008 10K

R3010 10K

R3021 10K

R3017 10K

MICOM_NON_MHL

MICOM_NON_GED

R3031 10K

MICOM_LCD/OLED

MICOM_GP3_12/15PIN

MICOM_TACT_KEY

R3013 10K

MICOM_NON_JAPAN

MICOM_NON_LOGO_LIGHT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Eye Sensor Option

MODEL_OPT_4

MODEL_OPT_2

0

1

0

N/A

CM3231_CAPELLA

(GP3 Soft touch) (GP4 Soft touch)

1

MC8101_ABOV

(TACT_KEY)

CM3231_CAPELLA

POWER_ON/OFF1

+3.3V_NORMAL

R3034

4.7K

POWER_DET

OPT

COMMERCIAL_12V_CTL

LED_B/GP4_LED_R

B

SOC_RESET

C

Q3000 MMBT3904(NXP)

EDID_WP

E

SOC_TX

AMP_MUTE

EDID_WP

EXT_AMP_RESET

EXT_AMP_MUTE

CEC_REMOTE

BAT54_SUZHO

SOC_RX

INV_CTL

D3000

D

G

S

For CEC

+3.5V_ST

R3028 27K

Q3001-*1 SI1012CR-T1-GE3 HDMI_CEC_FET_VISHAY

G

D

S

Q3001 RUE003N02

HDMI_CEC_FET_ROHM

R3029

120K

HDMI_CEC

2011.12.12

MICOM

30

BODY_SHIELD

LGE Internal Use Only

20

HP_DET

19

5V

18

GND

17

DDC_DATA

16

DDC_CLK

15

ARC

14

CE_REMOTE

13

CK-

12

CK_GND

11

CK+

10

D0-

9

D0_GND

8

EAG62611204

51U019S-312HFN-E-R-B-LG

EAG62611204

51U019S-312HFN-E-R-B-LG

EAG62611204

51U019S-312HFN-E-R-B-LG

JK3202

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11 10

9

8

7

6

5

4

3

2

1

JK3200

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11 10

9

8

7

6

5

4

3

2

1

JK3201

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

HP_DET

5V

GND

DDC_DATA

DDC_CLK

NC

CE_REMOTE

CK-

CK_GND

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

HP_DET

5V

GND

DDC_DATA

DDC_CLK

NC

CE_REMOTE

CK-

CK_GND

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

5V_HDMI_2

5V_HDMI_3

HDMI_HPD_1

R3207 0

R3208 0

CEC_REMOTE

CK-_HDMI1

CK+_HDMI1

D0-_HDMI1

D0+_HDMI1

D1-_HDMI1

D1+_HDMI1

D2-_HDMI1

D2+_HDMI1

DDC_SDA_1

DDC_SCL_1

HDMI1 With ARC

HDMI_HPD_2

R3209 0

R3210 0

R3204 0

R3205 0

DDC_SDA_2

DDC_SCL_2

HDMI_HPD_3

DDC_SDA_3

DDC_SCL_3

5V_HDMI_1

R3248

1K

OPT

R3249

3.9K

OPT

HDMI2

C3202 1uF

10V

HDMI3

SPDIF_OUT_ARC

OPT

C3226

0.1uF 16V

CEC_REMOTE

CK-_HDMI2

CK+_HDMI2

D0-_HDMI2

D0+_HDMI2

D1-_HDMI2

D1+_HDMI2

D2-_HDMI2

D2+_HDMI2

CEC_REMOTE

CK-_HDMI3

CK+_HDMI3

D0-_HDMI3

D0+_HDMI3

D1-_HDMI3

D1+_HDMI3

D2-_HDMI3

D2+_HDMI3

ARC

BODY_SHIELD

GND

20

HP_DET

19

5V

18

GND

17

DDC_DATA

16

DDC_CLK

15

NC

14

CE_REMOTE

13

CK-

12

CK_GND

11

CK+

10

D0-

9

D0_GND

8

EAG62611204

51U019S-312HFN-E-R-B-LG

JK3203

+5V_NORMAL

D3200

R3217

47K

+5V_NORMAL

D3201

R3218 47K

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

5V_HDMI_1

5V_HDMI_3

A2CA1

R3219 47K

A2CA1

R3220 47K

5V_HDMI_4

DDC_SDA_1

DDC_SCL_1

DDC_SDA_3

DDC_SCL_3

CEC_REMOTE

CK-_HDMI4

CK+_HDMI4

D0-_HDMI4

D0+_HDMI4

D1-_HDMI4

D1+_HDMI4

D2-_HDMI4

D2+_HDMI4

+5V_NORMAL

D3202

R3225

47K

+5V_NORMAL

D3203

R3226 47K

R3222 0

R3223 0

5V_HDMI_2

A2CA1

5V_HDMI_4

A2CA1

R3228 47K

D3205

R3229

47K

D3207

DDC_SDA_4

DDC_SCL_4

R3243 1K

1/16W 5%

5.6V

DDC_SDA_2

DDC_SCL_2

+3.5V_ST

DDC_SDA_4

DDC_SCL_4

HDMI_HPD_4

A2CA1

+3.3V_NORMAL

C3200 10uF 10V

C3223

0.047uF 25V

Q3200 MMBT3904(NXP)

L3200 BLM18PG121SN1D

5V_HDMI_4

MBR230LSFT1G

Limit 0.8A

+3.5V_ST

R3246

B

[EP]

R3200

3

R3247 10K

IC3200

FAULT

OUT_2

OUT_1

ILIM0

ILIM1

62K

1/10W

OPT

Limit 0.8A

B

C3205 10uF 10V

OUT

2

1

GND/ADJ

R3201

D3206

30V

62K

1/10W

10K

C

E

AZ1117BH-1.2TRE1

IN

IC3202

TPS2554

GND

THERMAL

11

1

2

3

4

5

MHL_DET

IN_1

IN_2

ILIM_SEL

EN

10

9

8

7

6

E

MMBT3906(NXP)

Q3201

C

HDMI4 With MHL

HDMI2

CK-_HDMI2

CK+_HDMI2

D0-_HDMI2

D0+_HDMI2

D1-_HDMI2

D1+_HDMI2

D2-_HDMI2

D2+_HDMI2

HDMI3

CK-_HDMI3

CK+_HDMI3

D0-_HDMI3

D0+_HDMI3

D1-_HDMI3

D1+_HDMI3

D2-_HDMI3

D2+_HDMI3

C3211

C3210

0.1uF

16V

C3201

C3203

10uF

10V

Vout=0.8*(1+R1/R2)

5%

1/16W

220K

R3206

C3204

0.1uF 16V

1/16W

10K

R3245

+5V_NORMAL

5%

C3206

0.1uF 16V

C3207

0.1uF 16V

C3208

0.1uF

C

D3204

A1

A2

L3201

BLM18PG121SN1D

C3216 10uF 10V

MHL_DET

R1XCN R1XCP R1X0N R1X0P R1X1N R1X1P R1X2N R1X2P

AVDD12_1

VDD12_1

R3XCN R3XCP R3X0N R3X0P R3X1N R3X1P R3X2N R3X2P

AVDD12_2

VDD33_1

R4XCN R4XCP

C3217

0.1uF 16V

HDMI1

D1-_HDMI1

D0-_HDMI1

D0+_HDMI1

D1+_HDMI1

D2-_HDMI1

D2+_HDMI1

R0X0N

R0X0P

R0X1N

R0X1P

R0X2N

R0X2P

AVDD12_3

VDD33_2

[EP]GND

81

82

83

84

85

86

87

88

1 2

THERMAL

3

89 4 5 6 7 8 9 10

SII9587CNUC

11 12 13 14

Device Address : 0XB0

15 16 17 18 19 20 21 22

23

R4X0N24R4X0P25R4X1N26R4X1P27R4X2N28R4X2P

D1-_HDMI4

D0+_HDMI4

D0-_HDMI4

CK+_HDMI4

CK-_HDMI4

D2-_HDMI4

D1+_HDMI4

HDMI4

29

VDD12_2

D2+_HDMI4

30

DSDA031DSCL0

DDC_SDA_1

CK-_HDMI1

CK+_HDMI1

L3202

TPVDD12

R0XCN

R0XCP

79

80

IC3201

FHD

32

R0PWR5V

CBUS_HPD0

DDC_SCL_1

HDMI_HPD_1

C3213

L3203

TCVDD12

77

78

33

34

DSDA135DSCL1

DDC_SDA_2

5V_HDMI_1

R3231 10

1uF

HDMI_CLK-

TXCN

76

DDC_SCL_2

1/16W

R3233

5.1K 5%

HDMI S/W OUTPUT

HDMI_RX1-

HDMI_RX0-

HDMI_RX0+

TX1N

TX0P

TX0N

73

74

37

38

DSDA339DSCL3

R1PWR5V

DDC_SDA_3

5V_HDMI_2

R3232 10

C3214

1uF

HDMI_RX1+

TX1P

71

72

40

CBUS_HPD3

DDC_SCL_3

HDMI_HPD_3

1/16W

R3234

5.1K 5%

HDMI_CLK+

TXCP

75

36

CBUS_HPD1

HDMI_HPD_2

HDMI_RX2-

HDMI_RX2+

ARC69TX2P

TX2N

70

41

42

DSDA443DSCL4

R3PWR5V

DDC_SDA_4

5V_HDMI_3

R3240 10

C3220

1uF

VDD12_3

67

68

66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

44

CBUS_HPD4

DDC_SCL_4

HDMI_HPD_4

1/16W

R3241

5.1K 5%

SPDIF_OUT_ARC

R3221

10

OPT

C3224

0.1uF 16V

RSVDL SPDIF_IN INT CSCL CSDA RESET_N TPWR GPIO1 GPIO0 CD-SENSE4 CD_SENSE3 GPIO2 CD_SENSE1 CD_SENSE0 WKUP LPSBV PWRMUX_OUT SBVCC5 R5PWR5V[VGA] DSCL5[VGA] DSDA5[VGA] R4PWR5V

C3219

1uF

16V

0.1uF

C3225

HDMI_WKUP

5V_HDMI_4

R3238 10

+3.3V_NORMAL

+3.5V_ST

R3216 10

C3209

0.1uF

16V

MHL_DET

1/16W R3239

5.1K 5%

1/16W R3213

5.1K 5%

C3212

1uF 10V

UD

R1XCN R1XCP R1X0N R1X0P R1X1N R1X1P R1X2N R1X2P

AVDD12_1

VDD12_1

R3XCN R3XCP R3X0N R3X0P R3X1N R3X1P R3X2N R3X2P

AVDD12_2

VDD33_1

R4XCN R4XCP

10K

R3202

R3224 33

R3211 33

R3236 33

R3237 33

R3214 33

+5V_NORMAL

C3215

0.1uF

16V

OPT

R3215 33

R3212 33

[EP]GND

1 2

THERMAL 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

23

R4X0N24R4X0P25R4X1N26R4X1P27R4X2N28R4X2P

OPT

C3218

10uF

10V

89

IC3201-*1

SII9587CNUC-3

29

30

DSDA031DSCL0

VDD12_2

+3.3V_NORMAL

32

33

34

36

37

38

40

DSDA135DSCL1

DSDA339DSCL3

R0PWR5V

R1PWR5V

CBUS_HPD0

CBUS_HPD1

CBUS_HPD3

10K

R3203

R3242 10

C3221

1uF 10V

12V_EXT_PWR_DET

VDD12_368ARC69TX2P70TX2N71TX1P72TX1N73TX0P74TX0N75TXCP76TXCN77TCVDD1278TPVDD1279R0XCN80R0XCP81R0X0N82R0X0P83R0X1N84R0X1P85R0X2N86R0X2P87AVDD12_388VDD33_2

67

RSVDL

66

SPDIF_IN

65

INT

64

CSCL

63

CSDA

62

RESET_N

61

TPWR

60

GPIO1

59

GPIO0

58

CD-SENSE4

57

CD_SENSE3

56

GPIO2

55

CD_SENSE1

54

CD_SENSE0

53

WKUP

52

LPSBV

51

PWRMUX_OUT

50

SBVCC5

49

R5PWR5V[VGA]

48

DSCL5[VGA]

47

DSDA5[VGA]

46

R4PWR5V

45

41

42

44

DSDA443DSCL4

R3PWR5V

CBUS_HPD4

SPDIF_OUT

HDMI_INT

I2C_SCL5

I2C_SDA5

HDMI_S/W_RESET

MHL_DET

10K

R3244

HDMI_WKUP

RGB_5V

RGB_DDC_SCL

RGB_DDC_SDA

C3222 10uF 10V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4

2011.10.19

HDMI 32

RGB/ PC AUDIO/ SPDIF

LGE Internal Use Only

RGB PC

DSUB_VSYNC

DSUB_HSYNC

DSUB_R+

DSUB_B+

DSUB_G+

M24C02-RMN6T

E0

E1

E2

VSS

1

RGB_EDID

2

3

4

IC3600

D3615

D3616

30V OPT

RGB_5V

VCC

8

WC

7

SCL

6

SDA

5

Closed to JACK

C3633

18pF

RGB_5V

R3641

2.7K

C3634 18pF

50V

A1

C

A2

MMBD6100

D3620

R3645

R3642

10K

2.7K

RGB_EDID

D3621 ADUC 5S 02 0R5L

5.5V OPT

91010

111112121313141415

6677889

112233445

JK3603

SLIM-15F-D-2

15

5

+5V_NORMAL

R3643 22

R3644 22

D3622 ADUC 5S 02 0R5L

5.5V OPT

NON_RGB_DEBUG

16

R3600

EDID_WP

RGB_DDC_SCL

RGB_DDC_SDA

0

+3.3V_NORMAL

R3646 10K

D3623

5.6V OPT

D3600 20V OPT

R3601

NON_RGB_DEBUG

DSUB_DET

+3.3V_NORMAL

SPDIF OUT

SPDIF_OUT

D3613-*1

5.5V

ADUC 5S 02 0R5L

ESD_MTK

RGB_DEBUG

R3602 100

SOC_RX

RGB_DEBUG

R3647 100

SOC_TX

D3601

20V

0

OPT

PC AUDIO

JK3601

KJA-PH-0-0177

5 GND

4 L

3 DETECT

1 R

R3615

33

ADUC 5S 02 0R5L

D3611

5.6V OPT

D3612

5.6V OPT

R3620

2.7K OPT

D3613

5.5V

OPT

D3611-*1

ESD_MTK

D3612-*1

ESD_MTK

C3615

0.1uF 16V

PC_L_IN

5.6V

PC_R_IN

5.6V

JK3602

2F11TC1-EM52-4F

VIN

A

VCC

B

GND

C

Fiber Optic

4

SHIELD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

JACK HIGH / MID

2011.11.21

36

RS232C

LGE Internal Use Only

0.1uF

RS232

C38000.1uF

C3801

C38020.1uF

C3803

DOUT2

12V_COMMERCIAL_OUT

12V 1A FOR COMMERCIAL(RS-232C POWER)

12V_COMMERCIAL_OUT

IC3800

+3.5V_ST

MAX3232CDR

C1+

V+

C1-

C2+

C2-

V-

RIN2

1

2

3

4

RS232

5

6

7

8

EAN41348201

VCC

16

GND

15

DOUT1

14

RIN1

13

ROUT1

12

DIN1

11

DIN2

10

ROUT2

9

+3.5V_ST

R3811

4.7K

IR_OUT

RS232

100

R3820

RS232

100

R3821

+3.5V_ST

OPT_RS232

R3834

10K

FOR COMMERCIAL

R3814

D3805 20V OPT

4.7K OPT

D3804

20V OPT

OPT

SOC_RX

SOC_TX

10

9

8

7

6

RS232

SPG09-DB-009

JK3803

+3.5V_ST

5

4

3

2

1

UART_4PIN_STRAIGHT

P3800

12507WS-04L

1

2

3

4

5

UART_4PIN_ANGLE

P3801

12507WR-04L

1

2

3

4

5

CVBS 1 PHONE JACK

AV_JACK_BLACK

JK3800

KJA-PH-1-0177

5 M5_GND

4 M4

3 M3_DETECT

1 M1

6 M6

AV_JACK_YELLOW

JK3800-*1

KJA-PH-1-0177-1

5 M5_GND

4 M4

3 M3_DETECT

1 M1

6 M6

D3800

5.6V OPT

D3801

5.6V

D3802

5.6V

+3.3V_NORMAL

R3810 10K

OPT

AV1_CVBS_DET

AV1_CVBS_IN

AV1_L_IN

AV1_R_IN

COMPONENT 1 PHONE JACK

COMP_JACK_BLACK

JK3801

KJA-PH-1-0177

5 M5_GND

4 M4

3 M3_DETECT

1 M1

6 M6

COMP_JACK_GREEN

JK3801-*1

KJA-PH-1-0177-2

5 M5_GND

4 M4

3 M3_DETECT

1 M1

6 M6

D3803

5.6V OPT

+3.3V_NORMAL

R3806

10K

COMP1_DET

COMP1_Y

COMP1_Pb

COMP1_Pr

ESD For MTK ESD For LG1152

D3803-*1

5.6V

ESD_MTK

D3800-*1

5.6V

ESD_MTK

D3801-*1

5.6V

ESD_MTK

D3802-*1

5.6V

ESD_MTK

D3803-*2

5.6V ESD_LG1152

D3800-*2

ESD_LG1152

D3801-*2

5.6V

ESD_LG1152

D3802-*2

5.6V

ESD_LG1152

5.6V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

JACK_COMMON

2011.11.21

38

USB_DM1

LGE Internal Use Only

USB_DP1

/RST_HUB

+3.3V_NORMAL

R4200

100K

C4200

0.1uF OPT

USB_HUB_IC_IN_DP

USB_HUB_IC_IN_DM

C4203

0.1uF

HS_IND/CFG_SEL[1]

SCL/SMBCLK/CFG_SEL[0]

SDA/SMBDATA/NON_REM[1]

100K

R4201

R4202

100K

R4203

100K

VBUS_DET

RESET_N

VDD33_2

NC_8

NC_7

NC_6

C4205

15pF

C4207

15pF

R4205

1%

1M

X4200

R4204

100K

SUSP_IND/LOCAL_PWR/NON_REM[0]

28

27

26

25

24

23

22

USB HUB

21

20

19

18

NC_5

24MHz

VDDA33_330USBDM_UP31USBDP_UP32XTALOUT

29

IC4200

USB2512B-AEZG

14

15

16

17

CRFILT

VDD33_1

OCS_N[2]

C4209

1uF

25V

C4208

0.1uF

12K

1/16W 1%

XTALIN/CLKIN

PLLFILT35RBIAS36VDD33_3

33

34

THERMAL

37

11

12

13

TEST

OCS_N[1]

R4206

1

2

3

4

5

6

7

8

9

10

VDDA33_2

[EP]VSS

USBDM_DN[1]

USBDP_DN[1]

USBDM_DN[2]

USBDP_DN[2]

VDDA33_1

NC_1

NC_2

NC_3

NC_4

C4210

0.1uF OPT

C4211

0.1uF OPT

C4212

0.1uF OPT

USB_DM2

C4213

0.1uF

USB_DP2

+3.3V_NORMAL

C4214

1uF 25V

C4201

4.7uF

C4202

0.1uF

R4209

100K OPT

OPT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

0.1uF

PRTPWR[2]/BC_EN[2]

1uF

25V

OPT

R4208 22

R4207 22

USB_CTL2

/USB_OCD2

C4204

C4206

PRTPWR[1]/BC_EN[1]

R4210 100K

OPT

USB_CTL1

/USB_OCD1

USB3_HUB

2011.06.13

42

+5V_USB FOR USB1

LGE Internal Use Only

POWER_ON/OFF2_4

+24V

L4305

BLM18PG121SN1D

C4324 10uF 35V

R4328

10K

C4327

0.1uF 16V

0.1uF

C4326

0.1uF 50V

OPT

330K

Vout=0.8*(1+R1/R2)

16V

R4329

C4329

0

BOOT

SS/TR

C4328

0.01uF 50V

R4330

VIN

EN

IC4305

TPS54331D

1

2

3

3A

4

+3.3V_NORMAL

R4327

R4323

10K

MAX 2A

D4304-*1

40V

SX34

L4308

6.8uH

PH

8

D4304

SMAB34

GND

7

COMP

6

VSENSE

5

C4333

C4336 22uF 10V

C4334 4700pF 50V

R4336

20K

0.1uF

16V

/USB_OCD1

820

1%

R4343

R1

R2

OPT

C4338

1%

1000pF

R4338

10K

50V

1%

2K

R4339

USB_CTL1

USB_DM1

USB_DP1

40V

C4332 47pF 50V

OPT

IN_1

IN_2

ILIM_SEL

IC4303

TPS2554

GND

1

2

3

4

EN

5

11

THERMAL

[EP]

FAULT

10

OUT_2

9

1/10W

C4323

10uF

10V

OPT

OUT_1

8

ILIM0

7

ILIM1

6

R4300

27K

R4341

27K

1/10W

OPT

D4303

RCLAMP0502BA

USB1

DVR Ready MAX 1.8A

3AU 04S-3 05-Z C-(LG )

JK4 303

1234

USB DOWN STR EAM

5

DEV_USB_DCDC_BD86180

IC4306-*1

BD86180MUV

EN

1

COMP

2

SS

3

RT

4

CTL2

5

CTL1

6

FLG2

7

FLG1

8

USB_OUT2

9

GND_1

10

GND_2

11

USB_OUT113USB_IN_1

12

+12V

L4306

BLM18PG121SN1D

C4325 10uF 16V

+5V_USB

[EP]GND

VREG

24

GND_3

25

23

THERMAL

VIN_2

22

VIN_1

21

PGND_2

20

PGND_1

19

BST

18

SW_2

17

SW_1

16

USB_IN_3

15

USB_IN_2

14

ESD for MTK

C4337

22uF

R4342

C4342 100pF 50V

R4332

10K

0.1uF 16V

10K

5%

C4340

4700pF

IC4306

SN1104041, DC-DC+2CH USB SW

[EP]GND C4300

V7V

24

C4341

4.7uF 10V

L4307

3.6uH

C4301

22uF

10V

C4331

0.1uF 16V

AGND_3

VIN_2

VIN_1

PGND_2

PGND_1

BST

LX_2

LX_1

SW_IN_3

SW_IN_2

SW_IN_1

THERMAL

25

23

22

21

20

19

18

17

16

15

14

13

EN

1

COMP

2

SS

3

ROSC

4

USB_DCDC_SN1104041

EN_SW2

5

EN_SW1

6

NFAULT2

7

NFAULT1

8

SW_OUT2

9

AGND_1

10

USB_DCDC_SN1104041

AGND_2

11

SW_OUT1

12

USB_DCDC_SN1104041

C4340-*1

0.01uF

50V

USB_DCDC_BD86180

+5V_USB_3

+5V_USB_2

POWER_ON/OFF2_4

10K

R4301

10K

R4302

+3.3V_NORMAL

10K

OPT

R4304

R4303

10K

OPT

USB_CTL2

/USB_OCD2

USB_DM2

USB_DP2

+5V_USB_2

C4322

10uF

10V

USB2

MAX 1.5A

3AU 04S-3 05-Z C-(LG )

OPT

D4302

RCLAMP0502BA

JK4 302

1234

USB DOWN STR EAM

5

USB3

+5V_USB_3

ESD for LG1152

MAX 1.5A

3AU 04S-3 05-Z C-(LG )

JK4 300

1234

D4300-*2

RCLAMP0502BA

ESD_LG1152

D4302-*1

RCLAMP0502BA

ESD_LG1152

D4303-*3

RCLAMP0502BA

ESD_LG1152

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

From SoC

USB_CTL3

/USB_OCD3

USB_DM3

USB_DP3

WIFI_DM

WIFI_DP

USB_WIFI

+5V_USB

L4302

WIFI120-ohm

BLM18PG121SN1D

C4319

0.1uF 16V

WIFI

For EMI

USB3_HUB_WiFi

C4320

0.1uF 16V

WIFI

C4310

10uF

C4321

10uF

WIFI

USB DOWN STR EAM

P4301

12507WR-04L

WIFI

1

2

3

4

5

.

5

OPT

D4300

10V

C4339

10uF

10V

WIFI

RCLAMP0502BA

MAX 0.4A

VDD

DM

DP

GND

2011.10.26

43

Full Scart(18 Pin Gender)

LGE Internal Use Only

D4611

5.6V OPT

D4609

D4600 20V OPT

5.5V OPT

D4610

5.5V OPT

D4600-*1 20V 10pF

ESD_MTK_SCART

D4606

5.6V OPT

D4607

5.6V OPT

D4608

5.6V OPT

D4603

D4604

D4601

5.6V OPT

D4602

5.5V OPT

19

DA1R018H91E

JK4600

EU

SHIELD

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

AV_DET

COM_GND

SYNC_IN

SYNC_OUT

SYNC_GND

RGB_IO

R_OUT

R_GND

G_OUT

G_GND

ID

B_OUT

AUDIO_L_IN

B_GND

AUDIO_GND

AUDIO_L_OUT

AUDIO_R_IN

AUDIO_R_OUT

D4611-*2

5.6V 200pF

ESD_LG1152_SCART

SC_CVBS_IN

D4609-*1

5.5V

15pF ESD_MTK_SCART

D4610-*1

5.5V

15pF

ESD_MTK_SCART

15pF ESD_MTK_SCART

D4603-*1

5.5V

15pF

ESD_MTK_SCART

D4604-*1

5.5V

15pF

ESD_MTK_SCART

D4600-*2

20V 10pF ESD_LG1152_SCART

D4606-*1

5.6V

200pF

ESD_MTK_SCART

D4601-*1

5.6V 200pF ESD_MTK_SCART

D4602-*1

5.5V

D4605

5.6V OPT

BLM18PG121SN1D

EU

EU C4600 1000pF 50V

BLM18PG121SN1D

EU

C4601 1000pF 50V

D4611-*1

5.6V 200pF

ESD_MTK_SCART

D4609-*2

5.5V 15pF ESD_LG1152_SCART

D4605-*1

5.6V 200pF

ESD_MTK_SCART

D4606-*2

5.6V 200pF

ESD_LG1152_SCART

L4600

L4601

+3.3V_NORMAL

EU R4601

10K

EU

C4604

0.1uF

R460075

EU

D4601-*2

5.6V 200pF ESD_LG1152_SCART

SC_L_IN

SC_R_IN

EU C4602 4700pF

EU C4603 4700pF

CLOSE TO JUNCTION

EU C4605 100uF 16V

SC_FB

SC_R

SC_G

SC_B

D4605-*2

5.6V 200pF ESD_LG1152_SCART

SC_ID

DTV/MNT_L_OUT

DTV/MNT_R_OUT

SC_DET

MMBT3906(NXP)

Gain=1+Rf/Rg

Q4600

+12V

EU

E

C

R4608

R4603 390

EU R4602

390

Rf

B

EU

470

Q4601

MMBT3904(NXP)

C

E

Rg

R4604 180

0

OPT

EU

R4605

EU

R4606 47K

B

EU

R4607 15K

EU

C4606

0.1uF 50V

EU

EU C4607 47uF 25V

EU

DTV/MNT_V_OUT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

SCART GENDER

2011.10.26

46

ZigBee_Radio Pulse M_REMOTE OPTION

LGE Internal Use Only

P4800

12507WR-08L

M_REMOTE

9

+3.3V_NORMAL

L4800

120-ohm

3.3V

1

GND

2

RX

3

TX

4

RESET

5

DC

6

DD

7

GND

8

C4800

0.1uF

M_REMOTE

AR4800 100 1/16W

M_REMOTE

M_REMOTE_RX

M_REMOTE_TX

M_RFModule_RESET

M_RFModule_ISP

3D_SYNC_RF

Only For PDP

3D_SYNC_RF

ALL M_REMOTE OPTION

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

MOTION REMOTE

2011.11.21

48

Ethernet Block

LGE Internal Use Only

LAN_JACK_POWER

JK5000

XRJH-01A-4-DA7-180-LG(B)

LAN_XML

P1[CT]

1

P2[TD+]

2

P3[TD-]

3

P4[RD+]

4

P5[RD-]

5

P6[CT]

6

P7

7

P8

8

P9

9

P10[GND]

10

P11

11

YL_C

D1

YL_A

D2

GN_C

D3

GN_A

D4

12

SHIELD

JK5000-*1 TLA-6T764

LAN_TDK

R1

1

R2

2

R3

3

R4

4

R5

5

R6

6

R7

7

R8

8

R9

9

R10[GND]

10

R11

11

YL_C

D1

YL_A

D2

GN_C

D3

GN_A

D4

12

SHIELD

C5000

0.1uF 16V

C5001

0.01uF 50V

D5000

5.5V OPT

C5002

0.1uF 16V

D5001

5.5V OPT

C5003

0.01uF 50V

D5002

5.5V

EPHY_TDP

EPHY_TDN

EPHY_RDP

EPHY_RDN

D5003

5.5V

OPT

ESD for MTK

D5000-*1

ESD_MTK

ADUC 5S 02 0R5L

D5001-*1

ESD_MTK

ADUC 5S 02 0R5L

D5002-*1

ESD_MTK

ADUC 5S 02 0R5L

D5003-*1

ESD_MTK

ADUC 5S 02 0R5L

ESD for LG1152

ESD_LG1152

D5000-*2

5.5V

ADUC 5S 02 0R5L

ESD_LG1152

D5001-*2

5.5V

ADUC 5S 02 0R5L

ESD_LG1152

D5002-*2

5.5V

ADUC 5S 02 0R5L

ESD_LG1152

D5003-*2

5.5V ADUC 5S 02 0R5L

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LAN_VERTICAL

2011.12.09

50

Ethernet Block

LGE Internal Use Only

+3.3V_NORMAL

LAN_JACK_POWER

ET_COL/SNI

EPHY_TDP

EPHY_TDN

EPHY_RDP

EPHY_RDN

C5200

4.7uF 10V

Place 0.1uF close to each power pins

C5201

0.1uF 16V

Route Single 50 Ohm, Differential 100 Ohm

+3.3V_NORMAL

C5203

0.1uF 16V

25MHz, CL 18pF, ESR , max 30 Ohm, +/-30ppm

Place this cap. near IC

C5204

C5205

10uF

0.1uF

10V

16V

OPT

+3.3V_NORMAL

Place this Res. near IC

R5204

2.49K 1%

R5203

4.7K

C5206 15pF 50V

C5207 15pF

50V

AVDD10OUT

AVDD33_1

X5200

25MHZ

MDI+[0]

MDI-[0]

MDI+[1]

MDI-[1]

RSET

RXDV

R5205

0

Place this cap. near IC

+3.3V_NORMAL

AVDD33_2

CKXTAL1

CKXTAL2

[EP]

30

31

32

1

THERMAL

2

33

3

4

RTL8201F-VB-CG

5

6

7

8

9

11

RXD[0]10RXD[1]

RXD[2]/INTB

R5207 22

R5206 22

R5201 22

EPHY_RXD0

EPHY_RXD1

C5208

0.1uF 16V

ET_RXER

DVDD10OUT

29

IC5200

12

13

RXC

RXD[3]/CLK_CTL

C5209

56pF

4.7K

EPHY_INT

R5208

C5210 10uF 10V

OPT

EPHY_CRS_DV

ET_COL/SNI

CRS/CRS_DV

COL28RXER/FXEN

26

27

14

15

TXC

DVDD33

L5211

C5202

Place near IC

56pF

EPHY_ACTIVITY

R521022

LED1/PHYAD[1]

25

LED0/PHYAD[0]/PMEB

24

MDIO

23

MDC

22

PHYRSTB

21

TXEN

20

TXD[3]

19

TXD[2]

18

TXD[1]

17

16

+3.3V_NORMAL

TXD[0]

100NH

EPHY_TXD0

C5211

0.1uF 16V

EPHY_LINK

EPHY_MDC

EPHY_EN

EPHY_TXD1

+3.3V_NORMAL

R5212

1.5K

1/16W

C5212

0.1uF OPT

+3.3V_NORMAL

4.7K

R5216

R5215

4.7K

R5217

5%

EPHY_MDIO

/RST_PHY

EPHY_LINK

EPHY_ACTIVITY

ET_RXER

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

EPHY_REFCLK

LG1152 A0

14ETHERNET 50

Q1801

LGE Internal Use Only

AMP_MUTE

DUAL COMPONENT

1ST : 0TRIY80001A 2ND : 0TR387500AA

L5400

CIS21J121

+24V_AMP

AUD_LRCH

AUD_LRCK

AUD_SCK

I2C_SDA1

I2C_SCL1

R5400

10K

C5401

0.1uF 50V

+3.3V_NORMAL

B

+24V

C5400

0.1uF 50V

C5402 100pF

50V

R5402 100

R5403 100

R5401

10K

C

Q5400

MMBT3904(NXP)

E

R5405

100

C5403 1000pF

50V

R5404

3.3K

1000pF

C5404

+3.3V_NORMAL

L5401

BLM18PG121SN1D

C5413

0.1uF 16V

C5407

4.7uF 10V

C5408 33pF 50V

OPT C5409

10uF

10V

OPT C5410 10uF

10V

C5411

0.1uF

C5412

0.1uF 16V

16V

OPT C5405

10uF

10V

C5406 33pF 50V

50V

AMP_RESET_N

AUD_MASTER_CLK

C5414 10uF 10V

AGND_PLL AVDD_PLL DVDD_PLL

LF

DGND_PLL

GND_1

DGND DVDD

SDATA

WCK BCK SDA

C5415

1000pF

50V

[EP]

1 2 3 4 5 6 7 8 9 10 11 12

GND_IO

CLK_I

VDD_IO

46

47

48

THERMAL

49

NTP-7500L

13

14

15

SCL

/FAULT

MONITOR0

50V

C5416

BST1A

/RESET

AD

43

44

45

IC5400

0x54

16

17

18

BST2B

MONITOR1

MONITOR2

C5417

22000pF

50V

22000pF

OUT1A_2

PGND1A

41

42

19

20

PGND2B

OUT2B_1

PVDD1_2

PVDD1_3

OUT1A_1

38

39

40

21

22

23

OUT2B_2

PVDD2_1

PVDD2_2

+24V_AMP

C5418

0.1uF 50V

PVDD1_1

37

36 35 34 33 32 31 30 29 28 27 26 25

24

PVDD2_3

C5420

0.1uF 50V

OUT1B_2 OUT1B_1 PGND1B BST1B VDR1 VCC_5 AGND VDR2 BST2A PGND2A OUT2A_2 OUT2A_1

+24V_AMP

C5419

0.1uF 50V

C5421

0.1uF 50V

R5406

3.3

C5422 10uF 35V

OPT

C5424

0.01uF 50V

C5423 10uF 35V

C5425 22000pF 50V

C5426 22000pF 50V

C54 27 1uF 25V

D5400

1N4148W

100V OPT

D5401

1N4148W

100V

OPT

D5402

1N4148W

100V OPT

D5403

1N4148W

100V

OPT

C54 28 1uF 25V

R5407

12

C5429 390pF

50V

C5430 390pF

50V

R5408

12

R5409

12

C5431 390pF

50V

C5432 390pF

50V

R5410

12

C5433 1uF 25V

R5414

12

R5412

12

R5413

12

R5411

12

L5404

10.0uH

NRS6045T100MMGK

L5405

10.0uH

NRS6045T100MMGK

L5402

10.0uH

NRS6045T100MMGK

L5403

10.0uH

NRS6045T100MMGK

C5434

0.47uF 50V

C5435

0.47uF

50V

C5436

0.1uF 50V

C5437

0.1uF 50V

C5438

0.1uF 50V

C5439

0.1uF

50V

R5415

5.1K

R5416

5.1K

R5417

5.1K

R5418

5.1K

SPK_L+

SPEAKER_L

SPK_L-

SPK_L+

SPK_L-

SPK_R+

SPK_R-

SPK_R+

SPEAKER_R

SPK_R-

WAFER-ANGLE

4

3

2

1

P5400

WOOFER_MUTE

TP5403

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

AMP_NEO

2011.11.21

54

+24V

LGE Internal Use Only

L5501

CIS21J121

WOOFER

+24V_AMP_WOOFER

C5529

0.1uF 50V

WOOFER

WOOFER AMP.

AUD_LRCH

AUD_LRCK

AUD_SCK

I2C_SDA1

I2C_SCL1

WOOFER

C5500 100pF

50V

WOOFER

R5501 100

WOOFER

R5502 100

WOOFER

C5501 1000pF 50V

WOOFER

R5503

3.3K

WOOFER

C5502

10uF

10V

C5503 33pF 50V

+3.3V_NORMAL

WOOFER

L5500

BLM18PG121SN1D

WOOFER

C5511

0.1uF 16V

WOOFER

C5504

OPT

4.7uF 10V

C5505 33pF 50V

WOOFER

WOOFER_MUTE

10uF

C5506 10V

C5507 10uF

10V

WOOFER

OPT

C5508

0.1uF 16V

OPT

WOOFER C5509

0.1uF 16V

WOOFER R5504

WOOFER

100

C5510

1000pF

50V

AMP_RESET_N

WOOFER

R5505

10K

AUD_MASTER_CLK

WOOFER

C5512 10uF 10V

AGND_PLL AVDD_PLL DVDD_PLL

DGND_PLL

GND_1

DGND DVDD

SDATA

WCK BCK SDA

LF

WOOFER

C5513

1000pF

1 2 3 4 5 6 7 8 9 10 11 12

50V

VDD_IO

[EP]

SCL

AD

GND_IO

CLK_I

46

47

48

THERMAL

49

NTP-7500L

13

14

15

/FAULT

MONITOR0

MONITOR1

WOOFER

50V

C5514

22000pF

BST1A

/RESET

43

44

45

WOOFER

IC5500

16

17

18

BST2B

MONITOR2

WOOFER C5515

22000pF

50V

OUT1A_2

PGND1A

41

42

19

20

PGND2B

OUT2B_1

PVDD1_2

PVDD1_3

OUT1A_1

38

39

40

21

22

23

OUT2B_2

PVDD2_1

PVDD2_2

+24V_AMP_WOOFER

WOOFER

C5516

0.1uF 50V

PVDD1_1

37

36 35 34 33 32 31 30 29 28 27 26 25

24

WOOFER

PVDD2_3

C5517

0.1uF 50V

WOOFER C5518

0.1uF 50V

OUT1B_2 OUT1B_1 PGND1B BST1B VDR1 VCC_5 AGND VDR2 BST2A PGND2A OUT2A_2 OUT2A_1

+24V_AMP_WOOFER

WOOFER

C5519

0.1uF 50V

OPT

R5506

3.3

WOOFER

C5520 10uF 35V

OPT C5522

0.01uF 50V

WOOFER C5521

10uF 35V

WOOFER

C5523 22000pF

50V

WOOFER

C5524 22000pF 50V

5%

4.7K R5517

1/16W

WOOFER_MONO

WOOFER C55 25 1uF 25V

WOOFER

C55 26 1uF 25V

WOOFER

C5531 1uF 25V

1N4148W

100V

OPT

D5501

1N4148W OPT

1N4148W

OPT

1N4148W OPT

D5500

100V

D5502

100V

D5503

100V

WOOFER_STEREO

WOOFER

R5507

12

WOOFER

C5527 390pF

50V

WOOFER C5528 390pF

50V WOOFER R5508

12

WOOFER_STEREO

R5500

12

C5530 390pF

50V

WOOFER_STEREO

WOOFER_STEREO C5533 390pF

50V

R5509

12

WOOFER_STEREO

WOOFER R5514

12

WOOFER

R5512

12

WOOFER_STEREO

R5511

12

R5510

12

L5503

10.0uH

NRS6045T100MMGK

L5504

10.0uH

NRS6045T100MMGK

WOOFER_STEREO

L5502

10.0uH

NRS6045T100MMGK

WOOFER_STEREO

L5505

10.0uH

NRS6045T100MMGK

WOOFER

C5532

0.47uF 50V

WOOFER_STEREO

C5536

0.47uF 50V

SPK_WOOFER_L-

SPK_WOOFER_L+

WOOFER C5534

0.1uF 50V

WOOFER

C5535

0.1uF 50V

SPK_WOOFER_R-

SPK_WOOFER_R+

WOOFER_STEREO

C5537

0.1uF 50V

WOOFER_STEREO

C5538

0.1uF 50V

WOOFER

R5515

5.1K

WOOFER

R5516

5.1K

WOOFER_STEREO

R5513

5.1K

WOOFER_STEREO

R5519

5.1K

SPK_WOOFER_L+

SPK_WOOFER_L-

SPK_WOOFER_R+

SPK_WOOFER_R-

P5500

FW25001-02(SPK 2P)

WOOFER

1

2

P5501

FW25003_03

1

2

3

DEV_WOOFER_STEREO

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

5%

4.7K R5518

1/16W

WOOFER_MONO

AUD_OUT >> EU/CHINA_HOTEL_OPT

LGE Internal Use Only

DTV/MNT_L_OUT

C6000 1uF 25V

EU

OPT C6002 6800pF

EU

R60002.2K

R6002

OPT

470K

SCART_AMP_L_FB

SCART_Lout

33pF

+12V

EU

IC6000

AZ4580MTR-E1

EU

VCC

8

OUT2

7

IN2-

6

IN2+

5

OUT1

EU

R600433K

C6003

EU

IN1-

IN1+

1

2

3

VEE

4

L6000

EU C6004

0.1uF 50V

SIGN600005

R6008 33K

C6005

33pF

EU

SCART_AMP_R_FB

SCART_Rout

OPT R6010

470K

R6011

OPT C6007 6800pF

2.2K

EU

C6008

1uF 25V

EU

DTV/MNT_R_OUT

[SCART AUDIO MUTE]

DTV/MNT_L_OUT

Q6000

MMBT3904(NXP)

DTV/MNT_R_OUT

Q6001

MMBT3904(NXP)

R6003

+3.5V_ST

R6012

4.7K

OPT

EU

10K

SCART_MUTE

C

E

C

E

EU

R6013

1K

B

EU

R6014

1K

B

EU

Q6002 MMBT3906(NXP)

E

C

EU

B

10K

EU

R6001

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

SCART AUDIO AMP

2011.11.21

60

CI POWER ENABLE CONTROL

LGE Internal Use Only

+5V_NORMAL

C6202

OPT

0.1uF 16V

PCM_5V_CTL

R6218 10K

CI

R6221 10K

OPT

R6223

4.7K

CI

B

CI

C

E

R6241 22K

R6242

2.2K

CI

Q6200 MMBT3904(NXP) CI

C6207

4.7uF 10V OPT

CI

Q6201

AO3407A

S

+5V_CI_ON

D

G

C6210 1uF 25V OPT

R6248

10K

CI

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Option FOR MTK

C6210-*1 1uF 25V

CI_MTK

Option FOR LG1152

CI SLOT

2011.10.31

62

T/C/S & H/NIM & T2/C TUNER(EU & CHINA)

LGE Internal Use Only

TU6504 TDSH-T151F

TW_H/NIM

RF_S/W_CTL

RESET

SCL

SDA

+B1[3.3V]

SIF

+B2[1.8V]

CVBS

IF_AGC

DIF[P]

DIF[N]

12

SHIELD

TDSS-G151D

1

2

3

4

5

6

7

8

9

10

11

TU6500

T/C_H/NIM_V

NC

RESET

SCL

SDA

+B1[3.3V]

SIF

+B2[1.8V]

CVBS

IF_AGC

DIF[P]

DIF[N]

12

SHIELD

1

2

3

4

5

6

7

8

9

10

11

TU6501

TDSN-G351D

T2/C_F/NIM_DEV

NC_1

RESET

SCL

SDA

+B1[3.3V]

SIF

+B2[1.8V]

CVBS

NC_2

NC_3

NC_4

+B3[3.3V]

+B4[1.23V]

NC_5

GND

ERROR

SYNC

VALID

MCLK

D0

D1

D2

D3

D4

D5

D6

D7

28

SHIELD

TDSQ-H051F

+5V[SPLITTER]

1

RESET

2

TU_SCL

3

TU_SDA

4

M_+3.3V

5

M_SIF

6

M_+1.8V

7

M_CVBS

8

M_IF_AGC

9

M_DIF[P]

10

M_DIF[N]

11

S_3.3V

12

S_1.8V

13

S_CVBS

14

GND_1

15

SD_ERROR

16

SD_SYNC

17

SD_VALID

18

SD_MCLK

19

SD_SERIAL_D0

20

N.C_1

21

N.C_2

22

N.C_3

23

N.C_4

24

N.C_5

25

N.C_6

26

N.C_7

27

GND_2

GND_3

SD_1.23V_DEMOD

SD_RESET

SD_3.3V_DEMOD

N.C_8

SD_SCL

SD_SDA

TU6502

CHB_V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

RF_SWITCH_CTL USE: T2/C,T/C,ATSC,DTMB.ISDB-T

TU6503

TDSQ-G051D

T/C/S2_V

N.C_1

RESET

SCL

SDA

+3.3V_TUNER

SIF

+1.8V_TUNER

CVBS

T/C_IF_AGC

T/C_DIF[P]

T/C_DIF[N]

N.C_2

N.C_3

N.C_4

GND_1

ERROR

SYNC

VALID

MCLK

D0

D1

D2

D3

D4

D5

D6

D7

GND_2

GND_3

+1.23V_S2_DEMOD

S2_RESET

+3.3V_S2_DEMOD

S2_F22_OUTPUT

S2_SCL

S2_SDA

LNB

GND_4

SHIELD

BR_F/NIM_V

TU6501-*1 TDSN-B051F

AT_H/NIM_V TU6500-*1 TDSS-H151F

NC

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

IF_AGC

9

DIF[P]

10

DIF[N]

11

12

SHIELD

28

SHIELD

CN_ATBM

TU6501-*2 TDSN-C251D

RF_S/W_CTL

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

NC_1

9

NC_2

10

NC_3

11

+B3[3.3V]

12

+B4[1.23V]

13

NC_4

14

GND

15

ERROR

16

SYNC

17

VALID

18

MCLK

19

D0

20

D1

21

D2

22

D3

23

D4

24

D5

25

D6

26

D7

27

28

SHIELD

RF_S/W_CTL

RESET

SCL

SDA

+B1[3.3V]

SIF

+B2[1.8V]

CVBS

NC_1

NC_2

NC_3

+B3[3.3V]

+B4[1.23V]

NC_4

GND

ERROR

SYNC

VALID

MCLK

D0

D1

D2

D3

D4

D5

D6

D7

28

SHIELD

CN_LG3921

TU6501-*3 TDSN-C051D

RF_S/W_CTL

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

NC_1

9

NC_2

10

NC_3

11

+B3[3.3V]

12

+B4[1.23V]

13

NC_4

14

GND

15

ERROR

16

SYNC

17

VALID

18

MCLK

19

D0

20

D1

21

D2

22

D3

23

D4

24

D5

25

D6

26

D7

27

T2/C/S2

TU6503-*1 TDSQ-G351D

N.C_1

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

N.C_2

9

N.C_3

10

N.C_4

11

+B3[3.3V]

12

+B4[1.23V]

13

N.C_5

14

GND_1

15

ERROR

16

SYNC

17

VALID

18

MCLK

19

D0

20

D1

21

D2

22

D3

23

D4

24

D5

25

D6

26

D7

27

GND_2

28

GND_3

29

+B5[1.23V]

30

S2_RESET

31

+B6[3.3V]

32

S2_F22_OUTPUT

33

S2_SCL

34

S2_SDA

35

LNB

36

GND_4

37

38

SHIELD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

38

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

SHIELD

1

2

3

4

5

6

7

8

9

close to TUNER

CHB

C6501 10uF 10V

OPT

C6551 100pF 50V

close to Tuner

C6500

L9 ATSC

0.1uF 16V

C6509

0.1uF 16V

CHB

close to TUNER

Seperate GND for CHB

CHB

+5V_TU

L6508

BLM18PG121SN1D

MTK/L9_DVB/ATSC/NTSC

R6509

33

R6510

33

+3.3V_TU

C6511 100pF 50V

C6550

C6505

0.1uF

16V

R6506

C6507 100pF 50V

T2/C&CHB&CN&BR

RF_SWITCH

R6500 0

R6508 100

C6514

0.1uF 16V

BLM18PG121SN1D

100

C6510 1000pF 50V

RF_SWITCH C6503

0.1uF 16V

C6508 18pF 50V

C6506 18pF 50V

should be guarded by groumd

BR_TW_CN_TUNER

R6508-*1

1K 5%

I2C_SCL6

I2C_SDA6

L6500

T/C&AT&CHB

C6513 4700pF

CN

50V

BR_TW_CN_TUNER

R6500-*1

1K 5%

RF_SWITCH_CTL

BR_TW_CN_TUNER

C6508-*1 68pF 50V

close to TUNER

0.1uF 16V

+1.8V_TU

IF_P

IF_N

C6516

0.1uF

16V

T2/C&CHB&CN&BR

NOT_T/C&AT&CHB

AR6500 0

NOT_T/C&AT&CHB

AR6501 0

AR6502 0

NOT_T/C&AT&CHB

DVB_S&CHB

C6512 100pF

LNB_OUT

+3.3V_TU

MTK/L9_DVB/ATSC/NTSC

BR_TW_CN_TUNER

+5V_TU

C6506-*1 68pF

R6516

50V

470

C6522

1. should be guarded by ground

2. No via on both of them

IF_AGC

3. Signal Width >= 12mils

T2/C&CN&BR

L6502

BLM18PG121SN1D

CHB

L6507

BLM18PG121SN1D

FE_TS_DATA[0] FE_TS_DATA[1] FE_TS_DATA[2] FE_TS_DATA[3]

FE_TS_DATA[4] FE_TS_DATA[5] FE_TS_DATA[6] FE_TS_DATA[7]

DVB_S&CHB

L6501

BLM18PG121SN1D

C6515

0.1uF DVB_S&CHB

LNB_TX

C6517 18pF 50V

OPT

C6518 18pF 50V

OPT

E

B

C

R6515

4.7K

Signal to Signal Width = 12mils

CHB

OPT

C6523

C6525

100pF

0.1uF

50V

16V

+1.23V_TU

+1.8V_TU

+1.23V_TU

C6519 10uF

10V

DVB_S&CHB

R6503 22

DVB_S&CHB

R6504 22

DVB_S&CHB

OPT

R6511 100K

C6520

0.1uF

16V

R6518 82

Q6500 MMBT3906(NXP)

Ground Width >= 24mils

OPT

C6528

10uF

6.3V

CHB_CVBS CHB_ERR CHB_SYNC CHB_VAL CHB_CLK

TU_TS_ERR FE_TS_SYNC TU_TS_VAL FE_TS_CLK

CHB_DATA FE_TS_DATA[0-7]

+3.3V_D_Demod OPT

R6512

2.2K

C6521

0.1uF OPT

/TU_RESET

+3.3V_D_Demod

R6513 10

DVB_S&CHB

OPT

C6524 100pF

TUNER_SIF

/S2_RESET

C6527

0.1uF OPT

R6521

220

E

Q6501 MMBT3906(NXP)

C

+3.3V_D_Demod

I2C_SCL4

I2C_SDA4

CHB_CVBS

CHB_ERR

CHB_SYNC

CHB_VAL CHB_CLK

CHB_DATA

ATV_OUT

2012 perallel because of derating

+3.3V_TU

+3.3V_TU_IN

NOT_T/C&AT

C6533

10uF

16V

C6531

0.1uF

ERROR & VALID PIN

TU_CVBS

T/C_H/NIM

NOT_DVB_S

Not_L9_T2/C/S

BLM18PG121SN1D

T/C/S2 T2/C_F/NIM T2/C/S2 CHB

DVB_S&CHB DVB_S&CHB DVB_S&CHB

NOT_T/C&AT

T/C&AT&CHB

Not_L9_T2/C/S

+5V_NORMAL

C6535 1uF OPT

+3.3V_D_Demod

NOT_T/C&AT

L6506

+3.3V_NORMAL

L9_T2/C/S

IC6500

74LVC1G08GW

TU_TS_VAL

TU_TS_ERR

DVB_S DVB_ST/C&AT&CHB T/C&AT&CHB

NOT_T/C&AT

T2/C

T2/C&CN

T2/C&CHB&CN

NOT_T/C&AT&CHBNOT_T/C&AT&CHB

NOT_DVB_S

Not_L9_T2/C/S Not_L9_T2/C/S

C6540

0.1uF

B

A

GND

NOT_T/C&AT

T2/C

T2/C&CN

T2/C&CHB&CN

NOT_T/C&AT&CHB

L9_T2/C/S

AP2132MP-2.5TRG1

PG

EN

R6523 10K

VIN

VCTRL

1

2

3

NOT_L9_T2/C/S

NOT_T/C&AT

IC6501

1

2

3

4

2A

EAN61387601

R6525 0

NOT_T/C&AT

T/C&AT&CHB

T2/C&CHB&CN

H/NIM&CHB

9

THERMAL

CHB

5

4

8

7

6

5

+3.3V_TU

VCC

L9_T2/C/S

Y

L9_T2/C/S

AT_H/NIM

NOT_DVB_S

Not_L9_T2/C/S

[EP]

GND

ADJ

VOUT

NC

C6544

Vout=0.6*(1+R1/R2)

NOT_T/C&AT

C6538 10uF

10V

Close to the tuner

L6503

BLM18PG121SN1D

C6529

C6526

0.1uF

22uF

16V

NOT_T/C&AT C6542

0.1uF

465mA(MAX)

+3.3V_TU

C6530

0.1uF

10V

16V

Close to the tuner

TUNER

+3.3V_TU

IC6503

AZ1117BH-1.8TRE1

IN

3

+5V_NORMAL

C6532

0.1uF

0.1uF 16V

R6526 100

1/16W 5%

NOT_T/C&AT

RF_SWITCH

NOT_T/C&AT&CHB

NOT_DVB_S

Not_L9_T2/C/S

T2 : Max 1.7A

else : Max 0.7A

NOT_T/C&AT

R6527 20K 1%

NOT_T/C&AT

R6528 11K 1% R6529 10K 1%

NOT_T/C&AT

OUT

2

1

ADJ/GND

L9/BR_TW_CN_TUNER

R6532-*1

BLM18PG121SN1D

120-ohm

NOT_L9_BR_TW_CN Tuner

R6532 0

16V

FE_TS_VAL

CN

BR

+1.23V_TU

R2

R1

CHB : Max 480mA

else : Max 240mA

+1.8V_TU

R6531 1

C6546

C6548

10uF

0.1uF

10V

16V

C6534

C6536

22uF

10V

Close to the tuner

2011.11.21

CN

R6528-*1 12K

1/16W 1%

NOT_T/C&AT

C6549 10uF

16V

150mA(MAX)

+5V_TU

22uF

10V

C6539

0.1uF 16V

LNB_TX

LNB_OUT ATV_OUT

+5V_TU

R6520 220

B

R6519

1K

OPT

65

DVB-S2 LNB Part Allegro

LGE Internal Use Only

DCDC_GND and A_GND are connected DCDC_GND and A_GND are connected in pin#27 PCB_GND and A_GND are connected

(Option:LNB)

LNB_OUT

C6915 18pF

OPT

C6916 18pF

LNB

Close to Tuner Surge protectioin

C6913 33pF

OPT

C6914 33pF

LNB

D6904

LNB

R6906

2.2K 1W

LNB

MBR230LSFT1G

C6900

0.22uF

LNB

25V

A_GND

2A

D6900

LNB

30V

D6901-*1

LNB_SX34

40V

D6901

LNB_SMAB34

40V

C6901

0.01uF 50V

LNB

C6912

C6902 1uF

68uF

50V LNB

close to Boost pin(#1)

LNB_TX

35V

LNB

C6904

0.1uF 50V

LNB

C6903 0.1uF

LNB

A_GND

C6905 22000pF

C6906

68uF

35V

LNB

DCDC_GND

LNB

D6902 LNB_SMAB34

40V

D6902-*1 LNB_SX34

40V

A_GND

D6903-*1

LNB_SX34

LNB_SMAB34

BOOST

VCP

TCAP

NC_1

TDO

EXTM

TDI

40V

D6903

40V

DCDC_GND

LNB

[EP]

1

2

3

4

5

6

7

GND

28

THERMAL

8

3A

LNB L6900

33UH

SP-7850_33

2.4A

BFI

VIN

GNDLX

24

25

26LX27

29

IC6900

A8290SETTR-T

LNB

9

10

SDA11ADD12SCL

VREG

LNB

R6901 33

R6900 33

LNB

OPT

C6907 0.22uF

C6908 27pF

Input trace widths should be sized to conduct at least 3A Ouput trace widths should be sized to conduct at least 2A

+12V_LNB

A_GND

C6911

0.1uF 50V

close to VIN pin(#25)

LNB

NC_9

23

13

NC_2

LNB

27pF

C6909

BFO

IRQ

OPT

C6910 10uF 25V

LNB

DCDC_GND

22

NC_8

21

NC_7

20

BFC

19

NC_6

18

NC_5

17

NC_4

16

NC_3

15

14

+3.3V_NORMAL

R6903

4.7K

LNB

R6904 0

A_GND

+12V

BLM18PG121SN1D

C6917

0.1uF 50V LNB

L6901

LNB

DCDC_GND

Max 1.3A

+12V_LNB

A_GND

C6918

0.1uF 50V

LNB

R6905 0

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

A_GND

I2C_SDA4

I2C_SCL4

LNB

2011.11.21

69

LOCAL DIMMING

LGE Internal Use Only

[To LED DRIVER]

P7600

12507WR-08L

L/DIM_OUT

1

2

3

4

5

6

7

8

9

+3.3V_NORMAL

R7600 10K OPT

R7601 10K

L/DIM_OUT

AR7600

33

1/16W

L/DIM_OUT

R7606 33

L/DIM_OUT

R7607

4.7K L/DIM_OUT

L/DIM0_SCLK

L/DIM0_MOSI

I2C_SCL1

I2C_SDA1

L/DIM0_VS

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LOCAL DIMMING

2011.12.13

76

[51Pin LVDS Connector]

LGE Internal Use Only

(For FHD FRC3 HS_LVDS) For LM9900

P7900

FI-RE51S-HF-J-R1500

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND

NC

LVDS_SEL

NC

L/DIM_ENABLE

GND

RA0N

RA0P

RA1N

RA1P

RA2N

RA2P

GND

RACLKN

RACLKP

GND

RA3N

RA3P

RA4N

RA4P

GND

BIT_SEL

RB0N

RB0P

RB1N

RB1P

RB2N

RB2P

GND

RBCLKN

RBCLKP

GND

RB3N

RB3P

RB4N

RB4P

GND

NC

VLCD

TP7910

TXC0N

TXC0P

TXC1N

TXC1P

TXC2N

TXC2P

TXCCLKN

TXCCLKP

TXC3N

TXC3P

TXC4N

TXC4P

TXD0N

TXD0P

TXD1N

TXD1P

TXD2N

TXD2P

TXDCLKN

TXDCLKP

TXD3N

TXD3P

TXD4N

TXD4P

L/DIM0_SCLK

L/DIM0_MOSI

L/DIM0_VS

I2C_BE_SDA1

I2C_BE_SCL1

FRC3_RESET

BPL_IN

LOCAL_DIM_EN LOCAL_DIM_EN

PANEL_VCC

120-ohm

L7900

C7900 10uF 16V

OPT

C7901 1000pF 50V

OPT

C7902

0.1uF 16V

OPT

10K

R7900

R7901 0

FRC3_FLASH_WP

L/DIM0_SCLK

L/DIM0_MOSI

L/DIM0_VS

I2C_BE_SDA1

I2C_BE_SCL1

FRC3_RESET

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LG1152 B0

Interface block

79 100

eMMC I/F

LGE Internal Use Only

EMMC_DATA[0-7]

EMMC_VCCQ

EMMC DATA LINE 47K PULL/UP

EMMC DATA LINE 10K PULL/UP

R8100 10K

R8101 10K

R8102 10K

R8103 10K

R8104 10K

R8105 10K

R8106 10K

C8107 10pF 50V

R8107 10K

DAT4

DAT3

R8100-*1 47K

R8102-*1 47K

R8101-*1 47K

EMMC_DATA[0] EMMC_DATA[1] EMMC_DATA[2] EMMC_DATA[3]

EMMC_DATA[4] EMMC_DATA[5] EMMC_DATA[6] EMMC_DATA[7]

EMMC_CLK EMMC_CMD EMMC_RST

R8103-*1 47K

R8104-*1 47K

R8105-*1 47K

R8106-*1 47K

R8107-*1 47K

AR8100 22 1/16W

AR8101 22 1/16W

AR8102 22

OPT

C8100

0.1uF

OPT

16V

Don’t Connect Power At VDDI

(Just Interal LDO Capacitor)

DAT5

DAT6

10K

R8117

EMMC_CLK_BALL

EMMC_CMD_BALL

10K

R8116

EMMC_RESET_BALL

EMMC_VCCQ

EMMC_VDDI

C8105

0.1uF 16V

EMMC_VDDI

C8106

2.2uF 10V

3.3V_EMMC

C8102

0.1uF 16V

DAT3 DAT4

DAT5

C8103

2.2uF 10V

C8104

0.1uF 16V

SDIN5D2-4G-974L1

A3

DAT0

A4

DAT1

A5

DAT2

B2

DAT3

B3

DAT4

B4

DAT5

B5

DAT6

B6

DAT7

M6

CLK

M5

CMD

A6

NC_3

A7

NC_4

C5

NC_23

E5

NC_42

E8

NC_43

E9

NC_44

E10

NC_45

F10

NC_52

G3

NC_58

G10

NC_59

H5

NC_66

J5

NC_73

K6

NC_80

K7

NC_81

K10

NC_82

P7

NC_116

P10

NC_119

K5

RESET

C6

VCCQ_1

M4

VCCQ_2

N4

VCCQ_3

P3

VCCQ_4

P5

VCCQ_5

E6

VCC_1

F5

VCC_2

J10

VCC_3

K9

VCC_4

C2

VDDI

E7

VSS_1

G5

VSS_2

H10

VSS_3

K8

VSS_4

C4

VSSQ_1

N2

VSSQ_2

N5

VSSQ_3

P4

VSSQ_4

P6

VSSQ_5

A1

NC_1

A2

NC_2

A8

NC_5

A9

NC_6

A10

NC_7

A11

NC_8

A12

NC_9

A13

NC_10

A14

NC_11

B1

NC_12

B7

NC_13

B8

NC_14

B9

NC_15

B10

NC_16

B11

NC_17

B12

NC_18

B13

NC_19

B14

NC_20

C1

NC_21

C3

NC_22

C7

NC_24

IC8100

C8

NC_25

C9

NC_26

C10

NC_27

C11

NC_28

C12

NC_29

C13

NC_30

C14

NC_31

D1

NC_32

D2

NC_33

D3

NC_34

D4

NC_35

D12

NC_36

D13

NC_37

D14

NC_38

E1

NC_39

E2

NC_40

E3

NC_41

E12

NC_46

E13

NC_47

E14

NC_48

F1

NC_49

F2

NC_50

F3

NC_51

F12

NC_53

F13

NC_54

F14

NC_55

G1

NC_56

G2

NC_57

G12

NC_60

G13

NC_61

G14

NC_62

H1

NC_63

H2

NC_64

H3

NC_65

H12

NC_67

H13

NC_68

H14

NC_69

J1

NC_70

J2

NC_71

J3

NC_72

J12

NC_74

J13

NC_75

J14

NC_76

K1

NC_77

K2

NC_78

K3

NC_79

K12

NC_83

K13

NC_84

K14

NC_85

L1

NC_86

L2

NC_87

L3

NC_88 NC_89 NC_90 NC_91 NC_92 NC_93 NC_94 NC_95 NC_96 NC_97 NC_98

NC_99 NC_100 NC_101 NC_102 NC_103 NC_104 NC_105 NC_106 NC_107 NC_108 NC_109 NC_110 NC_111 NC_112 NC_113 NC_114 NC_115 NC_117 NC_118 NC_120 NC_121 NC_122 NC_123

L12 L13 L14 M1 M2 M3 M7 M8 M9 M10 M11 M12 M13 M14 N1 N3 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P8 P9 P11 P12 P13 P14

SANDISK_EMMC_4GB

DAT5

DAT6

EMMC_RESET_BALL

EMMC_CMD_BALL

EMMC_CLK_BALL

A3 A4 A5 B2 B3 B4 B5 B6

M6 M5

A6 A7 C5 E5 E8

E9 E10 F10

G3 G10

H5

J5

K6

K7 K10

P7 P10

K5

C6

M4

N4

P3

P5

E6

F5 J10

K9

C2

E7

G5 H10

K8

C4

N2

N5

P4

P6

A1

A2

A8

A9 A10 A11 A12 A13 A14

B1

B7

B8

B9 B10 B11 B12 B13 B14

C1

C3

C7

IC8100-*3

H26M31001EFR

DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7

CLK CMD

NC_3 NC_4 NC_23 NC_42 NC_43 NC_44 NC_45 NC_52 NC_58 NC_59 NC_66 NC_73 NC_80 NC_81 NC_82 NC_116 NC_119

RESET

VCCQ_1 VCCQ_2 VCCQ_3 VCCQ_4 VCCQ_5

VCC_1 VCC_2 VCC_3 VCC_4

VDDI

VSS_1 VSS_2 VSS_3 VSS_4 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

NC_1 NC_2 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_24

C8

NC_25

C9

NC_26

C10

NC_27

C11

NC_28

C12

NC_29

C13

NC_30

C14

NC_31

D1

NC_32

D2

NC_33

D3

NC_34

D4

NC_35

D12

NC_36

D13

NC_37

D14

NC_38

E1

NC_39

E2

NC_40

E3

NC_41

E12

NC_46

E13

NC_47

E14

NC_48

F1

NC_49

F2

NC_50

F3

NC_51

F12

NC_53

F13

NC_54

F14

NC_55

G1

NC_56

G2

NC_57

G12

NC_60

G13

NC_61

G14

NC_62

H1

NC_63

H2

NC_64

H3

NC_65

H12

NC_67

H13

NC_68

H14

NC_69

J1

NC_70

J2

NC_71

J3

NC_72

J12

NC_74

J13

NC_75

J14

NC_76

K1

NC_77

K2

NC_78

K3

NC_79

K12

NC_83

K13

NC_84

K14

NC_85

L1

NC_86

L2

NC_87

L3

NC_88

L12

NC_89

L13

NC_90

L14

NC_91

M1

NC_92

M2

NC_93

M3

NC_94 NC_95 NC_96 NC_97 NC_98

NC_99 NC_100 NC_101 NC_102 NC_103 NC_104 NC_105 NC_106 NC_107 NC_108 NC_109 NC_110 NC_111 NC_112 NC_113 NC_114 NC_115 NC_117 NC_118 NC_120 NC_121 NC_122 NC_123

M7 M8 M9 M10 M11 M12 M13 M14 N1 N3 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P8 P9 P11 P12 P13 P14

DEV_HYNIX_EMMC_4GB

A3 A4 A5 B2 B3 B4 B5 B6

M6 M5

A6 A7 C5 E5 E8

E9 E10 F10

G3 G10

H5

J5

K6

K7 K10

P7 P10

K5

C6

M4

N4

P3

P5

E6

F5 J10

K9

C2

E7

G5 H10

K8

C4

N2

N5

P4

P6

A1

A2

A8

A9 A10 A11 A12 A13 A14

B1

B7

B8

B9 B10 B11 B12 B13 B14

C1

C3

C7

IC8100-*1

H26M21001ECR

DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7

CLK CMD

NC_3 NC_4 NC_23 NC_42 NC_43 NC_44 NC_45 NC_52 NC_58 NC_59 NC_66 NC_73 NC_80 NC_81 NC_82 NC_116 NC_119

RESET

VCCQ_1 VCCQ_2 VCCQ_3 VCCQ_4 VCCQ_5

VCC_1 VCC_2 VCC_3 VCC_4

VDDI

VSS_1 VSS_2 VSS_3 VSS_4 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5

NC_1 NC_2 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_24

C8

NC_25

C9

NC_26

C10

NC_27

C11

NC_28

C12

NC_29

C13

NC_30

C14

NC_31

D1

NC_32

D2

NC_33

D3

NC_34

D4

NC_35

D12

NC_36

D13

NC_37

D14

NC_38

E1

NC_39

E2

NC_40

E3

NC_41

E12

NC_46

E13

NC_47

E14

NC_48

F1

NC_49

F2

NC_50

F3

NC_51

F12

NC_53

F13

NC_54

F14

NC_55

G1

NC_56

G2

NC_57

G12

NC_60

G13

NC_61

G14

NC_62

H1

NC_63

H2

NC_64

H3

NC_65

H12

NC_67

H13

NC_68

H14

NC_69

J1

NC_70

J2

NC_71

J3

NC_72

J12

NC_74

J13

NC_75

J14

NC_76

K1

NC_77

K2

NC_78

K3

NC_79

K12

NC_83

K13

NC_84

K14

NC_85

L1

NC_86

L2

NC_87

L3

NC_88

L12

NC_89

L13

NC_90

L14

NC_91

M1

NC_92 NC_93 NC_94 NC_95 NC_96 NC_97 NC_98

NC_99 NC_100 NC_101 NC_102 NC_103 NC_104 NC_105 NC_106 NC_107 NC_108 NC_109 NC_110 NC_111 NC_112 NC_113 NC_114 NC_115 NC_117 NC_118 NC_120 NC_121 NC_122 NC_123

M2 M3 M7 M8 M9 M10 M11 M12 M13 M14 N1 N3 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P8 P9 P11 P12 P13 P14

HYNIX_EMMC_2GB

KLM2G1HE3F-B001

A3

DAT0

A4

DAT1

A5

DAT2

B2

DAT3

B3

DAT4

B4

DAT5

B5

DAT6

B6

DAT7

M6

CLK

M5

CMD

A6

NC_3

A7

NC_4

C5

NC_23

E5

NC_42

E8

NC_43

E9

NC_44

E10

NC_45

F10

NC_52

G3

NC_58

G10

NC_59

H5

NC_66

J5

NC_73

K6

NC_80

K7

NC_81

K10

NC_82

P7

NC_116

P10

NC_119

K5

RSTN

C6

VDD_1

M4

VDD_2

N4

VDD_3

P3

VDD_4

P5

VDD_5

E6

VDDF_1

F5

VDDF_2

J10

VDDF_3

K9

VDDF_4

C2

VDDI

C4

VSS_1

E7

VSS_2

G5

VSS_3

H10

VSS_4

K8

VSS_5

N2

VSS_6

N5

VSS_7

P4

VSS_8

P6

VSS_9

A1

NC_1

A2

NC_2

A8

NC_5

A9

NC_6

A10

NC_7

A11

NC_8

A12

NC_9

A13

NC_10

A14

NC_11

B1

NC_12

B7

NC_13

B8

NC_14

B9

NC_15

B10

NC_16

B11

NC_17

B12

NC_18

B13

NC_19

B14

NC_20

C1

NC_21

C3

NC_22

C7

NC_24

IC8100-*2

C8

NC_25

C9

NC_26

C10

NC_27

C11

NC_28

C12

NC_29

C13

NC_30

C14

NC_31

D1

NC_32

D2

NC_33

D3

NC_34

D4

NC_35

D12

NC_36

D13

NC_37

D14

NC_38

E1

NC_39

E2

NC_40

E3

NC_41

E12

NC_46

E13

NC_47

E14

NC_48

F1

NC_49

F2

NC_50

F3

NC_51

F12

NC_53

F13

NC_54

F14

NC_55

G1

NC_56

G2

NC_57

G12

NC_60

G13

NC_61

G14

NC_62

H1

NC_63

H2

NC_64

H3

NC_65

H12

NC_67

H13

NC_68

H14

NC_69

J1

NC_70

J2

NC_71

J3

NC_72

J12

NC_74

J13

NC_75

J14

NC_76

K1

NC_77

K2

NC_78

K3

NC_79

K12

NC_83

K13

NC_84

K14

NC_85

L1

NC_86

L2

NC_87

L3

NC_88

L12

NC_89

L13

NC_90

L14

NC_91

SAMSUNG_EMMC_2GB

NC_92 NC_93 NC_94 NC_95 NC_96 NC_97 NC_98

NC_99 NC_100 NC_101 NC_102 NC_103 NC_104 NC_105 NC_106 NC_107 NC_108 NC_109 NC_110 NC_111 NC_112 NC_113 NC_114 NC_115 NC_117 NC_118 NC_120 NC_121 NC_122 NC_123

M1 M2 M3 M7 M8 M9 M10 M11 M12 M13 M14 N1 N3 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P8 P9 P11 P12 P13 P14

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

DU1

DUMMY_1

DU2

DUMMY_2

DU3

DUMMY_3

DU4

DUMMY_4

DU5

DUMMY_5

DU6

DUMMY_6

DU7

DUMMY_7

DU8

DUMMY_8

DUMMY_9 DUMMY_10 DUMMY_11 DUMMY_12 DUMMY_13 DUMMY_14 DUMMY_15 DUMMY_16

DU9 DU10 DU11 DU12 DU13 DU14 DU15 DU16

DU1

DUMMY_1

DU2

DUMMY_2

DU3

DUMMY_3

DU4

DUMMY_4

DU5

DUMMY_5

DU6

DUMMY_6

DU7

DUMMY_7

DU8

DUMMY_8

DUMMY_9 DUMMY_10 DUMMY_11 DUMMY_12 DUMMY_13 DUMMY_14 DUMMY_15 DUMMY_16

DU9 DU10 DU11 DU12 DU13 DU14 DU15 DU16

eMMC

11.09.29

81

*LEX9 FORMATTER POWER SUPPLY

LGE Internal Use Only

If current of 12V is over 2A through 51P LVDS cable, use this power cable

PANEL_VCC

P8800

12507WR-04L

1

2

3

4

5

CIS21J121

C8800 10uF

25V

L8800

C8801 10uF

25V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LG1152

72" SUB POWER

2011.08.19 88

DDR0 PHY VREF

LGE Internal Use Only

DDR_A[0-13]

DDR_RESET_N

DDR_DATA[0-15]

Connect A13 for Using 2Gbit Memory

DDR_CLK

DDR_CLKN

+1.5VQ

DDR_ODT

R9400

200

DDR_RASN DDR_CASN

DDR_WEN

DDR_DQS_N[0]

DDR_DQS_N[1]

DDR_A[0] DDR_A[1] DDR_A[2] DDR_A[3] DDR_A[4] DDR_A[5] DDR_A[6] DDR_A[7] DDR_A[8] DDR_A[9] DDR_A[10] DDR_A[11] DDR_A[12] DDR_A[13]

DDR_BA[0] DDR_BA[1] DDR_BA[2]

R9401

DDR_CKE

DDR_DQS[0]

DDR_DQS[1]

DDR_DM[0] DDR_DM[1]

DDR_DATA[0] DDR_DATA[1] DDR_DATA[2] DDR_DATA[3] DDR_DATA[4] DDR_DATA[5] DDR_DATA[6] DDR_DATA[7]

DDR_DATA[8] DDR_DATA[9] DDR_DATA[10] DDR_DATA[11] DDR_DATA[12] DDR_DATA[13] DDR_DATA[14] DDR_DATA[15]

100 1%

IC9400

H5TQ1G63DFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

NC_1 NC_2 NC_3 NC_4 NC_6

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

M8

H1

L8

ZQ

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1 J9 L1 L9 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+0.75V_VREF_M0

R9402

240 1%

+0.75V_VREF_M1

+1.5VQ

DDR_A[0-13]

Connect A13 for Using 2Gbit Memory

DDR_DATA[0-15]

+0.75V_VREF_D0

+0.75V_VREF_D1

DDR_A[0] DDR_A[1] DDR_A[2] DDR_A[3] DDR_A[4] DDR_A[5] DDR_A[6] DDR_A[7] DDR_A[8] DDR_A[9] DDR_A[10] DDR_A[11] DDR_A[12]

DDR_A[13]

DDR_DATA[0] DDR_DATA[1] DDR_DATA[2] DDR_DATA[3] DDR_DATA[4] DDR_DATA[5] DDR_DATA[6] DDR_DATA[7] DDR_DATA[8] DDR_DATA[9] DDR_DATA[10] DDR_DATA[11] DDR_DATA[12] DDR_DATA[13] DDR_DATA[14] DDR_DATA[15]

DDR_CLK

DDR_CLKN

DDR_DQS[0]

DDR_DQS_N[0]

DDR_DQS[1]

DDR_DQS_N[1]

DDR_CKE

DDR_WEN DDR_RASN DDR_CASN

DDR_ODT

DDR_DM[0] DDR_DM[1] DDR_BA[0] DDR_BA[1] DDR_BA[2]

DDR_RESET_N

R9403 240

+1.5VQ

C9417

1000pF

R9409 1K 1%

+1.5VQ

R9410 1K 1%

R9411 1K 1%

+0.75V_VREF_D1

C9419

0.1uF

+0.75V_VREF_M1

C9421

1000pF

C9422

1000pF

C9420

0.1uF

R9406 1K 1%

R9407 1K 1%

C9410

OPT

+0.75V_VREF_M0

C9413

0.1uF

+1.5VQ

C9416

C9414

0.1uF

0.1uF OPT

OPT

R9408

1K 1%

C9415

0.1uF

C9418

0.1uF

IC9300 LG1132

V21

DDR_A[0]

B22

DDR_A[1]

V20

DDR_A[2]

T20

DDR_A[3]

C22

DDR_A[4]

T21

DDR_A[5]

C21

DDR_A[6]

T22

DDR_A[7]

C20

DDR_A[8]

U22

DDR_A[9]

D22

DDR_A[10]

B21

DDR_A[11]

D20

DDR_A[12]

U21

DDR_A[13]

B20

DDR_A[14]

M22

DDR_DQ[0]

G20

DDR_DQ[1]

N20

DDR_DQ[2]

F22

DDR_DQ[3]

N22

DDR_DQ[4]

F20

DDR_DQ[5]

N21

DDR_DQ[6]

F21

DDR_DQ[7]

H21

DDR_DQ[8]

L22

DDR_DQ[9]

G22

DDR_DQ[10]

M20

DDR_DQ[11]

H22

DDR_DQ[12]

L21

DDR_DQ[13]

H20

DDR_DQ[14]

L20

DDR_DQ[15]

E22

DDR_CK

E21

DDR_CK_N

K22

DDR_DQS[0]

K21

DDR_DQS_N[0]

J22

DDR_DQS[1]

J21

DDR_DQS_N[1]

E20

DDR_CKE

R20

DDR_WE_N

P20

DDR_RAS_N

P21

DDR_CAS_N

P22

DDR_ODT

G21

DDR_DM[0]

M21

DDR_DM[1]

R21

DDR_BA[0]

D21

DDR_BA[1]

R22

DDR_BA[2]

U20

DDR_RST_N

A20

1%

V22 A21

E19 F19 G19 H19 J19 J20 K19 K20 L19 M19 N19 P19 R19

DDR_ZQ_CAL

DDR_VREF0 DDR_VREF1

DDR_VDDQ_1 DDR_VDDQ_2 DDR_VDDQ_3 DDR_VDDQ_4 DDR_VDDQ_5 DDR_VDDQ_6 DDR_VDDQ_7 DDR_VDDQ_8 DDR_VDDQ_9 DDR_VDDQ_10 DDR_VDDQ_11 DDR_VDDQ_12 DDR_VDDQ_13

+1.5V_LG1132

L9400

BLM18SG121TN1D

C9401

4.7uF

+1.5VQ

R9404

1K 1%

R9405

C9400

1K

0.1uF

1%

+1.5VQ

DDR3 1.5V Decaps - Place these caps near Memory

C9404

C9405

C9402

0.1uF

DDR3 1.5V/0.75V Decap

- Place these caps near IC101

+0.75V_VREF_D0

C9403

0.1uF

C9408

0.1uF

OPT

+0.75V_VREF_D1

C9409

0.1uF

+1.5VQ

C9407

4.7uF

+0.75V_VREF_D0

C9406

0.1uF

C9411

0.1uF

1000pF

C9412

0.1uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LG1132 DDR3 2011. 06 .28

LG1132 DDR3

3D-Depth Analog for 2.5V

LGE Internal Use Only

+1.5V_DDR

+1.5V_LG1132

L9500

BLM18PG121SN1D

+5V_USB

ZD9500

5.48VTO5.76V

Place near USB JACK

L9 CORE for 1.0V

+3.3V_NORMAL

C9500

10uF

10V

+2.5V

VCC

IN

PG

EN

IC9500

1

2

3

1.5A

4

9

THERMAL

[EP]

OUT

8

FB

7

SS

6

GND

5

AP7173-SPG-13 HF(DIODES)

R9500 10K

Vout=0.8*(1+R1/R2)

C9501 2200pF 50V

Max 600 mA

R9502

R1

4.3K 1%

R9501 2K 1%

R2

+2.5V_LG1132

C9513 10uF 10V

C9514

0.1uF 16V

LG1152 for 1.0V

+1.0VDC

**NON UD Model

LG1132 DDR = 668Mhz

LG1152 1.0V ==> IC2306 LG1132 1.0V ==> IC2306

**UD Model

LG1132 DDR = 792Mhz

LG1152 1.0V ==> IC2501 LG1132 1.1V ==> IC2306

NON_UD CIC21J501NE

L9502

Max 2000 mA

+1.0V_VDD

(UD Model only / LG1132 DDR=792Mh)

+12V

UD

Switching freq: 700K

READY

L9501 BLM18PG121SN1D

C9502 10uF 16V

POWER_ON/OFF2_3

R1

UD

R9503

C9503 100pF

50V

UD

R9505

R2

Max 2000 mA

IC9501

TPS54327DDAR

R9504 10K

11K

33K

1%

UD

C9504

UD

1uF 10V

1%

UD

VREG5

C9505 3300pF 50V

VFB

EN

1

2

THERMAL

3

SS

4

3A

[EP]GND

VIN

8

VBST

9

7

UD

SW

6

GND

5

UD

Vout=0.765*(1+R1/R2)

16V

0.1uF C9506

UD

L9503

3.6uH

UD

+1.0V_VDD

C9507 22uF 10V

OPT C9508 22uF 10V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LG1132 Power 2011. 06. 28

LG1132 POWER

SOC_TXA0P

LGE Internal Use Only

SOC_TXA0N SOC_TXA1P SOC_TXA1N SOC_TXA2P

SOC_TXA2N SOC_TXACLKP SOC_TXACLKN

SOC_TXA3P

SOC_TXA3N

SOC_TXA4P

SOC_TXA4N

SOC_TXB0P

SOC_TXB0N

SOC_TXB1P

SOC_TXB1N

SOC_TXB2P

SOC_TXB2N SOC_TXBCLKP SOC_TXBCLKN

SOC_TXB3P

SOC_TXB3N

SOC_TXB4P

SOC_TXB4N

P9301

12507WS-04L

DEBUG

5

I2C_SDA2 I2C_SCL2

I2C_SDA1

I2C_SCL1

R9302

R9300 100

R9301 100

+3.3V_NORMAL

1

2

3

4

TXA0P TXA0N TXA1P TXA1N TXA2P TXA2N TXACLKP TXACLKN TXA3P TXA3N TXA4P TXA4N

TXB0P TXB0N TXB1P TXB1N TXB2P TXB2N TXBCLKP TXDCLKP TXBCLKN TXB3P TXB3N TXB4P TXB4N

0

OPT

100

R9303 100

R9345

0

OPT

R9344

R9304 100

R9305 100

TRST_N

SPI_SCLK

SPI_CS SPI_DI SPI_DO

I2C_SDA2 I2C_SCL2

TDO TDI TCK TMS

3D_DEPTH_RESET

XTAL_OUT

XTAL_IN

R9306 100

R9307 100

R9308 100

R9309 100

TRST_N

TXC0P TXC0N TXC1P TXC1N TXC2P TXC2N TXCCLKP TXCCLKN TXC3P TXC3N TXC4P TXC4N

TXD0P TXD0N TXD1P TXD1N TXD2P TXD2N

TXDCLKN TXD3P TXD3N TXD4P TXD4N

IC9300 LG1132

AB17

RXA0P

AA17

RXA0N

Y16

RXA1P

Y17

RXA1N

AA16

RXA2P

AB16

RXA2N

AB15

RXACLKP

AA15

RXACLKN

Y14

RXA3P

Y15

RXA3N

AA14

RXA4P

AB14

RXA4N

AB13

RXB0P

AA13

RXB0N

Y12

RXB1P

Y13

RXB1N

AA12

RXB2P

AB12

RXB2N

AB11

RXBCLKP

AA11

RXBCLKN

Y10

RXB3P

Y11

RXB3N

AA10

RXB4P

R9312 33 R9313 33

R9314 33

R9315 33 R9316 33 R9317 33 R9318 33

R9319 33

AB10

AB21 AA21

RXB4N

AB9

RXC0P

AA9

RXC0N

Y8

RXC1P

Y9

RXC1N

AA8

RXC2P

AB8

RXC2N

AB7

RXCCLKP

AA7

RXCCLKN

Y6

RXC3P

Y7

RXC3N

AA6

RXC4P

AB6

RXC4N

AB5

RXD0P

AA5

RXD0N

Y4

RXD1P

Y5

RXD1N

AA4

RXD2P

AB4

RXD2N

AB3

RXDCLKP

AA3

RXDCLKN

Y2

RXD3P

Y3

RXD3N

AA2

RXD4P

AB2

RXD4N

D3

UART_RXD

D2

UART_TXD

C2

SPI_SCLK

C1

SPI_CS

B1

SPI_DI

B2

SPI_DO

E2

SDA_M

E1

SCL_M

D1

SDA_S

E3

SCL_S

F2

SMODE

F1

TMODE0

G3

TMODE1

G2

TMODE2

G1

TMODE3

H1

TRST_N

H3

TDO

H2

TDI

J3

TCK

J2

TMS

F3

PORES_N

XTALO XTALI

R9310 100

R9311 100

SMODE TMODE0 TMODE1 TMODE2 TMODE3

TDO TDI TCK TMS

TXA0P TXA0N TXA1P TXA1N TXA2P

TXA2N TXACLKP TXACLKN

TXA3P

TXA3N

TXA4P

TXA4N

TXB0P

TXB0N

TXB1P

TXB1N

TXB2P

TXB2N TXBCLKP TXBCLKN

TXB3P

TXB3N

TXB4P

TXB4N

TXC0P

TXC0N

TXC1P

TXC1N

TXC2P

TXC2N TXCCLKP TXCCLKN

TXC3P

TXC3N

TXC4P

TXC4N

TXD0P

TXD0N

TXD1P

TXD1N

TXD2P

TXD2N TXDCLKP TXDCLKN

TXD3P

TXD3N

TXD4P

TXD4N

GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9]

GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31]

A10 B10 C9 C10 B9 A9 A8 B8 C7 C8 B7 A7

A6 B6 C5 C6 B5 A5 A4 B4 C3 C4 B3 A3

A18 B18 C17 C18 B17 A17 A16 B16 C15 C16 B15 A15

A14 B14 C13 C14 B13 A13 A12 B12 C11 C12 B11 A11

Y1 W3 W2 W1 V3 V2 V1 U3 U2 U1 T3 T2 T1 R3 R2 R1 P3 P2 P1 N3 N2 N1 M3 M2 M1 L1 L2 L3 K1 K2 K3 J1

TXA0P TXA0N TXA1P TXA1N TXA2P TXA2N TXACLKP TXACLKN TXA3P TXA3N TXA4P TXA4N

TXB0P TXB0N TXB1P TXB1N TXB2P TXB2N TXBCLKP TXBCLKN TXB3P TXB3N TXB4P TXB4N

TXC0P TXC0N TXC1P TXC1N TXC2P TXC2N TXCCLKP TXCCLKN TXC3P TXC3N TXC4P TXC4N

TXD0P TXD0N TXD1P TXD1N TXD2P TXD2N TXDCLKP TXDCLKN TXD3P TXD3N TXD4P TXD4N

Monitoring Pins for 3D-Depth Interanl status

R9320 10K

72INCH_LVDS_CD

R9321 10K

NON_72INCH_LVDS_AB

OPT

R9322 10K

R9323 10K

+3.3V_NORMAL

OPT

R9324 10K

R9326 10K

R9325 10K

R9327 10K

+3.3V_IO Decaps

+3.3V_IO

C9300

0.1uF 16V

C9304

0.1uF 16V

OPT

C9308

0.1uF 16V

C9311

C9312

10uF

10V

OPT

10V

XTAL(24.75MHz)

XTAL_IN

C9333 30pF 50V

SPI/I2C For Aardvak Interface

P9300

12507WR-10L

1

2

3

4

5

6

DEBUG

7

8

9

10

11

LG1132 HW RESET

SW9300

JTP-1127WEM

12

DEBUG

4 3

L9303

BLM18SG121TN1D

C9315

4.7uF 10V

+2.5V_LVDS_RX

C9318

4.7uF 10V

+2.5V_LG1132

R9329 1M

X9300

24.75MHz

X-TAL_1

GND_1

+3.3V_NORMAL

OPT

4

1

2

3

+3.3V_NORMAL

R9330 0

R9331 0

R9332 0

R9333 0

R9328

10K

C9336

4.7uF

GND_2

X-TAL_2

OPT

DEBUG

OPT

+2.5V LVDS_RX Decaps

+2.5V_LVDS_RX

C9321

0.1uF 16V

OPT

3D_DEPTH_RESET

C9324

0.1uF 16V

C9339 30pF 50V

SPI_CS

SPI_DO

SPI_SCLK

SPI_DI

3D_DEPTH_RESET

TMODE0

FLASH_WP

I2C_SDA2

I2C_SCL2

C9327

0.1uF 16V

OPT

XTAL_OUT

C9330

0.1uF 16V

SPI FLASH(4M Bit)

R9335

R9334

10K

4.7K

R9336

100K

OPT

R9337

33

1/16W

SPI_CS

SPI_DI

FLASH_WP

TEST MODE Configuration

LG1132 Has Internal Pull-up

Default Setting All ’H’ = Normal Operation Mode

TMODE[3:0] 0000 => System PLL Test 0001 => LVDS Rx Isolation Test 0010 => LVDS Tx Isolation Test 0011 => LVDS Bypass Test 0100 => ALL PLL Test 1001 => DDR PLL IsolationTest 1010 => Functional Test 1011 => MBIST 1100 => Scan Test(Normal) 1101 => Scan Test (Adaptive) 1110 => Display PLL Test 1111 => Normal Operation

System Configuration

Default Setting(’0’) 0 : Boot From Ext. Flash(Normal Booting) 1 : Internal RAM Boot (JTAG Booting)

+1.0V Power Separation

C9353

4.7uF 10V

DO[IO1]

GND

+1.0VDC

IC9301

W25X40BVSSIG

CS

1

2

WP

3

4

R9338 100 R9339 100 R9340 100 R9341 100

C9361

4.7uF 10V

VCC

8

HOLD

7

CLK

6

DI[IO0]

5

LG1132_FLASH

OPT OPT OPT OPT

R9342 100

+3.3V_NORMAL

R9343

3.3K

SMODE

TMODE0 TMODE1 TMODE2 TMODE3

C9365

0.1uF

SPI_SCLK

SPI_DO

+3.3V_IO

+2.5V_LVDS_RX

+2.5V_LVDS_TX

+1.0V_PLL_VDD

+2.5V_AVDD

+3.3V_XTAL_AVDD

+1.0VDC

AA22

AA19 AA20 AB20 AB19

H8

H9 H14 H15

J8 J15

K8 K15

L8 L15

M8 M15

N8 N15

P8 P15

R8

R9 R10 R11 R12 R13 R14 R15

F4

G4

H4

J4

K4

L4

M4

N4

P4

R4

T4

U4

W7

W8

W9 W10 W11 W12 W13 W14

H10 H11 H12 H13

D7

D8

D9 D10 D11 D12 D13 D14 D15 D16

Y21 Y22

Y20

A2 A19 B19 C19

D4

D5

D6 D17 D18 D19

E4

E5

E6

E7

E8

E9 E10 E11 E12 E13 E14 E15 E16

IC9300 LG1132

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24

VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 VDD33_7 VDD33_8 VDD33_9 VDD33_10 VDD33_11 VDD33_12

LVRX_VDD25_1 LVRX_VDD25_2 LVRX_VDD25_3 LVRX_VDD25_4 LVRX_VDD25_5 LVRX_VDD25_6 LVRX_VDD25_7 LVRX_VDD25_8

LVTX_VDD10_1 LVTX_VDD10_2 LVTX_VDD10_3 LVTX_VDD10_4

LVTX_VDD25_1 LVTX_VDD25_2 LVTX_VDD25_3 LVTX_VDD25_4 LVTX_VDD25_5 LVTX_VDD25_6 LVTX_VDD25_7 LVTX_VDD25_8 LVTX_VDD25_9 LVTX_VDD25_10

DISP_VDD DR3P_VDD SSP_VDD XTAL_VDD

DISP_AVDD DR3P_AVDD SSP_AVDD XTAL_AVDD

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23

VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119

E17 E18 F5 F18 G5 G18 H5 H18 J5 J9 J10 J11 J12 J13 J14 J18 K5 K9 K10 K11 K12 K13 K14 K18 L5 L9 L10 L11 L12 L13 L14 L18 M5 M9 M10 M11 M12 M13 M14 M18 N5 N9 N10 N11 N12 N13 N14 N18 P5 P9 P10 P11 P12 P13 P14 P18 R5 R18 T5 T18 T19 U5 U18 U19 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W4 W5 W6 W15 W16 W17 W18 W19 W20 W21 W22 Y18 Y19 AA1 AA18 AB18

+1.0VDC Decaps

+3.3V Power Separation

+3.3V_NORMAL

L9300

BLM18SG121TN1D

C9301

4.7uF 10V

+3.3V_IO

C9303

4.7uF 10V

+3.3V XTAL AVDD Decaps

+3.3V_XTAL_AVDD

+3.3V_IO

L9302

BLM18SG121TN1D

C9307

4.7uF 10V

C9310

4.7uF 10V

+3.3V_XTAL_AVDD

C9314

0.1uF 16V

+2.5V_LG1132

+2.5V_LVDS_TX

L9304

BLM18SG121TN1D

C9316

4.7uF 10V

+2.5V DDR PLL/SS PLL/DIS PLL AVDD Decaps

+2.5V_AVDD

L9305

BLM18SG121TN1D

C9317

4.7uF 10V

C9319

4.7uF 10V

C9320

4.7uF 10V

+2.5V_LVDS_TX

C9322

0.1uF 16V

+2.5V_AVDD

C9323

0.1uF 16V

OPT

C9326

0.1uF 16V

OPT

+2.5V LVDS_TX Decaps

C9328

0.1uF 16V

OPT

+1.0VDC

C9348

0.1uF 16V

OPT

+1.0V_XTAL/DDR3 PLL/SS PLL/DIS PLL_VDD

+1.0V_PLL_VDD

+1.0VDC

L9309

BLM18SG121TN1D

C9352

4.7uF 10V

C9357

4.7uF 10V

C9354

0.1uF 16V

OPT

+1.0V_PLL_VDD

C9359

0.1uF 16V

C9363

0.1uF 16V

C9356 10uF 10V

C9360 10uF 10V

C9364

0.1uF 16V

C9366

0.1uF 16V

OPT

MDS62110213

M9300

M9301

M9302

MDS62110213

M9303

MDS62110213

OPT

For Heat Sink

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LG1152 B0 3D Depth

2011. 11. 28

D13005-*1

LGE Internal Use Only

CDS2C20GTHB 20V

DEV_EPCOS_20V

D13006-*1 CDS2C20GTHB 20V

DEV_EPCOS_20V

IR

IR & KEY

COMMERCIAL

MMBT3904(NXP) COMMERCIAL_IR

R13001

Q13000

+3.5V_ST

COMMERCIAL_IR

1K

C

E

R13000 0

IR_BYPASS

COMMERCIAL_IR

R13002

10K

B

COMMERCIAL_IR

MMBT3904(NXP)

COMMERCIAL_IR

R13003

Q13001

+3.5V_ST

3.3K

IR_OUT

R13004

C

B

E

COMMERCIAL_IR

47K

COMMERCIAL

COMMERCIAL_IR_EU

R13005

22

MMBT3904(NXP)

COMMERCIAL_IR_EU

+3.5V_ST

R13007

10K

+3.5V_ST

R13009

1K

COMMERCIAL_IR_EU

C

Q13002

E

R13008 0

COMMERCIAL_IR_US

KEY1

KEY2

IR_BYPASS

COMMERCIAL_IR

R13011

10K

B

MMBT3904(NXP)

COMMERCIAL_IR

R13015

Q13004

R13017

10K

5%

R13013 100

R13014 100

+3.5V_ST

3.3K

+3.5V_ST

C

B

E

R13018

10K

5%

R13019

47K

COMMERCIAL_IR

+3.5V_ST

C13000

0.1uF

RGB Sensor

OPT

D13001

5.6V

D13000

OPT

AMOTECH CO., LTD.

5.6V

C13004 1000pF 50V

LED_B/GP4_LED_R

R13021 100

R13022 100

C13005

0.1uF

C13002

0.1uF

AMOTECH CO., LTD.

L13000

BLM18PG121SN1D

S/T_SCL

S/T_SDA

Soft Touch Micom D/L

EEPROM_SCL

EEPROM_SDA

+3.3V_NORMAL

L13001

BLM18PG121SN1D

16V

C13007

C13006

0.1uF 16V

100pF

50V

R13023 100

R13024 100

R13025 1.5K

D13004

5.6V

D13002

CDS3C05HDMI1

5.6V

D13003

CDS3C05HDMI1

5.6V

D13005 ADUC 20S 02 010L 20V

OPT

D13006 ADUC 20S 02 010L 20V

OPT

AMOTECH CO., LTD.

GP4_IR_10P

P13002

12507WR-10L

1

2

3

4

5

6

7

8

9

10

11

EEPROM_SCL

EEPROM_SDA

KEY1

KEY2

3.5V

LED_B/LOGO

3.3V

LED_R/BUZZ

S/T_SCL

ST_SDA

GND

IR

GND

IR_15P P13003

12507WR-15L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

.

Soft Touch Micom D/L

Zener Diode is

close to wafer

ESD for MTK

D13005-*2 ADUC 20S 02 010L

10pF

20V

ESD_MTK

D13006-*2 ADUC 20S 02 010L 20V

10pF

ESD_MTK

D13000-*1

200pF

5.6V ADMC 5M 02 200L

ESD_MTK

D13001-*1

5.6V

200pF

ADMC 5M 02 200L

ESD_MTK

D13004-*1

200pF

5.6V ADMC 5M 02 200L

ESD_MTK

ESD for LG1152

D13000-*2

200pF

5.6V ADMC 5M 02 200L

ESD_LG1152

D13001-*2

5.6V

200pF

ADMC 5M 02 200L

ESD_LG1152

D13004-*2

200pF

5.6V ADMC 5M 02 200L

ESD_LG1152

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

IR / KEY For LM9900

2011.10. 28

130

System Diagram – Focused on Digital Chip

LGE Internal Use Only

Tuner

HP out

Line out

Audio L/R

x6 ch

MIC

Tuner

CVBS(CHB)

CVBS(x8ch) Component

/RGB

DIF

Audio TS ES Display CPU/GPU

ADC

SIF

L9A L9D

Demod

AUD

PLL

Headphone

DAC DAC

ADC ADC

AAD AFE

AFE (CHB)

AFE (1ch)

AFE (3ch)

LVDS TX (HS)

UART x3I2C x9 SPI x2 SCI

UART x3I2C x12 SPI x2

SRAM DMAC

SC

MCU

SP

ROM

OTP

0

(CI)

TPI0

DSP

AAD

STP out

STP in

(CHB)

Upload

PES DEC

VDEC

core

TS

ENC

JPEG

PES

DEC

MCU

TS

Download

PESDEC

MAU

ICOD

MAU

vpes

(thumbnail)

VDEC

senc

SPE QME HME

IME

CVD

DVR MAU

SDEC

MAU

TPI1

STPI0

SDCAS

STPO

STPI1

DVB-CSA

DES

TDES

AES

apes

SDCORE

2-channel

time-shared

TP engine

vpes

ADEC VENC

PES

DEC

VDEC

core

DISP

IF

DEC

JPEG PNG

ADEC

MAU

TE

MCU

DEBLOCK

VLC

CMC

PREP

Core MAU

PREP MAU

DDR3 x16

DDR3 PHY

DDRC

MHz)

0

40

- Dual-core CPU (CA9)

x

64

- Dual-core GPU (Mail400)

-Multiple MCU (x4)

-Multiple DSP (x2)

Flexnoc (

- Multiple DDR3 Channel (x3)

S

2

TP in

TP out

SPDIF

Speaker

External I

SDIO

Digital

Audio output

Sound

Audio

(BTSC)

Global clock/reset/power mgt.

with PLL + DFT inside

LVDS RX (HS)

Display

PLL CPU

PLL

CRG

+DFT

DCO

CRG

+DFT

DDR3

PLL

DDR3

PLL

GPIO

GPIO WDG Timer

SCI

APB Br

eMMC/SD

USB x3 USB PHY

AHB

CI

SMC GEM

NANDC

L2 $ 1MB

Flexnoc

MHz)

L2 $

64KB

40

x

64

Flexnoc (

GFX

DDRC DDR3 PHY

PP PP

CA9 CA9

VP

DDR3 PHY

Mail400

eMMC/SD USB x3 DVB-CI

EB RGMII/RMII NAND (SLC)

JTAG

DDR3 x16

LVDS RX (HS)

Flexnoc (64x

40

0

MHz)

DDRC

HDMI RX

HDMI x4

MIXED IPs (Bus)

Line out

DAC

CVE

CVD

PRE3D

SMUX

Scaler(R)

IPC(R)

NR(R)

Scaler(L)

IPC(L)

NR(L)

MCU

PQ(R) OSDScaler(sub) 2Dto3D

PQ(L)

OSD

Right

Left

DE

LVDS TX (HS)

L9-3D

System Diagram – Focused on Interface between Analog and Digital Chip

LGE Internal Use Only

Dual Tuner

+ Demod for CHB

Line out (main audio)

DIF

SIF

MIC IN (Mono)

Audio L/R (5-ch)

SCART out

CVBS(CHB)

CVBS-Out CVBS-Out

CVBS(6ch)

Component(2ch)

PC-RGB

HDMI(1ch)

ARC

(1ch)

GBB AFE

1ch@30MHz

w/ PLL

BTSC AFE

10b@18.432MHz

w/ PLL

Audio-ADC

24b@48KHz

SW

Audio-ADC

24b@48KHz

Audio DAC

SW

HDMI-Rx 1.4 (1-port PHY)

3D, ARC, 4kx2k

SW

Audio DAC

CVBS AFE(CHB)

CVBS AFE(2-ch)

10b@165MHz

Analog Chip

1ch mono

1ch L/R

48KHz 48KHz

10b@27MHz

Video DAC

10b@27MHz

12b@54MHz

3ch Video

AFE

w/ LLPLL

HDMI

(1-Link)

Capture

Block (3CH)

3D or UD

Data bridge

Audio PLL

w/ DCO

Global Baseband

V/Q, DVB-T/C

Audio Codec0

(Digital Part)

Audio Codec1

(Digital Part)

12 : CVBS

Mux

I2C

10(data)+1(en)+5(gc)

I2S (mono)

I2S(stero)

3(lrck, lrch, sck)

6+1(clk)+2(gc)

6 (data)

5(gc)

LVDS

I2C

12

1 (ARC data)

6(gbb, l9da)

4(val, err, clk, sop) +8 (data)

Parallel TS

TS (from GCB)

3(lrck, lrch, sck)

I2S

I2S or SPDIF8

Audio Clocks9

I2C

interrupt

System

Demux

AAD

(THAT)

CVD (CHB)

LVDS

I2C

3(hdmi, 3ch, gbb)

Video Decoder

(Dual HD)

H.264 Encoder

SD upto 480p

Audio

Mux

Dual C-A9 (1GHz)

Graphic Engine

2D-VG / 3D Open-ES2.0

Channel Browser

CVBS

Encoder

Video

Mux

Audio

MLC NAND

Digital Chip

Audio DSP

Multi-STD

Audio Decoder

CPU

Diplay

Engine

MC NR,

Vertical MC IPC

Scaler, PE

OSD, VCR

Ethernet

MAC

Controller

USB2.0

Host (x3)

PHY

(3-port)

Sound

DSP

DDR3(x16) * 3

DDR3-PHY

Digital

Audio

Output

LVDS

(Headphone)

I2S

SPDIF

Video

OSD

Internal Clock Architecture – Digital Chip

LGE Internal Use Only

xi_main

xo_main

24Mhz

2 port USB PHY

1 port USB PHY

DDR3PLL

DDR3PLL1

SSC setting

- 0xFD3001CC

- 0xFD3001D0

DDR3PLL2

SSC setting

- 0xFD3001C4

- 0xFD3001D8

SSC setting

- 0xFD3001D4

- 0xFD3001D8

1.6Ghz

30/48 Mhz

30/48Mhz

1 Ghz

CT R

0 1 0 10 1

1/2

1/5

1.6Ghz

800Mhz

i_m01_ddrclk

i_m2_ddrclk

i_core800_clk

i_core320_clk

Clock Divide & Reset generation

w/ test logic

u_crg

Clock Divide & Reset generation

w/ test logic

Clock Divide & Reset generation

w/ test logic

Clock Divide & Reset generation

w/ test logic

Clock Divide & Reset generation

w/ test logic

USB controller

CPU

Memory Controller

Video/Audio Block

CPU peripherial

DCO

200Mhz

DCO

200Mhz

About 220 internally generated clocks

de_dco_out

27Mhz

sdec_dco_out

27Mhz

Glitch-free logic

between

de_dco_out and

sdec_dco_out

CT R

27Mhz

0 1

udnt_buf_dpll_fin

27Mhz

dcoin_clk

SSC setting

-0xFD300108

-0xFD30010C

DISPLL

u_DPLL

disp_fout

sclk

Clock Divide & Reset

generation w/ test logic

TE

DE

L9 Block Diagram (L9-B0 Features)

LGE Internal Use Only

HDMI1 HDMI2

HDMI3 HDMI4

Component

PC-RGB

(WUXGA)

TS In(CHB)

CVBS(CHB)

SIF(1 Ch)

Audio L/R

(5 Ch)

Line-Out

SCART

I2S

CVBS (8 Ch)

CVBS-Out

SCART

(2 Ch)

HDMI

SW

HDMI

(1 Ch)

L9A L9D

AUD

BB_TP_DATA

CHB_DATA

DAC_DATA

AAD_DATA

HSR_P/M

M-Remote_R/TX

DTV TS

EB_DATA

16 16

16

8

RMII

TXA/B

SPIDF_OUT

Built-in WiFi

PHY

51Pin LVDS

MICOM

CI Slot

DDR3 X 3

eMMC

USB2.0x3

Ethernet

Keypad IR

Motion-R

L9 A0 board TS operating block diagram

LGE Internal Use Only

DVB-T/C/S2 by tuner

-DVB-T/C : L9 internal demod

-DVB-S/S2 : Built-in tuner demod

-L9 TS in/out fixed type

-L9 TS out : No high impedance

[P_TS out]

L9 A0

[P_TS out]

L9 A0

DIF

tuner

TS High-Z

[P_TS in]

[ Internal demod without CI for T/C ]

DIF

tuner tuner

TS High-Z

[P_TS in]

[P_TS out]

[P_TS in]

[P_TS out]

CI

[P_TS out]

L9 A0

[P_TS out]

L9 A0

DIF

tuner

TS Output

IC2400

IC2401

[P_TS in]

[ external demod without CI for T2/S2]

DIF

TS Output

[P_TS in]

CI

[P_TS out]

[P_TS in]

CI

[P_TS out]

[ Internal demod with CI for T/C ]

[ external demod with CI for T2/S2]

L9 B0 board TS block Countermeasures

LGE Internal Use Only

◇ Parallel TS out pin Æ in/out pin change

- CI TS out port need to handle the high impedance. (Clock pin a separate control)

- tuner TS out High impedance required treatment.

- CI out TS for SDT parsing and demod out TS should be able to handle both.

DIF for T/C

Internal

T/C demod

Parallel TS out for T2/S2

Tuner

demod

TS parser

Parallel CI TS out for T/C/S

CI

Parallel CI TS in

TUNER

LGE Internal Use Only

DEV_H/NIM

TU2201 / TDSS-H151F

DEV_CHB

TU2203 / TDSQ-H051F

DEV_T2/C/S

TU2202/TDSQ-G251D

TUNER_SIF IF_AGC

TU_CVBS IF_AGC CHB_CVBS

CHB_ERR CHB_SOP CHB_VALID CHB_CLK CHB_DATA

FE_TS_DATA[0-7] FE_TS_SYNC FE_DVB_ERR FE_TS_CLK FE_TS_VAL

/S2_RESET

I2C_SCL4/ SDA4

RF_SWITCH_CTL TUNER_RESET I2C6_SCL/SDA

L9A

L9D

/PCM_CE1,2 TPO_DATA[0-7] CI_ADDR[0-14]

Buffer IC903

74LVC16244ADGG

/CI_CD1,2 CI_TS_DATA[0-7] CI_TS_CLK CI_VAL CI_TS_SYNC

Buffer

IC904

74LVC245A

CI_DATA[0-7]

LNB_OUT

LNB_TX

LNB Part Allegro

IC2300/ A8290SETTR-T

CI Slot

L9 B0 board TS block

LGE Internal Use Only

DVB

T2/C/S2

ATSC

With CHB

DIF

Parallel TS

Demod

L9B0_Ace

Serial TS(CHB)

Parallel TS Parallel TS

Parallel TS

Serial TS

P0

P1

TE

S0 S1

L9B0_D

PHY

JACK INTERFACE

LGE Internal Use Only

AV_L/R_IN

AV_CVBS_DET

SC_DET

SC_CVBS_IN

COMP_Y+/Pb+/Pr+

COMP_DETAV_CVBS_IN

SPDIF_OUT

PC_L/R_IN

HP_L/ROUT

SPDIF

PC_Audio

Earphone Block

SCART

SC_FB/ID_IN 2bit

SC_R/G/B 3bit

SC_L/R_IN

DTV/ATV_SELECT

DTV/MNT_V_OUT

MUX

IC2502

Main Chip

ATV_OUT

EEPROM

IC802/

R1EX24002ASAS0A

RGB_DDC_SCL/SDA 2bit

DSUB_R/G/B 3bit

DSUB_DET

EDID_WP

MICOM

RGB

Tuner

GP4 USB 3_Mid / High Power Block Diagram (Typ)

LGE Internal Use Only

12V

OCP

1.2A

DC-DC

(4A)

Fixed

1.2A

Tol. 20%

USB3

$0.055

External Hub Only

( 4:1 or 6:1)

18W

10W

24V

0.3A

0.4A

+ OCP $0.24

DC-DC

$0.145

OCP

Fixed

1.2A

Tol. 20%

5V

0.8A5V_Normal

400mA

OCP

0.8A

Tol. 10%

OCP

1.8A

Tol. 10%

USB2

$0.055

Wi-Fi

$0.044

MHL

USB1

HDD Only

$0.055

* DC-DC 효율미고려

GP4 USB 3_High Block Diagram

LGE Internal Use Only

SOC L9_A0

USB_DP/DM2

내부

HUB

USB_DP/DM1

EXT_INTR0

GPIO79

USB DP/DM

USB HUB

DP/DM

OCD /CTL

PCBA

DP/DM

OCD /CTL

DP/DM

OCD /CTL

*L9_B0에서는내부Hub 삭제예정

USB1

USB2

USB3

/ External Hub

BT_USB_DP/DM

USB DP/DM

Wi-fi module

HDMI

LGE Internal Use Only

HDMI_HPD_1 ~ 4

5V_HDMI_1 ~ 4

HDMI_HPD_1

HDMI

Switch

(IC3201 / SII9587B)

HDMI Out put 8bits

Main Chip

CSC/D_I2C 2bits

TMDS Link 8bits

DDC_I2C_ 2bits

TMDS Link 8bits

DDC_I2C_ 2bits

TMDS Link 8bits

DDC_I2C_ 2bits

CEC_REMOTE

HDMI_CEC

HDMI1

5V_HDMI_1

HDMI_HPD_2

HDMI_CEC

HDMI2

5V_HDMI_2

HDMI_HPD_3

HDMI_CEC

HDMI3

5V_HDMI_3

MICOM

(IC602)

CEC_REMOTE

TMDS Link 8bits

DDC_I2C_ 2bits

CEC_REMOTE

HDMI_HPD_4

HDMI_CEC

HDMI4/MHL

5V_HDMI_4

AUDIO

LGE Internal Use Only

MICOM

SCART

PC_L/R_IN

SC_L/R_IN

AV_L/R_IN

[AUAD_L_CH5_IN]

[AUAD_L_CH4_IN]

[AUAD_SCART0_OUTL/OUTR]

[AUAD_L_CH3_IN]

[I2SSCK_OUTA/GPIO]

[I2SWS_OUTA/GPIO]

[I2SSD_OUTA0/GPIO]

[SDA1/SCL1]

SCART_Lout/Rout

AUD_SCK/LRCK/LRCH

I2C2_SDA/SCL

OP AMP

DTV/MNT_L/R_OUT

MAIN

NTP7500

Mute

CTRL

[TR]

LPF

SCART_MUTE

AUDIO L/R OUT

4P wafer

LPF

L9

LG1152

GPIO52

Tuner

TR BUF

TU_SIF

[AAD_ADC_SIF]

[ARC0]

[HP_LOUT/ROUT]

[IEC958OUT]

AMP_RESET

AMP_MUTE

MICOM

SIDE_HP_MUTE

HP_LOUT/ROUT

HEAD PHONE

WOOFER

NTP7500

2P wafer

LPF

SPDIF_OUT

SPDIF_OUT_ARC

L9 I2C Map

LGE Internal Use Only

Amp

IC5400

NTP7400L

AMP (WOOFER)

IC5500

NTP7400L

FRCIII

LG1121

P_Gamma IC

BUF08630

PMIC

MAX17139

SPARTAN6

SERDES Rx/Tx

Left_

LED DRIVER

Right_

LED DRIVER

To LED DRIVER

P7600

12507WR-08L

51P LVDS Connector

P3500

FI_RE51S_VF_J_R1300

URSA5 DEBUG

SW 9600

JS2235S

MICOM

(Panel)

100Ω

33Ω

0Ω

+3.3V_Normal

3.3k Ω

+3.3V_Normal

3.3k Ω

I2C_SCL1

I2C_SDA1

I2C_SCL2

I2C_SDA2

SCL0/GPIO60

SDA0/GPIO59

SCL1/GPIO58

SDA1/GPIO57

IC100

LG1152

SCL5/GPIO66

SDA5/GPIO65

SCL3/GPIO70

SDA3/GPIO69

SCL4/GPIO68

SDA4/GPIO67

SCL1/GPIO58

SDA1/GPIO57

SCL2/GPIO56

SDA2/GPIO71

I2C_SCL6

I2C_SDA6

I2C_SCL4

I2C_SDA4

I2C_SCL5

I2C_SDA5

I2C_SCL2

I2C_SDA2

I2C_SCL3

I2C_SDA3

+3.3V_Normal

3.3k Ω

+3.3V_Normal

3.3k Ω

+3.3V_Normal

3.3k Ω

+3.3V_Normal

3.3k Ω

+3.3V_Normal

3.3k Ω

33Ω

22Ω

33Ω

Tuner

TU6503

TDSQ-G051D

LNB

IC6900

A8290SETTER-T

HDMI SWITCH

IC3201

SII9587CNUC

NVRAM

IC102

AT24C256C_SSHL_T

3D DEPTH

LG1131

MICOM

IC3000

T-R5F100GDAFB

Series Back-End Block

LGE Internal Use Only

FHD 240Hz (LM9500)

HS

SoC

LVDS

2-Link 2-Link

3D

Depth

LVDS

FHD 120Hz (LM8500)

HS

SoC

LVDS

2-Link 2-Link

3D

Depth

FHD 120Hz (OLED) _ Wall Pad

HS

LVDS

SoC

2-Link 2-Link

3D

Depth

LVDS

HS

LVDS

HS

FRC-III

SERDES

& OPTIC

Module TX

Vx1 HS

8-Lane

LVDS

4-Link

Optic Cable

T-con

LG5812

T-con

LG5822

SERDES

& OPTIC

Module RX

EPI

16 Lane

EPI

6 Lane

2-Link

HS

LVDS

240Hz

LCM

120Hz

LCM

FRC-III

LVDS

4-Link

120Hz T-con

MAIN

EPI

10 Lane

SUB

120Hz

OLED

UD

HS

LVDS

SoC

2-Link 2-Link

3D

Depth

HS

LVDS

FRC-III

Vx1 HS (TBD)

4 Lane

UD

Scaler

Vx1 HS

16 Lane

UD

T-con

EPI

UD

LCM

Dual 32 Lanes (84” 기준)

LG 72LM9500 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual