LG 60UF770T Schematic

Internal Use Only

North/Latin America http://aic.lgservice.com Europe/Africa http://eic.lgservice.com Asia/Oceania http://biz.lgservice.com

LED TV

SERVICE MANUAL

CHASSIS : LB59J

MODEL : 60UF770T/770V/770Y

60UF770T/770Y-TD 60UF770V-TZ

CAUTION

BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL69324412 (1508-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 10

BLOCK DIAGRAM .................................................................................. 17

EXPLODED VIEW .................................................................................. 26

SCHEMATIC CIRCUIT DIAGRAM ........................................... APPENDIX

TROUBLE SHOOTING GUIDE ................................................. APPENDIX

Only for training and service purposes

- 2 -

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks.

It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication. NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions on page 3 of this publication, always follow the safety precautions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power source before;

a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug

or other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver. CAUTION: A wrong part substitution or incorrect polarity installation of electrolytic capacitors may result in an explosion hazard.

2. Test high voltage only by measuring it with an appropriate high voltage meter or other voltage measuring device (DVM, FETVOM, etc) equipped with a suitable high voltage probe. Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable non-abrasive applicator; 10 % (by volume) Acetone and 90 % (by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture. Unless specied otherwise in this service manual, lubrication

of contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its electrical assemblies unless all solid-state device heat sinks are correctly installed.

7. Always connect the test receiver ground lead to the receiver chassis ground before connecting the test receiver positive lead. Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques should be used to help reduce the incidence of component damage caused by static by static electricity.

1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test.

2. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.

4. Use only an anti-static type solder removal device. Some sol-

der removal devices not classied as “anti-static” can generate electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or comparable conductive material).

7. Immediately before removing the protective material from the leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will be installed. CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity sufcient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle. Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F) b. Heat the component lead until the solder melts. c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand

against the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there only until the solder ows onto and around both the component lead and the foil. CAUTION: Work quickly to avoid overheating the circuit board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

Only for training and service purposes

- 4 -

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through which the IC leads are inserted and then bent at against the circuit foil. When holes are the slotted type, the following technique should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by gently prying up on the lead with the soldering iron tip as the solder melts.

2. Draw away the melted solder with an anti-static suction-type solder removal device (or with solder braid) before removing the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and solder it.

3. Clean the soldered areas with a small wire-bristle brush. (It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor Removal/Replacement

1. Remove the defective transistor by clipping its leads as close as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding leads extending from the circuit board and crimp the "U" with long nose pliers to insure metal to metal contact then solder each connection.

Power Output, Transistor Device Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as possible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit board.

3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder.

3. Solder the connections. CAUTION: Maintain original spacing between the replaced component and adjacent components and the circuit board to prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit board causing the foil to separate from or "lift-off" the board. The following guidelines and procedures should be followed whenever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the following procedure to install a jumper wire on the copper pattern side of the circuit board. (Use this technique only on IC connections).

1. Carefully remove the damaged copper pattern with a sharp knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper pattern and let it overlap the previously scraped end of the good copper pattern. Solder the overlapped area and clip off any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern at connections other than IC Pins. This technique involves the installation of a jumper wire on the component side of the circuit board.

1. Remove the defective copper pattern with a sharp knife. Remove at least 1/4 inch of copper, to ensure that a hazardous condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern break and locate the nearest component that is directly connected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the nearest component on one side of the pattern break to the lead of the nearest component on the other side. Carefully crimp and solder the connections. CAUTION: Be sure the insulated jumper wire is dressed so the it does not touch components or sharp edges.

Fuse and Conventional Resistor Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow stake.

2. Securely crimp the leads of replacement component around notch at stake top.

Only for training and service purposes

- 5 -

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This specification is applied to the LED TV used LB59H / LB59J chassis.

2. Requirement for Test

Each part is tested as below without special notice

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

each drawing and specification by part number in accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC specification

- Wireless : Wireless HD Specification (Option)

4. Model General Specification

No. Item Specication Remarks

1 Market Asia, Oceania, Africa, Middle East(PAL/DVB Market)

2 Television system

3 Channel Storage ATV / DTV - 1500EA

4 Receiving system

5 Video Input RCA PAL, SECAM, NTSC 4 System : PAL, SECAM, NTSC, PAL60

6 Component Input Y/Pb/Pr

7 Head phone out

8 HDMI Input HDMI1-DTV,HDMI2-DTV, *HDMI3-DTV PC(HDMI Ver. 1.4), Support HDCP, * HDMI3 : UF77/UF83

9 Audio Input DVI Audio, Component, AV1

10 SPDIF out SPDIF out

11 USB Input For My Media(Movie/Photo/Music List) or For SVC

1) PAL-BG/DK/I/I’

2) SECAM L/L’, DK, BG, I

3) DVB-T/T2, C, S/S2

Analog : Upper Heterodyne Digital : COFDM(DVB-T) Only DVB-T Model Digital : COFDM(DVB-T/T2) Only DVB-T2 Model Digital : QAM

Antenna, AV1, Component, HDMI1, HDMI2, HDMI3, USB1, USB2, USB3

► DVB-T

- Guard Interval(Bitrate_Mbit/s): 1/4, 1/8, 1/16, 1/32

- Modulation : Code Rate QPSK : 1/2, 2/3, 3/4, 5/6, 7/8 16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

► DVB-T2

- Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,

- Modulation : Code Rate QPSK : 1/2, 2/5, 2/3, 3/4, 5/6 16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

► DVB-C

- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s

- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM

► DVB-S/S2

- Symbolrate DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s DVB-S (QPSK) : 2 ~ 45Msymbol/s

- Viterbi DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8 DVB-S2 mode: 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10

Only for training and service purposes

- 6 -

5. External Input Support Format

5.1. 2D

(1) CVBS input

No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed Remarks

1 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I) NTSC-M

2 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I) NTSC-M

3 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz PAL-BDGHI

(2) Component (Y, CB/PB, CR/PR)

No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed

1 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I)

2 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I)

3 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz

4 720*480p 31.47 59.94 27.00 SDTV 480P

5 720*480p 31.50 60.00 27.03 SDTV 480P

6 720*576p 31.25 50.00 27.00 SDTV 576P 50Hz

7 1280*720 44.96 59.94 74.18 HDTV 720P

8 1280*720 45.00 60.00 74.25 HDTV 720P

9 1280*720 45.00 50.00 74.25 HDTV 720P 50Hz

10 1920*1080 28.13 50.00 74.25 HDTV 1080I 50Hz,

11 1920*1080 33.72 59.94 74.18 HDTV 1080I

12 1920*1080 33.75 60.00 74.25 HDTV 1080I

13 1920*1080 56.25 50.00 148.50 HDTV 1080P

14 1920*1080 67.50 60.00 148.50 HDTV 1080P

Only for training and service purposes

- 7 -

(3) HDMI (DTV)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks

1 640*480 31.47 59.94 25.13 SDTV 480P

2 640*480 31.50 60.00 25.13 SDTV 480P

3 720*480 15.73 59.94 13.50 SDTV, DVD 480I(525I)

Spec. out but display4 720*480 15.75 60.00 13.51 SDTV, DVD 480I(525I)

5 720*576 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz

6 720*480 31.47 59.94 27.00 SDTV 480P

7 720*480 31.50 60.00 27.03 SDTV 480P

8 720*576 31.25 50.00 27.00 SDTV 576P

9 1280*720 44.96 59.94 74.18 HDTV 720P

10 1280*720 45.00 60.00 74.25 HDTV 720P

11 1280*720 37.50 50.00 74.25 HDTV 720P

12 1920*1080 28.13 50.00 74.25 HDTV 1080I

13 1920*1080 33.72 59.94 74.18 HDTV 1080I

14 1920*1080 33.75 60.00 74.25 HDTV 1080I

15 1920*1080 26.97 23.98 63.30 HDTV 1080P

16 1920*1080 27.00 24.00 63.36 HDTV 1080P

17 1920*1080 33.71 29.97 79.12 HDTV 1080P

18 1920*1080 33.75 30.00 79.20 HDTV 1080P

19 1920*1080 56.25 50.00 148.50 HDTV 1080P

20 1920*1080 67.43 59.94 148.35 HDTV 1080P

21 1920*1080 67.50 60.00 148.50 HDTV 1080P

22 3840*2160 53.95 23.98 297.00 UDTV 2160P

23 3840*2160 54.00 24.00 297.00 UDTV 2160P

24 3840*2160 56.25 25.00 297.00 UDTV 2160P

25 3840*2160 61.43 29.97 297.00 UDTV 2160P

26 3840*2160 67.50 30.00 297.00 UDTV 2160P

27 3840*2160 112.50 50.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0

28 3840*2160 135.00 59.94 593.41 UDTV 2160P 8 bit / YCbCr 4:2:0

29 3840*2160 135.00 60.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0

30 4096*2160 53.95 23.98 297.00 UDTV 2160P

31 4096*2160 54.00 24.00 297.00 UDTV 2160P

32 4096*2160 56.25 25.00 297.00 UDTV 2160P

33 4096*2160 61.43 29.97 297.00 UDTV 2160P

34 4096*2160 67.50 30.00 297.00 UDTV 2160P

35 4096*2160 112.50 50.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0

36 4096*2160 135.00 59.94 593.41 UDTV 2160P 8 bit / YCbCr 4:2:0

37 4096*2160 135.00 60.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0

Only for training and service purposes

- 8 -

(4) HDMI Input (PC)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks

1 640*350 31.47 70.09 25.17 EGA

2 720*400 31.47 70.08 28.32 DOS

3 640*480 31.47 59.94 25.17 VESA(VGA)

4 800*600 37.88 60.32 40.00 VESA(SVGA)

5 1024*768 48.36 60.00 65.00 VESA(XGA)

6 1152*864 54.35 60.05 80.00 VESA

7 1360*768 47.712 60.015 84.75 VESA(WXGA)

8 1280*1024 63.98 60.02 109.00 SXGA

9 1920*1080 67.50 60.00 158.40 WUXGA(Reduced Blanking)

10 3840*2160 54.00 24.00 297.00 UDTV 2160P

11 3840*2160 56.25 25.00 297.00 UDTV 2160P

12 3840*2160 67.50 30.00 297.00 UDTV 2160P

13 4096*2160 53.95 23.98 297.00 UDTV 2160P

14 4096*2160 54.00 24.00 297.00 UDTV 2160P

Only for training and service purposes

- 9 -

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied to all of the LED TV with LB59H / LB59J chassis.

2. Designation

(1) Because this is not a hot chassis, it is not necessary to

use an isolation transformer. However, the use of isolation

transformer will help protect test instrument. (2) Adjustment must be done in the correct order. (3) The adjustment must be performed in the circumstance of

25 °C ± 5 °C of temperature and 65 % ± 10 % of relative

humidity if there is no specific designation. (4) The input voltage of the receiver must keep AC 100-240

V~, 50/60 Hz. (5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15 °C.

In case of keeping module is in the circumstance of 0 °C, it should be placed in the circumstance of above 15 °C for 2 hours.

In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15 °C for 3 hours.

[Caution] When still image is displayed for a period of 20 minutes or longer (Especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area.

3.2. LAN Inspection

3.2.1. Equipment & Condition

▪ Each other connection to LAN Port of IP Hub and Jig

3.2.2. LAN inspection solution

▪ LAN Port connection with PCB ▪ Network setting at MENU Mode of TV ▪ Setting automatic IP ▪ Setting state confirmation

- If automatic setting is finished, you confirm IP and MAC Address.

3.2.3. WIDEVINE key Inspection

- Confirm key input data at the "IN START" MENU Mode.



3. Automatic Adjustment

3.1. MAC address D/L, CI+ key D/L(Option), Widevine key D/L, ESN D/L, HDCP20 D/L

Connect: USB port Communication Prot connection

▪ Com 1,2,3,4 and 115200(Baudrate)

Mode check: Online Only

▪ Check the test process

: DETECT→MAC→ESN→Widevine→CI(option)→HDCP20 ▪ Play: Press Enter key ▪ Result: Ready, Test, OK or NG ▪ Printer Out (MAC Address Label)

3.3. LAN PORT INSPECTION(PING TEST)

Connect SET → LAN port == PC → LAN Port

SET PC

3.3.1. Equipment setting

(1) Play the LAN Port Test PROGRAM. (2) Input IP set up for an inspection to Test Program.

*IP Number : 12.12.2.2

3.3.2. LAN PORT inspection(PING TEST)

(1) Play the LAN Port Test Program. (2) Connect each other LAN Port Jack. (3) Play Test (F9) button and confirm OK Message. (4) Remove LAN cable.

Only for training and service purposes

- 10 -

3.4. Model name & Serial number Download

3.4.1. Model name & Serial number D/L

▪ Press "P-ONLY" key of service remote control.

(Baud rate : 115200 bps)

▪ Connect RS-232C Signal to USB Cable to USB. ▪ Write Serial number by use USB port. ▪ Must check the serial number at Instart menu.

3.4.2. Method & notice

(1) Serial number D/L is using of scan equipment. (2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory by D-book 4.0.

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded by OTA or service man, sometimes

model name or serial number is initialized.(Not always)

It is impossible to download by bar code scan, so It need

Manual download.

1) Press the "Instart" key of Adjustment remote control.

2) Go to the menu "7.Model Number D/L" like below photo.

3) Input the Factory model name(ex 47LB650V-ZA) or Serial number like photo.

4) Check the model name Instart menu. → Factory name

displayed. (ex 47LB650V-ZA)

5) Check the Diagnostics.(DTV country only) → Buyer

model displayed. (ex 47LB650V-ZA)

3.5. CI+ Key checking method

(Check the Section 3.1) Check whether the key was downloaded or not at ‘In Start’ menu. (Refer to below).

=> Check the Download to CI+ Key value in LGset.

3.5.1. Check the method of CI+ Key value

(1) Check the method on Instart menu (2) Check the method of RS232C Command

1) Into the main ass’y mode(RS232: aa 00 00)

CMD 1 CMD 2 Data 0

A A 0 0

2) Check the key download for transmitted command (RS232: ci 00 10)

CMD 1 CMD 2 Data 0

C I 1 0

3) Result value

- Normally status for download : OKx

- Abnormally status for download : NGx

3.5.2. Check the method of CI+ key value(RS232)

1) Into the main ass’y mode(RS232: aa 00 00)

CMD 1 CMD 2 Data 0

A A 0 0

2) Check the mothed of CI+ key by command (RS232: ci 00 20)

CMD 1 CMD 2 Data 0

C I 2 0

3) Result value i 01 OK 1d1852d21c1ed5dcx

CI+ Key Value

Only for training and service purposes

3.6. WIFI MAC ADDRESS CHECK

(1) Using RS232 Command

H-freq(kHz) V-freq.(Hz)

Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]

(2) Check the menu on in-start

- 11 -

4. Manual Adjustment

4.1. EDID(The Extended Display Identification Data)/DDC(Display Data Channel) download

4.1.1. Overview

It is a VESA regulation. A PC or a MNT will display an optimal resolution through information sharing without any necessity of user input. It is a realization of "Plug and Play".

4.1.2. Equipment

- Since embedded EDID data is used, EDID download JIG, HDMI cable and D-sub cable are not need.

- Adjustment remote control

4.1.3. Download method

(1) Press "ADJ" key on the Adjustment remote control, then

select "12.EDID D/L", By pressing "Enter" key, enter EDID D/L menu.

For HDMI EDID

DVI-D to HDMI or HDMI to HDMI

(2) Select "Start" button by pressing "Enter" key, HDMI1/

HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG.

4.1.4. EDID DATA

▪ Reference

- HDMI1 ~ HDMI3

- In the data of EDID, bellows may be different by Input mode.

0 1 2 3 4 5 6 7 8 9 A B C D E F

0x00 00 FF FF FF FF FF FF 00 1E 6D

ⓒ

0x01 0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80 0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 0x07 0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21 0x01 22 15 01 29 3D 06 C0 15 07 50 0x02 0x03 0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

ⓓ

ⓕ

10 28 10 E3 05 03 01 02 3A 80 18 71 38

ⓕ

ⓐ Product ID ⓑ Serial No: Controlled on production line. ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ → ‘01’, Year : ‘2015’ → ‘19’

ⓓ Model Name(Hex): LGTV ⓔ Checksum(LG TV): Changeable by total EDID data. ⓕ Vendor Specific(HDMI)

ⓐ ⓑ

ⓕ

ⓓ

ⓔ1

01

ⓔ2

(1) HDMI Deep Color OFF

# HDMI 1(C/S: E6 1D) EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50

A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1D

# HDMI2 (C/S: E6 0D) EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F

80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0D

# HDMI 3(C/S : E6 FD) EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

Only for training and service purposes

- 12 -

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FD

(2) HDMI Deep Color ON

# HDMI1 (C/S : A0 C7) EDID Block 0, Bytes 0-127 [00H-7FH]

0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 19 01 03 80 A0 5A 78 0 A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58 40 8 A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0 A 20 20 20 20 20 20 20 01 A0

EDID Block 1, Bytes 128-255 [80H-FFH]

0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 47 F1 58 10 9F 04 13 05 14 03 02 12 20 21 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06 A0 C0 15 07 50 09 57 07 6E 03 0C 00 10 00 B8 3C 20 B0 00 80 01 02 03 04 67 D8 5D C4 01 78 80 03 E3 05 C0 C0 00 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 D0 70 36 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E E0 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C7

* Checksum (HDMI 1/2)

Input

HDMI Deep Color On

FFh (Checksum)

HDMI Deep Color Off

FFh (Checksum)

HDMI1 A0 C7 E6 1D

HDMI2 E6 D E6 D

HDMI3 E6 FD E6 FD

4.3. White Balance Adjustment

4.3.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel's W/B deviation (2) How-it-works : When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to prevent saturation of Full Dynamic range and data, one of R/G/B is fixed at 192, and the other two is lowered to find the desired value.

(3) Adjustment condition : normal temperature

1) Surrounding Temperature : 25 °C ± 5 °C

2) Warm-up time: About 5 Min

3) Surrounding Humidity : 20 % ~ 80 %

4.3.2. Equipment

(1) Color Analyzer: CA-210 (LED Module : CH 14) (2) Adjustment Computer(During auto adj., RS-232C protocol

is needed) (3) Adjustment Remote control (4) Video Signal Generator MSPG-925F 720p/216-Gray

(Model: 204, Pattern: 49)

→ Only when internal pattern is not available

• Color Analyzer Matrix should be calibrated using CS-100.

4.3.3. Equipment connection MAP

Color Analyzer

Probe

RS- 232C

Pattern Generator

Signal Source

* If TV internal pattern is used, not needed

4.3.4. Adj. Command (Protocol)

START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP

- LEN: Number of Data Byte to be sent

- CMD: Command

- VAL: FOS Data value

- CS: Checksum of sent data

- A: Acknowledge Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]

RS-232C

Computer

RS-232C

Only for training and service purposes

- 13 -

▪ RS-232C Command used during auto-adjustment.

RS-232C COMMAND

[CMD ID DATA]

wb 00 00 Begin White Balance adjustment

wb 00 10 Gain adjustment(internal white pattern)

wb 00 1f Gain adjustment completed

wb 00 20 Offset adjustment(internal white pattern)

wb 00 2f Offset adjustment completed

wb 00 ff

End White Balance adjustment (internal pattern disappears)

Explanation

Ex) wb 00 00 → Begin white balance auto-adj.

wb 00 10 → Gain adj. ja 00 ff → Adj. data

jb 00 c0 ... ...

wb 00 1f → Gain adj. completed *(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. wb 00 ff → End white balance auto-adj.

** G-fix adjustment Adjust modes (Cool), Fix the G gain to 172 (default data) and change the others (G/B Gain). Adjust two modes(Medium / Warm), Fix the one of R/G/B gain to 192 (default data) and decrease the others.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 7.White Balance, you can select one of 2 Testpattern: ON, OFF. Default is inner(ON). By selecting OFF, you can adjust using RF signal in 216 Gray pattern.

▪ Adj. Map

Cool

Medium

Warm

Command

Adj. item

R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

R Cut

G Cut

B Cut

R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

R Cut

G Cut

B Cut

R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

R Cut

G Cut

(lower case ASCII)

CMD1 CMD2 MIN MAX

Data Range

(Hex.)

4.3.5. Adj. method

(1) Auto adj. method

1) Set TV in adj. mode using POWER ON key.

2) Zero calibrate probe then place it on the center of the Display.

3) Connect Cable.(RS-232C to USB)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sign), check adj. status pre mode. (Warm, Medium, Cool)

6) Remove probe and RS-232C cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need.

(2) Manual adjustment. method

1) Set TV in Adj. mode using POWER ON.

2) Zero Calibrate the probe of Color Analyzer, then place it on the center of LCD module within 10 cm of the surface.

3) Press ADJ key → EZ adjust using adj. R/C → 7. WhiteBalance then press the cursor to the right(key ►).

(When right key(►) is pressed 216 Gray internal pattern

will be displayed)

4) One of R Gain / G Gain / B Gain should be fixed at 192, and the rest will be lowered to meet the desired value.

5) Adjustment is performed in COOL, MEDIUM, WARM 3 modes of color temperature.

Default

(Decimal)

▪ Adjustment condition and cautionary items

1) Lighting condition in surrounding area Surrounding lighting should be lower 10 lux. Try to isolate adj. area into dark surrounding.

2) Probe location : Color Analyzer(CA-210) probe should be within 10 cm

and perpendicular of the module surface (80° ~ 100°)

3) Aging time

- After Aging Start, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked

using no signal or Full-white pattern.

4.3.6. Reference (White balance Adj. coordinate and color temperature)

▪ Luminance : 206 Gray ▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

Mode

Cool 0.271 0.270 13000 K 0.0000

Medium 0.286 0.289 9300 K 0.0000

Warm 0.313 0.329 6500 K 0.0000

Coordinate

x y

Temp ∆uv

▪ Standard color coordinate and temperature using CA-210(CH 14)

Mode

Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000

Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K 0.0000

Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000

Coordinate

x y

Temp ∆uv

4.3.7. LED White balance table

▪ Edge & ALEF LED module change color coordinate because

of aging time.

▪ Apply under the color coordinate table, for compensated

aging time.

Only for training and service purposes

- 14 -

▪ (Normal line) White balance table

Model : (normal line) LGD

Aging

time

(Min)

1 0-2 282 289 297 308 324 348

2 3-5 281 287 296 306 323 346

3 6-9 279 284 294 303 321 343

4 10-19 277 280 292 299 319 339

5 20-35 275 277 290 296 317 336

6 36-49 274 274 289 293 316 333

7 50-79 273 272 288 291 315 331

8 80-119 272 271 287 290 314 330

9 Over 120 271 270 286 289 313 329

▪ AUO, INX, Sharp, CSOT, BOE (Cool is 13000 K)

Target 278 280 293 299 320 339

Cool Medium Warm

x y x y x y

271 270 286 289 313 329

Cool Medium Warm

x y x y x y

271 270 285 293 313 329

4.4. Local Dimming Function Check

(1) Turn on TV. (2) At the Local Dimming mode, module Edge Backlight

moving right to left Back light of IOP module moving. (3) Confirm the Local Dimming mode. (4) Press “exit” Key.

4.6. Option selection per country

4.6.1. Overview

- Option selection is only done for models in AJ/JA/IL

4.6.2.Method

(1) Press "ADJ" key on the Adjustment remote control, then

select Country Group Menu.

(2) Depending on destination, select Country Group Code or

Country Group then on the lower Country option, select

US, CA, MX. Selection is done using +, - or ►◄ KEY.

4.7. HDMI ARC Function Inspection

(1) Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

(2) Test method

1) Insert the HDMI Cable to the HDMI ARC port from the master equipment. (HDMI 2)

4.5. Magic Motion Remote control test

- Equipment : RF Remote control for test, IR-KEY-Code Remote control for test

- You must confirm the battery power of RF-Remote control before test(recommend that change the battery per every lot)

- Sequence (test)

1) If you select the ‘start key(OK)’ on the Adjustment remote

control, you can pairing with the TV SET.

2) You can check the cursor on the TV Screen, when select

the "OK" key on the Adjustment remote control.

3) You must remove the pairing with the TV Set by select

‘Mute + OK Key’ on the Adjustment remote control.

Only for training and service purposes

2) Check the sound from the TV Set.

3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

4.8. Ship-out mode check (In-stop)

- After final inspection, press In-Stop key of the Adjustment remote control and check that the unit goes to Stand-by mode.

- 15 -

5. GND and Internal Pressure check

5.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power Cord is fully inserted to the SET. (If loose, re-insert)

(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord, Antenna cable and A/V arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER(GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically. (Remove CORD, A/V form AV JACK BOX.)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the pallet to move on to next process.

7.

USB S/W Download(Service only)

(1) Put the USB Stick to the USB socket. (2) Automatically detecting update file in USB Stick.

- If your downloaded program version in USB Stick is Older, it didn't work. But your downloaded version is Newer, USB data is automatically detecting.(Download

Version High & Power only mode, Set is automatically

Download)

(3) Show the message "Copying files from memory".

5.2. Checkpoint

▪ TEST voltage

- GND: 1.5 KV / min at 100 mA

- SIGNAL: 3 KV / min at 100 mA

▪ TEST time: 1 second ▪ TEST POINT

- GND TEST = POWER CORD GND & SIGNAL CABLE

METAL GND

- Internal Pressure TEST = POWER CORD GND & LIVE &

NEUTRAL

▪ LEAKAGE CURRENT: At 0.5 mArms

6. Audio

No. Item Min Typ Max Unit

Audio practical max

1

Output, L/R (Distortion

=10% max Output)

Speaker

2

(8 Ω Impedance)

Measurement condition: (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation (2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms

10 12 W

8.10 10.8 Vrms

10 12 W

EQ Off

AVL Off

Clear Voice Off

EQ On

AVL On

Clear Voice On

(4) Updating is starting. (5) Updating Completed, The TV will restart automatically.

(6) If your TV is turned on, check your updated version and

Tool option. (explain the Tool option, next stage)

* If downloading version is more new than your TV have, TV

can lost all channel data. In this case, you have to channel recover. if all channel data is cleared, you didn't have a DTV/ATV test on production line.

Only for training and service purposes

* After downloading, have to adjust TOOL OPTION again.

1) Push "IN-START" key in service remote control.

2) Select "Tool Option 1" and push "OK" key.

3) Punch in the number. (Each model has their number.)

8. Tool Option selection

▪ Method: Press Adj. key on the Adjustment remote control,

then select Tool option.

- 16 -

1. MAIN(LM14A+URSA11)

BLOCK DIAGRAM

4b’1010

Chip Config

51P/41P

Vx1

(512MB X 2EA)

DDR3 1866 X 32

X_TAL

24MHz

(512MB X 2EA)

DDR3 1866 X 32

EEPROM(NVRAM)

B

A

I2C 1

(HW Port)

B-CAS

DDR3 1866 X 32

URSA11

Mstar

LM14A

USB

(4GB)

eMMC

(256Kb)

(NTP7515)

(1Gb X 2EA)

MAIN Audio AMP

Woofer Audio AMP

I2S Out

I2C 4

HDMI

(NTP7515)

WIFI/BT Combo

USB_WIFI

SUB

CVBS/YPbPr

ASSY

IR / KEY

LOGO LIGHT(Ready)

CVBS/RGB

X_TAL

32.768KHz

(RENESAS

Sub Micom

R5F100GEAFB)

I2C 3

(HW Port)

ETHERNET

SPDIF OUT

P_TS

OCP

USB1 (3.0)

USB2 (2.0)

OCP

USB3 (2.0)

HDMI1(MHL) HDMI 2.0

HDMI2(ARC)

HDMI3(External EDID)

H/P

RS232C

SCART

(IN/OUT)

AV/COMP

OPTIC

LAN

P_TS

IF (+/-)

CVBS

CI Slot

P_TS

T2/C/S2 W/O AD

TUNER

(T2/C/A)

Air/

Cable

E

R

S_TS for JP

SMARTCARD_I/F

LNB

B-CAS

(JAPAN)

(S2)

DEMOD

(S2)

TUNER

DVB-S

A

R

Only for training and service purposes

- 17 -

2. I2C(LM14A+URSA11)

IC6900

LNB

TUNER

TU6704

IC100

NVRAM

TUNER

TU6704

MSTAR

33Ω

+3.3V_TU

1.8KΩ

LM14A

2C SCL/SDA4(SW)

I

GPIO19 / [LED0] / GPIO74

GPIO20 / [LED1] / GPIO75

33Ω

GPIO30 / SCK4

I2C_SCL/SDA2(HW)

+3.3V_NORMAL

GPIO31 / SDA4

I2C SCL/SDA3(HW)

GPIO28 / SCK0 / GPIO83

33Ω

1.8KΩ

+3.3V_LNA_TU

I2C SCL/SDA1(HW)

DDCR_CK/ SCK3 / GPIO54

DDCR_DA / SDA3 / GPIO53

GPIO29 / SDA0 /GPIO84

I2C_SCL/SDA6(SW)

DIM2 / TX4 / GPIO112

33Ω

1.8KΩ

2C SCL/SDA5(HW)

I

GPIO32 / SCK5 / GPIO87

GPIO33 / SDA5 / GPIO88

DIM3 / RX4 / GPIO113

I2C SCL/SDA7(HW)

TGPIO2 / SCK1 / GPIO159

TGPIO3 / SDA1 / GPIO160

1.8KΩ

+3.3V_NORMAL

100Ω

33pF

IC5900

NTP7515(Woofer AMP)

Only for training and service purposes

100Ω

IC5800

NTP7515(Main AMP)

1.8KΩ

+3.3V_NORMAL

33Ω

33pF

IC3000

MICOM

RENESAS

+3.3V_NORMAL

- 18 -

1.8KΩ

0Ω

P7201

LCD Panel

1.8KΩ

+3.3V_NORMAL

33Ω

URSA11 (LGE5352)

3. URSA11

Data_Format_0

Data_Format_1

I2C_SCL6

I2C_SDA6

HTPDAn_IN

LOCKAn_IN

SPI FLASH

41P

V x1

8 lane

LOCKAn

HTPDAn

XO_URSA

X-Tal

(24Mhz)

51P

V x1

8 lane

XIN_URSA

- 32MB (x1)

SPI_DI

Data_Format_1

Data_Format_0

SPI_DO/CK/CZ

UART1_TX

UART1_RX

URSA11

I2CS_SCL

I2CS_SDA

UART2_TX

UART2_RX

A_DDR3_DQ[31:0]

BA[2:0]/MCLK/MCKZ A_DDR3_A[15:0]/

DDR3 SDRAM

- 1Gbit (x16)

- 1866

DDR3 SDRAM

- 1Gbit (x16)

- 1866

URSA9_CONNECT

5 Pin

PANEL_VCC

T-CON POWER

I2C_SCL7

I2CS_SCL

I2CS_SDA

I2C_SDA7

Switch

URSA

DEBUG

UART

URSA PQ

UART2_TX

UART2_RX

(URSA DDR)

+1.5V_U_DDR

Power +12V

DC-DC Converter

(BD9D321EFJ _3A)

4 Pin

I2C_S Port

Jig Download

SDA2_+3.3V_DB

SCL2_+3.3V_DB

UART

Vx1 VIDEO 8Lane

Vx1 OSD 4Lane

LOCKAn_OSD / LOCKAN_Video

URSA SYS

UART1_TX

UART1_RX

(URSA)

+0.95V

LM14A

DC-DC Converter

(TPS53513RVER_8A)

Only for training and service purposes

- 19 -

4. POWER(LM14A+URSA11)

LDO DCDC

SW: beehive-204

Video : USB4K movie

Measurement condition

IR Assy

MICOM

URSA11

0.369A

IC2302

3.3V NORMAL / 6A

0.617A

Max(HDMI) : 0.776A

eMMC

1A

IC2301

1.8V eMMC

LM14A

DDR_VTT

DDR3*4EA

1.5V

IC402

IC2303

1.5V DDR / 3A

1.26A

DDR_VTT

0.98V Core / 6A

2.7A

H/P AMP

LM14A

IC2501

1.0V CPU Core / 4A

0.63A

LM14A

0.321A

LM14A

3.3V

IC200

AVDD_DMPLL

NVRAM

NTP7515

WIFI Combo

USB1

USB2/3

NTP7515

LM14A

URSA11

IC2502

IC13402

0.95V URSA Core / 8A

4.09A

URSA

DDR_VTT

DDR3*2EA

1.5V IC13000

URSA DDR_VTT

LNB option

IC13403

1.5V_U_DDR / 3A

LNB

PANEL_VCC

1.055A

1.37A

Max(Comp) : 1.6A

IC2305

5V NORMAL / 6A

Max(HDMI) : 0.32A

0.29A

0.48A Max(HDMI) : 0.89A

Tuner

Only for training and service purposes

0.09A

Wifi/MR connect 0.23A

3.5V

Stand_by : 0.0067A

12V

2.95A

- 20 -

24V

0.58A

Max(HDMI) : 0.951A

5. TUNER(LM14A+URSA11)

CI Slot

VCC

5V_CI_ON

+

CI 5V

Power detect

PCM_5V_CTL

LNB

IC6900

10K Ω

+5V_CI_ON

CAM_CD1_N

GPIO_PM[4]/GPIO14

LM14A

CI_CD1

CI_CD2

CI_MISTRT

/CI_CD1

/CI_CD2

OR

GATE

CI_MIVA_ERR

CI_MCLKI

PCM_CE1

/PCM_CE1

CI_IOWR

EB_BE_N1 EB_BE_NO

CI_IORD

CI_ADDR[0-14]

EB_DATA[0-7]

CI_ADDR[0-14]

CI_DATA[0-7]

EB_DATA[0-7]

EB_ADDR[0-14]

REG

PCM_RESET

CAM_WAIT_N

CAM_REG_N

PCM_RESET

CAM_WAIT_N

CAM_IREQ_N

CI_OE

CI_WE

/EB_WE_N /EB_OE_N

TS_OUT_VAL

TS_OUT_CLK

CI_TS_SYNC

CI_TS_VAL

CI_TS_CLK

TPI_SOP

TPI_VAL TPI_CLK

TS_OUT_SYNC

TS_OUT[0-7]

TPI_DATA[0-7]

33Ω

TPI_DATA[0-7]

TS_IN[0-7]

CI_MDI[0-7]

33Ω

FE_DEMOD1_TS_DATA [0-7]

PCM_D[0~7]

PCM_A[0~14]

TS1_CLK/GPIO172

TS1_VLD/GPIO174

TS1_SYNC/GPIO173

PCM_CD_N/GPIO151

PCM_CE_N/GPIO124

PCM_IORD_N/GPIO128

PCM_IOWR_N/GPIO130

PCM_RESET/GPIO150

PCM_WAIT_N/GPIO140

PCM_REG_N/GPIO144]

TS0_CLK/GPIO171

PCM_OE_N/GPIO126

PCM_WE_N/GPIO134

PCM_IRQA_N/GPIO135

TS0_D[0~7]

TS1_D[0~7]

TS0_VLD/GPIO169

TS0_SYNC/GPIO170

+2.5V_NORMAL

+3.3V_TUNER

[+3.3V_TUNER] 11

[+3.3V_LNA_TU] 1

[3.3V_Demod_TU] 26

TDJM-G301D

A8303SESTR-TB

TS1_CLK/GPIO172

TS1_SYNC/GPIO173

10 [TONECTRL]

2 [LNB]

7 [SCL]

8 [SDA]

GPIO31/SDA4/GPIO86

GPIO33/SDA5/GPIO88

GPIO30/SCK4/GPIO85

GPIO32/SCK5/GPIO87

TS1_VLD/GPIO174

TS1_D[0-7]

GPIO [175~182]

SPI1_CK/GPIO106

AL2 [VIFP]

AM2 [VIFM]

PM_SPI_CZ/GPIO0

AK1[SIFP]

AC6[CVBS0]

AK3[IF_AGC]

ADC_I_INP

33Ω

1.8KΩ

+3.3V_TU

LNB_TX

LNB_OUT

I2C_SCL2

I2C_SDA2

Demod_Core

[LNB_TX] 29

[LNB_OUT] 31

[I2C_SCL2_TU] 27

[+2.5V_DEMOD] 38

[1,1V_D_Demod_Core] 28

[I2C_SDA2_TU] 30

33 Ω

1.8KΩ FE_DEMOD1_TS_CLK

FE_DEMOD1_TS_SYNC

FE_DEMOD1_TS_VAL

+3.3V_LNA_TU

FE_DEMOD1_TS_ERROR

I2C_SCL5

I2C_SDA5

[I2C_SCL5_TU] 4

[I2C_SDA5_TU] 5

[FE_DEMOD1_TS_VAL] 16

[FE_DEMOD1_TS_SYNC] 15

[FE_DEMOD1_1_TS_CLK] 14

[FE_DEMOD1_TS_ERROR_TU] 12

FE_DEMOD1_TS_DATA[0-7]

FE_DEMOD1_TS_DATA[0] 17

FE_DEMOD1_TS_DATA[1] 18

FE_DEMOD1_TS_DATA[2] 19

FE_DEMOD1_TS_DATA[3] 20

FE_DEMOD1_TS_DATA[4] 21

FE_DEMOD1_TS_DATA[5] 22

FE_DEMOD1_TS_DATA[6] 23

FE_DEMOD1_TS_DATA[7] 24

RF_SWITCH_CTL

[RF_SWITCH_CTL] 2

ADC_I_INN

FILTER

IF_P

IF_N

IF_AGC

TU_CVBS

/TU_RESET1

[/TU_RESET1_TU] 25

TUNER_SIF

[IF_P] 6

[IF_N] 7

[TU_SIF_TU] 8

[IF_AGC_TU] 3

[TU_CVBS_TU] 9

Only for training and service purposes

- 21 -

6. VIDEO AUDIO IN(LM14A+URSA11)

Only for training and service purposes

- 22 -

7. AUDIO OUT(LM14A+URSA11)

Front_L

Front_R

Woofer_L

Woofer_R

SCART

JK4600

DTV/MNT_L/R_OUT

LPF

S

CART_MUTE

TR) (

Mute CTRL

P AMP

IC6000

O

Z4580MTR A

CART_L/ Rout S

LINEOUT_R2]

[ LINEOUT_L2]

[

DVB only

4P WAFER

UD_LRCK A

2P/ 4P WAFER

LPF

IC5800

NTP7515

Front AMP

I2S

UD_SCK A

AUD_LRCH

[ I2S_OUT_WS/ GPIO98]

I2S_OUT_SD/GPIO101] [

[ I2S_OUT_BCK/GPIO100]

LPF

ICOM

IC3000

M

TP7515

IC5900

oofer AMP

N

W

_MU

AMP

TE

I2C

2C_SCL4

I

I2C_SDA4

[ GPIO20/[ LED1] /GPIO75]

AMP_RESET_N

[ PWM3/ GPIO155]

[ GPIO19/[ LED0] /GPIO74]

LM14A

HEAD PHONE

JK3803

SIDE_HP_MUTE

LPF

HP_LOUT / HP_ROUT

[EARPHONE_OUTL]

[ EARPHONE_OUTR]

Only for training and service purposes

LINEIN_L0]

LINE_N_R0]

[

OMP1/AV1/ DVI_L_IN

OMP1/AV1/ DVI_R_IN

C

JK3802

[ LINEIN_L1]

[ LINE_N_R1]

DVB only

SC_L_IN / SC_R_IN

SCART

JK4600

[ SIFP]

TUNER_SIF

TR BUF

Tuner

[ SPDIF_OUT]

SPDIF_OUT

JK3800

- 23 -

8. HDMI(LM14A+URSA11)

CEC_REMOTE

Q3001

HDMI1.4

HDMI2&ARC

HDMI1.4

HDMI2.0

HDMI1&MHL

HDMI_CEC_MICOM

HDMI3&External EDID

RENESAS

MICOM(IC3000)

32.768kHz

IC3301

External EDID

X-Tal(X3000)

DDC_SCL_3

DDC_SDA_3

TMDS Link 8bits

[DDCDD_DA/GPIO45]

[DDCDD_CK/GPIO44]

Only for training and service purposes

DDC_SCL_2

DDC_SDA_2

LM14A

[DDCDB_CK/GPIO40]

HDMI_ARC

TMDS Link 8bits

[ARC0/GPIO6]

[DDCDB_DA/GPIO41]

- 24 -

DDC_SCL_1

DDC_SDA_1

TMDS Link 8bits

[DDCDA_DA/GPIO39]

[DDCDA_CK/GPIO38]

MHL_DET_LM15

[GPIO_PM[14]/GPIO24]

* TMDS Link 8bits = TMDS DATA 6bits(DATA0,1,2)+ TMDS CLK 2bits

9. USB / WIFI / M-REMOTE / UART(LM14A+URSA11)

WIFI Combo

+5V_USB_3

USB3

USB_DP3

USB_DM3

/USB_OCD3

USB_CTL3

6A

DCDC

+5V_USB_2

USB2

USB_DM2

USB2.0

IC2305

USB_DP2

USB_CTL2

/USB_OCD2

+5V_USB_1

USB1

USB_DP1

USB_DM1

SSUSB_RXP/SSUSB_RXN

USB3.0

OCP

IC4300

/USB_OCD1

SSUSB_TXP/SSUSB_TXN

RS232C_Debug(4P wafer)

RENESAS MICOM(IC3000)

WIFI_DP

WIFI_DM

USB_CTL1

M_RFModule_RESET

SOC_TX

SOC_RX

[DP_P2]

[DM_P2]

[TGPIO1/GPIO158]

[TGPIO0/GPIO157]

Only for training and service purposes

[DP_PSS]

[DP_PSS1]

[DM_PSS1]

[SAR0/GPIO46]

[SAR1/GPIO47]

[DM_PSS]

[SSUSB_TXP/N]

[SSUSB_RXP/N]

[DM_P0]

[DP_P0]

[GPIO4/RX1]

[GPIO3/TX1/GPIO58]

LM14A

- 25 -

[GPIO_PM[1]/PM_UART1/GPIO11]

[GPIO_PM[5]/PM_UART1/GPIO15]

[GPIO_PM[10]/[SPI-CZ2N]/GPIO20]

400

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

910

120

900

521

121

800

401

500

540

530

LV2

LV1

820

570

A10

Stand screw

200

Only for training and service purposes

- 26 -

A22

CHIP CONFIG

LGE Internal Use Only

CHIP_CONFIG[3:0] {LED1, SPI_DI,LED0, PWM_PM}

Value Mode Description 4’b1000 SB51_ExtSPI 51 boot from SPI 4’b1001 HEMCU_ExtSPI ARM boot from SPI 4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC 4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND 4’b1100 DBUS for test only 4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication 4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication 4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication;

+3.3V_NORMAL

OPT

R108 4.7K

R110 4.7K

OPT

R109 4.7K

R111 4.7K

OPT

R115 4.7K

R122 4.7K

OPT

R116 4.7K

R123 4.7K

LED1

SPI_DI_SOC

LED0 PWM_PM

LM14 HW Option

+3.3V_NORMAL

10K

BIT2_1

BIT0 BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT8

BIT9

BIT10

BIT11

20150123 version

BIT(0/1)

00

TW/COL

CN/HK

01

10

11

Display

BIT4

Resolution

BIT5

DVB

EU

AJJA

BIT0_1

BIT0_0

ATSC

US

KR

BR

CI

Low

LCD

FHD

BIT1_1

BIT3_1

R119 10K

R112

R105 10K

10K

BIT2_0

BIT1_0

R106 10K

R113

JP

OLED

High

UHD

BIT3_0

R120 10K

BIT5_1

BIT6_1

BIT4_1

R132 10K

R128 10K

R129 10K

BIT5_0

R133 10K

BIT(6/7)

00

01

10

11

R135 10K

BIT6_0

R136 10K

LM14A+URSA11 4K@60Hz LM14A+URSA11 4K@120Hz

R125 10K

BIT4_0

R126 10K

BIT8_1

BIT7_1

R138 10K

BIT8_0

BIT7_0

R139 10K

B/E(FRC)

LM14A only

N/A

BIT9_1

R140 10K

BIT9_0

R141 10K

NVRAM

Atmel_NVRAM

IC101

AT24C256C-SSHL-T

EAN61133501

ATMEL CORPORATION

A0

1

A1

2

A2

3

GND

4

R142 10K

R143 10K

VCC

8

WP

7

SCL

A0’h

6

SDA

5

BIT10_1

BIT11_1

R146 10K

R148 10K

BIT10_0

BIT11_0

R147 10K

R149 10K

BIT(2/3)

T2/C/S2 PIP

00

10

11 OS(DDR)

+3.3V_NORMAL

C100

0.1uF

Write Protection

- Low : Normal Operation

- High : Write Protection

33

AR101

EU/CIS

T2/C/S2

T2/C PIP

T/C

AJJA

T2/C/S2

T

T2

Rohm_NVRAM

IC101-*1

BR24G256FJ-3

EAN62389502

ROHM Semiconductor KOREA CORPORATION

A0

VCC

1

8

WP

A1

7

2

SCL

A2

6

3

GND

SDA

4

5

I2C_SCL1

I2C_SDA1

M_RFModule_RESET

TW/COL KR

T2/C PIP

T2/C

T/C

PWM_DIM

PWM_DIM2

FAN_ON

AMP_RESET_N

PWM_PM

/USB_OCD2

USB_CTL2

FRC_FLASH_WP

DDTS_TX

SPI_CK_SOC SPI_DI_SOC SPI_DO_SOC

/TU_RESET1

/SPI_CS

DDCA_CK DDCA_DA

SOC_TX

SOC_RX

FRC_FLASH_SEL_SOC

/TU_RESET2

I2C_SCL6 I2C_SDA6

I2C_SCL3 I2C_SDA3

I2C_SCL1

I2C_SDA1 I2C_SCL2 I2C_SDA2

I2C_SCL5

I2C_SDA5

CPU_VID0

CORE_VID0

LED0 LED1

WOL_WAKE_UP_SOC

CN/HK

ATSC NIM+T2

Default

ATSC+T201

ATSC

ATSC PIP

CPU_VID1

R167

D9

PWM0/GPIO152

F10

PWM1/GPIO153

F8

PWM2/GPIO154

E9

PWM3/GPIO155

N5

PWM_PM/GPIO7

F4

SAR0/GPIO46

G5

SAR1/GPIO47

E5

SAR2/GPIO48

E4

SAR3/GPIO49

G4

SAR5

W5

PM_SPI_CK/GPIO1

V4

PM_SPI_DI/GPIO2

V5

PM_SPI_DO/GPIO3

Y6

PM_SPI_CZ/GPIO0

0

Y4

GPIO_PM[6]/[SPI-CZ1N]/GPIO16

Y5

OPT

GPIO_PM[10]/[SPI-CZ2N]/GPIO20

AL8

DDCA_CK/GPIO8

AK8

DDCA_DA/GPIO9

AH28

GPIO3/TX1/GPIO58

AH29

GPIO4/RX1

AA4

GPIO23/[TX3]/GPIO78

W6

GPIO24/[RX3]/GPIO79

F14

DIM2/TX4/GPIO112

F12

DIM3/RX4/GPIO113

AJ27

GPIO2/GPIO57

AJ7

GPIO28/SCK0/GPIO83

AH8

GPIO29/SDA0/GPIO84

E11

DDCR_CK/SCK3/GPIO54

E10

DDCR_DA/SDA3/GPIO53

AJ6

GPIO30/SCK4/GPIO85

AG8

GPIO31/SDA4/GPIO86

AH7

GPIO32/SCK5/GPIO87

AJ8

GPIO33/SDA5/GPIO88

L6

VID0/GPIO50

M6

VID1/GPIO51

AD5

LED0/GPIO29

AD4

LED1/GPIO30

AB5

WOL_INT_OUT/[GPIO]/GPIO52

North.AM

ISDB PIP

Default

ISDB EXT

ISDB INT

BR

IC100

LGE5332(LM14A)

JP

Default

SPI_CK_SOC SPI_DI_SOC SPI_DO_SOC

LVSYNC/[VX1_0-] LHSYNC/[VX1_0+]

LDE/[VX1_1-] LCK/[VX1_1+]

R_ODD[7]/LVB0N/[VX1_2-] R_ODD[6]/LVB0P/[VX1_2+] R_ODD[5]/LVB1N/[VX1_3-] R_ODD[4]/LVB1P/[VX1_3+] R_ODD[3]/LVB2N/[VX1_4-]

R_ODD[2]/LVB2P/[VX1_4+] R_ODD[1]/LVBCLKN/[VX1_5-] R_ODD[0]/LVBCLKP/[VX1_5+]

G_ODD[7]/LVB3N/[VX1_6-]

G_ODD[6]/LVB3P/[VX1_6+]

G_ODD[5]/LVB4N/[VX1_7-]

G_ODD[4]/LVB4P/[VX1_7+]

G_ODD[3]/LVA0N/[OSD_0-]

G_ODD[2]/LVA0P/[OSD_0+]

G_ODD[0]/LVA1P/[OSD_1+]

G_ODD[1]/LVA1N/[OSD_1-]

B_ODD[7]/LVA2N/[OSD_2-]

B_ODD[6]/LVA2P/[OSD_2+] B_ODD[5]/LVACLKN/[OSD_3-] B_ODD[4]/LVACLKP/[OSD_3+]

B_ODD[3]/LVA3N/[LOCKN]

B_ODD[2]/LVA3P/[HTPDN] B_ODD[1]/LVA4N/[OSD_LOCKN] B_ODD[0]/LVA4P/[OSD_HTPDN]

GPIO_PM[0]/GPIO10

GPIO_PM[3]/GPIO13 GPIO_PM[4]/GPIO14 GPIO_PM[7]/GPIO17 GPIO_PM[8]/GPIO18 GPIO_PM[9]/GPIO19

GPIO_PM[13]/GPIO23

GPIO_PM[1]/PM_UART1/GPIO11 GPIO_PM[5]/PM_UART1/GPIO15

GPIO_PM[11]/PM_UART0/GPIO21 GPIO_PM[12]/PM_UART0/GPIO22

SPI1_DI/GPIO107 SPI1_CK/GPIO106 SPI2_DI/GPIO109 SPI2_CK/GPIO108

VSYNC_LIKE/GPIO105

DIM0/GPIO110 DIM1/GPIO111

T-con I2C

BIT8

Protocol

BIT9

Division

Interface

BIT10

BIT11

/SPI_CS

TXOSD_3P TXOSD_3N TXOSD_2P TXOSD_2N TXOSD_1P TXOSD_1N TXOSD_0P TXOSD_0N

V-BY-ONE

AF32 AF31 AG32 AG31

AH31 AH30 AJ31 AJ32 AK32 AK31 AL32 AL31 AK30 AL30 AK29 AL29

AK28 AM28 AL28 AK27 AK26 AL26 AM26 AK25 AL25 AK24 AL24 AK23

AE2

U6 P4 U5 AE5 AJ5 AG6

P5 P6 AJ4 AH4

G7

TESTPIN

E13 D12 F11 D11 E12 D14 E14

Low

16Kbit

NON_Division

EPI

WebOS Lite WebOS

LM14A+URSA9

FRC_FLASH_SEL_SOC

FRC_FLASH_WP

LOCKAn_OSD URSA9_CONNECT Data_Format_1

Data_Format_0

URSA_RESET_SoC L/D_VSYNC_SOC

L/D_CLK_SOC

L/D_DI_SOC

TXVBY1_0N TXVBY1_0P TXVBY1_1N TXVBY1_1P

TXVBY1_2N TXVBY1_2P TXVBY1_3N TXVBY1_3P TXVBY1_4N TXVBY1_4P TXVBY1_5N TXVBY1_5P TXVBY1_6N TXVBY1_6P TXVBY1_7N TXVBY1_7P

TXOSD_0N TXOSD_0P TXOSD_1N TXOSD_1P TXOSD_2N TXOSD_2P TXOSD_3N TXOSD_3P

COMP1_DET

DDTS_RX

PCM_5V_CTL

PMIC_RESET

COMPENSATION_DONE

URSA9_CONNECT

/USB_OCD1 USB_CTL1

DATA_FORMAT_0_SOC DATA_FORMAT_1_SOC

HP_DET

RF_SWITCH_CTL

L/D_DI_SOC

L/D_CLK_SOC L/D_VSYNC_SOC SC_DET AV1_CVBS_DET

High

32Kbit

4_Division

Vx1

LOCKAn_Video HTPDAn_Video LOCKAn_OSD HTPDAn_OSD

R175 22

COMPENSATION_DONE

DATA_FORMAT_1_SOC

DATA_FORMAT_0_SOC

HTPDAn_OSD

HTPDAn_Video

EB_DATA[0-7]

EB_ADDR[0-14]

SM_Vsel

SM_CLK

SM_RST

SM_IO

SM_VCC

SM_CD

1K

R176

TCON_I2C_EN

EMMC_DATA[0-7]

FAN_ON

CAM_IREQ_N

EB_OE_N EB_BE_N1 /PCM_CE1

EB_WE_N

CAM_CD1_N PCM_RESET CAM_REG_N

EB_BE_N0

CAM_WAIT_N

EMMC_CMD

EMMC_CLK

EMMC_RST

EMMC_STRB

BIT0 BIT1

BIT2

BIT3

BIT4

EB_DATA[0] EB_DATA[1] EB_DATA[2] EB_DATA[3] EB_DATA[4] EB_DATA[5] EB_DATA[6] EB_DATA[7]

EB_ADDR[0] EB_ADDR[1] EB_ADDR[2] EB_ADDR[3] EB_ADDR[4] EB_ADDR[5] EB_ADDR[6] EB_ADDR[7] EB_ADDR[8] EB_ADDR[9] EB_ADDR[10] EB_ADDR[11] EB_ADDR[12] EB_ADDR[13] EB_ADDR[14]

BIT5

EMMC_DATA[6] EMMC_DATA[7] EMMC_DATA[2] EMMC_DATA[1] EMMC_DATA[0] EMMC_DATA[3] EMMC_DATA[4] EMMC_DATA[5]

OLED

LM14A_ONLY

AH14

PCM_D[0]/GPIO147

AG13

PCM_D[1]/GPIO148

AG12

PCM_D[2]/GPIO149

AK22

PCM_D[3]/GPIO119

AK21

PCM_D[4]/GPIO120

AL21

PCM_D[5]/GPIO121

AM23

PCM_D[6]/GPIO122

AH20

PCM_D[7]/GPIO123

AG14

PCM_A[0]/GPIO146

AL20

PCM_A[1]/GPIO145

AG15

PCM_A[2]/GPIO143

AH15

PCM_A[3]/GPIO142

AM19

PCM_A[4]/GPIO141

AJ17

PCM_A[5]/GPIO139

AJ16

PCM_A[6]/GPIO138

AH17

PCM_A[7]/GPIO137

AM20

PCM_A[8]/GPIO131

AH19

PCM_A[9]/GPIO129

AJ20

PCM_A[10]/GPIO125

AK20

PCM_A[11]/GPIO127

AG17

PCM_A[12]/GPIO136

AJ19

PCM_A[13]/GPIO132

AG18

PCM_A[14]/GPIO133

AH18

PCM_IRQA_N/GPIO135

AM22

PCM_OE_N/GPIO126

AG20

PCM_IORD_N/GPIO128

AL22

PCM_CE_N/GPIO124

AK19

PCM_WE_N/GPIO134

AG21

PCM_CD_N/GPIO151

AH16

PCM_RESET/GPIO150

AJ14

PCM_REG_N/GPIO144

AG19

PCM_IOWR_N/GPIO130

AG16

PCM_WAIT_N/GPIO140

C7

EMMC_IO15/[GPIO]/GPIO189

C6

EMMC_IO17/[GPIO]/GPIO188

C8

EMMC_IO9/[EMMC_CMD]/GPIO183

B8

EMMC_IO14/[GPIO]/GPIO185

A9

EMMC_IO10/[EMMC_CLK]/GPIO186

B7

EMMC_IO16/[GPIO]/GPIO187

B9

EMMC_IO11/[EMMC_RSTN]/GPIO190

A8

EMMC_IO12/[GPIO]/GPIO184

C9

EMMC_IO8/[NAND-DQS]/GPIO191

B6

EMMC_IO13/[GPIO]/GPIO217

C10

EMMC_IO6/[EMMC_D6]/GPIO221

B11

EMMC_IO7/[EMMC_D7]/GPIO220

A11

EMMC_IO2/[EMMC_D2]/GPIO219

C11

EMMC_IO1/[EMMC_D1]/GPIO218

A12

EMMC_IO0/[EMMC_D0]/GPIO194

B12

EMMC_IO3/[EMMC_D3]/GPIO193

C12

EMMC_IO4/[EMMC_D4]/GPIO192

B13

EMMC_IO5/[EMMC_D5]/GPIO222

GST_A GCLK_A MCLK_A

EO_A

IC100

LGE5332(LM14A)

LM14A UF74

PMIC_RESET

LOCKOUT12

TS1_D0/GPIO182 TS1_D1/GPIO181 TS1_D2/GPIO180 TS1_D3/GPIO179 TS1_D4/GPIO178 TS1_D5/GPIO177 TS1_D6/GPIO176

TS1_D7/GPIO175 TS1_CLK/GPIO172 TS1_VLD/GPIO174

TS1_SYNC/GPIO173

TS0_D0/GPIO161

TS0_D1/GPIO162

TS0_D2/GPIO163

TS0_D3 TS0_D4/GPIO165 TS0_D5/GPIO166 TS0_D6/GPIO167 TS0_D7/GPIO168

TS0_CLK/GPIO171 TS0_VLD/GPIO169

TS0_SYNC/GPIO170

TS3_D0/GPIO206 TS3_D1/GPIO207 TS3_D2/GPIO208 TS3_D3/GPIO209 TS3_D4/GPIO210 TS3_D5/GPIO211 TS3_D6/GPIO212 TS3_D7/GPIO213

TS3_CLK/GPIO216 TS3_VLD/GPIO214

TS3_SYNC/GPIO215

GPIO8/[TS4_D[0]]/GPIO63

GPIO5/[TS4_CLK]/GPIO60 GPIO7/[TS4_VLD]/GPIO62

GPIO6/[TS4_SYNC]/GPIO61

VIFP VIFM

SIFP SIFM

IFAGC

TGPIO0/GPIO157 TGPIO1/GPIO158

TGPIO2/SCK1/GPIO159 TGPIO3/SDA1/GPIO160

NC_1 NC_2 NC_3 NC_4

NC_5

GPIO34/GPIO89

NC_6

AH13 AG11 AG10 AJ11 AH10 AJ13 AG9 AH9 AH11 AJ10 AH12

AK17 AL18 AK18 AL15 AL16 AK15 AM16 AK16 AL19 AM17 AL17

AH23 AH27 AJ23 AG27 AH24 AH26 AJ25 AG26 AH25 AJ26 AG24

AJ28 AG28 AJ29 AG29

AL2 AM2

AK1 AK2

AK3

AJ1 AJ2 R4 R5

AM7 AL7 AM8 AK7

AL5

AM5 M7

FE_DEMOD1_TS_DATA[0] FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[2] FE_DEMOD1_TS_DATA[3] FE_DEMOD1_TS_DATA[4] FE_DEMOD1_TS_DATA[5] FE_DEMOD1_TS_DATA[6] FE_DEMOD1_TS_DATA[7]

FE_DEMOD1_TS_CLK FE_DEMOD1_TS_VAL FE_DEMOD1_TS_SYNC

TPI_DATA[0] TPI_DATA[1] TPI_DATA[2] TPI_DATA[3] TPI_DATA[4] TPI_DATA[5] TPI_DATA[6] TPI_DATA[7]

TPI_CLK TPI_VAL TPI_SOP

POL

GST_A

GST

GCLK

GCLK_A

MCLK

MCLK_A

OPT_P

SOE

FB

EO_A

E/O

HCONV

DPM

LOCKOUT12

LOCK

FE_DEMOD3_TS_DATA FE_DEMOD3_TS_CLK FE_DEMOD3_TS_VAL FE_DEMOD3_TS_SYNC

Close to MSTAR

/USB_OCD3 USB_CTL3

I2C_SCL7 I2C_SDA7

C101 0.1uF C102 0.1uF

ANALOG SIF Close to MSTAR

CORE_VID1

TXVBY1_0N TXVBY1_0P TXVBY1_1N TXVBY1_1P

R183 100

R184 100

R182 10K

5V_DET_HDMI_1 /USB_OCD3 USB_CTL3

EPI

C103 0.1uF

C104 0.1uF

R185 47

R186 47

PZ1608U121-2R0TF

R187

0

LM14A UF68/64

/TU_RESET2

WOL_WAKE_UP_SOC

FE_DEMOD1_TS_DATA[0-7]

TPI_DATA[0-7]

OPT C107

100pF

OPT C109 33pF

R188

C105

300

1000pF

OPT

+3.3V_NORMAL

L100

C106

0.1uF

C108

0.047uF 25V

DTV_IF

IF_P

IF_N

OPT C110 33pF

TU_SIF

IF_AGC

R100

1.8K

R101

1.8K

+3.3V_LNA_TU

+3.3V_NORMAL

R102

1.8K

R104

1.8K

R103

1.8K

I2C_SDA_MICOM I2C_SCL_MICOM

R107

1.8K

I2C PULL UP

R124

1.8K

R114

1.8K

R121

1.8K

AR100 33

R127

1.8K

R130

1.8K

I2C_SDA3 I2C_SCL3

R131

1.8K

R134

1.8K

+3.3V_TU

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

R137

1.8K

I2C_SDA7 I2C_SCL7

I2C_SDA6 I2C_SCL6 I2C_SDA1 I2C_SCL1 I2C_SDA3 I2C_SCL3

I2C_SDA4 I2C_SCL4

I2C_SDA5 I2C_SCL5

I2C_SDA2 I2C_SCL2

I2C for URSA9 (URSA9 Only)

I2C for LCD Module

I2C for NAVRAM

I2C for Micom

I2C for Main Amp / Woofer AMP

I2C for tuner

I2C for tuner&LNB

GPIO PULL UP

+3.3V_NORMAL

OPT

R152 10K

R154 10K

R164 10K

R156 10K

R157 10K

R161 10K

Mstar Debug

MSTAR_DEBUG_OLD

MSTAR_DEBUG_NEW

P100

12507WS-04L

OPT

R165 10K

R170 10K

R166 10K

R168 10K

/TU_RESET1

RF_SWITCH_CTL

AMP_RESET_N

TCON_I2C_EN

/USB_OCD3

USB_CTL3

/USB_OCD2

USB_CTL2

M_RFModule_RESET

PCM_5V_CTL

1

2

DDCA_CK

3

DDCA_DA

4

5

P101

12505WS-04A00

1

2

3

4

5

RS232C_Debug

P102

12507WS-04L

5

+3.3V_NORMAL

1

2

3

4

OPT

DDTS_Debug

P103

12507WS-04L

R178 10K

SOC_RX

OPT

R179 10K

SOC_TX

5

+3.3V_NORMAL

1

2

3

4

OPT

R180 10K

DDTS_RX

OPT

R181 10K

DDTS_TX

BSD-15Y-LM14A-001_00-HD

2015-01-23LM14A

MAIN1_SYSTEM

01

AVDDL_MOD11

LGE Internal Use Only

AVDD15_MOD

C227 0.1uF

DVDD_DDR11

+1.1V_VDDC_CPU

DVDD_NODIE

5V_HDMI_1

C200

1uF 25V

+1.1V_VDDC

DVDD_DDR11

AVDD5V_MHL

R200

10

AD29 AD30

AA13 AF11

AA22 AA23 AA24 AA25 AB24 AB25

AE16 AF16

J9 J10 J11 J12 J13

K9 K10 K11 K12 K13

L9 L10 L11 L12 R11 R12 R13 T11 T12 T13 U11 U12 U13

W21 Y21

W20 Y20 U19 V19

U21 U22 U23 U24 U25 V23 V24 V25 W23 W24 W25 Y23 Y24 Y25

L13

K21 N21

M21 L21

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23

AVDDL_PREDRV_1 AVDDL_PREDRV_2 AVDDL_PREDRV_3 AVDDL_MOD_1 AVDDL_MOD_2 AVDDL_MOD_3 AVDD15_MOD_1 AVDD15_MOD_2 AVDDL_USB3_1 AVDDL_USB3_2

VDDC_CPU_1 VDDC_CPU_2 VDDC_CPU_3 VDDC_CPU_4 VDDC_CPU_5 VDDC_CPU_6 VDDC_CPU_7 VDDC_CPU_8 VDDC_CPU_9 VDDC_CPU_10 VDDC_CPU_11 VDDC_CPU_12 VDDC_CPU_13 VDDC_CPU_14 VDDC_CPU_15 VDDC_CPU_16 VDDC_CPU_17 VDDC_CPU_18 VDDC_CPU_19 VDDC_CPU_20

MCP_VDDC_1 MCP_VDDC_2

DVDD_NODIE

DVDD_DDR_1 DVDD_DDR_2

DVDD_DDR_3 DVDD_DDR_4

IC100

LGE5332(LM14A)

AVDD3P3_MHL3_1 AVDD3P3_MHL3_2

AVDD3P3_DADC_1 AVDD3P3_DADC_2

AVDD3P3_USB3_1 AVDD3P3_USB3_2

VDDP_3318_A/[3.3V/1.8V] VDDP_3318_C/[3.3V/1.8V]

AVDD_DDR_LDO_A AVDD_DDR_LDO_B

AVDD_HDMI_5V_PA

AVDD_DDR_VBP_A_1 AVDD_DDR_VBP_A_2 AVDD_DDR_VBP_A_3 AVDD_DDR_VBP_A_4

AVDD_DDR_VBN_A_1 AVDD_DDR_VBN_A_2 AVDD_DDR_VBN_A_3 AVDD_DDR_VBN_A_4

AVDD_DDR_VBP_B_1 AVDD_DDR_VBP_B_2 AVDD_DDR_VBP_B_3 AVDD_DDR_VBP_B_4

AVDD_DDR_VBN_B_1 AVDD_DDR_VBN_B_2 AVDD_DDR_VBN_B_3 AVDD_DDR_VBN_B_4

VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36 VDDC_37 VDDC_38 VDDC_39

VDD_SRAM_1 VDD_SRAM_2 VDD_SRAM_3

CTRL_SRAMLDO

EMMC_CTRL

AVDD_NODIE

AVDDL_MHL3_1 AVDDL_MHL3_2

AVDD3P3_ETH

AVDD3P3_ADC_1 AVDD3P3_ADC_2 AVDD3P3_USB_1 AVDD3P3_USB_2

AVDD_AU33

AVDD_EAR33

AVDD3P3_DMPLL

VDDP_1 VDDP_2

AVDD_MOD_1

AVDD_MOD_2 AVDD_LPLL_1 AVDD_LPLL_2

AVDD_PLL_A

AVDD_PLL_B

AVDD_DDR_A_1 AVDD_DDR_A_2 AVDD_DDR_A_3 AVDD_DDR_A_4 AVDD_DDR_A_5 AVDD_DDR_A_6 AVDD_DDR_A_7 AVDD_DDR_B_1 AVDD_DDR_B_2 AVDD_DDR_B_3 AVDD_DDR_B_4 AVDD_DDR_B_5 AVDD_DDR_B_6 AVDD_DDR_B_7

GND_EFUSE

AC17 AC18 AC19 AC20 AC21 AC22 AD17 AD18 AD19 AD20 AD21 AD22 AE19 AE20 AE21 AE22

AE31 AC24 AD23

AE30

A6

V7

L7 N12 R7 T7

AVDD_DMPLL

Y7 AB7 AB8 AA7 AA8 G9 G10 AB15 AF13 AD7 AE7 AF8 AE15 AF15

V17 V18 W19 Y19

N15 N16

H16 K16

J21 K17 K18 K19 L17 L19 L20 J23 K22 K23 M22 N22 N23 P23

L18 L22

H7

G8

C14 B14 J17 J18

B15 C15 J19 J20

AC30 AC31 K24 L24

AD31 AD32 L23 M24

+1.1V_VDDC

DVDD_DDR11

AVDD33_ADC

R201

0

AVDD_DMPLL

VDDP_NAND_A

AVDD_DDR

AVDDP3P3_MHL

AVDD_DMPLL

AVDD_AU33

AVDD5V_MHL

C2100.47uF

C2110.47uF

C2120.47uF

C2130.47uF

C2140.47uF

C2150.47uF

C216

0.47uF

C220

AVDDP3P3

VDDP_NAND_C

WOL POWER ENABLE CONTROL

+3.5V_ST

PZ1608U121-2R0TF

L203

+3.3V_NORMAL

C242

0.1uF

WOL_CTL

R2020

+3.5V_WOL

AVDD_DMPLL

WOL_WAKE_UP

AVDD_DDR

0.1uF C229

0.1uF

C219

0.1uF

C221

IN

R203 1K

EN

OPT

1st layer

0.1uF

C244

Close to chip side

C243

0.1uF 16V

WOL_WAKE_UP R205

10K

WOL_WAKE_UP

+3.3V_NORMAL

IC201

AP2151WG-7

5

4

AVDD_DMPLL

IC200

AP2121N-3.3TRE1

VIN

R1690

3

2

1

GND

WOL_WAKE_UP_SOC

GND JIG POINT

+1.8V

1

2

3

C245

VOUT

OUT

GND

FLG

4th layer

0.1uF

+3.5V_WOL

AVDD_DMPLL

C246 1uF 10V

JP202

JP204

JP203

L208

PZ1608U121-2R0TF

2A

L209

PZ1608U121-2R0TF

2A

R204 10K

OPT

JP205

VDDP_NAND_C

VDDP_NAND_A

+1.1V_VDDC_CPU

C266

0.1uF

C260 10uF 10V

C239

C236

0.1uF 10uF 10V

+1.1V_VDDC

1st layer

C263

0.1uF

10uF 10V

C278

C276

Close to chip side

1st layer

C205

0.1uF

10uF 10V

C230

Close to chip side

PZ1608U121-2R0TF

+3.3V_NORMAL

0.1uF

C299

0.1uF

C235

C234

+1.5V_DDR

AVDD_DDR

L227

PZ1608U121-2R0TF

L200

4A

C268 10uF 10V

C208 10uF 10V

+1.5V_Bypass Cap

1st layer

C209 0.1uF

L221

L219

C201 10uF 10V

C224 0.1uF

C225 0.1uF

Close to chip side

4th layer

AVDD33_ADC

C294 1uF 25V

Close to chip side

4th layer

AVDD_AU33

C292

0.47uF

6.3V

Close to chip side

BOTTOM_CAP_FOR_RIPPLE

C207 10uF 10V

PZ1608U121-2R0TF

2A

PZ1608U121-2R0TF

2A

4th layer

C322

BOTTOM_CAP_FOR_RIPPLE

Close to chip side

4th layer

C250

BOTTOM_CAP_FOR_RIPPLE

Close to chip side

C226 0.1uF

C204 0.1uF

C203 0.1uF

C295 1uF 25V

BOTTOM_CAP_FOR_RIPPLE

C323

10uF

0.1uF 16V

BOTTOM_CAP_FOR_RIPPLE C261

10uF

0.1uF 16V

C287 0.1uF

C251

C252

0.47uF

6.3V

+1.1V_Bypass Cap(CLOSE TO CHIP SIDE)

+1.1V_VDDC DVDD_DDR11

4th layer

C316

C247

0.47uF

6.3V

0.47uF 10uF

10V

C314

Close to chip side

+3.3V_Bypass Cap

+3.3V_NORMAL

C222 10uF 10V

+5V_NORMAL

RUE003N02

ROHM_HDMI_LEAK

S

Q200

C223 10uF 10V

HDMI_LEAK

R206 10K

G

D

C248

C249

0.47uF

6.3V

L215

PZ1608U121-2R0TF

2A

0

R207

non_HDMI_LEAK

D

VISHAY_HDMI_LEAK

Q200-*1

G

SI1012CR-T1-GE3

S

L202

PZ1608U121-2R0TF

2A

AVDD_DDR

PZ1608U121-2R0TF

AVDDP3P3

1st layer

C256 10uF 10V

Close to chip side

L226

PZ1608U121-2R0TF

2A

AVDD15_MOD

2A

L224

0.1uF

C274

L201

PZ1608U121-2R0TF

BOTTOM_CAP_FOR_RIPPLE

Close to chip side

AVDDL_MOD11

C307 0.1uF

C308 0.1uF

Close to chip side

4th layer

AVDDP3P3_MHL

C240

4th layer

0.47uF

C253

C311

BOTTOM_CAP_FOR_RIPPLE

C241

0.47uF

0.1uF

6.3V

4th layer

C257

C324

0.47uF

6.3V

Close to chip side

4th layer

C320

C238

0.47uF

6.3V

Close to chip side

C217

0.1uF 10uF

10V

BOTTOM_CAP_FOR_RIPPLE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LM14A

MAIN2_POWER

BSD-15Y-LM14A-002_00-HD

2014-12-21

2

M0_DDR_A0

LGE Internal Use Only

M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14 M0_DDR_A15

M0_DDR_BA0 M0_DDR_BA1

M0_DDR_BA2 M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN M0_DDR_ODT

M0_DDR_CKE

M0_DDR_RESET_N

M0_D_CLK

M0_D_CLKN

M0_DDR_CS1 M0_DDR_CS2

M0_DDR_DQ0 M0_DDR_DQ1

M0_DDR_DQ2

M0_DDR_DQ3

M0_DDR_DQ4 M0_DDR_DQ5 M0_DDR_DQ6 M0_DDR_DQ7 M0_DDR_DM0

M0_DDR_DQS0

M0_DDR_DQS_N0

M0_DDR_DQ8

M0_DDR_DQ9 M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15

M0_DDR_DM1 M0_DDR_DQS1

M0_DDR_DQS_N1

M0_DDR_DQ16

M0_DDR_DQ17 M0_DDR_DQ18 M0_DDR_DQ19 M0_DDR_DQ20 M0_DDR_DQ21 M0_DDR_DQ22 M0_DDR_DQ23

M0_DDR_DM2 M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQ24 M0_DDR_DQ25 M0_DDR_DQ26 M0_DDR_DQ27 M0_DDR_DQ28 M0_DDR_DQ29 M0_DDR_DQ30 M0_DDR_DQ31

M0_DDR_DM3 M0_DDR_DQS3

M0_DDR_DQS_N3

F17

IO[3]/A-A0[AB-A0]/A-A6

C17

IO[2]/A-A1[AB-A1]/A-A5

E17

IO[8]/A-A2[AB-A2]/A-A8

F18

IO[12]/A-A3[AB-A3]/A-A4

B18

IO[11]/A-A4[AB-A4]/A-BA1

E18

IO[14]/A-A5[AB-A5]/A-A0

A17

IO[10]/A-A6[AB-A6]/A-A1

D17

IO[13]/A-A7[AB-A7]/A-A2

C16

IO[0]/A-A8[AB-A8]/A-A9

E16

IO[5]/A-A9[AB-A9]/A-A11

B19

IO[9]/A-A10[AB-A10]/A-RASZ

B17

IO[6]/A-A11[AB-A11]/A-A7

D20

IO[26]/A-A12[AB-A12]/A-BG0

F16

IO[4]/A-A13[AB-A13]/A-PARITY

B16

IO[7]/A-A14[AB-A14]/A-A13

E20

IO[19]/A-A15[AB-A15]/A-A3

E19

IO[24]/A-BA0[AB-BA0]/A-A10

C18

IO[20]/A-BA1[AB-BA1]/A-CASZ

F19

IO[21]/A-BA2[AB-BA2]/A-BA0

G22

IO[15]/A-RASZ[AB-RASZ]/A-ODT

F21

IO[17]/A-CASZ[AB-CASZ]/A-WEZ

E21

IO[16]/A-WEZ[AB-WEZ]/A-A12

F20

IO[25]/A-ODT[AB-ODT]/A-ACTZ

C19

IO[18]/A-CKE[AB-CKE]/A-CKE

F15

IO[1]/A-RST[AB-RST]/A-RST

A20

IO[28]/A-MCLK[AB-MCLK]/A-MCLKZ

B20

IO[27]/A-MCLKZ[AB-MCLKZ]/A-MCLK

E15

IO[23]/A-CSB1[AB-CSB1]/A-CSB1

D15

IO[22]/A-CSB2[AB-CSB2]/A-CSB2

C23

IO[47]/A-DQ[0][A-DQL0]/A-DQ[0]

B22

IO[31]/A-DQ[1][A-DQL1]/A-DQ[1]

B24

IO[48]/A-DQ[2][A-DQL2]/A-DQ[2]

C21

IO[29]/A-DQ[3][A-DQL3]/A-DQ[3]

B25

IO[50]/A-DQ[4][A-DQL4]/A-DQ[6]

C20

IO[30]/A-DQ[5][A-DQL5]/A-DQ[7]

C24

IO[49]/A-DQ[6][A-DQL6]/A-DQ[4]

B21

IO[32]/A-DQ[7][A-DQL7]/A-DQ[5]

C22

IO[33]/A-DQM[0][A-DML]/A-DQM[0]

A23

IO[42]/A-DQS[0][A-DQSL]/A-DQS[0]

B23

IO[41]/A-DQSB[0][A-DQSLB]/A-DQSB[0]

D23

IO[35]/A-DQ[8][A-DQU0]/A-DQ[15]

D26

IO[45]/A-DQ[9][A-DQU1]/A-DQ[10]

E22

IO[38]/A-DQ[10][A-DQU2]/A-DQ[13]

D27

IO[46]/A-DQ[11][A-DQU3]/A-DQM[1]

F23

IO[36]/A-DQ[12][A-DQU4]/A-DQ[9]

E26

IO[43]/A-DQ[13][A-DQU5]/A-DQ[12]

D22

IO[34]/A-DQ[14][A-DQU6]/A-DQ[11]

E25

IO[44]/A-DQ[15][A-DQU7]/A-DQ[8]

E24

IO[37]/A-DQM[1][A-DMU]/A-DQ[14]

D24

IO[40]/A-DQS[1][A-DQSU]/A-DQS[1]

E23

IO[39]/A-DQSB[1][A-DQSUB]/A-DQSB[1]

C28

IO[69]/A-DQ[16][B-DQL0]/A-DQ[16]

C26

IO[53]/A-DQ[17][B-DQL1]/A-DQ[17]

B29

IO[70]/A-DQ[18][B-DQL2]/A-DQ[18]

A26

IO[54]/A-DQ[19][B-DQL3]/A-DQ[19]

C29

IO[72]/A-DQ[20][B-DQL4]/A-DQ[22]

C25

IO[52]/A-DQ[21][B-DQL5]/A-DQ[23]

A29

IO[71]/A-DQ[22][B-DQL6]/A-DQ[20]

B26

IO[51]/A-DQ[23][B-DQL7]/A-DQ[21]

B27

IO[55]/A-DQM[2][B-DML]/A-DQM[2]

B28

IO[64]/A-DQS[2][B-DQSL]/A-DQS[2]

C27

IO[63]/A-DQSB[2]/[B-DQSLB]/A-DQSB[2]

E29

IO[58]/A-DQ[24][B-DQU0]/A-DQ[31]

C31

IO[67]/A-DQ[25][B-DQU1]/A-DQ[26]

E27

IO[56]/A-DQ[26][B-DQU2]/A-DQ[29]

D31

IO[66]/A-DQ[27][B-DQU3]/A-DQM[3]

D29

IO[59]/A-DQ[28][B-DQU4]/A-DQ[25]

D30

IO[65]/A-DQ[29][B-DQU5]/A-DQ[28]

E28

IO[57]/A-DQ[30][B-DQU6]/A-DQ[27]

C30

IO[60]/A-DQ[31][B-DQU7]/A-DQ[24]

B31

IO[68]/A-DQM[3][B-DMU]/A-DQ[30]

A31

IO[62]/A-DQS[3][B-DQSU]/A-DQS[3]

B30

IO[61]/A-DQSB[3][B-DQSUB]/A-DQSB[3]

IC100

LGE5332(LM14A)

IO[75]/B-A0[CD-A0]/B-A6 IO[80]/B-A1[CD-A1]/B-A5 IO[83]/B-A2[CD-A2]/B-A8 IO[79]/B-A3[CD-A3]/B-A4

IO[87]/B-A4[CD-A4]/B-BA1

IO[86]/B-A5[CD-A5]/B-A0 IO[90]/B-A6[CD-A6]/B-A1 IO[78]/B-A7[CD-A7]/B-A2 IO[77]/B-A8[CD-A8]/B-A9

IO[73]/B-A9[CD-A9]/B-A11

IO[93]/B-A10[CD-A10]/B-RASZ

IO[84]/B-A11[CD-A11]/B-A7

IO[85]/B-A12[CD-A12]/B-BG0

IO[74]/B-A13[CD-A13]/B-PARITY

IO[81]/B-A14[CD-A14]/B-A13

IO[96]/B-A15[CD-A15]/B-A3

IO[88]/B-BA0[CD-BA0]/B-A10

IO[92]/B-BA1[CD-BA1]/B-CASZ

IO[82]/B-BA2[CD-BA2]/B-BA0 IO[97]/B-RASZ[CD-RASZ]/B-ODT IO[94]/B-CASZ[CD-CASZ]/B-WEZ

IO[89]/B-WEZ[CD-WEZ]/B-A12

IO[95]/B-ODT[CD-ODT]/B-ACTZ

IO[91]/B-CKE[CD-CKE]/B-CKE

IO[76]/B-RST[CD-RST]/B-RST

IO[101]/B-MCLK[CD-MCLK]/B-MCLKZ

IO[100]/B-MCLKZ[CD-MCLKZ]/B-MCLK

IO[99]/B-CSB1[CD-CSB1]/B-CSB1 IO[98]/B-CSB2[CD-CSB2]/B-CSB2

IO[120]/B-DQ[0][C-DQL0]/B-DQ[0] IO[104]/B-DQ[1][C-DQL1]/B-DQ[1] IO[121]/B-DQ[2][C-DQL2]/B-DQ[2] IO[102]/B-DQ[3][C-DQL3]/B-DQ[3] IO[123]/B-DQ[4][C-DQL4]/B-DQ[6] IO[105]/B-DQ[5][C-DQL5]/B-DQ[7] IO[122]/B-DQ[6][C-DQL6]/B-DQ[4] IO[103]/B-DQ[7][C-DQL7]/B-DQ[5]

IO[106]/B-DQM[0][C-DML]/B-DQM[0]

IO[115]/B-DQS[0][C-DQSL]/B-DQS[0]

IO[114]/B-DQSB[0][C-DQSLB]/B-DQSB[0]

IO[109]/B-DQ[8][C-DQU0]/B-DQ[15]

IO[116]/B-DQ[9][C-DQU1]/B-DQ[10] IO[107]/B-DQ[10][C-DQU2]/B-DQ[13] IO[119]/B-DQ[11][C-DQU3]/B-DQM[1]

IO[111]/B-DQ[12][C-DQU4]/B-DQ[9] IO[117]/B-DQ[13][C-DQU5]/B-DQ[12] IO[108]/B-DQ[14][C-DQU6]/B-DQ[11]

IO[118]/B-DQ[15][C-DQU7]/B-DQ[8]

IO[110]/B-DQM[1][C-DMU]/B-DQ[14] IO[113]/B-DQS[1][C-DQSU]/B-DQS[1]

IO[112]/B-DQSB[1][C-DQSUB]/B-DQSB[1]

IO[145]/B-DQ[16][D-DQL0]/B-DQ[16] IO[126]/B-DQ[17][D-DQL1]/B-DQ[17] IO[143]/B-DQ[18][D-DQL2]/B-DQ[18] IO[127]/B-DQ[19][D-DQL3]/B-DQ[19] IO[142]/B-DQ[20][D-DQL4]/B-DQ[22] IO[124]/B-DQ[21][D-DQL5]/B-DQ[23] IO[144]/B-DQ[22][D-DQL6]/B-DQ[20] IO[125]/B-DQ[23][D-DQL7]/B-DQ[21]

IO[128]/B-DQM[2][D-DML]/B-DQM[2] IO[137]/B-DQS[2][D-DQSL]/B-DQS[2]

IO[136]/B-DQSB[2][D-DQSLB]/B-DQSB[2]

IO[131]/B-DQ[24][D-DQU0]/B-DQ[31] IO[141]/B-DQ[25][D-DQU1]/B-DQ[26]

IO[130]_/B-DQ[26][D-DQU2]/B-DQ[29]

IO[140]/B-DQ[27][D-DQU3]/B-DQM[3] IO[129]/B-DQ[28][D-DQU4]/B-DQ[25] IO[139]/B-DQ[29][D-DQU5]/B-DQ[28] IO[132]/B-DQ[30][D-DQU6]/B-DQ[27] IO[138]/B-DQ[31][D-DQU7]/B-DQ[24]

IO[133]/B-DQM[3][D-DMU]/B-DQ[30] IO[135]/B-DQS[3][D-DQSU]/B-DQS[3]

IO[134]/B-DQSB[3][D-DQSUB]/B-DQSB[3]

DDR_VTT

AR400

M0_DDR_A14

M0_DDR_A8

M0_DDR_A11

M0_DDR_A6

M0_DDR_A1

M0_DDR_A4 M0_DDR_A12 M0_DDR_BA1

M0_DDR_A13

M0_DDR_A9

M0_DDR_A7

M0_DDR_A2

M0_DDR_A5

M0_DDR_A3

M0_DDR_A0

M0_DDR_BA0 M0_DDR_BA2 M0_DDR_A15 M0_DDR_A10

M0_DDR_WEN

M0_DDR_CASN

M0_DDR_ODT

M0_DDR_RASN

M0_DDR_CKE

M0_D_CLKN

M0_D_CLK

AVDD_DDR

R410

R411

AVDD_DDR

R408

R409

56 1/16W

AR401 56 1/16W

AR402 56 1/16W

AR403 56 1/16W

AR404 56 1/16W

AR405 56 1/16W

AR406 56 1/16W

1K 1%

M0_DDR_VREFDQ

C472

0.1uF C474 1000pF 50V

M1_DDR_VREFDQ

C516

0.1uF C517 1000pF 50V

DDR_VTT

AVDD_DDR

C414 10uF 10V

CIS2 1J121

C424 0.1uF

C425 0.1uF

C426 0.1uF

C427 0.1uF

C428 0.1uF

C429 0.1uF

C430 0.1uF

C431 0.1uF

C432 0.1uF

C433 0.1uF

C434 0.1uF

C435 0.1uF

C436 0.1uF

C437 0.1uF

* DDR_VTT

R443 10K

1/16W 1%

L400

C417 10uF 10V

C535 10uF 10V

AVDD_DDR

R416

R417

C421 10uF 10V

1%

1/16W

1K 1%

AVDD_DDR

R414

R415

10K

R444

M0_1_DDR_VREFDQ

C479

0.1uF

M1_1_DDR_VREFDQ

1K 1%

C518

0.1uF

1K 1%

AP2303MPTR-G1

VIN

GND

VREFEN

VOUT

C543

0.1uF 16V

C483 1000pF 50V

1

2

3

4

C519 1000pF 50V

IC402

THERMAL

9

M1_DDR_A14

M1_DDR_A8

M1_DDR_A11

M1_DDR_A6

M1_DDR_A1

M1_DDR_A4 M1_DDR_A12 M1_DDR_BA1

M1_DDR_A13

M1_DDR_A9

M1_DDR_A7

M1_DDR_A2

M1_DDR_A5

M1_DDR_A3

M1_DDR_A0

M1_DDR_BA0 M1_DDR_BA2 M1_DDR_A15 M1_DDR_A10

M1_DDR_WEN

M1_DDR_CASN

M1_DDR_ODT

M1_DDR_RASN

M1_DDR_CKE

M1_D_CLKN

M1_D_CLK

AVDD_DDR

[EP]

NC_3

8

NC_2

7

VCNTL

6

NC_1

5

AVDD_DDR

R446

10K

1K

R405

1% 10K

R445

1K

R422

M8

H1

L8

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1 J9 L1 L9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

AVDD_DDR

C410 C411

M1_DDR_VREFDQ

R404

C468

0.1uF

C469

0.1uF

SS_DDR3_4Gb_25n

IC403-*1

K4B4G1646D-BCMA

EAN63391401

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M0_DDR_VREFDQ

R400

240

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

IC400-*1

IC400-*2

K4B4G1646D-BCMA

H5TQ4G63CFR_RDC

EAN63391401

EAN63053202

N3

M8

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

VREFCA

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

N7

K2

A12/BC

VDD_4

T3

K8

A13

VDD_5

T7

N1

A14

VDD_6

N9

M7

N9

VDD_7

NC_5

VDD_7

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

C1

VDDQ_3

CK

C9

K9

C9

VDDQ_4

CKE

VDDQ_4

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

Hynix_DDR3_2Gb

SS_DDR3_2Gb

IC400-*4

IC400-*3

H5TQ2G63FFR-RDC

K4B2G1646Q-BCMA

EAN63648701

EAN63667401

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

240

DDR3 1.5V bypass Cap - Place these caps near Memory

Hynix_DDR3_4Gb_25n

SS_DDR3_2Gb

IC403-*2

IC403-*3

H5TQ4G63CFR_RDC

K4B2G1646Q-BCMA

EAN63053202

EAN63667401

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

L8

R8

L8

ZQ

A6

ZQ

R2

A7

T8

A8

B2

R3

B2

VDD_1

A9

VDD_1

D9

L7

D9

VDD_2

A10/AP

VDD_2

G7

R7

G7

VDD_3

A11

VDD_3

K2

N7

VDD_4

A12/BC

VDD_4

K8

T3

VDD_5

A13

N1

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

VREFCA

VREFDQ

ZQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

NC_1 NC_2 NC_3 NC_4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

Hynix_DDR3_2Gb

IC403-*4

H5TQ2G63FFR-RDC

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14 M0_DDR_A15

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_D_CLK

M0_D_CLKN M0_DDR_CKE

M0_DDR_CS2 M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQS3

M0_DDR_DQS_N3

M0_DDR_DM2 M0_DDR_DM3

M0_DDR_DQ16 M0_DDR_DQ17 M0_DDR_DQ18 M0_DDR_DQ19 M0_DDR_DQ20 M0_DDR_DQ21 M0_DDR_DQ22 M0_DDR_DQ23

M0_DDR_DQ24 M0_DDR_DQ25 M0_DDR_DQ26 M0_DDR_DQ27 M0_DDR_DQ28 M0_DDR_DQ29 M0_DDR_DQ30 M0_DDR_DQ31

M8

H1

L8

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1 J9 L1 L9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13

M1_DDR_A14

M1_DDR_A15

M1_DDR_BA0 M1_DDR_BA1

M1_DDR_BA2

M1_DDR_CKE

M1_DDR_CS2

M1_DDR_ODT M1_DDR_RASN M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQS2

M1_DDR_DQS_N2

EAN63648701

M8

VREFCA

H1

VREFDQ

M1_DDR_DQS3

L8

ZQ

M1_DDR_DQS_N3

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

M1_DDR_DM2

VDD_7

R1

VDD_8

R9

VDD_9

M1_DDR_DM3

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

M1_DDR_DQ16

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

M1_DDR_DQ17

J1

NC_1

J9

NC_2

L1

M1_DDR_DQ18

NC_3

L9

NC_4

M1_DDR_DQ19

A9

VSS_1

B3

VSS_2

M1_DDR_DQ20

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

M1_DDR_DQ21

VSS_6

M1

VSS_7

M9

VSS_8

P1

M1_DDR_DQ22

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

M1_DDR_DQ23

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

M1_DDR_DQ24

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

M1_DDR_DQ25

G9

VSSQ_9

M1_DDR_DQ26 M1_DDR_DQ27 M1_DDR_DQ28 M1_DDR_DQ29 M1_DDR_DQ30 M1_DDR_DQ31

Hynix_DDR3_4Gb_29n

IC400

H5TQ4G63AFR-RDC

EAN63053201

N3

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14 M0_DDR_A15

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_D_CLK

M0_D_CLKN M0_DDR_CKE

M0_DDR_CS1 M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS0

H28 K31 J29 K27 K30 J28 K32 H31 J32 G30 L30 J30 L29 G31 J31 M28 L28 L31 K28 N28 N27 L27 M27 M31 G32 N32 M30 G29 F32

T31 P30 T30 P31 U30 N31 U31 N30 R31 T32 R30

P27 U29 P28 U27 R28 V28 P29 U28 T28 T27 R27

AA31 W31 AA30 W32 AB31 V31 AB32 V30 W30 Y30 Y31

Y28 AB27 V27 AB29 W28 AB28 W27 AA27 Y27 AA28 Y29

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8 M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14 M1_DDR_A15 M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2 M1_DDR_RASN M1_DDR_CASN M1_DDR_WEN M1_DDR_ODT M1_DDR_CKE M1_DDR_RESET_N M1_D_CLK M1_D_CLKN M1_DDR_CS1 M1_DDR_CS2

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7 M1_DDR_DM0 M1_DDR_DQS0 M1_DDR_DQS_N0

M1_DDR_DQ8 M1_DDR_DQ9 M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15 M1_DDR_DM1 M1_DDR_DQS1 M1_DDR_DQS_N1

M1_DDR_DQ16 M1_DDR_DQ17 M1_DDR_DQ18 M1_DDR_DQ19 M1_DDR_DQ20 M1_DDR_DQ21 M1_DDR_DQ22 M1_DDR_DQ23 M1_DDR_DM2 M1_DDR_DQS2 M1_DDR_DQS_N2

M1_DDR_DQ24 M1_DDR_DQ25 M1_DDR_DQ26 M1_DDR_DQ27 M1_DDR_DQ28 M1_DDR_DQ29 M1_DDR_DQ30 M1_DDR_DQ31 M1_DDR_DM3 M1_DDR_DQS3 M1_DDR_DQS_N3

M0_DDR_DQS_N0

M0_DDR_DQS_N1

M1_DDR_RESET_N

M1_DDR_DQS0

M1_DDR_DQS_N0

M1_DDR_DQS1

M1_DDR_DQS_N1

M1_DDR_DM0 M1_DDR_DM1

M0_DDR_DQS1

M0_DDR_DM0 M0_DDR_DM1

M1_DDR_A0

M1_DDR_A1

M1_DDR_A2 M1_DDR_A3

M1_DDR_A4

M1_DDR_A5 M1_DDR_A6

M1_DDR_A7

M1_DDR_A8

M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14 M1_DDR_A15

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_D_CLK

M1_D_CLKN M1_DDR_CKE

M1_DDR_CS1 M1_DDR_ODT

M1_DDR_RASN M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7

M1_DDR_DQ8 M1_DDR_DQ9

M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ2 M0_DDR_DQ3 M0_DDR_DQ4 M0_DDR_DQ5 M0_DDR_DQ6 M0_DDR_DQ7

M0_DDR_DQ8

M0_DDR_DQ9 M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15

+1.5V_Bypass Cap Close to DDR Power Pin

AVDD_DDR

C400 0.1uF

C401 0.1uF

Hynix_DDR3_4Gb_29n

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

C402 0.1uF

IC403

H5TQ4G63AFR-RDC

EAN63053201

DDR3

A0

4Gbit

A1

(x16)

A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

VREFCA

VREFDQ

ZQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

NC_1 NC_2 NC_3 NC_4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

M8

H1

L8

ZQ

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

Hynix_DDR3_4Gb_29n

IC401

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_Bypass Cap Close to DDR Power Pin

4Gbit (x16)

VREFCA

VREFDQ

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9

AVDD_DDR

C403 0.1uF

C404 0.1uF

C405 0.1uF

Hynix_DDR3_4Gb_29n

IC404

H5TQ4G63AFR-RDC

EAN63053201

N3

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8 M1_DDR_A9

M1_D_CLK

M1_D_CLKN

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M0_1_DDR_VREFDQ

M8

H1

L8

R403

ZQ

AVDD_DDR B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

240

C440

0.1uF

C441

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3

M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

IC401-*1

K4B4G1646D-BCMA

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13

NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

IC401-*2

H5TQ4G63CFR_RDC

EAN63391401

EAN63053202

M8

VREFCA

N3

M8

A0

VREFCA

P7

A1

P3

H1

A2

VREFDQ

N2

H1

A3

VREFDQ

P8

A4

P2

L8

A5

ZQ

R8

L8

A6

ZQ

R2

A7

T8

B2

A8

VDD_1

R3

B2

D9

A9

VDD_1

VDD_2

L7

D9

G7

A10/AP

VDD_2

VDD_3

R7

G7

K2

A11

VDD_3

VDD_4

N7

K2

K8

A12/BC

VDD_4

VDD_5

T3

K8

N1

A13

VDD_5

VDD_6

T7

N1

N9

A14

VDD_6

VDD_7

M7

N9

R1

NC_5

VDD_7

VDD_8

R1

R9

VDD_8

VDD_9

R9

M2

VDD_9

BA0

N8

BA1

M3

A1

BA2

VDDQ_1

A1

A8

VDDQ_1

VDDQ_2

A8

J7

C1

VDDQ_2

CK

VDDQ_3

K7

C1

C9

VDDQ_3

CK

VDDQ_4

K9

C9

D2

CKE

VDDQ_4

VDDQ_5

D2

E9

VDDQ_5

VDDQ_6

E9

L2

F1

VDDQ_6

CS

VDDQ_7

F1

K1

H2

VDDQ_7

ODT

VDDQ_8

H2

J3

H9

VDDQ_8

RAS

VDDQ_9

H9

K3

VDDQ_9

CAS

L3

J1

WE

NC_1

J1

J9

NC_1

NC_2

J9

T2

L1

NC_2

RESET

NC_3

L1

L9

NC_3

NC_4

L9

T7

NC_4

NC_6

F3

DQSL

G3

DQSL

A9

VSS_1

A9

C7

B3

VSS_1

DQSU

VSS_2

B3

B7

E1

VSS_2

DQSU

VSS_3

E1

G8

VSS_3

VSS_4

G8

E7

J2

VSS_4

DML

VSS_5

J2

D3

J8

VSS_5

DMU

VSS_6

J8

M1

VSS_6

VSS_7

M1

E3

M9

VSS_7

DQL0

VSS_8

M9

F7

P1

VSS_8

DQL1

VSS_9

P1

F2

P9

VSS_9

DQL2

VSS_10

P9

F8

T1

VSS_10

DQL3

VSS_11

T1

H3

T9

VSS_11

DQL4

VSS_12

T9

H8

VSS_12

DQL5

G2

DQL6

H7

B1

DQL7

VSSQ_1

B1

B9

VSSQ_1

VSSQ_2

B9

D7

D1

VSSQ_2

DQU0

VSSQ_3

D1

C3

D8

VSSQ_3

DQU1

VSSQ_4

D8

C8

E2

VSSQ_4

DQU2

VSSQ_5

E2

C2

E8

VSSQ_5

DQU3

VSSQ_6

E8

A7

F9

VSSQ_6

DQU4

VSSQ_7

F9

A2

G1

VSSQ_7

DQU5

VSSQ_8

G1

B8

G9

VSSQ_8

DQU6

VSSQ_9

G9

A3

VSSQ_9

DQU7

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3

M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

SS_DDR3_2Gb

IC401-*3

K4B2G1646Q-BCMA

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13

NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

Hynix_DDR3_2Gb

IC401-*4

H5TQ2G63FFR-RDC

EAN63648701

EAN63667401

M8

N3

VREFCA

A0

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

M1_1_DDR_VREFDQ

M8

VREFCA

H1

VREFDQ

L8

R419

240

C490

0.1uF

C491

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

Hynix_DDR3_4Gb_25n

SS_DDR3_4Gb_25n

IC404-*2

IC404-*1

H5TQ4G63CFR_RDC

K4B4G1646D-BCMA

EAN63053202

EAN63391401

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3

M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

SS_DDR3_2Gb

IC404-*3

K4B2G1646Q-BCMA

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13

NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

Hynix_DDR3_2Gb

IC404-*4

H5TQ2G63FFR-RDC

EAN63648701

EAN63667401

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

ZQ

AVDD_DDR B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

AR407 56 1/16W

AR408 56 1/16W

AR409 56 1/16W

AR410 56 1/16W

AR411 56 1/16W

AR412 56 1/16W

AR413 56 1/16W

OPT

M0_DDR_RESET_N

OPT

1%

+3.3V_NORMAL

M1_DDR_RESET_N

CIS2 1J121

DDR_VTT

M0_DDR_CKE

M1_DDR_CKE

C544 10uF

L401

10V

C453 0.1uF

C454 0.1uF

C455 0.1uF

C456 0.1uF

C457 0.1uF

C458 0.1uF

C459 0.1uF

C460 0.1uF

C461 0.1uF

C462 0.1uF

C463 0.1uF

C464 0.1uF

C465 0.1uF

C466 0.1uF

R412 56 1%

R413 56 1%

R427 56 1%

R428 56 1%

C477

0.01uF 50V

1K

M0_D_CLK

M0_D_CLKN

1K

C497

0.01uF 50V

M1_D_CLKN

R418

R433

M1_D_CLK

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+1.5V_Bypass Cap Close to DDR Power Pin

AVDD_DDR

C446 0.1uF

C444 0.1uF

C445 0.1uF

+1.5V_Bypass Cap Close to DDR Power Pin

AVDD_DDR

C475 0.1uF

C480 0.1uF

C476 0.1uF

LM14A

LM14A DDR

BSD-15Y-LM14A-004_00-HD

2014-12-30

04

COMPENSATION_DONE_1

LGE Internal Use Only

DPC_CTRL

12V_ON

OLED

TDI0

TDI0_1

R602 0

R603 0 OPT

+3.3V_NORMAL

Jtag I/F

JTAG

1K

R614

For Main

JTAG

1K

R616

TRST_N0 TDI0 TDO0 TMS0 TCK0 SOC_RESET

C600

0.1uF

SW600

JS2235S

1

OPT

2

3

JTAG

6

5

4

R604 0

R605 0 OPT

TDO0

OPT

TDO0_1

JTAG

P600

12505WS-10A00

JTAG

11

1

2

3

4

5

6

7

8

9

10

JTAG

1K

R612

1K

JTAG

R609

Clock for MSD808KWD

MAIN Clock(24Mhz)

5pF

C614

5pF

C615

System Clock for Analog block(24Mhz)

GND_1

2

3

X-TAL_2

X-TAL_1

1

4

GND_2

24MHz

X600

R635

1M

XIN_MAIN

XOUT_MAIN

HDMI 1.4b &2.0 MHL OPT

D0-_HDMI1 D0+_HDMI1 D1-_HDMI1 D1+_HDMI1 D2-_HDMI1 D2+_HDMI1 CK-_HDMI1 CK+_HDMI1 DDC_SCL_1 DDC_SDA_1

HDMI_HPD_1

5V_DET_HDMI_1

D0-_HDMI2 D0+_HDMI2 D1-_HDMI2 D1+_HDMI2 D2-_HDMI2 D2+_HDMI2 CK-_HDMI2 CK+_HDMI2 DDC_SCL_2 DDC_SDA_2

HDMI_HPD_2

5V_DET_HDMI_2

D0-_HDMI3 D0+_HDMI3 D1-_HDMI3 D1+_HDMI3 D2-_HDMI3 D2+_HDMI3 CK-_HDMI3 CK+_HDMI3 DDC_SCL_3 DDC_SDA_3

HDMI_HPD_3

5V_DET_HDMI_3

TMS0

TDI0_1

R600

0

SPDIF_OUT

JTAG R601

URSA_RESET_SoC

BIT6 BIT7 BIT8 BIT9

JTAG

0

LGE5332(LM14A)

T2

A_RX0N

T3

A_RX0P

U1

A_RX1N

V2

A_RX1P

V3

A_RX2N

W2

A_RX2P

R1

A_RXCN

R2

A_RXCP

R6

DDCDA_CK/GPIO38

T5

DDCDA_DA/GPIO39

Y2

HOTPLUGA

V6

CEC0/GPIO5

U4

HOTPLUGA_HDMI20_5V/GPIO34

L1

B_RX0N

M2

B_RX0P

M3

B_RX1N

N2

B_RX1P

P2

B_RX2N

P1

B_RX2P

K2

B_RXCN

K3

B_RXCP

L4

DDCDB_CK/GPIO40

L5

DDCDB_DA/GPIO41

M4

HOTPLUGB/GPIO31

M5

HOTPLUGB_HDMI20_5V/GPIO35

D2

C_RX0N

D3

C_RX0P

E2

C_RX1N

E3

C_RX1P

F2

C_RX2N

F1

C_RX2P

C3

C_RXCN

D1

C_RXCP

H6

DDCDC_CK/GPIO42

H5

DDCDC_DA/GPIO43

K6

HOTPLUGC/GPIO32

J6

HOTPLUGC_HDMI20_5V/GPIO36

G2

D_RX0N

G3

D_RX0P

H2

D_RX1N

H3

D_RX1P

J2

D_RX2N

J1

D_RX2P

F3

D_RXCN

G1

D_RXCP

J4

DDCDD_CK/GPIO44

K5

DDCDD_DA/GPIO45

H4

HOTPLUGD/GPIO33

J5

HOTPLUGD_HDMI20_5V/GPIO37

B5

SPDIF_IN/GPIO96

A5

SPDIF_OUT/GPIO97

IC100

LINEIN_L0 LINEIN_R0 LINEIN_L1 LINEIN_R1 LINEIN_L2 LINEIN_R2

MICCM0

MICIN0 LINEOUT_L2 LINEOUT_R2

EARPHONE_OUTL EARPHONE_OUTR

ARC0/GPIO6

AVSS_VRM_ADC

I2S_IN_BCK/GPIO94

I2S_IN_SD/GPIO95 I2S_IN_WS/GPIO93

I2S_OUT_BCK/GPIO100

I2S_OUT_MCK/GPIO99

I2S_OUT_WS/GPIO98

I2S_OUT_SD/GPIO101 I2S_OUT_SD1/GPIO102 I2S_OUT_SD2/GPIO103 I2S_OUT_SD3/GPIO104

GPIO_PM[14]/GPIO24

GPIO_PM[15]/GPIO25

GPIO_PM[16]/GPIO26

IC100

LGE5332(LM14A)

0.047uF

0.047uF 1000pF

C620

C621

C622

C624

C627 C628 C629

C631 C632

0.047uF

C616 C617 0.047uF C618 0.047uF

AA2 AA1

AA6 AA5

AA3 AC1 AC2

AB2 AB3

AD3 AD2 AD1

AC3

AD6

AC6 AC5 AB6

AC4

Y3

Y1

RIN0P GIN0M GIN0P

BIN0P

HSYNC0 VSYNC0

RIN1P GIN1M GIN1P

BIN1P SOGIN1

RIN2P GIN2M GIN2P

BIN2P

VCOM

CVBS0 CVBS1 CVBS2

CVBS_OUT1

GPIO19/[LED0]/GPIO74 GPIO20/[LED1]/GPIO75

RESET

XTAL_IN

XTAL_OUT

IRIN/GPIO4

DM_P0 DP_P0 DM_P1 DP_P1 DM_P2

DP_P2 SSUSB_TXP SSUSB_TXN

DM_PSS

DP_PSS SSUSB_RXP SSUSB_RXN

SSUSB_TXP1 SSUSB_TXN1

DM_PSS1

DP_PSS1 SSUSB_RXP1 SSUSB_RXN1

TN TP RN RP

B1 C1 A2 B2

D4 T6

D5

AM4 AK4

F5

A4 B4 C4 B3 AL6 AK6 AM14 AL14 AM13 AK13 AK12 AL13 AK9 AL10 AM10 AK10 AM11 AL11

BIT11

C633 0.1uF C634 0.1uF

EPHY_TDN EPHY_TDP EPHY_RDN EPHY_RDP

I2C_SCL4 I2C_SDA4

SOC_RESET

XIN_MAIN XOUT_MAIN

WIFI_DM WIFI_DP

USB_DM3

USB_DP3 SSUSB_TXP SSUSB_TXN USB_DM1 USB_DP1 SSUSB_RXP SSUSB_RXN

USB_DM2

USB_DP2

AC-coupling CAP

Place near by MST

C612

1000pF

OPT

R624 33

R625

R626

R628 33

50V

33

R630 33 R631 R632

R634 33

R619 68

68

68 33

C613 0.047uF

R620 33 R621 33 R622 33

AF6 AE6 AF2 AF1 AG5 AG4

AF3 AG1 AH2 AH3

AF4 AF5

P3

AG3

VAG

AG2

D8

0

JTAG

D6

R606

C5

G6 E6 F6 E8 F9 E7 F7

R6440

AG7 AH6 AH5

C601

2.2uF C602

2.2uF C603

2.2uF C604

2.2uF

C605 1uF

TCK0

JTAG

BIT10

DPC_CTRL

12V_ON

MHL_DET_LM15 COMPENSATION_DONE_1 /MHL_OCP

C606 10uF 10V

1K

R608

R610 22

R611 22

COMP1/AV1/DVI_L_IN COMP1/AV1/DVI_R_IN SC_L_IN SC_R_IN

SCART_Lout SCART_Rout

HP_LOUT HP_ROUT

HDMI_ARC

1uF

C609

+3.3V_NORMAL

R618 22

C607

22pF

C608 22pF

JTAG

R613 0

L60 0

PZ1 608U 121- 2R0T F

47K

R615

JTAG

C611 22pF

TDO0_1

TRST_N0

AUD_SCK

AUD_LRCK AUD_LRCH

SC_R

SC_G

SC_B

SC_ID SC_FB

COMP1_Pr

COMP1_Y

COMP1_Pb

TU_CVBS

AV1_CVBS_IN

SC_CVBS_IN

DTV/MNT_V_OUT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LM14A

MAIN4_EXT_IN/OUTPUT

BSD-15Y-LM14A-006_00-HD

2015-01-08

06

LG 60UF770T Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual