LG 49UF7600, 65UF8500, 65UF8600, 60UF77, 60UF76 Service Manual
Printed in KoreaP/NO : MFL68704428 (1503-REV00)
CHASSIS : LA53J
MODEL : 49UF7600 49UF7600-UJ
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
LED TV
SERVICE MANUAL
North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
Internal Use Only
- 2 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
CONTENTS
CONTENTS .............................................................................................. 2
SAFETY PRECAUTIONS ........................................................................ 3
SERVICING PRECAUTIONS ................................................................... 4
SPECIFICATION ...................................................................................... 6
ADJUSTMENT INSTRUCTION .............................................................. 14
BLOCK DIAGRAM .................................................................................. 26
EXPLODED VIEW .................................................................................. 27
SCHEMATIC CIRCUIT DIAGRAM ............................................APPENDIX
TROUBLE SHOOTING GUIDE .................................................APPENDIX
- 3 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
IMPORTANT SAFETY NOTICE
SAFETY PRECAUTIONS
- 4 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the
SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conict between the
following servicing precautions and any of the safety precautions
on page 3 of this publication, always follow the safety precautions.
Remember: Safety First.
General Servicing Precautions
1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board mod-
ule or any other receiver assembly.
b. Disconnecting or reconnecting any receiver electrical plug or
other electrical connection.
c. Connecting a test substitute in parallel with an electrolytic
capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an explosion hazard.
2. Test high voltage only by measuring it with an appropriate
high voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".
3. Do not spray chemicals on or near this receiver or any of its
assemblies.
4. Unless specied otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)
CAUTION: This is a ammable mixture.
Unless specied otherwise in this service manual, lubrication of
contacts in not required.
5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.
6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.
7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.
8. Use with this receiver only the test xtures specied in this
service manual.
CAUTION: Do not connect the test xture ground strap to any
heat sink in this receiver.
Electrostatically Sensitive (ES) Devices
Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some eld-effect transistors
and semiconductor “chip” components. The following techniques
should be used to help reduce the incidence of component damage caused by static by static electricity.
1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging
wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test.
2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.
4. Use only an anti-static type solder removal device. Some solder
removal devices not classied as “anti-static” can generate
electrical charges sufcient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate
electrical charges sufcient to damage ES devices.
6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or
comparable conductive material).
7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the
brushing together of your clothes fabric or the lifting of your
foot from a carpeted oor can generate static electricity sufcient to damage an ES device.)
General Soldering Guidelines
1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500 °F to 600 °F.
2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.
3. Keep the soldering iron tip clean and well tinned.
4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.
5. Use the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.
(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-
type solder removal device or with solder braid.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
(500 °F to 600 °F)
b. First, hold the soldering iron tip and solder the strand against
the component lead until the solder melts.
c. Quickly move the soldering iron tip to the junction of the
component lead and the printed circuit foil, and hold it there
only until the solder ows onto and around both the component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
d. Closely inspect the solder area and remove any excess or
splashed solder with a small wire-bristle brush.
- 5 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent at against the circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.
Removal
1. Desolder and straighten each IC lead in one operation by
gently prying up on the lead with the soldering iron tip as the
solder melts.
2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing
the IC.
Replacement
1. Carefully insert the replacement IC in the circuit board.
2. Carefully bend each IC lead against the circuit foil pad and
solder it.
3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).
"Small-Signal" Discrete Transistor
Removal/Replacement
1. Remove the defective transistor by clipping its leads as close
as possible to the component body.
2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.
Power Output, Transistor Device
Removal/Replacement
1. Heat and remove all solder from around the transistor leads.
2. Remove the heat sink mounting screw (if so equipped).
3. Carefully remove the transistor from the heat sink of the circuit
board.
4. Insert new transistor in the circuit board.
5. Solder each transistor lead, and clip off excess lead.
6. Replace heat sink.
Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC connections).
1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).
2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.
4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the
good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.
At Other Connections
Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.
1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly connected to the affected copper pattern.
3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.
- 6 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement
.
1. Application range
This spec sheet is applied to the LED TV used LA53J chassis
2. Test condition
Each part is tested as below without special notice.
1) Temperature : 25 ºC ± 5 ºC(77±9ºF), CST : 40 ºC±5 ºC
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
Standard input voltage (100~240V@ 50/60Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 20 minutes prior to
the adjustment.
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : UL, CSA, CE, IEC specification
- EMC : FCC, ICES, CE, IEC specification
- Wireless : Wireless HD Specification (Option)
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LGE Internal Use Only
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4. General Specification
No Item Specication Remark
1. Display Screen Device 86” wide color display module LC860EQF-FHF1 (3D,T240)
79” wide color display module LC790EQF-FHF1 (3D,T240)
LC790EQF-FGM1 (2D,T240)
70” wide color display module HC700EQF-VHEQ1 (2D,M120)
65” wide color display module LC650EQF-FHM1 (2D,T240)
LC650EQF-FHM2 (2D,T240)
LC650EQF-PHF1 (3D,T240)
LC650VQF-FHF1 (3D,T240,Curved)
60” wide color display module LC600EQF-FHM1 (2D,T240)
LC600EQF-PHF1 (3D,T240)
55” wide color display module LC550EQE-FHM1 (2D,T120)
LC550EQE-FHM2 (2D,T120)
LC550EQE-PHF1 (3D,T120)
LC550VQF-FHF1 (3D,T240,Curved)
49” wide color display module LC490EQE-FHM1 (2D,T120)
LC490EQE-FHM2 (2D,T120)
LC490EQE-XHF1 (3D,T120)
43” wide color display module LC430EQE-FHM1 (2D,T120)
LC430EQE-FHM2 (2D,T120)
40” wide color display module HC400EQN-VCEQ1 (2D,T120)
HC400EQN-VCEQ2 (2D,T120)
2. Aspect Ratio 16:9 All
3. LCD Module 86” QWUXGA TFT LCD
79” QWUXGA TFT LCD
70” QWUXGA TFT LCD
65” QWUXGA TFT LCD
60” QWUXGA TFT LCD
55” QWUXGA TFT LCD
49” QWUXGA TFT LCD
49” QWUXGA TFT LCD
40” QWUXGA TFT LCD
4. Operating Environment TFT 1) Temp. : 0 ~ 40 deg
2) Humidity : 0 ~ 85%
LGE SPEC
ALEF Temp. : 0 ~ 50 deg
Humidity : 20 ~ 90%
5. Storage Environment TFT Temp. : -20 ~ 60 deg
Humidity : 10 ~ 90%
ALEF Temp. : -20 ~ 60 deg
Humidity : 10 ~ 90%
6. Input Voltage AC100 ~ 240V, 50/60Hz
7. Display Colors 1.06 B (10-bit) Except FHD 60Hz models
16.7 M (8-bit) Only FHD 60Hz models
Surface Treatment Hard coating (2H), Anti-glare
- 8 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
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5. External input format
5.1. 2D Mode
5.1.1. Component input(Y, CB/PB, CR/PR)
5.1.2. HDMI Input (PC/DTV)
No
Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2. 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3. 720*480 31.50 60 27.027 SDTV 480P
4. 720*480 31.47 59.94 27.0 SDTV 480P
5. 1280*720 45.00 60.00 74.25 HDTV 720P
6. 1280*720 44.96 59.94 74.176 HDTV 720P
7. 1920*1080 33.75 60.00 74.25 HDTV 1080I
8. 1920*1080 33.72 59.94 74.176 HDTV 1080I
9. 1920*1080 67.500 60 148.50 HDTV 1080P
10. 1920*1080 67.432 59.94 148.352 HDTV 1080P
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed
HDMI-PC EGA
1 640*350 31.468 70.09 25.17 DOS Х
2 720*400 31.469 70.08 28.32 VESA(VGA) O
3 640*480 31.469 59.94 25.17 VESA(SVGA) O
4 800*600 37.879 60.31 40.00 VESA(XGA) O
5 1024*768 48.363 60.00 65.00 VESA O
6 1152*864 54.348 60.053 80.00 VESA (SXGA) O
7 1280*1024 63.981 60.020 108.00 VESA (WXGA) O
8 1360*768 47.712 60.015 85.50 WUXGA
(Reduced Blanking)
O
9 1920*1080 67.5 60 148.5
Only UD Model
O
10 3840*2160 54 24.00 297.00
Only UD Model
O
11 3840*2160 56.25 25.00 297.00
Only UD Model
O
12 3840*2160 67.5 30.00 297.00
Only UD Model
O
14 4096*2160 54 24 297
Only UD Model
O
15 4096*2160 56.25 25 297
Only UD Model
O
16 4096*2160 67.5 30 297
Only UD Model
O
17 4096*2160 67.5 30 297
Only UD Model
O
- 9 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
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HDMI-DTV
1 640 * 480 31.469 59.94 25.125 SDTV 480P
2 640 * 480 31.5 60 25.125 SDTV 480P
3 720 * 480 31.5 60 27.027 SDTV 480P
4 720 * 480 31.47 59.94 27.00 SDTV 480P
5 1280*720 45.00 60.00 74.25 HDTV 720P
6 1280*720 44.96 59.94 74.176 HDTV 720P
7 1920*1080 33.75 60.00 74.25 HDTV 1080I
8 1920*1080 33.72 59.94 74.176 HDTV 1080I
9 1920*1080 67.50 60 148.50 HDTV 1080P
10 1920*1080 67.432 59.94 148.35 HDTV 1080P
11 1920*1080 27.000 24.000 74.25 HDTV 1080P
12 1920*1080 26.97 23.976 74.176 HDTV 1080P
13 1920*1080 33.75 30.000 74.25 HDTV 1080P
14 1920*1080 33.71 29.97 74.176 HDTV 1080P
15 3840*2160 67.5 30.00 297.00 UDTV 2160P
16 3840*2160 61.43 29.97 296.703 UDTV 2160P
17 3840*2160 56.25 25.00 297.00 UDTV 2160P
18 3840*2160 54.0 24.00 297.00 UDTV 2160P
19 3840*2160 53.95 23.976 296.703 UDTV 2160P
20 3840*2160 135 59.94 594 UDTV 2160P(HDMI 1,2 only)
21 3840*2160 135 60 594 UDTV 2160P(HDMI 1,2 only)
22 4096*2160 53.95 23.98 296.703 UDTV 2160P
23 4096*2160 54 24 297 UDTV 2160P
24 4096*2160 56.25 25 297 UDTV 2160P
25 4096*2160 61.43 29.97 296.703 UDTV 2160P
26 4096*2160 67.5 30 297 UDTV 2160P
27 4096*2160 135 59.94 594 UDTV 2160P(HDMI 1,2 only)
28 4096*2160 135 60 594 UDTV 2160P(HDMI 1,2only)
- 10 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
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5.2. 3D Mode
5.2.1. HDMI Input 1.4b (3D supported mode automatically)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock
(MHz)
VIC 3D input proposed
mode
Proposed
1 640*480 31.46 / 31.5 59.94/ 60 25.17/25.2 1 Top-and-Bottom
Side-by-side(half)
Secondary(SDTV 480P)
Secondary(SDTV 480P)
62.93 / 63 59.94/ 60 50.35/50.4 1 Frame packing
Line alternative
Secondary(SDTV 480P)
(SDTV 480P)
31.46 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)
2 720*480 31.46 / 31.5 59.94 / 60 27.00/27.03 2,3 Top-and-Bottom
Side-by-side(half)
Secondary(SDTV 480P)
Secondary(SDTV 480P)
62.93 / 63 59.94 / 60 54/54.06 2,3 Frame packing
Line alternative
Secondary(SDTV 480P)
(SDTV 480P)
31.46 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)
3 1280*720 44.96 / 45 59.94 / 60 74.18/74.25 4 Top-and-Bottom
Side-by-side(half)
Primary(HDTV 720P)
Primary(HDTV 720P)
89.91 / 90 59.94 / 60 148.35/148.5 4 Frame packing
Line alternative
Primary(HDTV 720P)
(HDTV 720P)
44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)
4 1920*1080 33.72 / 33.75 59.94 / 60 74.18/74.25 5 Top-and-Bottom
Side-by-side(half)
Secondary(HDTV 1080I)
Primary(HDTV 1080I)
67.43 / 67.5 59.94 / 60 148.35/148.5 5 Frame packing
Field alternative
Primary(HDTV 1080I)
(HDTV 1080I)
33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)
26.97 / 27 23.97 / 24 74.18/74.25 32 Top-and-Bottom
Side-by-side(half)
Primary(HDTV 1080P)
Primary(HDTV 1080P)
43.94 / 54 23.97 / 24 148.35/148.5 32 Frame packing
Line alternative
Primary(HDTV 1080P)
(HDTV 1080P)
26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)
28.125 25 74.25 33 Top-and-Bottom
Side-by-side(half)
Secondary(HDTV 1080P)
Secondary(HDTV 1080P)
56.25 25 148.5 33 Frame packing
Line alternative
Secondary(HDTV 1080P)
(HDTV 1080P)
28.125 25 148.5 33 Side-by-side(Full) (HDTV 1080P)
33.716 / 33.75 29.976 / 30.00 74.18/74.25 34 Top-and-Bottom
Side-by-side(half)
Primary(HDTV 1080P)
Secondary(HDTV 1080P)
67.432 / 67.5 29.976 / 30.00 148.35/148.5 34 Frame packing
Line alternative
Primary(HDTV 1080P)
(HDTV 1080P)
33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)
67.43 / 67.5 59.94 / 60 148.35/148.50 16 Top-and-Bottom
Side-by-side(half)
Primary(HDTV 1080P)
Secondary(HDTV 1080P)
- 11 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
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5.2.2. HDMI 1.4/2.0(3D Supported mode manaually)
5.2.3. HDMI-PC Input (3D) (3D Supported Mode Manually)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock
(MHz)
Proposed 3D input proposed mode
1. 720*480 31.5 60 27.03 SDTV 480P 2D to 3D, Side by Side(Half),
Top & Bottom, Checker Board,
Frame Sequential,
Row Interleaving, Column Interleaving
2. 1280*720 45.00 60.00 74.25 HDTV 720P
3. 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(Half),
Top & Bottom
4. 1920*1080 27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half),
Top & Bottom, Checker Board,
Row Interleaving,
Column Interleaving
5. 1920*1080 28.12 25 74.25 HDTV 1080P
6. 1920*1080 33.75 30.00 74.25 HDTV 1080P
7. 1920*1080 67.50 60.00 148.5 HDTV 1080P 2D to 3D, Side by Side(Half),
Top & Bottom,
Checker Board,
Single Frame Sequential,
Row Interleaving, Column Interleaving
8. 3840*2160 53.95 23.976 296.703 HDTV 2160P
9. 3840*2160 54 24.00 297.00 HDTV 2160P
10. 3840*2160 56.25 25.00 297.00 HDTV 2160P
11. 3840*2160 61.43 29.970 296.703 HDTV 2160P
12. 3840*2160 67.5 30.00 297.00 HDTV 2160P
13. 4096*2160 53.95 23.976 296.703 HDTV 2160P
14. 4096*2160 54 24.00 297.00 HDTV 2160P
15. 4096*2160 56.25 25.00 297.00 HDTV 2160P
16. 4096*2160 61.43 29.970 296.703 HDTV 2160P
17. 4096*2160 67.5 30.00 297.00 HDTV 2160P
18. 3840*2160 135 60 594 HDTV 2160P 2D to 3D, Top & Bottom(half),
Side by Side(half), Port3 Only
19. 4096*2160 135 60 594 HDTV 2160P 2D to 3D, Top & Bottom(half),
Side by Side(half), Port3 Only
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock
(MHz)
Proposed 3D input proposed mode
1. 1024*768 48.36 60 65 HDTV 768P 2D to 3D,
Side by Side(half), Top & Bottom
2. 1360*768 47.71 60 85.5 HDTV 768P 2D to 3D,
Side by Side(half), Top & Bottom
3. 1920*1080 67.500 60 148.50 HDTV 1080P 2D to 3D,
Side by Side(half), Top & Bottom,
Checker Board, Single Frame
Sequential, Row Interleaving,
Column Interleaving
4. 3840*2160
4096*2160
54 24.00 296.703 HDTV 2160P 2D to 3D,
Top & Bottom(half), Side by Side(half),
56.25 25.00 297
67.5 30.00 296.703
5. 3840*2160
4096*2160
135 60 594 HDTV 2160P 2D to 3D,
Top & Bottom(half), Side by Side(half),
Port3 Only
6. Others - - - 640*350
720*400
640*480
800*600
1152*864
2D to 3D,
Side by Side(half), Top & Bottom
- 12 -
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Copyright © LG Electronics. Inc. All rights reserved.
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5.2.4. RF Input(3D supported mode manually)
5.2.5. RF Input (3D supported mode automatically)
5.2.6. USB, DLNA (Movie) Input (3D supported mode manually)
5.2.7. USB, DLNA (Photo) Input (3D supported mode manually)
5.2.8. USB, DNLA Input (3D supported mode automatically)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1280*720 37.500 50 74.25 HDTV 720P 2D to 3D, Side by Side, Top & Bottom
2 1920*1080 28.125 50 74.25 HDTV 1080I 2D to 3D, Side by Side, Top & Bottom
No. Signal 3D input proposed mode
1 Frame Compatible Side by Side(Half), Top & Bottom
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 Under 704x480 - - - 2D to 3D
2 Over 704x480
interlaced
- - - 2D to 3D, Side by Side(Half), Top & Bottom
3 Over 704x480
progressive
- 60 - 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Row Interleaving,
Column Interleaving, Frame Sequential
4 Over 704x480
progressive
- others - 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Row Interleaving,
Column Interleaving
5 Over 2160P - 24/25/30/60 - 2D to 3D, Side by Side(Half),
Top & Bottom, USB Only
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 USB(Photo) - - - 2D to 3D, Side by Side(Half), Top & Bottom
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 1080P 33.75 30 - Side by Side(Half), Top & Bottom, Checker Board,
MPO(Photo)
2 2160p 67.5 30 297 MPO(Photo), JPS(Photo)
- 13 -
LGE Internal Use Only
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5.2.9. Component Input(3D supported mode manually)
5.2.10. Miracast, Widi (3D supported mode manually)
**Remark: 3D Input mode
No. Side by Side Top & Bottom Checkerboard Single Frame
Sequential
Frame Packing Line
Interleaving
Column
Interleaving
1
R
L
R
L
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1 1280*720 45.00 60.00 74.25 HDTV 720P 2D to 3D,
Side by Side(Half),
Top & Bottom
2 1280*720 37.500 50 74.25 HDTV 720P
3 1920*1080 33.75 60.00 74.25 HDTV 1080I
4 1920*1080 28.125 50.00 74.25 HDTV 1080I
5 1920*1080 27.00 24.00 74.25 HDTV 1080P
6 1920*1080 28.12 25 74.25 HDTV 1080P
7 1920*1080 33.75 30.00 74.25 HDTV 1080P
8 1920*1080 67.50 60.00 148.5 HDTV 1080P
9 1920*1080 56.250 50 148.5 HDTV 1080P
10 Others - - - SDTV
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 1024X768p - 30 / 60 - 2D to 3D, Side by Side(Half), Top & Bottom
2 1280x720p - 30 / 60 -
3 1920X1080p 30 / 60
4 Others - 2D to 3D
- 14 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range
This spec. sheet applies to LA53J Chassis applied LED TV all
models manufactured in TV factory
2. Specification.
(1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation
transformer will help protect test instrument
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 ±5ºC of temperature and 65±10% of relative humidity if
there is no specific designation
(4) The input voltage of the receiver must keep 100~240V,
50/60Hz
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15ºC
▪ In case of keeping module is in the circumstance of 0°C, it
should be placed in the circumstance of above 15°C for 2
hours
▪ In case of keeping module is in the circumstance of below
-20°C, it should be placed in the circumstance of above 15°C
for 3 hours
* Caution) When still image is displayed for a period of 20
minutes or longer (especially where W/B scale is
strong. Digital pattern 13ch and/or Cross hatch
pattern 09ch), there can some afterimage in the
black level area.
3. Adjustment items
3.1. Main PCB check process
▪ MAC Address Download
▪ ADC adjustment : 480i Comp1, 1920*1080 Comp1
▪ EDID/DDC download
Above adjustment items can be also performed in Final
Assembly if needed. Both Board-level and Final assembly
adjustment items can be check using In-Start Menu 1.ADJUST
CHECK.
3.2. Final assembly adjustment
▪ White Balance adjustment
▪ RS-232C functionality check
▪ PING Test
▪ Factory Option setting per destination
▪ Ship-out mode setting (In-Stop)
3.3. Etc.
▪ Ship-out mode
▪ Service Option Default
▪ USB Download(S/W Update, Option, Service only)
▪ ISP Download (Option)
4. Automatic Adjustment
4.1. ADC Adjustment
ADC adjustment is needed to find the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
deviation.
4.1.1. Equipment & Condition
(1) USB to RS-232C Jig
(2) MSPG-925 Series Pattern Generator(MSPG-925FA,
pattern -65)
- Resolution : 480i Comp1
1080P Comp1
- Pattern : Horizontal 100% Color Bar Pattern
- Pattern level : 0.7±0.1 Vp-p
- Image
4.1.2. Adjustment method
▪ Using USB, adjust items listed in 3.1 in the other shown in
“4.1.3.3”
4.1.3. 3 Adj. protocol
Protocol Command Set ACK
Enter adj. mode aa 00 00 a 00 OK00x
Source change xb 00 40
xb 00 60
b 00 OK04x (Adjust 480i, 1080p Comp1 )
b 00 OK06x (Adjust 1920*1080 RGB)
Begin adj. ad 00 10
Return adj. result OKx (Case of Success)
NGx (Case of Fail)
Read adj. data (main)
ad 00 20
(sub )
ad 00 21
(main)
000000000000000000000000007c007b006dx
(Sub)
000000070000000000000000007c0083
0077x
Conrm adj. ad 00 99 NG 03 00x (Fail)
NG 03 01x (Fail)
NG 03 02x (Fail)
OK 03 03x (Success)
End adj. ad 00 90 a 00 OK90x
Ref.) ADC Adj. RS232C Protocol_Ver1.0
Adj. order
▪ aa 00 00 [Enter ADC adj. mode]
▪ xb 00 04 [Change input source to Component1(480i&1080p)]
▪ ad 00 10 [Adjust 480i&1080p Comp1]
▪ xb 00 06 [Change input source to RGB(1024*768)]
▪ ad 00 10 [Adjust 1920*1080 RGB]
▪ aa 00 90 End adj.
- 15 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
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4.2. MAC address, ESN, Widevine, HDCP2.0
key D/L
4.2.1. Equipment & Condition
1) Play file: keydownload.exe
4.2.2. Communication Port connection
1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)
2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)
4.2.3. Download process
1) Select the download items.
2) Mode check: Online Only
3) Check the test process : DETECT -> MAC -> Widevine
4) Play: START
5) Check of result: Ready, Test, OK or NG
4.2.4. Communication Port connection
1) ) Connect: PCBA Jig -> RS-232C Port == PC -> RS-232C
Port
4.2.5. Download
1) AJ/JA Models (15Y LCD TV + MAC + Widevine + ESN +
HDCP2.0)
4.3. LAN Inspection
4.3.1. Equipment & Condition
▪ Each other connection to LAN Port of IP Hub and Jig
4.3.2. LAN inspection solution
▪ LAN Port connection with PCB
▪ Network setting at MENU Mode of TV
▪ Setting automatic IP
▪ Setting state confirmation
- If automatic setting is finished, you confirm IP and MAC
Address.
4.3.3. LAN PORT INSPECTION (PING TEST)
1) Play the LAN Port Test PROGRAM.
2) Input IP set up for an inspection to Test
Program.
*IP Number : 12.12.2.2.
- 16 -
LGE Internal Use Only
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4.3.4. LAN PORT inspection (PING TEST)
1) Play the LAN Port Test Program.
2) connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) remove LAN CABLE
4.4. Model name & Serial number Download
4.4.1. Model name & Serial number D/L
▪ Press “Power on” key of service remocon.(Baud rate :
115200 bps)
▪ Connect RS-232C Signal to USB Cable to USB.
▪ Write Serial number by use USB port.
▪ Must check the serial number at Instart menu.
■ Method & Notice
A. Serial number D/L is using of scan equipment.
B. Setting of scan equipment operated by Manufacturing
Technology Group.
C. Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded By OTA or Service man,
sometimes model name or serial number is initialized. ( not
always)
It is impossible to download by bar code scan, so It need
Manual download.
a. Press the ‘INSTART’ key of ADJ remote controller.
b. Go to the menu ‘7. Model Number D/L’ like below photo.
c. Input the Factory model name or Serial number like below
photo.
d. Check the model name INSTART menu -> Factory name
displayed
e. Check the Diagnostics (DTV country only) -> Buyer model
displayed
4.5. WIFI MAC ADDRESS CHECK
4.5.1. Using RS232 Command
Command Set ACK
Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]
■ Check the menu on in-start
- 17 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
5. Manual Adjustment
5.1. ADC adjustment is not needed because of
OTP (Auto ADC adjustment)
5.2. EDID
(The Extended Display Identification Data)
/ DDC (Display Data Channel) download
5.2.1. Overview
It is a VESA regulation. A PC or a MNT will display an optimal
resolution through information sharing without any necessity of
user input. It is a realization of “Plug and Play”.
5.2.2. Equipment
▪ Since embedded EDID data is used, EDID download JIG,
HDMI cable and D-sub cable are not need.
▪ Adjust remocon
5.2.3. Download method
1) Press Adj. key on the Adjust remocon, then select “12.EDID
D/L”.
By pressing Enter key, enter EDID D/L menu
2) Select [Start] button by pressing Enter key, HDMI1 / HDMI2
/ HDMI3 / HDMI4 are Writing and display OK or NG.
5.2.4. EDID DATA
▪ Reference
- HDMI1 ~ HDMI3
- HDMI1 ~ HDMI4
- In the data of EDID, bellows may be different by Input mode
ⓐ Product ID
ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ -> ‘01’
Year : ‘2015’ -> ‘19
ⓓ Model Name(Hex): LGTV
ⓔ Checksum(LG TV): Changeable by total EDID data.
ⓕ Vendor Specific(HDMI)
5.2.4.1. EDID
# DTS HDMI1 (C/S: A0,E5)_6G_UHD Deep Color ON
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
- 18 -
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# DTS HDMI1 (C/S: E6 72)_3G_UHD Deep Color OFF
EDID Block 0, Bytes 0-12
EDID Block 1, Bytes 128-255
# DTS HDMI2 (C/S: A0,D5)_6G_UHD Deep Color ON
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
# DTS HDMI2 (C/S: E6 62)_3G_UHD Deep Color OFF
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
# DTS HDMI3 (C/S: E6 52)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
- 19 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
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# AC3 HDMI1 (C/S: E7 8B)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
# AC3 HDMI2 (C/S: E7 7B)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
# AC3 HDMI3 (C/S: A1 8A)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
# AC3 HDMI4 (C/S: E7 5B)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
# PCM HDMI1 (C/S: F7 FD)
EDID Block 0, Bytes 0-127
- 20 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
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EDID Block 1, Bytes 128-255
# PCM HDMI2 (C/S: E7 E2)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
# PCM HDMI3 (C/S: A1 FC)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
# PCM HDMI4 (C/S: E7 BD)
EDID Block 0, Bytes 0-127
EDID Block 1, Bytes 128-255
* Checksum (HDMI 1/2/3/4)
Input DTS FFh
(Checksum(6G)
DTS FFh
(Checksum(3G)
PCM FFh
(Checksum)
AC3 FFh
(Checksum)
HDMI1 A0 E5 E6 72 8B 8B E7 FD
HDMI2 A0 D5 E6 62 7B 7B E7 ED
HDMI3 E6 52 8A 8A A1 FC
5.3. Camera Port Inspection
(1) Objective : To check how it connects between Camera and
PCBA normally, and their Function
(2) Test Method : This Inspection is available only Power-Only
Status.
i) Push Camera Up
ii) Camera’s Preview picture appears on TV Set
iii) Push Camera Down
(3) RS-232C Command
RS-232C COMMAND
Explanation
CMD DATA ID
Ai 00 23 Camera Function Start.
Ai 00 24 Camera Function End.
- 21 -
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5.4. V-COM Adjust
(*) ONLY FOR GP2 2010year model. GP3 LW Series
[2011year] spec out !
5.5. White Balance Adjustment
5.5.1. Overview
5.5.1.1. W/B adj. Objective & How-it-works
(1) Objective: To reduce each Panel’s W/B deviation
(2) How-it-works: When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.
(3) Adj. condition: normal temperature
- Surrounding Temperature: 25±5 °C
- Warm-up time: About 5 Min
- Surrounding Humidity: 20% ~ 80%
5.5.2. Equipment
(1) Color Analyzer: CA-210 (LED Module : CH 14)
(2) Adj. Computer (During auto adj., RS-232C protocol is
needed)
(3) Adjust Remocon
(4) Video Signal Generator MSPG-925F 720p/204-Gray
(Model: 217, Pattern: 49)
※ Color Analyzer Matrix should be calibrated using CS-1000
5.5.3. Equipment connection MAP
5.5.4. Adj. Command (Protocol)
<Command Format>
START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS
A STOP
- LEN: Number of Data Byte to be sent
- CMD : Command
- VAL : FOS Data value
- CS : Checksum of sent data
- A : Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
(1) RS-232C Command used during auto-adj.
RS-232C COMMAND
Explanation
CMD DATA ID
wb 00 00 Begin White Balance adj.
wb 00 10 Gain adj.(internal white pattern)
wb 00 1f Gain adj. completed
wb 00 20 Offset adj.(internal white pattern)
wb 00 2f Offset adj. completed
wb 00 ff End White Balance adj.
(internal pattern disappears )
Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
jb 00 c0
...
...
wb 00 1f -> Gain adj. complete
*(wb 00 20(start), wb 00 2f(endc)) -> Off-set adj.
wb 00 ff -> End white balance auto adj.
(2) Adjustment Map
Applied Model : ALL MODELS
Adj. item Command
(lower caseASCII)
Data Range
(Hex.)
CMD1 CMD2 MIN MAX
Cool R Gain j g 00 C0
G Gain j h 00 C0
B Gain j i 00 C0
Medium R Gain j a 00 C0
G Gain j b 00 C0
B Gain j c 00 C0
Warm R Gain j d 00 C0
G Gain j e 00 C0
B Gain j f 00 C0
Color Analyzer
Computer
Pattern Generator
RS-232C
RS-232C
RS-232C
Probe
Signal Source
* If TV internal pattern is used, not needed
- 22 -
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5.5.5. Adjustment method
5.5.5.1. Auto WB calibration
(1) Set TV in adj. mode using POWER ONNY key
(2) Zero calibrate probe then place it on the center of the
Display
(3) Connect Cable (RS-232C to USB)
(4) Select mode in adj. Program and begin adj.
(5) When adj. is complete (OK Sign), check adj. status pre
mode(Warm, Medium, Cool)
(6) Remove probe and RS-232C to USB cable to complete adj.
▪ W/B Adj. must begin as start command “wb 00 00” , and
finish as end command “wb 00 ff”, and Adj. offset if need
5.5.5.2. Manual adj. method
1) Set TV in Adj. mode using POWER ON
2) Zero Calibrate the probe of Color Analyzer, then place it on
the center of LCD module within 10cm of the surface..
3) Press ADJ key -> EZ adjust using adj. R/C -> 7. White-
Balance then press the cursor to the right (KEY►).
(When KEY(►) is pressed 216 Gray internal pattern will be
displayed)
4) One of R Gain / G Gain / B Gain should be fixed at 192, and
the rest will be lowered to meet the desired value.
5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of
color temperature.
** R-fix adjustment
Adjust modes (Cool), Fix the R gain to 210 (default data) and
change the others (G/B Gain ).
- Adjust the R gain more than 210 ( If G gain or B gain is less
than 0 , R gain can adjust more than 210 ) and
change the others ( G/B Gain ).
Adjust two modes (Medium / Warm), Fix the one of R/G/B gain
to 192 (default data) and decrease the others.
▪ If internal pattern is not available, use RF input. In EZ Adj.
menu 7.White Balance, you can select one of 2 Test-pattern:
ON, OFF. Default is inner(ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.
▪ Adj. condition and cautionary items
1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to isolate
adj. area into dark surrounding.
2) Probe location
- PDP : Color Analyzer (CA-100, CA-100+, CA210) probe
should be firmly attached to the Module
- LCD : Color Analyzer (CA-210) probe should be within 10cm
and perpendicular of the module surface (80°~ 100°)
3) Aging time
- After Aging Start, Keep the Power ON status during 5
Minutes.
- In case of LCD, Back-light on should be checked using no
signal or Full-white pattern.
5.5.6. Reference (White Balance Adj. coordinate and
color temperature)
▪ Luminance: 206 Gray
▪ Standard color coordinate and temperature using CS-1000
(over 26 inch)
Mode
Coordinate
Temp △uv
X Y
Cool 0.271 0.270 13,000K 0.0000
Medium 0.283 0.289 9,300K 0.0000
Warm 0.313 0.329 6,500K 0.0000
▪ Standard color coordinate and temperature using CA-210
(CH 14)
Mode
Coordinate
Temp △uv
X Y
Cool 0.271±0.002 0.270±0.002 13000K 0.0000
Medium 0.286±0.002 0.289±0.002 9300K 0.0000
Warm 0.313±0.002 0.329±0.002 6500K 0.0000
5.5.7. EDGE & IOL LED White balance table
▪ Edge & ALEF LED module change color coordinate because
of aging time
▪ apply under the color coordinate table, for compensated
aging time
(Normal line) Edge & ALEF LED White balance table
- gumi(Mar~Dec) & Global
Model : (normal line)LGD
webOS
Aging time
(Min)
Cool Medium Warm
X Y X Y X Y
271 270 285 293 313 329
1 0-2 281 287 295 310 320 342
2 3-5 280 285 294 308 319 340
3 6-9 278 284 292 307 317 339
4 10-19 276 281 290 304 315 336
5 20-35 275 277 289 300 314 332
6 36-49 274 274 288 297 313 329
7 50-79 273 272 287 295 312 327
8 80-119 272 271 286 294 311 326
9 Over 120 271 270 285 293 310 325
- 23 -
LGE Internal Use Only
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- gumi Winter table(Jan, Fab) – Gumi producing model use only
Model : (normal line) LGD
webOS
Aging time
(Min)
Cool Medium Warm
X Y X Y X Y
271 270 285 293 313 329
1 0-2 283 292 297 315 322 347
2 3-5 282 290 296 313 321 345
3 6-9 280 288 294 311 319 343
4 10-19 277 284 291 307 316 339
5 20-35 275 279 289 302 314 334
6 36-49 274 275 288 298 313 330
7 50-79 273 272 287 295 312 327
8 80-119 272 271 286 294 3 11 326
9 Over 120 271 270 285 293 310 325
- (Aging Chamver)Edge&ALEF
Model : (aging chamber)LGD,
webOS
Aging time
(Min)
Cool Medium Warm
X Y X Y X Y
271 270 285 293 313 329
1 0-5 280 285 294 308 319 340
2 6-10 276 280 290 303 315 335
3 11-20 272 275 286 298 311 330
4 21-30 269 272 283 295 308 327
5 31-40 267 268 281 291 306 323
6 41-50 266 265 280 288 305 320
7 51-80 265 263 279 286 304 318
8 81-119 264 261 278 284 303 316
9 Over 120 264 260 278 283 303 315
5.6. Local Dimming Function Check
Step 1) Turn on TV
Step 2) At the Local Dimming mode, module Edge Backlight
moving right to left
Back light of IOP module moving
Step 3) confirm the Local Dimming mode
Step 4) Press “exit” Key
5.7. Magic Motion Remocon test
- Equipment : RF Remocon for test, IR-KEY-Code Remocon
for test
- You must confirm the battery power of RF-Remocon before
test
(recommend that change the battery per every lot)
- Sequence (test)
a) if you select the ‘start key(OK)’ on the controller, you can
pairing with the TV SET.
b) You can check the cursor on the TV Screen, when select
the ‘OK Key’ on the controller
c) You must remove the pairing with the TV Set by select
‘Mute + OK Key’ on the controller
5.8. 3D function test
(Pattern Generator MSHG-600, MSPG-6100 [SUPPORT
HDMI1.4])
* HDMI mode NO. 872 , pattern No.83
1) Please input 3D test pattern like below (HDMI mode NO. 872 ,
pattern No.83)
2) When 3D OSD appear automatically , then select green button
3) Don’t wear a 3D Glasses, Check the picture like below
- 24 -
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Copyright © LG Electronics. Inc. All rights reserved.
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5.9. EYE-Q Green Function Inspection
step 1) Turn on the TV..
Step 2) Press 'EYE button' on the adjustment remote-controller.
Step 3) Cover 'Eye Q sensor' on the front of set with your hands,
hold it for 6 seconds.
Step 4) Check "the Sensor Data" on the screen, make certain that
Data is below 10. If Data isn’t below 10 in 6 seconds, Eye
Q sensor would be bad. You should change Eye Q
sensor.
Step 5) Uncover your hands from Eye Q sensor, hold it for 6
seconds.
Step 6) Check "Back Light(xxx)" on the screen, check data
increase . You should change Eye Q sensor
5.10. Ship-out mode check (In-stop)
▪ After final inspection, press In-Stop key of the Adj. R/C and
check that the unit goes to Stand-by mode.
6. GND and Internal Pressure check
6.1. Method
1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET. (If loose,
re-insert)
2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V arrive
to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX)
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.
6.2. Checkpoint
(1) Test voltage
- GND: 1.5KV/min at 100mA
- SIGNAL: 3KV/min at 100mA
(2) TEST time: 1 second
(3) TEST POINT
- GND Test = POWER CORD GND and SIGNAL CABLE GND.
- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.
(4) LEAKAGE CURRENT: At 0.5mArms
7. AUDIO output check
No Item Min Typ Max Unit Remark
1 Audio practical
max Output, L/R
(Distortion=10%
max Output)
10.0
8.10
12.0
10.8WVrms
EQ Off
AVL Off
Clear Voice Off
2
Speaker
(8Ω Impedance)
10 12 W EQ On
AVL On
Clear Voice On
*Measurement condition:
(1) RF input: Mono, 1KHz sine wave signal, 100% Modulation
(2) CVBS, Component: 1KHz sine wave signal (0.4Vrms)
(3) RGB PC: 1KHz sine wave signal (0.7Vrms)
Tuner GND is separated.
- 25 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
8. USB S/W Download
(optional, Service only)
(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick
- If your downloaded program version in USB Stick is lower
than that of TV set, it didn’t work. Otherwise USB data is
automatically detected.
(3) Show the message “Copying files from memory”
(4) Updating is staring
(5) Updating Completed, The TV will restart automatically
(6) If your TV is turned on, check your updated version and
Tool option.
* If downloading version is more high than your TV have, TV
can lost all channel data. In this case, you have to channel
recover. If all channel data is cleared, you didn’t have a DTV/
ATV test on production line.
* After downloading, TOOL OPTION setting is needed again.
(1) Push "IN-START" key in service remote controller.
(2) Select "Tool Option 1" and Push “OK” button.
(3) Punch in the number. (Each model has their number.)
- 26 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
MAIN Audio AMP
(NTP7514)
Mstar
LM15U
CI Slot
P_TS
P_TS
T/C Demod
IF (+/-)
USB1 (3.0)
OPTIC
LAN
DDR3 1866 X 32
(512MB X 2EA)
HDMI3
HDMI2(ARC)
HDMI1
Analog Demod
EEPROM(NVRA
M)
(256Kb)
HDMI
Air/
Cable
TUNER
(T2/C/A)
TUNER
(S2)
DVB-S
DEMOD
(S2)
LNB
USB2 (2.0)
51P
eMMC
(4GB)
Sub Micom
(RENESAS
R5F100GEAFB)
DDR3 1866 X 32
(256MB X 2EA)
P_TS
X_TAL
24MHz
T2/C/S2 W/O AD
A
B
X_TAL
32.768KHz
I2S Out
I2C 4
Vx1
USB
P_TS
I2C 1
H/P
AV/COMP
SCART
(IN/OUT)
OCP
R
E
R
CVBS/YPbPr
CVBS/RGB
SPDIF OUT
ETHERNET
I2C 3
(HW Port)
SUB
ASSY
IR / KEY
LOGO LIGHT(Ready
WIFI/BT Combo
USB_WIFI
CVBS
SMARTCARD_I/F
B-CAS
B-CAS
(JAPAN)
Chip Config
4b’1010
C
DDR3 1866 X 32
(512MB X 2EA)
USB3 (2.0)
I2C 6
BLOCK DIAGRAM
- 27 -
LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EXPLODED VIEW
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced w ith the same components as
recommended in this manual to prevent Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
IMPORTANT SAFETY NOTICE
200
400
540
521
800
121
120
820
530
A10
A22
Stand screw
LV1
901
900
350
*Option
200T
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2014-12-17LM15U
1
MAIN1_SYSTEM
FE_DEMOD1_TS_DATA[4]
TPI_DATA[2]
EB_ADDR[0]
FE_DEMOD1_TS_DATA[3]
EMMC_DATA[1]
FE_DEMOD1_TS_DATA[6]
EMMC_DATA[0]
EB_ADDR[1]
EMMC_DATA[2]
EB_ADDR[4]
EMMC_DATA[7]
TPI_DATA[0-7]
EMMC_DATA[6]
EMMC_DATA[3]
EB_ADDR[3]
EB_ADDR[2]
EB_ADDR[5]
EMMC_DATA[4]
EMMC_DATA[5]
EB_ADDR[6]
EB_DATA[6]
TPI_DATA[7]
FE_DEMOD1_TS_DATA[7]
EB_ADDR[10]
FE_DEMOD1_TS_DATA[1]
TPI_DATA[3]
EB_DATA[1]
EB_ADDR[9]
TPI_DATA[6]
EB_ADDR[14]
TPI_DATA[0]
TPI_DATA[5]
TPI_DATA[4]
EB_ADDR[8]
TPI_DATA[1]
FE_DEMOD1_TS_DATA[2]
EB_DATA[3]
EB_DATA[5]
EB_DATA[4]
EB_DATA[7]
EB_ADDR[13]
EB_ADDR[12]
EB_DATA[2]
EB_ADDR[7]
EB_DATA[0]
EB_ADDR[11]
FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[0]
TPO_DATA[1]
TPO_DATA[6]
TPO_DATA[7]
TPO_DATA[0]
TPO_DATA[2]
TPO_DATA[4]
TPO_DATA[5]
TPO_DATA[3]
I2C_SCL7
PWM_PM
USB_CTL3
BIT7
AMP_RESET_N
I2C_SCL1
USB_CTL2
TXOSD_1P
LOCKAn_Video
I2C_SDA3
DDCA_DA
USB_CTL1
BIT0
I2C_SDA3
TXVBY1_0P
BIT11
TXVBY1_6N
TPI_SOP
EB_BE_N1
BIT8
FRC_FLASH_WP
FE_DEMOD1_TS_SYNC
DDTS_RX
I2C_SDA4
I2C_SDA3
EB_ADDR[0-14]
SPI_DI_SOC
BIT2
TXVBY1_6P
TXVBY1_7N
FE_DEMOD1_TS_CLK
TXVBY1_4P
+3.3V_NORMAL
TXVBY1_2P
SOC_TX
WOL_WAKE_UP
I2C_SCL1
TXOSD_2N
I2C_SCL2
5V_DET_HDMI_2
DDCA_DA
DDTS_TX
I2C_SCL_MICOM
TXVBY1_1P
+3.3V_NORMAL
BIT9
/PCM_CE1
PWM_DIM2
TCON_I2C_EN
TCON_I2C_EN
BIT8
AMP_RESET_N
M_RFModule_RESET
EB_OE_N
/USB_OCD3
I2C_SDA6
SOC_TX
SC_DET
EMMC_CLK
BIT6
BIT7
I2C_SDA1
/USB_OCD1
I2C_SCL3
+3.3V_NORMAL
BIT0
M_RFModule_RESET
AVDD_3P3
LED1
FE_DEMOD3_TS_SYNC
SOC_RX
+3.3V_TU
EMMC_DATA[0-7]
TXOSD_3P
PCM_RESET
EB_WE_N
I2C_SDA1
BIT4
FRC_FLASH_SEL
USB_CTL2
+3.3V_LNA_TU
+3.3V_NORMAL
/USB_OCD2
+3.3V_NORMAL
HP_DET
TXOSD_0N
EMMC_CMD
TXVBY1_4N
HTPDAn_OSD
SPI_CK_SOC
RF_SWITCH_CTL
DDTS_TX
I2C_SDA6
HTPDAn_Video
L_DIM_EN
URSA_RESET_SoC
BIT10
I2C_SDA7
I2C_SDA1
TXVBY1_3N
I2C_SCL3
+3.3V_NORMAL
FE_DEMOD3_TS_DATA
I2C_SDA2
TXVBY1_2N
/USB_OCD1
TPI_VAL
I2C_SCL4
URSA9_CONNECT
SPI_DO_SOC
BIT11
IF_P
I2C_SCL5
BIT6
BIT1
CORE_VID0
I2C_SDA7
I2C_SDA_MICOM
CAM_IREQ_N
BIT1
DDTS_RX
CPU_VID0
LED0
TXVBY1_3P
FE_DEMOD3_TS_CLK
/TU_RESET1
TXVBY1_1N
EB_BE_N0
LED0
3D_EN
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_DATA[0-7]
5V_DET_HDMI_3
AV2_CVBS_DET
EB_DATA[0-7]
TXVBY1_5P
TXOSD_0P
PCM_5V_CTL
I2C_SCL3
/TU_RESET1
TXVBY1_7P
TXOSD_1N
PWM_PM
TPI_DATA[0-7]
+3.3V_NORMAL
+3.3V_NORMAL
BIT3
EMMC_STRB
TXOSD_3N
PCM_5V_CTL
I2C_SCL6
I2C_SCL6
5V_DET_HDMI_1
FE_DEMOD3_TS_VAL
SOC_RX
BIT4
DDCA_CK
BIT2
TXVBY1_5N
HTPDAn_OSD
BIT9
IF_N
BIT5
BIT10
TU_SIF
SPI_DI_SOC
CAM_WAIT_N
LED1
PWM_DIM
+3.5V_ST
/SPI_CS
TXVBY1_0N
AV1_CVBS_DET
I2C_SDA5
CAM_REG_N
/USB_OCD2
COMP1_DET
BIT5
EMMC_RST
BIT3
I2C_SCL7
RF_SWITCH_CTL
+3.3V_NORMAL
TPI_CLK
+3.3V_NORMAL
CAM_CD1_N
I2C_SCL1
TXOSD_2P
LOCKAn_OSD
IF_AGC
USB_CTL1
DDCA_CK
HTPDAn_Video
L/D_CLK_SOC
L/D_VSYNC_SOC
L/D_DI_SOC
+3.3V_NORMAL
L/D_CLK_SOC
L/D_VSYNC_SOC
L/D_DI_SOC
SPI_DO_SOC
SPI_DI_SOC
SPI_CK_SOC
/SPI_CS
FRC_FLASH_SEL
FRC_FLASH_WP
TXOSD_0P
TXOSD_0N
TXOSD_1N
TXOSD_2N
TXOSD_2P
TXOSD_3P
TXOSD_3N
TXOSD_1P
LOCKAn_OSD
URSA9_CONNECT
COMPENSATION_DONE
COMPENSATION_DONE
FAN_ON
FAN_ON
DATA_FORMAT_0_SOC
DATA_FORMAT_1_SOC
DATA_FORMAT_1_SOC
DATA_FORMAT_0_SOC
IC102-*1
BR24G256FJ-3
Rohm_NVRAM
3
A2
2
A1
4
GND
1
A0
5
SDA
6
SCL
7
WP
8
VCC
R107
10K
BIT1_0
R166 4.7K
R142
10K
R139
1.8K
P102
12507WS-04L
UART_4PIN_WAFER
1
2
3
4
5
R116 10K
BIT4_1
R124 10K
BIT8_1
R111 10K
BIT3_0
R177
10K
OPT
R122 10K
BIT7_1
R141 100
R157 4.7K
R135
1.8K
R121 10K
BIT7_0
R150 10K
R105 10K
OPT
R100 10K
OPT
R163 4.7K
R183 10K
OPT
R167
0
FRC_FLASH_SEL
C103
0.1uF
C122
100pF
OPT
R158 4.7K
OPT
R120 10K
BIT6_1
P103
12505WS-04A00
MSTAR_DEBUG_OLD
1
2
3
4
5
R132
1.8K
R14447
R110 10K
BIT2_1
R175
22
R153 10K
C120 0.1uF
R173
10K
HTPDAn_OSD_Pull_down
C123
33pF
OPT
R133
1.8K
R161 4.7K
OPT
R104 10K
BIT0_1
R152 10K
R1910
OPT
R128
1.8K
R182 10K
R143
0
R115 10K
BIT4_0
R103 10K
BIT0_0
R172
10K
HTPDAn_Video_Pull_down
R118 10K
R136
1.8K
P101
12507WS-04L
MSTAR_DEBUG_NEW
1
2
3
4
5
R125
1.8K
R108
10K
BIT1_1
C125
0.1uF
C121 0.1uF
R164 4.7K
OPT
R151 10K
C127
0.047uF
25V
R184 10K
OPT
R101 10K
OPT
R140 100 C118 0.1uF
R179
10K
U_SPI_WP_f_SoC
R102 10K
OPT
R117 10K
OPT
R170 10K
R174 0
R134
1.8K
R178
10K
OPT
R123 10K
BIT8_0
R129
1.8K
R185 10K
R160 10K
P100
12507WS-04L
DDTS_Debug
1
2
3
4
5
R126
10K
OPT
R162 4.7K
R154 10K
OPT
R14547
R148
1.8K
IC102
AT24C256C-SSHL-T
Atmel_NVRAM
EAN61133501
3
A2
2
A1
4
GND
1
A0
5
SDA
6
SCL
7
WP
8
VCC
R106
1.8K
R165 4.7K
OPT
R159 10K
HDMI_EXT_EDID
R171 10K
OPT
R147
1.8K
R109 10K
BIT2_0
R155
4.7K
OPT
C126
33pF
OPT
R112 10K
BIT3_1
R168
0
OPT
R146
300
OPT
R131
10K
WOL_WAKE_UP
C124
1000pF
OPT
R130
1.8K
R119 10K
BIT6_0
R1800
OPT
R1870
WOL_WAKE_UP
R149 10K
C119 0.1uF
R181 10K
NON_HDMI_EXT_EDID
R169 10K
R127
1.8K
LD100
19-21 /R6C-FR1 S1L/3T
VBY1_LOCK_LED
Q100
2N3906S-RTK
KEC_VBY1_LOCK_LED_TR
E
B
C
L100
PZ1608U121-2R0TF
Q100-*1
MMBT3906(NXP)
NXP_VBY1_LOCK_LED_TR
E
B
C
/TU_RESET2
R195
3.3K
VBY1_LOCK_LED
R176
1K
BIT13
BIT12
R186 10K
R189 10K
R156 10K
OPT
R188 10K
OPT
BIT13
BIT12
TPO_CLK
TPO_DATA[0-7]
TPO_SOP
TPO_VAL
AR101
33
AR100
33
IC100
LGE5331(LM15U)
PWM0/GPIO157
A16
PWM1/GPIO158
C15
PWM2/GPIO159
A15
PWM3/GPIO160
B15
PWM4/GPIO161
C14
PWM_PM/GPIO10
E4
SAR0/GPIO50
H6
SAR1/GPIO51
J6
SAR2/GPIO52
G5
SAR3/GPIO53
J5
SAR5
D1
SPI_CK/GPIO1
D2
SPI_DI/GPIO2
D3
SPI_DO/GPIO3
E2
SPI_CZ0/GPIO0
F1
SPI_CZ1/GPIO_PM6/GPIO19
E3
SPI_CZ2/GPIO_PM10/GPIO23
F2
DDCA_CK/UART0_RX/GPIO11
N5
DDCA_DA/UART0_TX/GPIO12
P5
GPIO67/TX1
C9
GPIO68/RX1
A10
GPIO69/TX2
E9
GPIO70/RX2
F9
GPIO71/TX3
F10
GPIO72/RX3
G10
GPIO76/TX4
D9
GPIO77/RX4
M7
GPIO94/TX5
P6
GPIO95/RX5
N6
GPIO62
A12
GPIO63
A13
GPIO64
C12
GPIO65
B12
GPIO66
C11
GPIO73
B10
GPIO74
C10
GPIO75
B11
GPIO81/TX2
F6
GPIO82/RX2
F5
GPIO88/SCK0
K6
GPIO89/SDA0
L7
DDCR_CK/GPIO59
C16
DDCR_DA/GPIO58
B16
VID0/GPIO55
D5
VID1/GPIO56
D4
LED0/GPIO32
H4
LED1/GPIO33
H5
WOL/GPIO57
L5
LVSYNC/VBY0M
AB36
LHSYNC/VBY0P
AB35
LDE/VBY1M
AC36
LCK/VBY1P
AC37
B0M/VBY2M
AD37
B0P/VBY2P
AD36
B1M/VBY3M
AD35
B1P/VBY3P
AE36
B2M/VBY4M
AF36
B2P/VBY4P
AF37
BCKM/VBY5M
AF35
BCKP/VBY5P
AG37
B3M/VBY6M
AG35
B3P/VBY6P
AH36
B4M/VBY7M
AH35
B4M/VBY7P
AJ36
A0M/VBY_OSD_0M
AJ35
A0P/VBY_OSD_0P
AK37
A1M/VBY_OSD_1M
AK36
A1P/VBY_OSD_1P
AK35
A2M/VBY_OSD_2M
AL35
A2P/VBY_OSD_2P
AM36
ACKM/VBY_OSD_3M
AM37
ACKP/VBY_OSD_3P
AM35
A3M/LOCKN
AJ33
A3P/HTPDN
AJ34
A4M/OSD_LOCKN
AJ32
A4P/OSD_HTPDN
AJ31
GPIO_PM0/GPIO13
AD5
GPIO_PM2/GPIO15
AD6
GPIO_PM3/GPIO16
AE2
GPIO_PM4/GPIO17
AE3
GPIO_PM7/GPIO20
AF4
GPIO_PM8/GPIO21
AG5
GPIO_PM9/GPIO22
AG6
GPIO_PM13/GPIO26
AH6
GPIO_PM17/GPIO30
AJ5
GPIO_PM18/GPIO31
AJ4
GPIO_PM1/GPIO14
K5
GPIO_PM5/GPIO18
L6
GPIO_PM11/GPIO24
M5
GPIO_PM12/GPIO25
M6
AV_LNK/GPIO9
L4
TEST
J15
GPIO112/SPI1_DI
A18
GPIO111/SPI1_CK
B18
GPIO114/SPI2_DI
C17
GPIO113/SPI2_CK
B17
GPIO110/VSYNC_LIKE
C18
GPIO115/DIM0
D18
GPIO116/DIM1
E18
GPIO117/DIM2
F18
GPIO118/DIM3
E17
IC100
LGE5331(LM15U)
PCMDATA[0]/GPIO152
AT13
PCMDATA[1]/GPIO153
AT9
PCMDATA[2]/GPIO154
AR13
PCMDATA[3]/GPIO124
AT17
PCMDATA[4]/GPIO125
AR16
PCMDATA[5]/GPIO126
AT16
PCMDATA[6]/GPIO127
AR21
PCMDATA[7]/GPIO128
AT18
PCMADR[0]/GPIO151
AU10
PCMADR[1]/GPIO150
AT14
PCMADR[2]/GPIO148
AR10
PCMADR[3]/GPIO147
AT19
PCMADR[4]/GPIO146
AR18
PCMADR[5]/GPIO144
AU19
PCMADR[6]/GPIO143
AT11
PCMADR[7]/GPIO142
AT12
PCMADR[8]/GPIO136
AT20
PCMADR[9]/GPIO134
AU14
PCMADR[10]/GPIO130
AU16
PCMADR[11]/GPIO132
AR20
PCMADR[12]/GPIO141
AR12
PCMADR[13]/GPIO137
AU13
PCMADR[14]/GPIO138
AR19
PCMIRQA/GPIO140
AU20
PCMOEN/GPIO131
AT21
PCMIORD/GPIO133
AR15
PCMCEN/GPIO129
AU17
PCMWEN/GPIO139
AR11
PCMCD/GPIO156
AR17
PCMRST/GPIO155
AU11
PCMREG/GPIO149
AR14
PCMIOWR/GPIO135
AT15
PCMWAIT/GPIO145
AT10
NAND_ALE/GPIO194
D7
NAND_WPZ/GPIO193
F7
NAND_CEZ/EMMC_CMD/GPIO188
G7
NAND_CLE/GPIO190
E6
NAND_REZ/EMMC_CLK/GPIO191
F8
NAND_WEZ/GPIO192
E7
NAND_RBZ/EMMC_RSTN/GPIO195
E8
NAND_CEZ1/GPIO189
D6
NAND_DQS/GPIO196
D8
NAND_AD0/EMMC_D6/GPIO226
A6
NAND_AD1/EMMC_D7/GPIO225
C6
NAND_AD2/EMMC_D2/GPIO224
A7
NAND_AD3/EMMC_D1/GPIO223
B7
NAND_AD4/EMMC_D0/GPIO199
C7
NAND_AD5/EMMC_D3/GPIO198
B8
NAND_AD6/EMMC_D4/GPIO197
C8
NAND_AD7/EMMC_D5/GPIO227
B9
PCM2_CD/GPIO123
AM4
PCM2_CE/GPIO119
AP4
PCM2_IRQA/GPIO120
AL5
PCM2_WAIT/GPIO121
AN4
PCM2_RESET/GPIO122
AL4
TS1DATA_[0]/GPIO187
AL6
TS1DATA_[1]/GPIO186
AM6
TS1DATA_[2]/GPIO185
AP8
TS1DATA_[3]/GPIO184
AN7
TS1DATA_[4]/GPIO183
AM5
TS1DATA_[5]/GPIO182
AM7
TS1DATA_[6]/GPIO181
AN5
TS1DATA_[7]/GPIO180
AN6
TS1CLK/GPIO177
AL7
TS1VALID/GPIO179
AP5
TS1SYNC/GPIO178
AP6
TS0DATA_[0]/GPIO166
AP10
TS0DATA_[1]/GPIO167
AN10
TS0DATA_[2]/GPIO168
AM8
TS0DATA_[3]/GPIO169
AM10
TS0DATA_[4]/GPIO170
AM11
TS0DATA_[5]/GPIO171
AM12
TS0DATA_[6]/GPIO172
AN8
TS0DATA_[7]/GPIO173
AM9
TS0CLK/GPIO176
AN11
TS0VALID/GPIO174
AN9
TS0SYNC/GPIO175
AP9
TS2DATA_[0]/GPIO200
AM14
TS2DATA_[1]/GPIO204
AP15
TS2DATA_[2]/GPIO205
AN12
TS2DATA_[3]/GPIO206
AN15
TS2DATA_[4]/GPIO207
AN14
TS2DATA_[5]/GPIO208
AM16
TS2DATA_[6]/GPIO209
AN13
TS2DATA_[7]/VSENSE/GPIO210
AM15
TS2CLK/GPIO203
AP13
TS2VALID/GPIO201
AP12
TS2SYNC/GPIO202
AM13
TS3DATA_[0]/GPIO211
AM18
TS3DATA_[1]/GPIO212
AP16
TS3DATA_[2]/GPIO213
AM19
TS3DATA_[3]/GPIO214
AN18
TS3DATA_[4]/GPIO215
AP19
TS3DATA_[5]/GPIO216
AN20
TS3DATA_[6]/GPIO217
AP18
TS3DATA_[7]/GPIO218
AN19
TS3CLK/GPIO221
AN17
TS3VALID/GPIO219
AM17
TS3SYNC/GPIO220
AN16
VIFP
AP1
VIFM
AP2
SIFP
AN2
SIFM
AN1
IF_AGC
AP3
TGPIO0/GPIO162
AR2
TGPIO1/GPIO163
AM2
TGPIO2/GPIO164
AK5
TGPIO3/GPIO165
AK6
URSA_RESET_SoC
T2
UHD
NVRAM
4_Division
RS232C_Debug
11
T ATSC
11
Mstart Debug
High
ANALOG SIF
Default
DVB
I2C PULL UP
BIT6
BR/PH
OLEDLCD
I2C for tuner&LNB
FOR HDMI2.0
BR
Division
BIT11
I2C for LCD Module
01
Display
CN/HK
ISDB INT
T2/C PIP
11
T2/C/S2
Default
CHIP CONFIG
00
20140701 version
JP
LM15U HW Option
NON_EXTERNAL
BIT5
Close to MSTAR
TW/COL
LM15U only
ISDB PIPDefault
Low
Model
I2C for tuner
JP
DDTS_Debug
High
T2/C PIP
I2C for Micom
KR
Value Mode Description
4’b1000 SB51_ExtSPI 51 boot from SPI
4’b1001 HEMCU_ExtSPI ARM boot from SPI
4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC
4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND
4’b1100 DBUS for test only
4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication
4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication
4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication;
00
T2/C/S2 PIP
CN/HKBIT(2/3)
LM15U+URSA
BIT10
URSA11
BIT(0/1)
EXTERNAL
Write Protection
- Low : Normal Operation
- High : Write Protection
BIT9
EU/CIS
10
DTV_IF
EU
ISDB EXT
North.AM
CI+
Sri Lanka
01
Support
NONE
JP
AJJA
I2C for URSA9 (URSA9 Only)
GPIO PULL UP
KR
ATSC NIM+T2
T2/C/S2
10
TW/COL
Resolution
01
BIT(7/8)
AJJA
ATSC
A0’h
T/C
NON_Division
CHIP_CONFIG[3:0]
{LED1, SPI_DI,LED0, PWM_PM}
T/C
I2C for NAVRAM
URSA11-P
Close to MSTAR
FHD
BIT4
T2/C
10
I2C for Main Amp / Woofer AMP
EXTERNAL EDID
URSA9
00
Low
V-BY-ONE
B/E(FRC)
ATSC+T2
US
LM15U+URSA9
ATSC PIP
OLED LM15U_ONLY
BIT12
BIT13
New CI PathOld CI Path
VID
VID Enable VID Disable
Reserved
Copyright ⓒ 2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
11/05/31
WOL_CTL
C271
10uF
10V
C232
0.1uF
C221
0.1uF
C239
0.1uF
AVDD_AU33
+3.3V_NORMAL
+3.3V_NORMAL
C235
0.1uF
C216
4.7uF
+1.1V_VDDC
+3.5V_ST
C264
10uF
10V
AVDDL_MOD11
C252
0.1uF
DVDD_DDR11
JP202
C320
0.1uF
OPT
C243
0.1uF
R2020
DVDD_DDR11
C306
0.1uF
+1.5V_DDR
+1.1V_VDDC_CPU
JP204
AVDD_AU33
R201
1K
OPT
C310
0.1uF
C222
10uF
10V
C219
0.1uF
JP205
C244 0.1uF
C277
0.1uF
JP203
+1.1V_VDDC
VDDC15_M0
C265
0.1uF
AVDD33
AVDD_PLL33
VDDC15_M1
C200
1uF
25V
AVDD5V_MHL
C238 0.1uF
C261
10uF
10V
AVDD33
5V_HDMI_3
C275
0.1uF
C236
10uF
10V
DVDD_NODIE
R200
10
C217
10uF
10V
C256
10uF
10V
AVDDL_MOD11
C202
10uF
10V
AVDD_PLL33
C250
0.1uF
C285
0.1uF
C201
10uF
10V
C220
4.7uF
C302
10uF
10V
VDDC15_M0
VDDC15_M0
C304
0.1uF
AVDDL_HDMI11
C274
0.1uF
VDDP_NAND
+1.1V_VDDC_CPU
C286
0.1uF
AVDD5V_MHL
+1.1V_VDDC
DVDD_DDR11
C203 0.1uF C224 0.1uF
+3.3V_NORMAL
C263
10uF
10V
C225 0.1uF
C249
0.1uF
AVDD33
+1.8V
VDDC15_M1
C228
10uF
10V
C204 0.1uF
C251
0.1uF
VDDC15_M1
C324
0.1uF
OPT
VDDP_NAND
+3.5V_WOL
C253
0.1uF
OPT
IC200
AP2151WG-7
3
FLG
2
GND
4
EN
1
OUT
5
IN
L227
PZ1608U121-2R0TF
L200
PZ1608U121-2R0TF
L201
PZ1608U121-2R0TF
L202
PZ1608U121-2R0TF
L203
PZ1608U121-2R0TF
L204
PZ1608U121-2R0TF
L212
PZ1608U121-2R0TF
L215
PZ1608U121-2R0TF
L222
PZ1608U121-2R0TF
OPT
L223
PZ1608U121-2R0TF
L226
PZ1608U121-2R0TF
AVDD_3P3
C206
1uF
10V
C205
0.1uF
16V
IC201
AP2121N-3.3TRE1
1
GND
2
VOUT
3
VIN
AVDD_3P3
VDDC15_M1
VDDC15_M0
VDDC15_M0
+3.5V_WOL
AVDD_3P3
C316
10uF
10V
OPT
C226 0.1uF
C317
10uF
10V
C287 0.1uF
C323
10uF
10V
C276
0.1uF
C278
0.1uF
C207
10uF
10V
C209 0.1uF
C218 0.1uF
C208
10uF
10V
C223
10uF
10V
C2270.47uF
C2290.47uF
C2300.47uF
C2310.47uF
C2340.47uF
C2400.47uF
C322
10uF
10V
C314
0.47uF
OPT
C315
0.47uF
OPT
C311
0.47uF
C241
0.47uF
L205
PZ1608U121-2R0TF
C210
0.47uF
AVDDL_HDMI11
R203
10K
OPT
IC100
LGE5331(LM15U)
VDDC_1
L10
VDDC_2
L11
VDDC_3
L12
VDDC_4
L13
VDDC_5
L14
VDDC_6
M10
VDDC_7
M11
VDDC_8
M12
VDDC_9
M13
VDDC_10
M14
VDDC_11
N10
VDDC_12
N11
VDDC_13
N12
VDDC_14
N13
VDDC_15
V12
VDDC_16
V13
VDDC_17
V14
VDDC_18
W12
VDDC_19
W13
VDDC_20
W14
VDDC_21
Y12
VDDC_22
Y13
VDDC_23
Y14
VDDC_24
AF18
VDDC_25
AF19
VDDC_26
AF20
VDDC_27
AG18
VDDC_28
AG19
VDDC_29
AG20
VDDC_30
AG21
VDDC_31
AG22
VDDC_32
AH18
VDDC_33
AH19
VDDC_34
AH20
VDDC_35
AH21
VDDC_36
AH22
AVDDL_PREDRV_1
W23
AVDDL_PREDRV_2
Y23
AVDDL_MOD_1
W24
AVDDL_MOD_2
Y24
AVDD15_MOD_1
Y25
AVDD15_MOD_2
Y26
AVDDL_USB3_1
AF14
AVDDL_USB3_2
AF15
VDDC_CPU_1
AA21
VDDC_CPU_2
AA27
VDDC_CPU_3
AA28
VDDC_CPU_4
AA29
VDDC_CPU_5
AB21
VDDC_CPU_6
AB22
VDDC_CPU_7
AB23
VDDC_CPU_8
AB24
VDDC_CPU_9
AB25
VDDC_CPU_10
AB26
VDDC_CPU_11
AB27
VDDC_CPU_12
AB28
VDDC_CPU_13
AB29
VDDC_CPU_14
AC21
VDDC_CPU_15
AC22
VDDC_CPU_16
AC23
VDDC_CPU_17
AC24
VDDC_CPU_18
AC25
VDDC_CPU_19
AC26
VDDC_CPU_20
AC27
VDDC_CPU_21
AC28
VDDC_CPU_22
AC29
VDDC_CPU_23
AC30
VDDC_CPU_24
AD27
VDDC_CPU_25
AD28
VDDC_CPU_26
AD29
VDDC_CPU_27
AD30
DVDD_NODIE
N14
DVDD_DDR_1
R22
DVDD_DDR_2
R24
DVDD_DDR_C
AF24
DVDD_DDR_RX_A
P22
DVDD_DDR_RX_B
T24
DVDD_DDR_RX_C
AF25
AVDD_NODIE
V7
AVDDL_MHL3_1
T13
AVDDL_MHL3_2
T14
AVDD3P3_MHL3_1
L8
AVDD3P3_MHL3_2
M8
AVDD3P3_ETH
W7
AVDD3P3_DADC_1
AD7
AVDD3P3_DADC_2
AD8
AVDD3P3_ADC_1
Y7
AVDD3P3_ADC_2
Y8
AVDD3P3_USB_1
AL10
AVDD3P3_USB_2
AL11
AVDD3P3_USB3_1
AH14
AVDD3P3_USB3_2
AH15
AVDD_AU33
AH7
AVDD_EAR33
AG7
AVDD3P3_DMPLL
AL12
VDDP_1
AK15
VDDP_2
AL15
AVDD_MOD_1
W26
AVDD_MOD_2
Y27
AVDD_LPLL_1
Y28
AVDD_LPLL_2
Y29
AVDD_PLL_A
U18
AVDD_PLL_B
U19
AVDD_PLL_C
AL18
VDDP_3318_A_CAP
L17
VDDP_3318_C_CAP
L15
VDDP_3318_A
G8
VDDP_3318_C
H7
AVDD_DDR_A_CMD_1
M20
AVDD_DDR_A_CMD_2
M21
AVDD_DDR_A_MCK
N21
AVDD_DDR_A_DAT_1
M22
AVDD_DDR_A_DAT_2
N22
AVDD_DDR_A_DAT_3
N23
AVDD_DDR_A_DAT_4
N24
AVDD_DDR_B_CMD_1
N25
AVDD_DDR_B_CMD_2
N26
AVDD_DDR_B_MCK
P25
AVDD_DDR_B_DAT_1
R25
AVDD_DDR_B_DAT_3
T25
AVDD_DDR_B_DAT_4
U25
AVDD_DDR_B_DAT_2
R26
AVDD_DDR_C_CMD_1
AE25
AVDD_DDR_C_CMD_2
AE26
AVDD_DDR_C_MCK
AF26
AVDD_DDR_C_DAT_1
AE22
AVDD_DDR_C_DAT_2
AE23
AVDD_DDR_C_DAT_3
AE24
AVDD_DDR_C_DAT_4
AF22
AVDD_DDR_LDO_A
N20
AVDD_DDR_LDO_B
P24
AVDD_DDR_LDO_C
AD25
AVDD_HDMI_5V_PA
U7
AVDD_HDMI_5V_PC
P7
GND_EFUSE
P8
AVDD_DDR_VBP_A_1
L20
AVDD_DDR_VBP_A_2
L21
AVDD_DDR_VBN_A_1
M24
AVDD_DDR_VBN_A_2
M25
AVDD_DDR_VBP_B_1
U27
AVDD_DDR_VBP_B_2
V27
AVDD_DDR_VBN_B_1
U26
AVDD_DDR_VBN_B_2
V26
AVDD_DDR_VBP_C_1
AD21
AVDD_DDR_VBP_C_2
AD22
AVDD_DDR_VBN_C_1
AD23
AVDD_DDR_VBN_C_2
AD24
C211
0.47uF
C212
20pF
50V
LM15U_DDR_EMI
C213
20pF
50V
LM15U_DDR_EMI
C214
20pF
50V
LM15U_DDR_EMI
LM15U
02
2014-08-26
LM15U POWER
Close to chip side
Close to chip side
Close to chip side
Close to chip side
Close to chip side
2A
Close to chip side
Close to chip side
2A
Close to chip side
Close to chip side
4th layer
4th layer
4th layer
4th layer
4th layer
+3.3V_Bypass Cap
4th layer
+1.1V_Bypass Cap(CLOSE TO CHIP SIDE)
4th layer
GND JIG POINT
4th layer
4th layer
WOL POWER ENABLE CONTROL
1st layer
+1.5V_Bypass Cap
2A
2A
2A
2A
2A
2A
2A
Close to chip side
1st layer
1st layer
Close to chip side
Close to chip side
1st layer
Close to chip side
1st layer
2A
Copyright ⓒ 2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
THERMAL
THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2014-12-18
MAIN3_DDR 4
LM15U
M2_DDR_A8
R408
1K 1%
M2_DDR_A11
R406
240
M2_DDR_DQ11
R414
1K 1%
M0_DDR_BA0
M2_DDR_A4
M2_DDR_DQ4
C402 0.1uF
M2_DDR_DQ3
M0_DDR_DQ7
M2_DDR_DQS_N3
M2_DDR_A4
C400 0.1uF
VDDC15_M1
M1_DDR_DQ15
M2_DDR_A13
M2_DDR_A9
M2_DDR_A10
M0_DDR_DQ26
M2_DDR_A6
R403
240
M2_DDR_DQ23
M0_DDR_A0
M2_DDR_DQ14
M1_DDR_DQ0
M2_DDR_CKE
C401 0.1uF
M2_DDR_DM0
M0_DDR_DQ25
M2_DDR_RESET_N
M2_D_CLK
M0_DDR_A7
M0_DDR_A1
M2_DDR_A2
M1_DDR_DQ29
M2_DDR_A15
VDDC15_M0
VDDC15_M1
M0_DDR_DQ10
VDDC15_M0
M0_DDR_A11
M2_DDR_DQ30
M0_DDR_VREFDQ
M2_DDR_DM1
M2_DDR_DQ30
M0_DDR_DQS2
M1_DDR_DM1
M0_DDR_A0
VDDC15_M1
M2_DDR_CS2
M1_DDR_DQ9
M2_DDR_DQS3
C412 0.1uF
M2_DDR_DQ0
M1_DDR_DQS_N0
M0_DDR_DQ30
M0_DDR_DQ22
M0_DDR_DQS1
M2_DDR_DQ24
M2_DDR_A3
M2_DDR_CASN
M0_DDR_WEN
M0_DDR_DQ14
M0_DDR_WEN
M0_DDR_DQS3
M2_DDR_A2
M2_DDR_RASN
M0_DDR_DM1
M2_DDR_DQ12
M0_DDR_A12
M0_DDR_VREFDQ
VDDC15_M0
M0_DDR_A7
M2_DDR_A14
M2_DDR_BA2
M0_DDR_DQ0
VDDC15_M0
M1_DDR_A7
M0_DDR_A14
M1_DDR_DQ19
M1_DDR_DQ17
M0_DDR_DQS3
M2_DDR_DM0
M2_DDR_DQS0
M1_DDR_A7
M2_DDR_A7
M1_DDR_A9
M0_DDR_RASN
M0_DDR_DQS_N1
M1_DDR_DM3
M0_DDR_BA0
VDDC15_M1
M2_DDR_DQ29
M0_DDR_DQ21
M1_DDR_DQS_N3
VDDC15_M1
M1_DDR_DQS2
M0_DDR_DQ17
M0_DDR_DQS0
M1_DDR_DQS3
M1_DDR_DQ11
M2_DDR_DQ3
M0_DDR_A4
M0_DDR_DQ24
C506 0.1uF
VDDC15_M0
R432
1K 1%
M1_DDR_A13
M1_DDR_DQ30
M1_DDR_A1
H5TQ4G63AFR-RDC
IC406
Hynix_DDR3_4Gb_29n
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M2_DDR_A9
M1_DDR_A0
M1_DDR_DQ13
M1_DDR_DQ2
M2_DDR_A12
M1_DDR_ODT
M0_DDR_DQ25
M1_D_CLK
M1_DDR_BA2
M2_D_CLKN
M2_DDR_A0
M1_DDR_DQ14
M0_DDR_CASN
M0_DDR_CKE
C503
0.1uF
M1_DDR_DQS_N2
M0_DDR_A4
M1_DDR_RESET_N_1
M0_DDR_A10
C504 0.1uF
M2_DDR_DQS_N1
M1_DDR_DQ2
C410
0.1uF
M0_DDR_RESET_N
M2_DDR_DQ29
M1_DDR_BA0
M0_DDR_BA2
M0_DDR_DQ28
M1_DDR_CKE
M0_DDR_A11
M2_DDR_RESET_N
M2_DDR_BA1
M1_DDR_ODT
M1_DDR_DQ16
M1_DDR_A15
M2_DDR_DQ27
C413 0.1uF
M1_DDR_RESET_N
M0_DDR_DQ29
M1_DDR_DQ22
M2_DDR_A8
M2_DDR_DQ25
M1_DDR_A8
M0_DDR_DQ5
M0_DDR_ODT
M2_DDR_BA1
C415 0.1uF
M1_DDR_DQ13
M1_DDR_DM3
M0_DDR_DQ4
M0_D_CLKN
M2_DDR_A11
M2_D_CLK
M1_DDR_DQ18
M1_DDR_DM2
M0_DDR_DQ19
M2_DDR_A3
C444 0.1uF
M1_DDR_A3
M1_D_CLK
M0_DDR_DQ4
M0_DDR_DQ30
M2_DDR_BA0
M2_DDR_DQ28
M1_DDR_A1
M0_DDR_DM0
R411
1K 1%
M2_DDR_DQ7
M1_D_CLKN
M1_DDR_A3
R435
10K
M0_DDR_ODT
M0_DDR_A15
M2_DDR_ODT
M2_DDR_A12
M1_DDR_DQS1
M1_DDR_A0
M0_DDR_DQS0
M2_DDR_A1
M1_DDR_A0
M1_DDR_DQ24
R434
1K
M0_DDR_DQ26
M0_1_DDR_VREFDQ
M2_DDR_DQ1
M0_DDR_DQS_N3
VDDC15_M0
M1_DDR_VREFDQ
C490
0.1uF
Q400
MMBT3904(NXP)
NXP_DDR_RES0_TR
E
B
C
C440
0.1uF
R416
1K 1%
M2_DDR_A7
M1_DDR_BA0
M0_DDR_DQ10
M0_DDR_DQ1
M2_DDR_DQS1
M1_DDR_DQ19
M1_DDR_DQ7
M0_DDR_CKE
M0_DDR_A8
M2_DDR_A13
M2_DDR_A14
M0_DDR_A5
M1_DDR_A12
H5TQ4G63AFR-RDC
IC405
Hynix_DDR3_4Gb_29n
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M1_DDR_A13
M1_DDR_BA2
M0_DDR_RESET_N_1
M1_DDR_DQ18
M1_DDR_DQ25
M2_DDR_DQS2
M2_DDR_A1
M1_DDR_DQ27
M0_DDR_DM0
M0_DDR_DQS_N2
M2_DDR_A5
M1_D_CLKN
H5TQ4G63AFR-RDC
IC400
Hynix_DDR3_4Gb_29n
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M1_DDR_DQS0
M0_DDR_RESET_N
M1_DDR_DQ20
M2_DDR_DQ9
M2_DDR_DQ17
M1_DDR_DQ28
M0_DDR_DQ18
M0_DDR_A9
M1_DDR_A15
H5TQ4G63AFR-RDC
IC401
Hynix_DDR3_4Gb_29n
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M1_DDR_A15
M1_DDR_RESET_N
M0_DDR_RESET_N
M1_DDR_BA0
M2_DDR_A13
M2_DDR_DM1
C491
0.1uF
M0_DDR_DQS_N0
M0_DDR_A13
M2_DDR_DQ28
M1_DDR_A2
H5TQ4G63AFR-RDC
IC403
Hynix_DDR3_4Gb_29n
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M1_DDR_A6
M0_DDR_DQS2
M1_DDR_DQ26
M2_DDR_A11
M2_DDR_DQ0
M1_DDR_WEN
M1_D_CLKN
M1_DDR_DM0
VDDC15_M0
H5TQ4G63AFR-RDC
IC404
Hynix_DDR3_4Gb_29n
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M1_DDR_A5
Q401
MMBT3904(NXP)
NXP_DDR_RES1_TR
E
B
C
M1_DDR_DQ7
M0_DDR_RASN
M2_DDR_DQ2
M1_DDR_DQ21
VDDC15_M0
M1_DDR_BA1
C445 0.1uF
M1_DDR_A14
M1_DDR_RESET_N_1
R426
1K 1%
M1_DDR_A2
M2_DDR_CS1
M2_DDR_ODT
M1_DDR_DQ1
M0_DDR_DQ7
M0_DDR_DQ9
C446 0.1uF
M1_DDR_DQ0
M2_DDR_RESET_N_1
M1_DDR_A9
M0_DDR_DQ3
R436
1K
M2_DDR_DQS_N2
M1_DDR_DQS3
C479
0.1uF
M0_DDR_A5
C475 0.1uF
M1_DDR_DQS_N1
M2_D_CLKN
M1_DDR_CASN
C470
0.1uF
R437
10K
M0_DDR_A6
M1_DDR_A1
M2_DDR_DQ15
M0_DDR_DQ2
C441
0.1uF
M1_DDR_A11
M2_DDR_DQ26
M1_DDR_DQ31
M0_DDR_DQ14
M2_DDR_RESET_N
R431
1K 1%
M2_DDR_ODT
M1_DDR_A4
M2_DDR_DQ16
VDDC15_M0
M0_DDR_DQ2
M1_DDR_DQ10
M1_DDR_CASN
M2_DDR_DM3
M1_DDR_DQ28
M2_DDR_VREFDQ
M2_DDR_DQ24
M1_DDR_DQS_N0
M2_DDR_DQ6
M0_DDR_A10
M1_DDR_DQ3
M1_DDR_WEN
M2_DDR_DQ27
M0_DDR_DQS_N0
Q402
MMBT3904(NXP)
NXP_DDR_RES2_TR
E
B
C
VDDC15_M0
M2_DDR_A4
M1_DDR_A10
M2_DDR_DQ8
M1_DDR_DQ14
M0_DDR_DQ11
M1_DDR_DQ5
M2_DDR_DQ10
M1_DDR_DQ3
M2_DDR_RESET_N_1
M1_DDR_DQ5
M1_DDR_A9
M2_DDR_DQ10
M1_DDR_DQS_N3
M2_DDR_DQ31
M1_DDR_RESET_N
M0_D_CLKN
M0_DDR_A12
M2_DDR_DQS1
M1_DDR_DM2
R438
1K
M1_DDR_DQ10
M0_DDR_DQ16
M2_DDR_DQ21
M1_DDR_RASN
M2_DDR_DQ11
M0_DDR_DQ29
M0_DDR_DQ0
M0_DDR_CKE
M2_DDR_DQ21
M1_DDR_DQ17
R439
10K
M1_DDR_DQ6
M0_DDR_A12
M2_DDR_CS2
M1_DDR_DQ12
M2_DDR_A8
M0_DDR_DQS1
M0_DDR_BA2
M0_DDR_BA1
M2_DDR_A3
M1_DDR_DQ11
R405
1K
M1_DDR_A14
M1_DDR_A5
M1_DDR_A10
M2_DDR_DQ20
M0_DDR_DQ17
M0_DDR_DQ23
M0_DDR_A2
M2_DDR_DQ18
M1_DDR_CKE
R418
1K
M0_DDR_DQ12
M1_DDR_DQ12
VDDC15_M1
M1_DDR_DQ29
M2_DDR_DQ9
M1_DDR_DQ1
M0_DDR_DQ27
M1_DDR_WEN
M0_DDR_A8
M1_1_DDR_VREFDQ
R433
1K
M0_DDR_DQ15
M1_DDR_RASN
M2_DDR_CASN
M2_DDR_DQ22
M0_DDR_RESET_N_1
M1_DDR_DQ8
M1_DDR_A4
M0_DDR_A13
M1_D_CLK
R422
1K
M0_DDR_DQ13
M0_DDR_DQ15
M2_DDR_WEN
M1_DDR_DQ30
M2_DDR_DQ19
M0_DDR_BA1
M1_DDR_DQS1
M0_DDR_DQ5
M0_DDR_A4
M1_DDR_A5
R420
1K
M0_DDR_DQ3
M0_DDR_DQ6
M2_DDR_DQ19
M1_DDR_A11
M2_DDR_DQS2
M0_DDR_DQS_N2
M1_DDR_A10
M0_DDR_A9
M0_DDR_BA2
M1_DDR_A12
R424
1K
M0_DDR_DM3
M1_DDR_A3
M2_DDR_DQS0
M1_DDR_CKE
C493 0.1uF
M1_DDR_DQ23
M0_DDR_DQ24
M0_DDR_DM1
M0_DDR_A0
M1_DDR_DQ26
R4400
OPT
M1_DDR_A11
M0_DDR_DQ8
C515
0.1uF
M1_DDR_BA1
VDDC15_M0
M0_DDR_A14
M0_DDR_A1
M0_DDR_BA0
M1_DDR_DQ6
R4410
OPT
M1_DDR_CKE
M2_DDR_A14
M1_DDR_A13
M2_DDR_A6
R425
1K 1%
M0_DDR_A3
R417
1K 1%
M0_D_CLK
M1_DDR_A14
R4420
OPT
M0_1_DDR_VREFDQ
M0_DDR_DQ20
M2_DDR_BA2
M1_DDR_RESET_N
M2_DDR_DQ8
M1_DDR_CASN
M0_DDR_DQS_N3
M1_DDR_DQ24
M0_DDR_RASN
M1_DDR_A6
R410
1K 1%
M0_D_CLK
M2_DDR_DQS_N2
C469
0.1uF
C514
0.1uF
M0_DDR_DQ8
M0_DDR_DM3
M0_DDR_DQ18
M0_DDR_CASN
M1_DDR_DQ23
C473
0.1uF
M0_DDR_DM2
M2_DDR_A5
M1_DDR_A8
M2_DDR_DQS_N3
M0_DDR_BA1
M1_DDR_A6
M2_DDR_CKE
M1_DDR_DQ31
M0_DDR_A15
M1_DDR_DQ9
M0_DDR_DQ27
M2_DDR_A2
M1_DDR_DQ8
M2_DDR_BA0
VDDC15_M0
M0_DDR_DM2
M0_DDR_DQ28
R423
56
1%
M1_DDR_DQ21
M0_DDR_RESET_N
M1_DDR_RASN
C411
0.1uF
M2_DDR_DQS_N0
M2_DDR_DQ5
M1_DDR_A2
M2_DDR_DQ18
M1_DDR_DQS_N2
M0_DDR_DQ23
M0_DDR_CKE
M0_DDR_A3
C468
0.1uF
M0_DDR_DQ22
M2_DDR_DQ26
M2_DDR_DQ13
M1_DDR_DQ22
M0_DDR_DQ1
M0_DDR_DQ21
R421
56
1%
M0_DDR_DQ31
M0_DDR_A14
M1_DDR_DM1
M0_DDR_A2
M2_DDR_DQ6
M1_DDR_DQ4
M2_DDR_DQ14
M0_DDR_DQ9
M0_DDR_A15
M0_DDR_A11
R404
240
M0_DDR_A13
M2_DDR_A9
M1_DDR_DQ16
M2_DDR_A6
M1_DDR_DQS0
M2_D_CLK
M0_DDR_DQ13
M0_DDR_A6
M2_DDR_A5
R419
240
C472
0.1uF
R407
240
C492 0.1uF
M0_D_CLKN
M1_DDR_A4
C482 0.1uF
M0_DDR_DQS_N1
VDDC15_M1
M0_DDR_DQ19
M0_DDR_A1
M2_DDR_CKE
M0_DDR_CASN
M2_DDR_CKE
M0_DDR_ODT
M1_DDR_DM0
M0_DDR_DQ20
C534
0.01uF
50V
M0_D_CLK
M0_DDR_A10
M2_DDR_WEN
M2_DDR_DQS_N1
M2_DDR_DM2
M0_DDR_CS1
M1_DDR_A7
M2_DDR_DQ20
C476 0.1uF
M0_DDR_DQ16
M2_DDR_RESET_N
M0_DDR_A3
M0_DDR_A9
M2_DDR_DQS_N0
M2_DDR_A0
M2_DDR_DQ31
M0_DDR_CS2
M1_DDR_DQ25
M2_DDR_DQ25
C480 0.1uF
M2_1_DDR_VREFDQ
M2_D_CLKN
M1_DDR_DQS_N1
M0_DDR_WEN
M2_DDR_DM2
M2_DDR_BA1
M2_DDR_BA2
M1_DDR_CS1
M1_DDR_BA2
M2_DDR_RASN
R412
56
1%
M0_DDR_DQ31
C516
0.1uF
M1_DDR_ODT
M0_DDR_A7
M2_DDR_CASN
M2_DDR_A0
M2_DDR_A12
M1_DDR_CS2
M1_DDR_DQ20
M2_D_CLK
C477
0.01uF
50V
R400
240
C517
1000pF
50V
M1_DDR_DQS2
M0_DDR_A5
M2_DDR_BA0
M2_DDR_A15
M0_DDR_CS1
M1_DDR_BA1
C502
0.1uF
M0_D_CLKN
M0_DDR_A8
M1_DDR_VREFDQ
M2_DDR_DQS3
M2_DDR_DQ2
M0_DDR_CS2
M2_DDR_DM3
R413
56
1%
VDDC15_M0
M1_DDR_DQ4
M2_DDR_DQ13
M2_1_DDR_VREFDQ
M1_DDR_CS1
M1_DDR_DQ15
M2_DDR_A1
M0_D_CLK
C519
1000pF
50V
M0_DDR_A2
M2_DDR_DQ5
M2_DDR_VREFDQ
M1_DDR_CS2
M1_DDR_A12
R415
1K 1%
M0_DDR_DQ12
M2_DDR_A10
M2_DDR_A7
C474
1000pF
50V
M1_DDR_A8
M2_DDR_DQ23
M2_DDR_DQ15
C483
1000pF
50V
M2_DDR_DQ1
R427
56
1%
R409
1K 1%
M0_DDR_DQ11
M2_DDR_CS1
M2_DDR_DQ22
C471
1000pF
50V
M2_D_CLKN
M1_D_CLK
M0_DDR_DQ6
M2_DDR_DQ12
M2_DDR_WEN
C478
1000pF
50V
M2_DDR_RASN
C497
0.01uF
50V
C518
0.1uF
M0_DDR_A6
M2_DDR_A15
M2_DDR_DQ17
M1_D_CLKN
VDDC15_M0
M2_DDR_DQ4
C505 0.1uF
M2_DDR_A10
R428
56
1%
M1_1_DDR_VREFDQ
M1_DDR_DQ27
M2_DDR_DQ7
M2_DDR_DQ16
M0_DDR_A14
M1_DDR_RASN
M2_DDR_RASN
L402
CIS21J1 21
M0_DDR_CASN
M1_DDR_A0
L400
CIS21J1 21
C456 0.1uF
M2_D_CLK
C464 0.1uF
M2_DDR_A10
M2_D_CLKN
R446
10K
1/16W
1%
M0_DDR_BA0
VDDC15_M0
C457 0.1uF
C414
10uF
25V
C454 0.1uF
C530 0.1uF
C460 0.1uF
M0_DDR_BA1
C543
0.1uF
16V
M2_DDR_A0
C455 0.1uF
C429 0.1uF
C417
10uF
25V
M1_D_CLKN
C466 0.1uF
M1_DDR_A10
C532 0.1uF
C533 0.1uF
R444
10K
1/16W
1%
C459 0.1uF
M1_DDR_BA1
M2_DDR_A2
C535
10uF
25V
M0_DDR_A8
M1_DDR_A1
C431 0.1uF
M2_DDR_A9
C437 0.1uF
DDR_VTT
R443
10K
1/16W
1%
DDR_VTT_1
C522 0.1uF
C462 0.1uF
C434 0.1uF
C546
0.1uF
16V
M1_DDR_A11
M2_DDR_BA2
L401
CIS21J1 21
M1_DDR_A13
C526 0.1uF
C427 0.1uF
C531 0.1uF
M1_DDR_A12
M0_DDR_A1
R445
10K
1/16W
1%
M0_DDR_A12
VDDC15_M1
C544
10uF
10V
M1_D_CLK
M0_DDR_ODT
M1_DDR_A15
M0_D_CLKN
M2_DDR_A8
C528 0.1uF
M2_DDR_A7
M0_DDR_A15
C523 0.1uF
C527 0.1uF
M1_DDR_ODT
M2_DDR_A12
M0_DDR_A10
M1_DDR_A9
C436 0.1uF
DDR_VTT_1
M1_DDR_A5
M1_DDR_BA2
M0_DDR_CKE
C425 0.1uF
L403
CIS21J1 21
C524 0.1uF
M1_DDR_A3
C525 0.1uF
M1_DDR_WEN
M2_DDR_A11
M2_DDR_A3
M1_DDR_A14
DDR_VTT
M2_DDR_A13
M2_DDR_A6
C545
10uF
10V
C465 0.1uF
C428 0.1uF
+3.3V_NORMAL
M0_DDR_RASN
M2_DDR_A15
M2_DDR_WEN
M1_DDR_A2
C461 0.1uF
M2_DDR_A1
M1_DDR_CKE
C521 0.1uF
M1_DDR_BA0
M2_DDR_A14
M2_DDR_BA1
+3.3V_NORMAL
C430 0.1uF
C537
10uF
10V
C520 0.1uF
M1_DDR_A8
M2_DDR_BA0
C432 0.1uF
C426 0.1uF
C433 0.1uF
M0_DDR_A6
M0_DDR_BA2
C453 0.1uF
M0_DDR_A9
M2_DDR_CASN
M2_DDR_A4
C542
10uF
25V
M0_DDR_A7
M2_DDR_ODT
M0_DDR_A11
C424 0.1uF
M0_DDR_A0
C541
10uF
25V
C463 0.1uF
M1_DDR_A4
M0_DDR_A13
C421
10uF
10V
M0_D_CLK
C435 0.1uF
M0_DDR_WEN
M1_DDR_A6
M1_DDR_CASN
M0_DDR_A2
C536
10uF
25V
C529 0.1uF
M2_DDR_A5
M0_DDR_A3
DDR_VTT
C458 0.1uF
M1_DDR_A7
M2_DDR_CKE
M0_DDR_A4
M0_DDR_A5
IC407
AP2303MPTR-G1
3
VREFEN
2
GND
4
VOUT
1
VIN
5
NC_1
6
VCNTL
7
NC_2
8
NC_3
9
[EP]
IC402
AP2303MPTR-G1
3
VREFEN
2
GND
4
VOUT
1
VIN
5
NC_1
6
VCNTL
7
NC_2
8
NC_3
9
[EP]
K4B4G1646D-BCMA
IC400-*1
SS_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B4G1646D-BCMA
IC401-*1
SS_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B4G1646D-BCMA
IC403-*1
SS_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B4G1646D-BCMA
IC405-*1
SS_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B4G1646D-BCMA
IC406-*1
SS_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B4G1646D-BCMA
IC404-*1
SS_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
AR400
56
1/16W
AR404
56
1/16W
AR407
56
1/16W
AR420
56
1/16W
AR403
56
1/16W
AR413
56
1/16W
AR408
56
1/16W
AR406
56
1/16W
AR410
56
1/16W
AR405
56
1/16W
AR417
56
1/16W
AR419
56
1/16W
AR414
56
1/16W
AR401
56
1/16W
AR418
56
1/16W
AR402
56
1/16W
AR409
56
1/16W
AR416
56
1/16W
AR415
56
1/16W
AR412
56
1/16W
AR411
56
1/16W
H5TQ4G63CFR_RDC
IC400-*2
Hynix_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC403-*2
Hynix_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC401-*2
Hynix_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC404-*2
Hynix_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC406-*2
Hynix_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC405-*2
Hynix_DDR3_4Gb_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B2G1646Q-BCMA
IC405-*3
SS_DDR3_2Gb
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B2G1646Q-BCMA
IC406-*3
SS_DDR3_2Gb
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ2G63FFR-RDC
IC405-*4
Hynix_DDR3_2Gb
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ2G63FFR-RDC
IC406-*4
Hynix_DDR3_2Gb
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
IC100
LGE5331(LM15U)
A_A0
F21
A_A1
C21
A_A2
E21
A_A3
F22
A_A4
B22
A_A5
E22
A_A6
A21
A_A7
D21
A_A8
C20
A_A9
E20
A_A10
B23
A_A11
B21
A_A12
D24
A_A13
F20
A_A14
B20
A_A15
E24
A_BA0
E23
A_BA1
C22
A_BA2
F23
A_RASZ
G26
A_CASZ
F25
A_WEZ
E25
A_ODT
F24
A_CKE
C23
A_RST
F19
A_MCLK
A24
A_MCLKZ
B24
A_CSB1
E19
A_CSB2
D19
A_DQ[0]
C27
A_DQ[1]
B26
A_DQ[2]
B28
A_DQ[3]
C25
A_DQ[4]
B29
A_DQ[5]
C24
A_DQ[6]
C28
A_DQ[7]
B25
A_DQM[0]
C26
A_DQS[0]
A27
A_DQSB[0]
B27
A_DQ[8]/DQU0
D27
A_DQ[9]/DQU1
D30
A_DQ[10]/DQU2
E26
A_DQ[11]/DQU3
D31
A_DQ[12]/DQU4
F27
A_DQ[13]/DQU5
E30
A_DQ[14]/DQU6
D26
A_DQ[15]/DQU7
E29
A_DQM[1]
E28
A_DQS[1]
D28
A_DQSB[1]
E27
A_DQ[16]/DQL0
C32
A_DQ[17]/DQL1
C30
A_DQ[18]/DQL2
B33
A_DQ[19]/DQL3
A30
A_DQ[20]/DQL4
C33
A_DQ[21]/DQL5
C29
A_DQ[22]/DQL6
A33
A_DQ[23]/DQL7
B30
A_DQM[2]
B31
A_DQS[2]
B32
A_DQSB[2]
C31
A_DQ[24]/DQU0
E33
A_DQ[25]/DQU1
C35
A_DQ[26]/DQU2
E31
A_DQ[27]/DQU3
D35
A_DQ[28]/DQU4
D33
A_DQ[29]/DQU5
D34
A_DQ[30]/DQU6
E32
A_DQ[31]/DQU7
C34
A_DQM[3]
B35
A_DQS[3]
A35
A_DQSB[3]
B34
B_A0
G33
B_A1
J36
B_A2
H34
B_A3
J32
B_A4
J35
B_A5
H33
B_A6
J37
B_A7
G36
B_A8
H37
B_A9
F35
B_A10
K35
B_A11
H35
B_A12
K34
B_A13
F36
B_A14
H36
B_A15
L33
B_BA0
K33
B_BA1
K36
B_BA2
J33
B_RASZ
M33
B_CASZ
M32
B_WEZ
K32
B_ODT
L32
B_CKE
L36
B_RST
F37
B_MCLK
M37
B_MCLKZ
L35
B_CSB1
F34
B_CSB2
E37
B_DQ[0]
R36
B_DQ[1]
N35
B_DQ[2]
R35
B_DQ[3]
N36
B_DQ[4]
T35
B_DQ[5]
M36
B_DQ[6]
T36
B_DQ[7]
M35
B_DQM[0]
P36
B_DQS[0]
R37
B_DQSB[0]
P35
B_DQ[8]/DQU0
N32
B_DQ[9]/DQU1
T34
B_DQ[10]/DQU2
N33
B_DQ[11]/DQU3
T32
B_DQ[12]/DQU4
P33
B_DQ[13]/DQU5
U33
B_DQ[14]/DQU6
N34
B_DQ[15]/DQU7
T33
B_DQM[1]
R33
B_DQS[1]
R32
B_DQSB[1]
P32
B_DQ[16]/DQL0
Y36
B_DQ[17]/DQL1
V36
B_DQ[18]/DQL2
Y35
B_DQ[19]/DQL3
V37
B_DQ[20]/DQL4
AA36
B_DQ[21]/DQL5
U36
B_DQ[22]/DQL6
AA37
B_DQ[23]/DQL7
U35
B_DQM[2]
V35
B_DQS[2]
W35
B_DQSB[2]
W36
B_DQ[24]/DQU0
W33
B_DQ[25]/DQU1
AA32
B_DQ[26]/DQU2
U32
B_DQ[27]/DQU3
AA34
B_DQ[28]/DQU4
V33
B_DQ[29]/DQU5
AA33
B_DQ[30]/DQU6
V32
B_DQ[31]/DQU7
Y32
B_DQM[3]
W32
B_DQS[3]
Y33
B_DQSB[3]
W34
C_A0
AM34
C_A1
AR35
C_A2
AP34
C_A3
AM33
C_A4
AT34
C_A5
AN33
C_A6
AU35
C_A7
AR36
C_A8
AU36
C_A9
AR37
C_A10
AT33
C_A11
AT35
C_A12
AP31
C_A13
AP35
C_A14
AT37
C_A15
AN31
C_BA0
AN32
C_BA1
AR34
C_BA2
AM32
C_RASZ
AM29
C_CASZ
AM30
C_WEZ
AN30
C_ODT
AM31
C_CKE
AR33
C_RST
AP37
C_MCLK
AU32
C_MCLKZ
AT32
C_CSB1
AN34
C_CSB2
AP36
C_DQ[0]
AR29
C_DQ[1]
AT30
C_DQ[2]
AT28
C_DQ[3]
AR31
C_DQ[4]
AT27
C_DQ[5]
AR32
C_DQ[6]
AR28
C_DQ[7]
AT31
C_DQM[0]
AR30
C_DQS[0]
AU29
C_DQSB[0]
AT29
C_DQ[8]/DQU0
AN27
C_DQ[9]/DQU1
AP25
C_DQ[10]/DQU2
AN29
C_DQ[11]/DQU3
AN24
C_DQ[12]/DQU4
AN28
C_DQ[13]/DQU5
AN25
C_DQ[14]/DQU6
AP28
C_DQ[15]/DQU7
AN26
C_DQM[1]
AM26
C_DQS[1]
AM27
C_DQSB[1]
AM28
C_DQ[16]/DQL0
AR24
C_DQ[17]/DQL1
AR26
C_DQ[18]/DQL2
AT23
C_DQ[19]/DQL3
AU26
C_DQ[20]/DQL4
AR23
C_DQ[21]/DQL5
AR27
C_DQ[22]/DQL6
AU23
C_DQ[23]/DQL7
AT26
C_DQM[2]
AT25
C_DQS[2]
AT24
C_DQSB[2]
AR25
C_DQ[24]/DQU0
AN23
C_DQ[25]/DQU1
AN21
C_DQ[26]/DQU2
AM25
C_DQ[27]/DQU3
AM21
C_DQ[28]/DQU4
AM23
C_DQ[29]/DQU5
AM22
C_DQ[30]/DQU6
AM24
C_DQ[31]/DQU7
AT22
C_DQM[3]
AR22
C_DQS[3]
AP21
C_DQSB[3]
AP22
Q400-*1
2N3904S
KEC_DDR_RES0_TR
E
B
C
Q401-*1
2N3904S
KEC_DDR_RES1_TR
E
B
C
Q402-*1
2N3904S
KEC_DDR_RES2_TR
E
B
C
+1.5V_Bypass Cap
Close to DDR Power Pin
DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
+1.5V_Bypass Cap
Close to DDR Power Pin
+1.5V_Bypass Cap
Close to DDR Power Pin
+1.5V_Bypass Cap
Close to DDR Power Pin
+1.5V_Bypass Cap
Close to DDR Power Pin
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
+1.5V_Bypass Cap
Close to DDR Power Pin
DDR3 1.5V bypass Cap - Place these caps near Memory
* DDR_VTT
Copyright ⓒ 2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
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