LG 60LM7200UA Schematic

Internal Use Only

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

LED LCD TV

SERVICE MANUAL

CHASSIS : LA22E

MODEL : 60LM7200 60LM7200-UA

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL67460446 (1209-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ....................................................................................... 4

ADJUSTMENT INSTRUCTION .............................................................. 10

EXPLODED VIEW .................................................................................. 20

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental shorts of th e cir cuitry that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exp ose d metallic par t. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This spec sheet is applied all of the 32”, 42”, 47”, 55”, 65”
LCD TV with LA22E chassis

2. Test condition

Each part is tested as below without special notice.

1) Temperature : 20 ºC ± 5 ºC

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage

- AC 110-240 V~, 50/60 Hz
* Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed
ea ch drawing and s pe cificatio n b y p art number in
accordance with BOM.

5) The receiver must be operated for about 5 minutes prior to
the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety: CE, IEC specification

- EMC: CE, IEC specification

- Wireless : WirelessHD Specification (Option)

.

4. General Specification

No Item Specication Remark

1 Receiving System 1) ATSC / NTSC-M

2 Available Channel 1) VHF : 02~13

2) UHF : 14~69

3) DTV : 02-69

4) CATV : 01~135

5) CADTV : 01~135

3 Input Voltage 1) AC 100 ~ 240V 50/60Hz

4 Market NORTH AMERICA

5 Screen Size 60 inches

6 Aspect Ratio 16:9

7 Tuning System FS

8 Module LC600EUD-FEF1 LGD

9 Operating Environment 1) Temp : 0 ~ 40 deg

2) Humidity : ~ 80 %

10 Storage Environment 1) Temp : -20 ~ 60 deg

2) Humidity : ~ 85 %

120V, 50/60Hz on the label (USA)

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Supported video resolutions

5.1. 2D mode

5.1.1. Component Video Input (Y, CB/PB, CR/PR)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1. 720*480 15.73 60.00 13.5135 SDTV ,DVD 480I

2. 720*480 15.73 59.94 13.50 SDTV ,DVD 480I

3. 720*480 31.50 60.00 27.027 SDTV 480P

4. 720*480 31.47 59.94 27.00 SDTV 480P

5. 1280*720 45.00 60.00 74.25 HDTV 720P

6. 1280*720 44.96 59.94 74.176 HDTV 720P

7. 1920*1080 33.75 60.00 74.25 HDTV 1080I

8. 1920*1080 33.72 59.94 74.176 HDTV 1080I

9. 1920*1080 67.50 60.00 148.50 HDTV 1080P

10. 1920*1080 67.432 59.94 148.352 HDTV 1080P

11. 1920*1080 27.00 24.00 74.25 HDTV 1080P

12. 1920*1080 26.97 23.94 74.176 HDTV 1080P

13. 1920*1080 33.75 30.00 74.25 HDTV 1080P

14. 1920*1080 33.71 29.97 74.176 HDTV 1080P

5.1.2. RGB Input (PC)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1 640*350 31.468 70.09 25.17 EGA X

2 720*400 31.469 70.08 28.32 DOS O

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1152*864 54.348 60.053 VESA

7 1360*768 47.712 60.015 85.50 VESA (WXGA) X

8 1920*1080 67.5 60.00 148.5 WUXGA(CEA861D) O

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.1.3. HDMI Input 1 (PC/DTV)

No Resolution H-freq(kHz) V-freq.(Hz)

PC (DVI)

1 640*350 31.468 70.09 25.17 EGA X

2 720*400 31.469 70.08 28.32 DOS O

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1152*864 54.348 60.053 VESA O

7 1280*1024 63.981 60.020 VESA(SXGA)

8 1360*768 47.712 60.015 85.50 VESA (WXGA)

9 1920*1080 67.5 60.00 148.5 HDTV 1080P

DTV

1 720*480 31.50 60.00 27.027 SDTV 480P

2 720*480 31.47 59.94 27.00 SDTV 480P

3 1280*720 45.00 60.00 74.25 HDTV 720P

4 1280*720 44.96 59.94 74.176 HDTV 720P

5 1920*1080 33.75 60.00 74.25 HDTV 1080I

6 1920*1080 33.72 59.94 74.176 HDTV 1080I

7 1920*1080 67.50 60.00 148.50 HDTV 1080P

8 1920*1080 67.432 59.94 148.352 HDTV 1080P

9 1920*1080 27.00 24.00 74.25 HDTV 1080P

10 1920*1080 26.97 23.976 74.176 HDTV 1080P

11 1920*1080 33.75 30.00 74.25 HDTV 1080P

12 1920*1080 33.71 29.97 74.176 HDTV 1080P

Pixel

clock(MHz)

Proposed Remark

WUXGA(Reduced Blanking)

O FHD only

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2. 3D mode

5.2.1. RF Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 45 60 74.25 HDTV 1080I Side by Side, Top & Bottom

2 1280*720 45 60 74.25 HDTV 720P Side by Side, Top & Bottom

5.2.2. USB Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 33.75 30.00 74.25 HDTV 1080p Side by Side, Top & Bottom,

Checkerboard, MPO (Photo)

5.2.3. RGB-PC Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 66.587 59.934 138.5 HDTV 1080p Side by Side, Top & Bottom

5.2.4. DLNA Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1920*1080 33.75 30 74.25 HDTV 1080p Side by Side, Top & Bottom,

Checker board

5.2.5. HDMI 1.3

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Remark

1 1280*720p 45.00 60.00 74.25 Side by Side , Top & Bottom

2 1920*1080i 33.75 60.00 74.25 Side by Side , Top & Bottom

3 1920*1080p 67.50 60.00 148.50 Side by Side , Top & Bottom

Checkerboard
Single Frame Sequential

4 1920*1080p 27.00 24.000 74.25 Side by Side , Top & Bottom

Checkerboard

5 1920*1080p 33.75 30.000 74.25 Side by Side, Top & Bottom

Checkerboard

Only for training and service purposes

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.6. HDMI 1.4a

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1280*720p 90.00 60.00 148.50 Mandatory Frame Packing,

2 1280*720p 45.00 60.00 74.25 Mandatory Top & Bottom

3 1920*1080i 33.75 60.00 74.25 Mandatory Side by Side (Half)

4 1920*1080p 54.00 24.000 148.50 Mandatory Frame Packing,

5 1920*1080p 27.00 24.000 74.25 Mandatory Top & Bottom

6 1280*720p 45.00 60.00 74.25 Primary Side by Side (Half)

7 1920*1080i 67.50 60.00 148.50 Primary Frame Packing

8 1920*1080p 67.50 60.00 148.50 Primary Top & Bottom

9 1920*1080p 27.00 24.000 74.25 Primary Side by Side (Half)

10 1920*1080p 67.50 30.000 148.50 Primary Frame Packing,

11 1920*1080p 33.75 30.000 74.25 Primary Top & Bottom

12 1920*1080i 33.75 60.00 74.25 Secondary Top & Bottom

13 1920*1080p 67.50 60.00 148.50 Secondary Side by Side (Half)

14 1920*1080p 33.75 30.000 74.25 Secondary Side by Side (Half)

15 720*480p 63.00 60.00 54.054 Secondary (16:9) Frame Packing,

16 720*480p 31.50 60.00 27.027 Secondary (16:9) Top & Bottom

17 720*480p 31.50 60.00 27.027 Secondary (16:9) Side by Side (Half)

18 720*480p 63.00 60.00 54.054 Secondary (4:3) Frame Packing,

19 720*480p 31.50 60.00 27.027 Secondary (4:3) Top & Bottom

20 720*480p 31.50 60.00 27.027 Secondary (4:3) Side by Side (Half)

21 640*480p 63.00 60.00 50.40 Secondary Frame Packing,

22 640*480p 31.50 60.00 25.20 Secondary Top & Bottom

23 640*480p 31.50 60.00 25.20 Secondary Side by Side (Half)

24 1280*720p 90.00 60.00 148.50 Line Alternative

25 1280*720p 45.00 60.00 148.50 Side by Side (Full)

26 1920*1080i 67.50 60.00 148.50 Field Alternative

27 1920*1080i 33.75 60.00 148.50 Side by Side (Full)

28 1920*1080p 54.00 24.000 148.50 Line Alternative

29 1920*1080p 27.00 24.000 148.50 Side by Side (Full)

30 1920*1080p 67.50 30.000 148.50 Line Alternative

31 1920*1080p 33.75 30.000 148.50 Side by Side (Full)

32 720*480p 63.00 60.00 54.054 16:9 Line Alternative

33 720*480p 31.50 60.00 54.054 16:9 Side by Side (Full)

34 720*480p 63.00 60.00 54.054 4:3 Line Alternative

35 720*480p 31.50 60.00 54.054 4:3 Side by Side (Full)

36 640*480p 63.00 60.00 50.40 Line Alternative

37 640*480p 31.50 60.00 50.40 Side by Side (Full)

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.3. 2D to 3D Mode

R

L

R

L

- Supports this function in all mode.

5.4. Remark: 3D Input mode

No. Side by Side Top & Bottom Checkerboard Single Frame Sequential Frame Packing

1

Only for training and service purposes

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet applies to LA22E Chassis applied LCD TV all
models manufactured in TV factory.

2. Specification

(1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation

transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of

25 ±5 °C of temperature and 65±10% of relative humidity if

there is no specific designation.
(4) The input voltage of the receiver must keep 100~240V,

50/60Hz.
(5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15 °C
In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours

In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above
15°C for 3 hours.

[Caution]
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong.
Digital pattern 13ch and/or Cross hatch pattern 09ch), there
can some afterimage in the black level area

4. MAIN PCBA Adjustments

4.1. ADC Calibration

- An ADC calibration is not necessary because MAIN SoC
(LGE35230) is already calibrated from IC Maker

- If it needs to adjust manually, refer to appendix.

4.2. MAC Address, ESN Key and Widevine
Key download

4.2.1. Equipment & Condition

1) Play file: keydownload.exe

4.2.2. Communication Port connection

1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

4.2.3. Download process

1) Select the download items.

2) Mode check: Online Only

3) Check the test process

- US, C anada m odels : DETEC T -> M AC_ WR IT E ->
WIDEVINE_WRITE

- Korea, Mexico m odels: DET ECT -> MAC_WRI TE ->
WIDEVINE_WRITE

4) Play : START

5) Check of result: Ready, Test, OK or NG

4.2.4. Communication Port connection

1) Connect: PCBA Jig -> RS-232C Port == PC -> RS-232C

Port

3. Adjustment items

3.1. Main PCBA Adjustments

(1) ADC adjustment: Component 480i, 1080p / RGB-PC 1080p
(2) EDID downloads for HDMI and RGB-PC

3.2. Final assembly adjustment

(1) White Balance adjustment
(2) RS-232C functionality check
(3) Factory Option setting per destination
(4) Shipment mode setting (IN-STOP)
(5) GND and HI-POT test

3.3. Appendix

(1) Tool option menu, USB Download (S/W Update, Option and

Service only)
(2) Manual adjustment for ADC calibration and White balance.
(3) Shipment conditions, Channel pre-set

Only for training and service purposes

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.2.5. Download

1) US, Canada, Mexico mo del s (11Y LCD TV + MAC +
Widevine + ESN Key)

2) Korea and Philippine models (11Y LCD TV + MAC +
Widevine Only)

4.3. LAN PORT INSPECTION(PING TEST)

4.3.1. Equipment setting

1) Play the LAN Port Test PROGRAM.

2) Input IP set up for an inspection to Test
Program.

*IP Number : 12.12.2.2.

4.3.2. LAN PORT inspection (PING TEST)

1) Play the LAN Port Test Program.

2) connect each other LAN Port Jack.

3) Play Test (F9) button and confirm OK Message.

4) remove LAN CABLE

4.2.6. Inspection

- In INSTART menu, check these keys.

Only for training and service purposes

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.4. EDID Download

4.4.1. Overview

- It is a VESA regulation. A PC or a MNT will display an optimal

resolution through information sharing without any necessity
of user input. It is a realization of “Plug and Play”.

4.4.2. Equipment

(1) Since EDID data is embedded, EDID download JIG, HDMI

cable and D-sub cable are not need.

(2) Adjust by using remote controller.

4.4.3. Download method

(1) Press Adj. key on the Adj. R/C,
(2) Select EDID D/L menu.
(3) By pressing Enter key, EDID download will begin
(4) If Download is successful, OK is display, but If Download is

failure, NG is displayed.

(5) If Download is failure, Re-try downloads.

※Caution: When EDID Download, must remove RGB/HDMI

Cable.

4.4.4. EDID DATA

4.4.4.1. 2D PCM(US) _ XvYcc : 0n

ⓔ Checksum(LG TV): Changeable by total EDID data.

ⓔ1 ⓔ2 ⓔ3

HDMI1 43 F2 X

HDMI2 43 E2 X

HDMI3 43 D2 X

HDMI4 43 C2 X

RGB X X 5C

ⓕ Vendor Specific(HDMI)

INPUT MODEL NAME(HEX)

HDMI1 67 03 0C 00 10 00 80 2D

HDMI2 67 03 0C 00 20 00 80 2D

HDMI3 67 03 0C 00 30 00 80 2D

HDMI4 67 03 0C 00 40 00 80 2D

4.4.4.2. 3D PCM(US) _ XvYcc : 0n

▪Reference

- HDMI1 ~ HDMI4 / RGB

- In the data of EDID, bellows may be different by S/W or Input

mode.

ⓐ Product ID

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ -> ‘01’
Year : ‘2012’ -> ‘16’
ⓓ Model Name(Hex): LGTV

Chassis MODEL NAME(HEX)

LA22E

00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓐ Product ID

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ -> ‘01’
Year : ‘2012’ -> ‘16’
ⓓ Model Name(Hex): LGTV

Chassis MODEL NAME(HEX)

LA22E

ⓔ Checksum(LG TV): Changeable by total EDID data.

HDMI1 43 64 X

HDMI2 43 54 X

HDMI3 43 44 X

HDMI4 43 34 X

RGB X X 5C

00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ1 ⓔ2 ⓔ3

Only for training and service purposes

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ⓕ Vendor Specific(HDMI)

INPUT MODEL NAME(HEX)

HDMI1 78 03 0C 00 10 00 80 2D 20 C0 0E 01 4F 00 FE

08 10 06 10 18 10 28 10 38 10

HDMI2 78 03 0C 00 20 00 80 2D 20 C0 0E 01 4F 00 FE

08 10 06 10 18 10 28 10 38 10

HDMI3 78 03 0C 00 30 00 80 2D 20 C0 0E 01 4F 00 FE

08 10 06 10 18 10 28 10 38 10

HDMI4 78 03 0C 00 40 00 80 2D 20 C0 0E 01 4F 00 FE

08 10 06 10 18 10 28 10 38 10

4.4.4.3. 3D PCM(US) _ XvYcc : 0ff

▪Reference

- HDMI1 ~ HDMI4 / RGB

- In the data of EDID, bellows may be different by S/W or Input

mode.

ⓐ Product ID

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ -> ‘01’
Year : ‘2012’ -> ‘16’
ⓓ Model Name(Hex): LGTV

Chassis MODEL NAME(HEX)

LA22E

ⓔ Checksum(LG TV): Changeable by total EDID data.

HDMI1 43 B5 X

HDMI2 43 A5 X

HDMI3 43 95 X

HDMI4 43 85 X

RGB X X 5C

00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ1 ⓔ2 ⓔ3

ⓕ Vendor Specific(HDMI)

INPUT MODEL NAME(HEX)

HDMI1 67 03 0C 00 10 00 80 2D

HDMI2 67 03 0C 00 20 00 80 2D

HDMI3 67 03 0C 00 30 00 80 2D

HDMI4 67 03 0C 00 40 00 80 2D

4.4.4.4. 3D PCM(US) _XvYcc : off

ⓐ Product ID

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ -> ‘01’
Year : ‘2012’ -> ‘16’
ⓓ Model Name(Hex): LGTV

Chassis MODEL NAME(HEX)

LA22E

ⓔ Checksum(LG TV): Changeable by total EDID data.

HDMI1 43 68 X

HDMI2 43 58 X

HDMI3 43 48 X

HDMI4 43 38 X

RGB X X 5C

ⓕ Vendor Specific(HDMI)

INPUT MODEL NAME(HEX)

HDMI1 78 03 0C 00 10 00 80 2D 20 C0 0E 01 4F 00 FE

HDMI2 78 03 0C 00 20 00 80 2D 20 C0 0E 01 4F 00 FE

HDMI3 78 03 0C 00 30 00 80 2D 20 C0 0E 01 4F 00 FE

HDMI4 78 03 0C 00 40 00 80 2D 20 C0 0E 01 4F 00 FE

00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ1 ⓔ2 ⓔ3

08 10 06 10 18 10 28 10 38 10

08 10 06 10 18 10 28 10 38 10

08 10 06 10 18 10 28 10 38 10

08 10 06 10 18 10 28 10 38 10

Only for training and service purposes

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Final Assembly Adjustment

If TV internal pattern is used, not needed

5.1. White Balance Adjustment

5.1.1. Overview

5.1.1.1. W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel’s W/B deviation
(2) How-it-works: When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.

(3) Adj. condition: normal temperature

- Surrounding Temperature: 25±5 °C

- Warm-up time: About 5 Min

- Surrounding Humidity: 20% ~ 80%

- Before White balance adjustment, Keep power on status,

don’t power off

5.1.1.2. Adj. condition and cautionary items

(1) Lighting condition in surrounding area surrounding lighting

should be lower 10 lux. Try to isolate adj. area into dark
surrounding.

(2) Probe location: Color Analyzer (CA-210) probe should be

within 10cm and perpendicular of the module surface
(80°~ 100°)
(3) Aging time

- After Aging Sta rt, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked using no

signal or Full-white pattern.

5.1.2. Equipment

(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:

CH14)
(2) Adj. Computer (During auto adj., RS-232C protocol is

needed)
(3) Adjust Remocon
(4) Vi deo Signal Generator MSPG-925F 720p/204- Gray

(Model: 217, Pattern: 49)
※ Color Analyzer Matrix should be calibrated using CS-1000

5.1.3. Equipment connection

5.1.4. Adjustment Command (Protocol)

(1) RS-232C Command used during auto-adj.

RS-232C COMMAND

CMD DATA ID

Explanation

Wb 00 00 Begin White Balance adj.

Wb 00 ff End White Balance adj.

(internal pattern disappears )

(2) Adjustment Map

Adj. item Command

(lower caseASCII)

CMD1 CMD2 MIN MAX

Cool R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

Medium R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

Warm R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

Data Range
(Hex.)

5.1.5. Adjustment method

5.1.5.1 Auto WB calibration
(1) Set TV in ADJ mode using P-ONLY key (or POWER ON

key)

(2) Place optical probe on the center of the display

- It need to check probe condition of zero calibration before
adjustment.

(3) Connect RS-232C Cable
(4) Select mode in ADJ Program and begin a adjustment.
(5) When WB adjustment is completed with OK message,

check adjustment status of pre-set mode (Cool, Medium,
Warm)

(6) Remove probe and RS-232C cable.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need

Probe

RS-232C

Signal Source

※

Only for training and service purposes

※

Color Analyzer

RS-232C

Computer

RS-232C

Pattern Generator

5.1.6. Reference (White Balance Adj. coordinate and
color temperature)

(1) Luminance: 204 Gray, 80IRE
(2) Standard color coordinate and temperature using CS-1000

(over 26 inch)

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.1.7. Reference (White Balance Adj. coordinate and
color temperature)

▪ Luminance: 204 Gray
▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

Mode

Cool 0.269 0.273 13,000K 0.0000

Medium 0.285 0.293 9,300K 0.0000

Warm 0.313 0.329 6,500K 0.0000

▪ S ta ndard co lo r c oo rdi na te an d t emper at ure usin g

CA-210(CH 14)

(1) LGD and 65”AUO

Mode

Cool 0.269±0.002 0.273±0.002 13,000K 0.0000

Medium 0.285±0.002 0.293±0.002 9,300K 0.0000

Warm 0.313±0.002 0.329±0.002 6,500K 0.0000

(2) O/S Module(AUO, CMI, Sharp,IPS…)

Mode

Cool 0.271±0.002 0.276±0.002 13,000K 0.0000

Medium 0.287±0.002 0.296±0.002 9,300K 0.0000

Warm 0.315±0.002 0.332±0.002 6,500K 0.0000

▪ S ta ndard co lo r c oo rdi na te an d t emper at ure usin g

CA-210(CH-14) – by aging time

(1) Only Kumi factory in Korea

(2) Other factories(Only LS5700 series Module & 65LM6200-UA)

Aging time

GP4

1 0-2 280 287 296 307 320 337

2 3-5 279 285 295 305 319 335

3 6-9 277 284 293 304 317 334

4 10-19 276 283 292 303 316 333

5 20-35 274 280 290 300 314 330

6 36-49 272 277 288 297 312 327

7 50-79 271 275 287 295 311 325

8 80-119 270 274 286 294 310 324

9 Over 120 269 273 285 293 309 323

Coordinate

X Y

Coordinate

X Y

Coordinate

X Y

(Min)

Temp △uv

Temp △uv

Temp △uv

Cool Medium Warm

X Y X Y X Y

269 273 285 293 313 329

5.2. Tool Option setting & Inspection per
countries

5.2.1. Overview

(1) Tool option selection is only done for models in Non-USA

North America due to rating

(2) Applied model: LA02D and LA02E Chassis applied to

CANADA and MEXICO

5.2.2. Country Group selection

(1) Press ADJ key on the Adj. R/C, and then select Country

Group Menu

(2) Depending on destination, select KR or US, then on the

lower Country option, select US, CA, MX.

Selection is done using +, - KEY

5.2.3. Tool Option Inspection

(1) Press ADJ key on the Adj. R/C, and then select Country Grou

Model Tool 1 Tool 2 Tool 3 Tool 4 Tool 5 Tool 6 Tool 7

32LS5700-UA 356 8259 9997 13006 21015 1322 8971

42LS5700-

UA(AUO)

42LS5700-UA 358 8259 9997 13004 21015 1322 13067

47LS5700-

UA(AUO)

47LS5700-UA 359 8259 9997 13004 21015 1322 12555

55LS5700-

UA(AUO)

55LS5700-UA 361 8259 9997 13004 21015 1321 12555

60LS5700-

UA(Sharp)

42LS5750-UB 358 8259 9997 13004 21015 1322 13067

42LS5750-

UB(AUO)

47LS5750-UB 359 8259 9997 13004 21015 1322 12555

47LS5750-

UB(AUO)

55LS5750-UB 361 8259 9997 13004 21015 1321 12555

55LS5750-

UB(AUO)

60LS5750-

UB(Sharp)

32LM6200-UE 116 8259 26381 13006 23063 1322 8971

42LM6200-UE 118 8259 26381 13004 23063 1322 13067

47LM6200-UE 119 8259 26381 13004 23063 1322 12555

55LM6200-UE 121 8259 26381 13004 23063 1321 12555

65LM6200-UB 36987 8259 26381 13006 23063 1321 12427

42LM6210-UD 118 8259 26381 13004 23063 1322 13067

47LM6210-UD 119 8259 26381 13004 23063 1322 12555

47LM6250-UD 119 8259 26381 13004 23063 1322 12555

55LM6250-UD 121 8259 26381 13004 23063 1321 12555

● Tool option can be reconstructed by Software

4454 8259 9997 13006 21143 1322 13067

4455 8259 9997 13006 21143 1322 12555

4457 8259 9997 13006 21143 1321 12555

39274 8259 9997 13006 21015 1321 12555

4454 8259 9997 13006 21143 1322 13067

4455 8259 9997 13006 21143 1322 12555

4457 8259 9997 13006 21143 1321 12555

39274 8259 9997 13006 21015 1321 12555

Only for training and service purposes

- 15 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.3. Local Dimming Inspection

(1) Press ‘TILT” key of the Adj. R/C and check movin g

patterns. The black bar patterns moves from top to bottom.

If a local dimming function does not work, a whole screen

shows full white.

<T120 Model>

<T240 Model>
※ Except No local-dimming models

5.4. EYE-Q Check

Step 1) Turn on the TV..
Step 2) Press ' EY E button' o n t he adjustm en t remote -

controller.

Step 3) Cover 'Eye Q sensor' on the front of set with your

hands, hold it for 6 seconds.

Step 4) Check "the Sensor Data" on the screen, make certain

that Data is below 10. If Data isn’t below 10 in 6
seconds, Eye Q sensor would be bad. You should
change Eye Q sensor.

Step 5) Uncover your hands from Eye Q sensor, hold it for 6

seconds.

Step 6) Check "Back Light(xxx)" on the screen, check data

increase . You should change Eye Q sensor.

5.5. Magic Motion remote controller Check

5.5.1. Test equipment

▪ RF-remote controller for check, IR-KEY-COD E rem ote

controller.

▪ Check AA battery before test. A recommendation is that a

tester change battery every lots.

5.5.2. Test

(1) Make pairing with TV set by pressing “Start key(Wheel

key)” on RCU.
(2) Check a cursor on screen by pressing ‘Wheel key” of RCU
(3) Stop paring with TV set by pressing “Back+ Home” key of

RCU

5.5.3. Applied models

Chassis Model Name Magic RF receiver

LA22E 32/42/47/55LS5700-UA Built-in

42/47/55/65LM6200-UA

32/42/47/55LS5700-UA

42/47/55LM6700-UA

47/55LM7600-UA

※ LW5700-UE series: An USB dongle-type receiver will be

supplied in form of accessory. So this pairing test is not
necessary for these models.

5.6. Wi-Fi MAC Address Check

5.6.1. Using RS232 Command

Command Set ACK

Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]

5.6.2. Check the menu on in-start

<Step 2>

<Step 4>

Only for training and service purposes

<Step 3>

<Step 5>

<Step 6>

- 16 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.7. 3D pattern test (Only for 3D models)

5.7.1. Test equipment

(1) Pattern Generator MSHG-600 or MSPG-6100 (HDMI 1.4

support)

(2) Pattern: HDMI mode (model No. 872, pattern No. 83)

5.8. HDMI ARC Function Inspection

5.8.1. Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

5.7.2. Test method

(1) Input 3D test signal as Fig.1.

(2) Press ‘OK” key as a 3D input OSD is shown.
(3) Check pattern as Fig2 without 3D glasses. (3D mode

without 3D glasses)

Fig.2 Fig.3

<OK in 3D mode without 3D glasses> <NG in 3D mode without 3D glasses>

5.8.2. Test method

(1) Insert the HDMI Cable to the HDMI ARC port from the

master equipment (HDMI1)

(2) Check the sound from the TV Set

(3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

Only for training and service purposes

* Remark: Inspect in Power Only Mode and check SW version

in a master equipment

5.9. Ship-out mode check (In-stop)

▪ After final inspection, press In-Stop key of the Adj. R/C and

check that the unit goes to Stand-by mode

- 17 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

6. AUDIO output check

6.1. Audio input condition

(1) RF input: Mono, 1KHz sine wave signal, 100% Modulation
(2) CVBS, Component: 1KHz sine wave signal (0.4Vrms)
(3) RGB PC: 1KHz sine wave signal (0.7Vrms)

6.2. Specification

No Item Min Typ Max Unit Remark

1 Audio

practical

max Output,

L/R

9.0

8.5

10.0

8.9

12.0

9.9WVrms

(1) Measurement

condition

- EQ/AVL/Clear

Voice: Off

(2) Speaker (8Ω

Impedance)

8. USB S/W Download
(optional, Service only)

(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick

- If your downloaded program version in USB Stick is lower

than that of TV set, it didn’t work. Otherwise USB data is
automatically detected.

(3) Show the message “Copying files from memory”

7. GND and HI-POT Test

7.1. GND & HI-POT auto-check preparation

(1) Check the POWER CABLE and SIGNAL CABE insertion

condition

7.2. GND & HI-POT auto-check

(1) Pallet moves in the station. (POWER CORD / AV CORD is

tightly inserted)
(2) Connect the AV JACK Tester.
(3) Controller (GWS103-4) on.
(4) GND Test (Auto)

- If Test is failed, Buzzer operates.

- If Test is passed, execute next process (Hi-pot test).
(Remove A/V CORD from A/V JACK BOX)
(5) HI-POT test (Auto)

- If Test is failed, Buzzer operates.

- If Test is passed, GOOD Lamp on and move to next process

automatically.

7.3. Checkpoint

(1) Test voltage

- GND: 1.5KV/min at 100mA

- SIGNAL: 3KV/min at 100mA
(2) TEST time: 1 second
(3) TEST POINT

- GND Test = POWER CORD GND and SIGNAL CABLE GND.

- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.
(4) LEAKAGE CURRENT: At 0.5mArms

(4) Updating is staring.

(5) Updating Completed, The TV will restart automatically
(6) If your TV is turned on, check your updated version and

Tool option.

* If downloading version is more high than your TV have, TV

can lost all channel data. In this case, you have to channel
recover. If all channel data is cleared, you didn’t have a DTV/
ATV test on production line.

* After downloading, TOOL OPTION setting is needed again.
(1) Push "IN-START" key in service remote controller.
(2) Select "Tool Option 1" and Push “OK” button.
(3) Punch in the number. (Each model has their number.)

Only for training and service purposes

- 18 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

9. Optional adjustments

9.1. Manual ADC Calibration

9.1.1. Equipment & Condition

(1) Adjustment Remocon
(2) 801GF (802B , 80 2F, 802R) or MSPG925FA Pat tern

Generator

- Resolution : 4 80 i Co mp 1 (M SP G-9 25FA : mo de l-2 09,

pattern-65)

- Resolution : 1080p Comp1 ( MSPG-925FA: model-225,

pattern-65)

- Resolution : 1 080 p RG B (M SPG -92 5FA: m ode l-2 25,

pattern-65)

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level : 0.7±0.1 Vp-p

9.1.2. Adjust method

8.1.2.1 ADC 480i/1080p Comp1, RGB
(1) Check connected condition of Comp1/RGB cable to the

equipment
(2) Give a 480i Mode, Horizontal 100% Color Bar Pattern to

Comp1. (MSPG-925FA -> Model: 209, Pattern: 65)
(3) Change input mode as Component1 and picture mode as

“Standard”
(4) Press the In-start Key on the ADJ remote after at least 1

min of signal reception. Then, select 7.External ADC. And

Press OK or Right Button for going to sub menu.
(5) Press OK in Comp 480i menu
(6) Give a 1080p Mode, Horizontal 100% Color Bar Pattern to

Comp1. (MSPG-925FA -> Model: 225, Pattern: 65)
(7) Press OK in Comp 1080p menu
(8) Perform (6) and (7) in RGB-PC
(9) If ADC Comp is successful, “ADC Component Success” is

displayed. If ADC calibration is failure, “ADC Component

Fail” is displayed.
(10) If ADC calibration is failure, after rechecking ADC pattern

or condition, retry calibration

(11) If ADC RG B calibr ation is succe ss ful, “ADC RGB

Success” is displayed. If ADC calibration is failure, “ADC
RGB Fail” is displayed.

(12) If ADC calibration is failure, after recheck ADC pattern or

condition, retry calibration

9.2. Manual White balance Adjustment

9.2.1. Adj. condition and cautionary items

(1) Lighting condition in surrounding area surrounding lighting

should be lower 10 lux. Try to isolate adj. area into dark
surrounding.

(2) Probe location: Color Analyzer (CA-210) probe should be

within 10cm and perpendicular of the module surface
(80°~ 100°)
(3) Aging time

▪ After Aging Start, Ke ep the Power ON status during 5

Minutes.

▪ In case of LCD, Back-light on should be checked using no

signal or Full-white pattern.

9.2.2. Equipment

(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:

CH14)
(2) Adj. Computer (During auto adj., RS-232C protocol is

needed)
(3) Adjust Remocon
(4) Vi deo Sig nal Generator MSP G-925F 720p/216 -Gray

(Model: 217, Pattern: 78)

9.2.3. Adjustment

(1) Set TV in Adj. mode using POWER ON
(2) Zero Calibrate the probe of Color Analyzer, then place it on

the center of LCD module within 10cm of the surface.
(3) Press ADJ key -> EZ adjust using adj. R/C -> 6. White-

Balance then press the cursor to the right (KEY►).
When KEY(►) is pressed 216 Gray internal pattern will be

displayed.

(4) One of R Gain / G Gain / B Gain should be fixed at 192,

and the rest will be lowered to meet the desired value.
(5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of

color temperature.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 6.White Balance, you can select one of 2 Test-pattern:
ON, OFF. Default is inner(ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.

Only for training and service purposes

- 19 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

300

710

570

410

400

560

900

LV2

LV1

530

200

Only for training and service purposes

540

521

700

- 20 -

810

510

120

121

500

501

910

Dual Play

AG1

A22

A21

A2

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

EAX6430790* : LD22* / LC22*

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

EAX6443420* : LT22* / LJ22* / LA22* / LB22*

Crystal Matching Test result
: 27pF -> 20pF -> 24pF

+3.3V_NORMAL

R103

4.7K

R104

4.7K
OPT

R105

4.7K
OPT

NVRAM

IC104

AT24C256C-SSHL-T

A0

1

A1

2

A2

3

GND

4

VCC

8

WP

7

SCL

6

SDA

5

NVRAM_ATMEL

HDCP EEPROM

HDCP_EEPROM_ST

IC100

M24C16-R

NC_1

NC_2

NC_3

VSS

VCC

8

1

WC

2

7

SCL

3

6

SDA

4

5

+3.3V_NORMAL

+3.3V_NORMAL

R181 4.7K

R191 22

R192 22

IC104-*1

M24256-BRMN6TP

E0

VCC

1

8

WC

E1

7

2

SCL

E2

6

3

SDA

VSS

5

4

NVRAM_ST

Write Protection

- Low : Normal Operation

- High : Write Protection

R136 33

R137 33

HDCP_EEPROM_MICRO

C101

0.1uF
16V

VSS

I2C_SCL1

I2C_SDA1

A0

A1

A2

I2C_SCL5

I2C_SDA5

IC100-*1

24LC16B

1

2

3

4

IC104-*2

R1EX24256BSAS0A

A0

1

A1

2

A2

3

VSS

4

NVRAM_RENESAS

VCC

8

WP

7

SCL

6

SDA

5

VCC

8

WP

7

SCL

6

SDA

5

JTAG

JTRST#

JTDI
JTMS
JTCLK

JTDO

R143 33

MTK_JTAG

AR100

+3.3V_NORMAL

R147
1K

OPT

R148
1K

I2C_1 : AMP, L/DIMMING,HDCP KEY
I2C_2 : T-CON
I2C_3 : MICOM
I2C_4 : S/Demod,T2/Demod, LNB
I2C_5 : NVRAM
I2C_6 : TUNER_MOPLL(T/C,ATV)

R160

R186

R156

2.7K

4.7K

2.7K

R189

4.7K

MTK_EPI

R164

2.7K

MTK_DVB_C2_TUNER

R177

2.7K

MODEL_OPT_0

MODEL_OPT_1

I2C_SCL1
I2C_SDA1

I2C_SCL2
I2C_SDA2
I2C_SCL3
I2C_SDA3
I2C_SCL4
I2C_SDA4
I2C_SCL5
I2C_SDA5

I2C_SCL6
I2C_SDA6

STB_SCL
STB_SDA

OPCTRL_11_SCL
OPCTRL_10_SDA

OSCL1

OSDA1
OSCL2
OSDA2
OSCL0
OSDA0

OPCTRL_1_SCL

OPCTRL_0_SDA

+3.3V_NORMAL

I2C

R110 33
R111 33

R112 33
R113 33
R114 33
R115 33
R116 33
R117 33
R118 33
R121 33
R122 33
R123 33

R106

R101

4.7K

MTK_FRC3/URSA5

MTK_Int_FRC/URSA5

R128

R131

1.2K

1.2K

Model Option

R125

4.7K

R108

4.7K

4.7K
MTK_FHD

MTK_OPTIC_Tx_IC

R134

R139

2.7K

2.7K

R130

4.7K

MTK_3D_DEPTH_IC

R142

2.7K

R132

4.7K
MTK_CP_BOX

MTK_DDR_768MB

R135

R173

2.7K

4.7K

+3.3V_NORMAL

R188

R185

2.7K

2.7K

R140

4.7K

R175

4.7K

MTK_DVB_S_TUNER

MTK_DVB_T2_TUNER

MODEL_OPT_2

MODEL_OPT_3
/S2_RESET

MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6

R102

4.7K

R107

4.7K

MTK_NO_FRC/FRC3

MTK_NO_FRC/Int_FRC

R109

MTK_HD

4.7K

R129

4.7K

R127

4.7K

MTK_NON_OPTIC_Tx_IC

MTK_NON_3D_DEPTH_IC

R133

4.7K

R138

4.7K

MTK_NON_CP_BOX

MTK_DDR_DEFAULT

R141

4.7K

MTK_NON_DVB_T2_TUNER

R187

R184

4.7K

MTK_NON_DVB_S_TUNER

MTK_NON_DVB_C2_TUNER

4.7K

R190

4.7K

MTK_NON_EPI

M_RFModule_ISP

MODEL_OPT_8

MODEL_OPT_9

MODEL_OPT_10

MODEL_OPT_7

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

10K

R150
1K

R151
1K

OPT

+3.3V_NORMAL

R144
10K

MTK_JTAG

R153
1K
OPT

R154
1K

+3.3V_NORMAL

R145
10K

MTK_JTAG

LED_PWM0
LED_PWM1
OPCTRL3

R146
10K

MTK_JTAG

R149
10K

+3.3V_NORMAL

NO_FRC

MODEL_OPT_0

MODEL_OPT_1

0

0

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6

MODEL_OPT_7

MODEL_OPT_8

MODEL_OPT_9

MODEL_OPT_10

3D DEPTH

DDR

CP BOX

T2 Tuner

S Tuner

Reserved

EPI

MODEL OPTION 8 is just for CP Box
It should not be appiled at MP

MTK_JTAG
R152

1K

12507WS-12L

MTK_JTAG

P100

1

2

3

4

5

6

7

8

9

10

11

12

13

Close to eMMC Flash
(IC8100)

EMMC_CLK

STRAPPING LED_PWM0 LED_PWM1 OPCTRL3

ICE mode + 27M + Serial boot 0 0 0

ICE mode + 27M + ROM to Nand boot 0 0 1

ICE mode + 27M + Rom to eMMC boot 0 1 0
from eMMC pins (share pins w/s NAND)

ICE mode + 27M + ROM to eMMC boot 0 1 1
from SDIO pins

MT5369_RM

IC105-*1

LGE2112-AL

SoC
internal
FRC

0

1

HIGH

FHD

OPTIC

3D_Depth_IC

DDR_768MB

Enable

Support

Support

Support

LG FRC2

1

0

LOW

HD

NON_OPTIC

NON_3D_Depth_IC

DDR_Default

Disable

Not Support

Not Support

Default

Not Support

Reserved

1

1

AC1
AC2

A3
A4
B4
C4
D4
B3

C3
AC3
AC4

G10

G9

G13
G21

F10

D9

C9

A20
A21

E18
F17
E17
E16
D14

B14

A13
G11
D16

F18

C15
A15
F13
C14
F11
E15
D13
B15
E14
F16
E13
B13
A14
F14
F15

HEAT SINK SMD GASKET

MTK_H/S_3.5T

MDS62110213

DDRV_44
DDRV_45
DDRV_1
DDRV_2
DDRV_5
DDRV_8
DDRV_10
DDRV_4
DDRV_7
DDRV_46
DDRV_47

MEMTP
MEMTN

RVREF_B
RVREF_A

ARCKE

ARCLK1
ARCLK1

ARCLK0
ARCLK0

ARODT
ARRAS
ARCAS
ARCS
ARWE

ARRESET

ARBA0
ARBA1
ARBA2

ARCSX

ARA14
ARA13
ARA12
ARA11
ARA10
ARA9
ARA8
ARA7
ARA6
ARA5
ARA4
ARA3
ARA2
ARA1
ARA0

M100

MTK_H/S_3.5T

ARDQM0
ARDQS0
ARDQS0

ARDQ0
ARDQ1
ARDQ2
ARDQ3
ARDQ4
ARDQ5
ARDQ6
ARDQ7

ARDQM1
ARDQS1
ARDQS1

ARDQ8

ARDQ9
ARDQ10
ARDQ11
ARDQ12
ARDQ13
ARDQ14
ARDQ15

ARDQM2
ARDQS2
ARDQS2
ARDQ16
ARDQ17
ARDQ18
ARDQ19
ARDQ20
ARDQ21
ARDQ22
ARDQ23

ARDQM3
ARDQS3
ARDQS3
ARDQ24
ARDQ25
ARDQ26
ARDQ27
ARDQ28
ARDQ29
ARDQ30
ARDQ31

AVDD33_MEMPLL
AVSS33_MEMPLL

DVSS_50
DVSS_48

M101

MDS62110213

C19
C21
B21
C23
B17
D23
C17
D24
C16
C24
D15

D21
B20
C20
A17
A23
D17
B23
D20
D22
D19
C22

A7
B9
A9
C12
D6
B12
C5
C13
A5
A12
B5

E10
C8
D8
C6
D10
D7
C11
C7
C10
B7
B10

N14
N15

R1
P21

MTK_H/S_3.5T

MDS62110213

M102

R174

10K

M103

MDS62110213

MTK_H/S_3.5T

MT5369_TS_OUT[0-7]

/USB_OCD2
/USB_OCD1
/USB_OCD3

USB_CTL2
USB_CTL1
USB_CTL3

M104

MDS61887710

MTK_H/S_9.5T

MT5369_MCLKI

MT5369_MIVAL_ERR

MT5369_MISTRT

SOC -> CI SLOT

CI_DATA[0-7]

SOC -> CI SLOT

C102

C100

0.1uF

0.1uF
OPT

OPT

CI_ADDR[0-14]

CI SLOT -> SOC

C103

C105

0.1uF

0.1uF

OPT

OPT

SC_ID_SOC

CI_DATA[0]
CI_DATA[1]
CI_DATA[2]
CI_DATA[3]
CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

C104

C106

0.1uF

0.1uF
OPT

R193

R176
R162
R163

MODEL_OPT_4

AVDD_33SB

AVDD_33SB

VDD3V3

MT5369_TS_OUT[0]
MT5369_TS_OUT[1]
MT5369_TS_OUT[2]
MT5369_TS_OUT[3]
MT5369_TS_OUT[4]
MT5369_TS_OUT[5]
MT5369_TS_OUT[6]
MT5369_TS_OUT[7]

MT5369_TS_IN[0]
MT5369_TS_IN[1]
MT5369_TS_IN[2]
MT5369_TS_IN[3]

MT5369_TS_IN[4]
MT5369_TS_IN[5]
MT5369_TS_IN[6]
MT5369_TS_IN[7]

ERROR_OUT

OPT

MODEL_OPT_7

NON_EU

10K

10K
10K
10K

M_RFModule_RESET

JTCLK
JTDI
JTDO
JTMS

JTRST#

OSDA0
OSCL0

OSDA1
OSCL1

MT5369_XTAL_OUT

C116

0.1uF

C117

0.1uF

C118

0.1uF

OPC_EN
/TU_RESET
/S2_RESET

MT5369_XTAL_IN

C107

2.2uF
10V

CI_ADDR[0]
CI_ADDR[1]
CI_ADDR[2]
CI_ADDR[3]
CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]
CI_ADDR[8]
CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

EPI_LOCK6
MODEL_OPT_0
MODEL_OPT_1

MODEL_OPT_3

M_RFModule_ISP

MODEL_OPT_5
MODEL_OPT_6

X-TAL

C108

2.2uF
10V

AP14
AM14
AR14
AR15
AN14

AP12
AN12

AP15
AN15

AT34
AU34

AK27
AH26

AK18
AK17

AK23
AM27

AJ20

AN23
AN24
AP23
AR23
AU23
AT23
AM24
AM23

H32
F37
F36
G37
G36
G35
G34
H34
L34
L32
K33
K32
H33
L35
K36
J32
J34
K34
K35
K37
J36
J37
J35
J33
G33
H35
H31
F34
E36
N33
P32
M35
M37
M33
F35
E35
E37
N32
M34
M36
M32
L33
E33
E32
F32
A29
D31
C31
E30
E31
F31
E29
AP9
AT9
AR9
AU9

X100

27MHz

C113

24pF

MT5369_NON_RM

IC105

LGE2112

JTCK
JTDI
JTDO
JTMS
JTRST

OSDA0
OSCL0

OSDA1
OSCL1

XTALI
XTALO

AVDD33_XTAL_STB
AVSS33_XTAL_STB

AVDD33_VGA_STB
AVSS33_VGA_STB

AVDD33_PLLGP
AVSS33_PLLGP

AVDD10_LDO

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55

ADIN0_SRV
ADIN1_SRV
ADIN2_SRV
ADIN3_SRV
ADIN4_SRV
ADIN5_SRV
ADIN6_SRV
ADIN7_SRV

MID_MAIN_1

C115

24pF

U0TX
U0RX

U1RX
U1TX

POWE

POOE
POCE1
POCE0

PDD7

PDD6

PDD5

PDD4

PDD3

PDD2

PDD1

PDD0

PARB
PACLE
PAALE

EMMC_CLK

OPWRSB

ORESET

OIRI

FSRC_WR

STB_SCL
STB_SDA

DEMOD_RST

DEMOD_TSCLK
DEMOD_TSDATA0
DEMOD_TSDATA1
DEMOD_TSDATA2
DEMOD_TSDATA3
DEMOD_TSDATA4
DEMOD_TSDATA5
DEMOD_TSDATA6
DEMOD_TSDATA7

DEMOD_TSSYNC

DEMOD_TSVAL

CI_INT

CI_TSCLK

CI_TSDATA0

CI_TSSYNC

CI_TSVAL

PVR_TSCLK
PVR_TSVAL

PVR_TSSYNC
PVR_TSDATA0
PVR_TSDATA1

SPI_CLK1

SPI_CLK

SPI_DATA

SPI_CLE

OPWM2
OPWM1
OPWM0

SD_D0
SD_D1
SD_D2

SD_D3
SD_CMD
SD_CLK

LDM_CS

LDM_CLK

LDM_VSYNC

LDM_DO
LDM_DI

LED_PWM1
LED_PWM0

OPCTRL11
OPCTRL10

OPCTRL9
OPCTRL8
OPCTRL7
OPCTRL6
OPCTRL5
OPCTRL4
OPCTRL3
OPCTRL2
OPCTRL1
OPCTRL0

IC
R119

MT5369_XTAL_OUTMT5369_XTAL_IN

0

+3.3V_NORMAL

AR18
AP18

AU16
AT16

A35
C33
B34
D33
D29
C30
D30
B31
A31
B32
A32
C32
D32
A34
C34
C29

AM20

SOC_TX
SOC_RX

EMMC_DATA[7]
EMMC_DATA[6]
EMMC_DATA[5]
EMMC_DATA[4]
EMMC_DATA[3]
EMMC_DATA[2]

EMMC_DATA[1]

R165

4.7K

EMMC_CMD

EMMC_DATA[0]
EMMC_CLK

R167

4.7K

M_REMOTE_RX
M_REMOTE_TX

+3.3V_NORMAL

+3.3V_NORMAL

EMMC_DATA[2-7]

AM22

AU21

D27

AT21
AR21

T34
T32
T36
U36
T33
T30
V33
V32
V31
V30
T35
T31

N36
T37
R35
R37
R36

R34
R32
R33
P33
P34

N37
P35
N34
N35

AU12
AT12
AR12

A37
C35
A36
B35
B36
B37

AT11
AU11
AR10
AM9
AP10

AN22
AP21

AU20
AT20
AN18
AP20
AM18
AN19
AP19
AR19
AN21
AM19
AN20
AR20

AMP_RESET_SOC AMP_RESET_N

OPT

R159 4.7K

STB_SCL
STB_SDA

PCM_RST
FE_TS_CLK

/CI_CD2
/CI_CD1
/PCM_IORD
/PCM_IOWR

SMARTCARD_CLK

SMARTCARD_PWR_SEL

SMARTCARD_RST
SMARTCARD_DET
SMARTCARD_VCC
SMARTCARD_DATA

AMP_RESET_BY_SOC

FOR JAPAN

R124

33

IR

FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]
FE_TS_DATA[4]
FE_TS_DATA[5]
FE_TS_DATA[6]
FE_TS_DATA[7]

FE_TS_SYNC
FE_TS_VAL

/PCM_REG

/PCM_CE1

MT5369_TS_SYNC

/PCM_WE
/PCM_OE

MT5369_TS_VAL

CI_A_VS1

MT5369_TS_CLK
/PCM_IRQA
/PCM_WAIT

+3.3V_NORMAL

R166

2.7K
OPT

R169 10K

OPT

L/DIM0_SCLK
L/DIM0_VS
L/DIM0_MOSI

LED_PWM1
LED_PWM0

5V Tolerance

OPCTRL_11_SCL

OPCTRL_10_SDA
COMP1_DET
SC_DET
DSUB_DET
HP_DET
AV1_CVBS_DET

AMP_RESET_SOC
OPCTRL3

RF_SWITCH_CTL
OPCTRL_1_SCL
OPCTRL_0_SDA

R100

10K

R172

22

CI SLOT -> SOC

CI SLOT -> SOC

CI SLOT -> SOC

R168

4.7K
OPT

R120
1K

PWM1_PULL_DOWN_1K

AMP_RESET_BY_SOC

33

R158

2011.12.13

8

R157

4.7K
OPT

R178

4.7K
OPT

R155
10K

OPT

SOC_RESET

C114

0.1uF
16V

FE_TS_DATA[0-7]

EXTERNAL DEMOD

-> SOC

R161

4.7K
OPT

R171

22

22

R170

R126
1K

PWM2_PULL_DOWN_1K

SMARTCARD_CLK

SMARTCARD_PWR_SEL

SMARTCARD_RST

SMARTCARD_DET

SMARTCARD_VCC

SMARTCARD_DATA

FOR JAPAN

C120

2.2uF
10V
OPT

PWM_DIM2
PWM_DIM1
A_DIM

PLACE AT JACK SIDE

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

DDC_SCL_2_JACK
DDC_SCL_3_JACK

DDC_SCL_1_SOC
DDC_SCL_4_JACK

DDC_SDA_2_JACK
DDC_SDA_3_JACK

DDC_SDA_1_SOC
DDC_SDA_4_JACK

5V_HDMI_2_JACK
5V_HDMI_3_JACK

5V_HDMI_1_SOC

5V_HDMI_4_JACK

HDMI_HPD_2_JACK
HDMI_HPD_3_JACK

HDMI_HPD_1_SOC
HDMI_HPD_4_JACK

+1.2V_MTK_AVDD

C303

0.1uF

VDD3V3

C304

0.1uF

Port was changed !!!!

VDD3V3

C308

0.1uF

C302

0.1uF

VDD3V3

0.1uF

C306

0.1uF

C307

R304
R305
R306
R307 1K

USB_DP3
USB_DM3

USB_DP2
USB_DM2

WIFI_DP

USB_DP1
USB_DM1

+1.2V_MTK_AVDD

C316

0.1uF

HP_LOUT_AMP

HP_ROUT_AMP

1K
1K
1K

WIFI_DM

PC_L_IN

PC_R_IN

AA32

AG33
AE33
AC33
AH32

AF33
AD33
AB33
AH33

AG31
AE31
AC31
AH31

AG32
AE32
AC32
AJ32

AA24

Y24
W24

AB24

AB29
AA29

Y29

AC29

AB30
AD30
AF31
AF32

C36
C37

D36
D37

AT13
AU13

AT14
AU14

D35

AP13

D34

AR13

W35
W34
Y34
Y35

U24
V24

W30

W36
W37

BLM18PG121SN1D

BLM18PG121SN1D

R300
470K

OPT

R301
470K

OPT

HDMI_CEC

HDMI_0_SCL
HDMI_1_SCL
HDMI_2_SCL
HDMI_3_SCL

HDMI_0_SDA
HDMI_1_SDA
HDMI_2_SDA
HDMI_3_SDA

HDMI_0_PWR5V
HDMI_1_PWR5V
HDMI_2_PWR5V
HDMI_3_PWR5V

HDMI_0_HPD
HDMI_1_HPD
HDMI_2_HPD
HDMI_3_HPD

AVDD12_HDMI_0_RX
AVDD12_HDMI_1_RX
AVDD12_HDMI_2_RX
AVDD12_HDMI_3_RX

AVDD33_HDMI_0_RX
AVDD33_HDMI_1_RX
AVDD33_HDMI_2_RX
AVDD33_HDMI_3_RX

AVSS33_HDMI_RX_1
AVSS33_HDMI_RX_2
AVSS33_HDMI_RX_3
AVSS33_HDMI_RX_4

USB_DP_P0
USB_DM_P0

USB_DP_P1
USB_DM_P1

USB_DP_P2
USB_DM_P2

USB_DP_P3
USB_DM_P3

AVDD33_USB_P0P1
AVDD33_USB_P2P3

AVSS33_USB_P1
AVSS33_USB_P2

PCIE11_TXP
PCIE11_TXN
PCIE11_RXN
PCIE11_RXP

AVDD12_PCIE11
AVDD33_PCIE11

AVSS12_PCIE11

PCIE11_REFCKN
PCIE11_REFCKP

HP_OUT
L303

HP_OUT
L302

Place at JACK SIDE

ARC

IC105

LGE2112

HP_OUT
C332

0.22uF
10V

HP_OUT
C331

0.22uF
10V

R302

180

HDMI_0_RX_0B

HDMI_0_RX_1B

HDMI_0_RX_2B

HDMI_0_RX_CB

HDMI_1_RX_0B

HDMI_1_RX_1B

HDMI_1_RX_2B

HDMI_1_RX_CB

HDMI_2_RX_0B

HDMI_2_RX_1B

HDMI_2_RX_2B

HDMI_2_RX_CB

HDMI_3_RX_0B

HDMI_3_RX_1B

HDMI_3_RX_2B

HDMI_3_RX_CB

HP_ROUT

1608 sizs For EMI

C300
560pF
50V
OPT

1608 sizs For EMI

C301
560pF
50V
OPT

R303

82

HDMI_0_RX_0

HDMI_0_RX_1

HDMI_0_RX_2

HDMI_0_RX_C

HDMI_1_RX_0

HDMI_1_RX_1

HDMI_1_RX_2

HDMI_1_RX_C

HDMI_2_RX_0

HDMI_2_RX_1

HDMI_2_RX_2

HDMI_2_RX_C

HDMI_3_RX_0

HDMI_3_RX_1

HDMI_3_RX_2

HDMI_3_RX_C

TXVP_0
TXVN_0

RXVN_1
RXVP_1

PHYLED1
PHYLED0

REXT

AVDD12_REC

AVDD33_COM

AVDD33_LD

AVSS33_LD
AVSS33_COM
AVSS12_REC

HP_LOUT

R314

0

R336

0

10V

C311 1uF

AG35
AG34
AG37
AG36
AF35
AF34
AH35
AH34

AE37
AE36
AD35
AD34
AC35
AC34
AE35
AE34

AB35
AB34
AA35
AA34
AA37
AA36
AC37
AC36

AK35
AK34
AJ35
AJ34
AJ37
AJ36
AJ33
AK33

AT18
AU18

AU17
AT17

AN16
AM16

AD15

AD14

AD16
AD17

AL16
AL15
AL14

C314
100pF
50V

OPT

C315
100pF
50V
OPT

+5V_NORMAL

R308

1.2K
OPT

R309
100K

+1.2V_MTK_AVDD

C323

0.1uF

C319
10uF
16V

C320
10uF
16V

HDMI_ARC

D0+_HDMI2_JACK
D0-_HDMI2_JACK
D1+_HDMI2_JACK
D1-_HDMI2_JACK
D2+_HDMI2_JACK
D2-_HDMI2_JACK
CK+_HDMI2_JACK
CK-_HDMI2_JACK

D0+_HDMI3_JACK
D0-_HDMI3_JACK
D1+_HDMI3_JACK
D1-_HDMI3_JACK
D2+_HDMI3_JACK
D2-_HDMI3_JACK
CK+_HDMI3_JACK
CK-_HDMI3_JACK

D0+_HDMI1_SOC
D0-_HDMI1_SOC
D1+_HDMI1_SOC
D1-_HDMI1_SOC
D2+_HDMI1_SOC
D2-_HDMI1_SOC
CK+_HDMI1_SOC
CK-_HDMI1_SOC

D0+_HDMI4_JACK
D0-_HDMI4_JACK
D1+_HDMI4_JACK
D1-_HDMI4_JACK
D2+_HDMI4_JACK
D2-_HDMI4_JACK
CK+_HDMI4_JACK
CK-_HDMI4_JACK

R31524K

VDD3V3

C328

0.1uF

PC_L_IN_SOC

PC_R_IN_SOC

EPHY_TDP
EPHY_TDN

EPHY_RDN
EPHY_RDP

IF_P

IF_N

DSUB_VSYNC

DSUB_HSYNC

T/C&AT&CHB
R346 0

Close to Tuner

R331 0

T/C&AT&CHB

1608 sizs For EMI

AOCLKN
AOCLKP

AECLKN
AECLKP

BOCLKN
BOCLKP

BECLKN
BECLKP

AR0_ADAC
AL0_ADAC

AR1_ADAC
AL1_ADAC

AR2_ADAC
AL2_ADAC

AR3_ADAC
AL3_ADAC

AVDD33_DAC

AVSS33_DAC

ASPDIF0
ASPDIF1

AOBCK
AOLRCK
AOMCLK

AOSDATA4
AOSDATA3
AOSDATA2
AOSDATA1
AOSDATA0

HSYNC

VSYNC

VGA_SDA
VGA_SCL

VDACX_OUT
VDACY_OUT

AVDD12_RGB

AVSS12_RGB

AO3N
AO3P
AO4N
AO4P

AO2N
AO2P
AO1N
AO1P
AO0N
AO0P

AE4N
AE4P
AE3N
AE3P

AE2N
AE2P
AE1N
AE1P
AE0N
AE0P

BO4N
BO4P
BO3N
BO3P

BO2N
BO2P
BO1N
BO1P
BO0N
BO0P

BE4N
BE4P
BE3N
BE3P

BE2N
BE2P
BE1N
BE1P
BE0N
BE0P

ALIN

COM
SOG

COM1
PB1P
PR1P

Y1P
SOY1
COM0
PB0P
PR0P

Y0P
SOY0

R328
470K

OPT

R329
470K
OPT

RP
GP
BP

R333

120-ohm
C344
27pF
50V
OPT

CHANGE SYMBOL

AG3
AG4
AG1
AG2
AF3
AF4
AE3
AE4
AE1
AE2
AD1
AD2

AL3
AL4
AL1
AL2
AK3
AK4
AJ3
AJ4
AJ1
AJ2
AH3
AH4

AT2
AU2
AT1
AU1
AR1
AR2
AP1
AP2
AN1
AN2
AM3
AM4

AT6
AU6
AP6
AR6
AP5
AR5
AT4
AU4
AP4
AR4
AP3
AR3

AN35
AN34

AM32
AM34

AM37
AM33

AM36
AM35

AG30
AF30

AK30
AE30

Y33
AR16
Y32
AR11
AP11
AM12
AM10
AM11
AN11
AN10
AN9

AN25
AM25
AR25
AR24
AU24
AP24
AT24
AR22
AP22

AT26
AR26
AP26
AU26
AP25
AU28
AT28
AR28
AP27
AR27

AU30
AP29

AD20
AD21

AD19

AJ22
AJ21
AL24

C348
100pF
50V

R3761.2K
R3771.2K

Don’t use as GPIO

C3660.01uF
C3670.01uF
C3680.01uF
C3690.01uF
C3701500pF

OPT

R3490
R3500

1608 sizs For EMI

R344

30K

C338
560pF
50V
OPT

1608 sizs For EMI

R345

30K

C339
560pF
50V
OPT

TXC4N
TXC4P
TXC3N
TXC3P
TXCCLKN
TXCCLKP
TXC2N
TXC2P
TXC1N
TXC1P
TXC0N
TXC0P

TXD4N
TXD4P
TXD3N
TXD3P
TXDCLKN
TXDCLKP
TXD2N
TXD2P
TXD1N
TXD1P
TXD0N
TXD0P

TXA4N

CH3

TXA4P
TXA3N
TXA3P
TXACLKN

CH2

TXACLKP
TXA2N
TXA2P
TXA1N

CH1

TXA1P
TXA0N
TXA0P

TXB4N
TXB4P
TXB3N
TXB3P
TXBCLKN
TXBCLKP
TXB2N

CH6

TXB2P
TXB1N

CH5

TXB1P
TXB0N

CH4

TXB0P

C397
1200pF

C365

C380

0.01uF

0.1uF

R366 100
R367 100
R368 100

RGB_DDC_SDA
RGB_DDC_SCL

C3710.01uF
C3720.01uF
C3730.01uF
C3740.01uF
C3751500pF

VDD3V3

+1.2V_MTK_AVDD

R330
75
1%

C342
100pF
50V

C343
100pF
50V

C398

1200pF

R371 100

R356100
R357100
R358100
R359100

R361100
R362100
R363100
R364100

DTV/MNT_V_OUT_SOC

C382

0.1uF

C340
47pF
50V

C345
10uF
16V

C346
10uF
16V

HP_OUT

HP_OUT

R3781.2K
R3791.2K

DAC_3V3

DSUB_HSYNC_SOC
DSUB_VSYNC_SOC

R3511.2K
R3521.2K

C399
1200pF

C387
22pF
OPT

For PCB Pattern

COMP1_Pb_SOC
COMP1_Pr_SOC
COMP1_Y_SOC

AV1_CVBS_IN_SOC

C377
1200pF

1200pF

HP_OUT

C400
1200pF

SPDIF_OUT

ARC

C389

C393

22pF

22pF

OPT

OPT

SC_COM_SOC
SC_G_SOC
SC_R_SOC
SC_B_SOC
SC_FB_SOC

AV1_L_IN_SOC

AV1_R_IN_SOC

C383

HP_OUT

C396
33pF
OPT

HP_OUT

HP_OUT

R3691.2K
R3701.2K

C390
1200pF

HP_OUT

AUD_SCK
AUD_LRCK
AUD_MASTER_CLK
AUD_LRCH

C395
1200pF
HP_OUT

1.0Vpp

COMP1_Y

COMP1_Pb

COMP1_Pr

For PCB Pattern

HP_ROUT_MAIN
HP_LOUT_MAIN

SCART_Rout_SOC
SCART_Lout_SOC

AUDIO_R_OUT_COMMERCIAL
AUDIO_L_OUT_COMMERCIAL

ZD302

5.48VTO5.76V

ZD303

5.48VTO5.76V

ZD304

5.48VTO5.76V
ZD305

5.48VTO5.76V

ZD306

5.48VTO5.76V
ZD307

5.48VTO5.76V

PLACE AT JACK SIDE

C333

R322

47pF

75

50V

C335

R321

47pF

75

50V

C334

R320

47pF

75

50V

L300

BLM15BD121SN1

D301
ADLC 5S 02 015

5.5V

L301

BLM15BD121SN1

D300
ADLC 5S 02 015

5.5V

L304

BLM15BD121SN1

D302
ADLC 5S 02 015

5.5V

1608 sizs For EMI

0

R374

C388
27pF
50V
OPT

1608 sizs For EMI

0

R373

C386
27pF
50V
OPT

1608 sizs For EMI

0

R372

C385
27pF
50V

FOR EMI

OPT

DSUB_R+

DSUB_G+

DSUB_B+

C394
27pF
50V
OPT

C391
27pF
50V
OPT

C392
27pF
50V
OPT

R355
75

1%

R354
75

1%

R353
75

1%

MT5369_TS_OUT[0-7]

CI_DATA[0-7]

C384
10pF
50V

C379
10pF
50V

C378
10pF
50V

MT5369_MCLKI

MT5369_MIVAL_ERR

MT5369_MISTRT

COMP1_Y_SOC

COMP1_Pb_SOC

COMP1_Pr_SOC

CI_ADDR[0-14]

CI_DATA[0]
CI_DATA[1]
CI_DATA[2]
CI_DATA[3]
CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

MT5369_TS_OUT[0]
MT5369_TS_OUT[1]
MT5369_TS_OUT[2]
MT5369_TS_OUT[3]
MT5369_TS_OUT[4]
MT5369_TS_OUT[5]
MT5369_TS_OUT[6]
MT5369_TS_OUT[7]

MT5369_TS_IN[0]
MT5369_TS_IN[1]
MT5369_TS_IN[2]
MT5369_TS_IN[3]
MT5369_TS_IN[4]
MT5369_TS_IN[5]
MT5369_TS_IN[6]
MT5369_TS_IN[7]

SC_ID_SOC

/CI_CD2

/CI_CD1
/PCM_IORD
/PCM_IOWR

PCM_RST

/PCM_REG

/PCM_CE1

MT5369_TS_SYNC

/PCM_WE

/PCM_OE

MT5369_TS_VAL

CI_A_VS1

MT5369_TS_CLK

/PCM_IRQA

/PCM_WAIT
SC_R_IN_SOC
SC_L_IN_SOC

SC_CVBS_IN_SOC

SC_COM_SOC

SC_G_SOC
SC_R_SOC
SC_B_SOC

SC_FB_SOC

DTV/MNT_V_OUT_SOC

SCART_Rout_SOC
SCART_Lout_SOC

PCM_5V_CTL

SC_DET

CI_ADDR[0]
CI_ADDR[1]
CI_ADDR[2]
CI_ADDR[3]
CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]
CI_ADDR[8]
CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

TP307
TP308
TP309
TP310
TP311

TP312
TP313
TP314
TP315
TP316
TP317
TP318
TP319
TP320
TP321
TP322
TP323
TP324
TP325
TP326
TP327
TP328
TP329
TP330
TP331
TP332
TP333
TP334
TP335
TP336
TP337
TP338
TP339
TP340
TP341
TP342
TP343
TP344
TP345
TP346
TP347
TP348
TP349
TP350
TP351
TP352
TP353
TP354
TP355
TP356
TP357
TP358

TP359
TP360
TP361
TP362
TP363
TP364
TP365
TP366
TP367
TP368
TP369
TP370
TP371
TP372
TP373
TP374
TP375

TP377

TP378

AV1_CVBS_IN

2K

2K

+1.2V_MTK_AVDD

C350

0.1uF

For PCB Pattern

AV1_R_IN_SOC
AV1_L_IN_SOC

R334 51

T/C&AT&CHB

R335 51

T/C&AT&CHB

T/C&AT&CHB

R332 10K

Close to Tuner

C341

0.047uF
T/C&AT&CHB

For PCB Pattern

SC_R_IN_SOC
SC_L_IN_SOC

PC_R_IN_SOC
PC_L_IN_SOC

TUNER_SIF

DSUB_VSYNC_SOC

DSUB_HSYNC_SOC

C354

0.1uF

C347

0.1uF

SC_CVBS_IN_SOC

AV1_CVBS_IN_SOC

TU_CVBS

VDD3V3

R311 30K

R339

2.2K
OPT

MODEL_OPT_2

R310 30K

R338 0

C352 0.01uF

+1.2V_MTK_AVDD

C351

0.1uF

R341 100
R340 100

MODEL_OPT_8
MODEL_OPT_9

MODEL_OPT_10

GCLK_SOC
MCLK_SOC

GST_SOC

VCOM_DYN

PMIC_RESET

2D/3D_CTL

PCM_5V_CTL

EMMC_RST

C305

1uF
25V

C358

0.01uF
50V

VDD3V3

T/C&AT&CHB

R342 10K
C355

0.047uF
T/C&AT&CHB

Close to MT5369

OSCL2
OSDA2

EO_SOC

R343

24K
1%

R337 0

VDD3V3

C362

0.1uF

C363

1uF
25V

TP300

C360 0.047uF
C359 0.047uF

C361 1uF

VDD3V3

C364

0.1uF

C329

5pF
50V
OPT

C330

5pF
50V

OPT

C309
OPT

IF_AGC

R323

C336

10V

T/C&AT&CHB

C337 1uF

10V

T/C&AT&CHB

22

T/C&AT&CHB

1uF

T/C&AT&CHB

C312

C310

R325

OPT

R326

33pF

Close to MT5369

33pF

OPT

R324

22

F27
E27
F30
F29
B27
A27
B28
A28
C28
D28
E28
F28
B29

AG6
AJ6
AF6
AE6
AH7

AJ5
AG5
AF5
AE5
AH5

AG7

AU37
AU35
AT35
AT37
AU36
AP34
AT36
AR37
AR33
AP32
AR36
AP37
AR35
AP36

AL31
AJ28

AJ27

AN28

AU32
AT32

AD22

AL27

AM28
AJ26

U35
U34

AP31
AN30

V35
V34

AP28
AR29

AT30
AR30
AR31
AN29
AP30

AK24
AK25

AL25
AM26

ZD300

5.48VTO5.76V
ZD301

5.48VTO5.76V

AV1_L_IN

AV1_R_IN

LGE2112

TCON0
TCON1
TCON2
TCON3
TCON4
TCON5
TCON6
TCON7
TCON8
TCON9
TCON10
TCON11
TCON12

AVDD12_LVDS_1
AVDD12_LVDS_2
AVDD12_VPLL
AVDD33_LVDSB
AVDD33_LVDSA

AVSS12_LVDS_2
AVSS12_LVDS_1
AVSS12_VPLL
AVSS33_LVDSB
AVSS33_LVDSA

REXT_VPLL

AIN0_R_AADC
AIN0_L_AADC
AIN1_R_AADC
AIN1_L_AADC
AIN2_R_AADC
AIN2_L_AADC
AIN3_R_AADC
AIN3_L_AADC
AIN4_R_AADC
AIN4_L_AADC
AIN5_R_AADC
AIN5_L_AADC
AIN6_R_AADC
AIN6_L_AADC

AVDD33_AADC
AVSS33_AADC

VMID_AADC

MPXP

ADCINP_DEMOD
ADCINN_DEMOD

AVDD33_DEMOD

AVDD12_DEMOD

AVSS33_DEMOD
AVSS12_DEMOD

IF_AGC
RF_AGC

LOUTN
LOUTP

OSCL2
OSDA2

SC0
SY0

CVBS3P
CVBS2P
CVBS1P
CVBS0P
CVBS_COM

AVDD33_CVBS_1
AVDD33_CVBS_2

AVSS33_CVBS_1
AVSS33_CVBS_2

IC105

AVDD33_VDAC_BG

AVSS33_VDAC_BG

AVDD33_DAC1

AVSS33_DAC1

AVDD33_VDAC

AVSS33_VDAC

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

MID_MAIN_2

2011.12.19

9

+3.3V_NORMAL

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

BLM18PG121SN1D

C500
10uF

VDD3V3

L500

L501

BLM18PG121SN1D

POWER_ON/OFF1

VDD3V3

C503
10uF

60mA

C510

0.1uF

AVDD_33SB

C501

0.1uF

TP500

C504

2.2uF

+1.2V_MTK_CORE

+1.2V_MTK_CORE

+1.2V_MTK_CORE +1.2V_MTK_AVDD

+5V_NORMAL

C526
10uF
10V

C506

C524

10uF

10uF

C539

C543

10uF

0.1uF

L502

BLM18PG121SN1D

5600mA

C505
10uF

C546

0.1uF

C525
10uF

IC501

AP1117E33G-13

INADJ/GND

OUT

C529

0.1uF

C548

0.1uF

C502

0.1uF

C532

0.1uF

C550

0.1uF

DAC_3V3

C535

0.1uF

C552

0.1uF

R500
1

C540
10uF
10V

C553

0.1uF

C544

0.1uF
16V

+1.2V_MTK_CORE

AA14
AB14
AC14
AC19

AC15

AC16

AA23

IC105

LGE2112

AR7

VCCK_43

AT7

VCCK_45

AU7

VCCK_47

AP8

VCCK_42

AR8

VCCK_44

AT8

VCCK_46

AU8

VCCK_48

AM7

VCCK_37

AN7

VCCK_39

AP7

VCCK_41

AM8

VCCK_38

AN8

VCCK_40

P14

VCCK_1

R14

VCCK_9

T14

VCCK_11

U14

VCCK_13

V14

VCCK_14

W14

VCCK_16

Y14

VCCK_18
VCCK_20
VCCK_22
VCCK_23
VCCK_28

P15

VCCK_2
VCCK_24

P16

VCCK_3
VCCK_25

V23

VCCK_15

W23

VCCK_17

Y23

VCCK_19
VCCK_21

VCCK_31
VCCK_32
VCCK_36

VCCK_8
VCCK_10
VCCK_12
VCCK_33
VCCK_30

VCCK_7
VCCK_29

VCCK_6
VCCK_27

VCCK_5
VCCK_26

VCCK_4
VCCK_34
VCCK_35

VCC3IO_B_4
VCC3IO_B_2
VCC3IO_B_1
VCC3IO_B_3
VCC3IO_A_5
VCC3IO_A_7
VCC3IO_A_6
VCC3IO_A_8
VCC3IO_A_3
VCC3IO_A_4
VCC3IO_A_2
VCC3IO_A_1

AC22
AC23
AD24
P23
R24
T24
AC24
AC21
P20
AC20
P19
AC18
P18
AC17
P17
AD18
AD23

AL9
AK10
AK9
AK11
H29
J29
H30
J30
G31
G32
F33
E34

+1.2V_MTK_CORE

VDD3V3

AA15
AB15

AA16
AB16

AA17
AB17

R2
R3
J4
R4
Y4
F5
J5
R5
Y5
W5
L7
M7

R7
AA5
AB5

K7

U7

W7

E9

E8

F9
G14

J6
R15
T15
U15
V15
W15
Y15

H11
R16
T16
U16
V16
W16
Y16

R17
T17
U17
V17
Y17
T18
V18
Y18
T19
V19
Y19
W17

R18
AB6
H19
H22
J11
J12
J22

DVSS_51
DVSS_52
DVSS_37
DVSS_53
DVSS_107
DVSS_20
DVSS_38
DVSS_54
DVSS_108
DVSS_95
DVSS_44
DVSS_46
DVSS_56
DVSS_120
DVSS_130
DVSS_43
DVSS_77
DVSS_97
DVSS_13
DVSS_12
DVSS_22
DVSS_28
DVSS_39
DVSS_57
DVSS_68
DVSS_78
DVSS_87
DVSS_99
DVSS_112
DVSS_122
DVSS_132
DVSS_34
DVSS_58
DVSS_69
DVSS_79
DVSS_88
DVSS_100
DVSS_113
DVSS_123
DVSS_133
DVSS_59
DVSS_70
DVSS_80
DVSS_89
DVSS_114
DVSS_71
DVSS_90
DVSS_115
DVSS_72
DVSS_91
DVSS_116
DVSS_101
DVSS_124
DVSS_134
DVSS_60
DVSS_131
DVSS_35
DVSS_36
DVSS_40
DVSS_41
DVSS_42

IC105

LGE2112

DVSS_55
DVSS_62
DVSS_73
DVSS_83

DVSS_92
DVSS_104
DVSS_117
DVSS_127
DVSS_137

DVSS_29

DVSS_63

DVSS_74

DVSS_84

DVSS_93
DVSS_105
DVSS_118
DVSS_128
DVSS_138

DVSS_64

DVSS_75

DVSS_85

DVSS_94
DVSS_106
DVSS_119
DVSS_129
DVSS_139

DVSS_65

DVSS_76

DVSS_86
DVSS_140

DVSS_96

DVSS_30

DVSS_27
DVSS_109

DVSS_17

DVSS_25

DVSS_45

DVSS_66

DVSS_7

DVSS_14

DVSS_8
DVSS_18
DVSS_26
DVSS_33

DVSS_136
DVSS_126

DVSS_49

DVSS_103

DVSS_82
DVSS_61

DVSS_110
DVSS_135
DVSS_125
DVSS_102

DVSS_81

DVSS_121

DVSS_47
DVSS_67
DVSS_98

DVSS_111

DVSS_11
DVSS_21

R6
R20
T20
U20
V20
W20
Y20
AA20
AB20
G16
R21
T21
U21
V21
W21
Y21
AA21
AB21
R22
T22
U22
V22
W22
Y22
AA22
AB22
R23
T23
U23
AB23
W6
G17
F25
Y6
E21
F21
L8
T7
D11
E11
D12
E22
F22
G25
AB19
AA19
P22
W19
U19
R19
Y7
AB18
AA18
W18
U18
AA7
N22
T8
W8
Y8
E7
F8

+3.3V_NORMAL

3.3V_EMMC

L504
BLM18PG121SN1D

C512

0.1uF
16V

+3.3V_NORMAL

EMMC_VCCQ

L506
BLM18PG121SN1D

C522

0.1uF
16V

LAN_JACK_POWER

TP501

SMD Gaskit

LAN RGB COMP

M501

M500

SMD_GASKIT_8.5T_LAN

M503

MDS62110217

SMD_GASKIT_12.5T_HDMI2

MDS62110209

MDS62110209

SMD_GASKIT_8.5T_RGB

HDMI2~3HDMI1~2 USB1~2 USB3

M504

MDS62110217

SMD_GASKIT_12.5T_USB1

SMD_GASKIT_12.5T_USB3

M502

MDS62110209

SMD_GASKIT_8.5T_COMP

M506

M505

MDS62110217

MDS62110217

SMD_GASKIT_12.5T_HDMI1

DECAP FOR SOC (HIDDEN - UCC) DECAP FOR SOC (BOTTOM)

+1.2V_MTK_CORE

+1.5V_DDR

C508

0.1uF

C514

0.1uF

C520

0.1uF

C523

0.1uF

C527

0.1uF

+1.2V_MTK_CORE

C531

0.1uF

+1.5V_DDR

C533

0.1uF

C536

0.1uF

C537

0.1uF

C545

0.1uF

C547

0.1uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

MID_MAIN_3

2011.12.09

10

K4B2G1646C-HCK0

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

IC701-*2

RVREF_A

RVREF_B

+1.5V_DDR

+1.5V_DDR

R730
1K
1%

R731
1K
1%

R732
1K
1%

R733
1K
1%

+1.5V_DDR

+1.5V_DDR

C750

0.1uF

C745

0.1uF

RVREF_A

C746

0.1uF

C747

0.1uF

C748

0.1uF

C749

0.1uF

RVREF_B

ARA[0-14]

C752

0.1uF

C751

0.1uF

ARCKE

ARCLK1

/ARCLK1

ARCLK0

/ARCLK0

ARODT
/ARRAS
/ARCAS

/ARCS

/ARWE

ARREST

ARBA0

ARBA1

ARBA2

C754

0.1uF

C753

0.1uF

+1.5V_DDR

TP700
TP701

ARA[14]
ARA[13]
ARA[12]
ARA[11]
ARA[10]
ARA[9]
ARA[8]
ARA[7]
ARA[6]
ARA[5]
ARA[4]
ARA[3]
ARA[2]
ARA[1]
ARA[0]

C756

0.1uF

C755

0.1uF

C758

0.1uF

C757

0.1uF

LGE2112

AC1

DDRV_44

AC2

DDRV_45

A3

DDRV_1

A4

DDRV_2

B4

DDRV_5

C4

DDRV_8

D4

DDRV_10

B3

DDRV_4

C3

DDRV_7

AC3

DDRV_46

AC4

DDRV_47

G10

MEMTP

G9

MEMTN

G13

RVREF_B

G21

RVREF_A

F10

ARCKE

D9

ARCLK1

C9

ARCLK1

A20

ARCLK0

A21

ARCLK0

E18

ARODT

F17

ARRAS

E17

ARCAS

E16

ARCS

D14

ARWE

B14

ARRESET

A13

ARBA0

G11

ARBA1

D16

ARBA2

F18

ARCSX

C15

ARA14

A15

ARA13

F13

ARA12

C14

ARA11

F11

ARA10

E15

ARA9

D13

ARA8

B15

ARA7

E14

ARA6

F16

ARA5

E13

ARA4

B13

ARA3

A14

ARA2

F14

ARA1

F15

ARA0

IC105

1uF

C702
1uF

ARDQM0
ARDQS0
ARDQS0

ARDQ0
ARDQ1
ARDQ2
ARDQ3
ARDQ4
ARDQ5
ARDQ6
ARDQ7

ARDQM1
ARDQS1
ARDQS1

ARDQ8

ARDQ9
ARDQ10
ARDQ11
ARDQ12
ARDQ13
ARDQ14
ARDQ15

ARDQM2
ARDQS2
ARDQS2
ARDQ16
ARDQ17
ARDQ18
ARDQ19
ARDQ20
ARDQ21
ARDQ22
ARDQ23

ARDQM3
ARDQS3
ARDQS3
ARDQ24
ARDQ25
ARDQ26
ARDQ27
ARDQ28
ARDQ29
ARDQ30
ARDQ31

AVDD33_MEMPLL
AVSS33_MEMPLL

DVSS_50
DVSS_48

10uF
10V

C704
10uF
10V

C19

ARDQM0

C21

ARDQS0

B21
C23
B17
D23
C17
D24
C16
C24
D15

D21
B20
C20
A17
A23
D17
B23
D20
D22
D19
C22

A7
B9
A9
C12
D6
B12
C5
C13
A5
A12
B5

E10
C8
D8
C6
D10
D7
C11
C7
C10
B7
B10

N14
N15

R1
P21

/ARDQS0

ARDQM1
ARDQS1
/ARDQS1

ARDQM2
ARDQS2
/ARDQS2

ARDQM3
ARDQS3
/ARDQS3

AVDD3V3_MEMPLL

AVDD3V3_MEMPLL

0.1uF

ARDQ[0-7]

ARDQ[8-15]

ARDQ[16-23]

ARDQ[24-31]

+3.3V_NORMAL

L700

BLM18PG121SN1D

C700

C701

C703

IC701

H5TQ2G63BFR-PBC

R710

ARA[14]

A_RVREF4

A_RVREF1

+1.5V_DDR

A10/AP

A12/BC

RESET

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

ARA[10]

L7

ARA[11]

R7

A11

ARA[12]

N7

ARA[13]

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

VREFCA

H1

VREFDQ

1%
240

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

DDR_HYNIX

+1.5V_DDR

A_RVREF1

C713

R706

0.1uF
1K
1%

R707
1K

C714

1%

0.1uF

+1.5V_DDR

A_RVREF4

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

DDR_SS

IC701-*1

NT5CB128M16BP-DI

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_7

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

DDR_NANYA

C715

R708

0.1uF
1K
1%

R709
1K

C716

1%

0.1uF

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

NC_6

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

ARA[0]
ARA[1]
ARA[2]
ARA[3]
ARA[4]
ARA[5]
ARA[6]
ARA[7]
ARA[8]
ARA[9]

ARBA0
ARBA1
ARBA2

ARCKE

/ARCS
ARODT
/ARRAS
/ARCAS
/ARWE

ARREST

ARDQS0
/ARDQS0

ARDQS1
/ARDQS1

ARDQM0
ARDQM1

ARA[0-13]

ARCLK0

R712
100
5%

/ARCLK0

ARDQ[0-7]

ARDQ[8-15]

ARCLK1

/ARCLK1

ARDQ[16-23]

ARDQ[24-31]

ARA[0-13]

R714
100
5%

/ARRAS
/ARCAS

ARREST

ARDQS2

/ARDQS2

ARDQS3

/ARDQS3

ARDQM2

ARDQM3
ARDQ[16]
ARDQ[17]
ARDQ[18]
ARDQ[19]
ARDQ[20]
ARDQ[21]
ARDQ[22]
ARDQ[23]

ARDQ[24]
ARDQ[25]
ARDQ[26]
ARDQ[27]
ARDQ[28]
ARDQ[29]
ARDQ[30]
ARDQ[31]

ARBA0
ARBA1
ARBA2

ARCKE

/ARCS
ARODT

/ARWE

ARA[0]
ARA[1]
ARA[2]
ARA[3]
ARA[4]
ARA[5]
ARA[6]
ARA[7]
ARA[8]
ARA[9]
ARA[10]
ARA[11]
ARA[12]
ARA[13]

IC703

H5TQ2G63BFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

DDR_HYNIX

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

A_RVREF2

M8

A_RVREF3

H1

1%

240

R716

L8

ZQ

+1.5V_DDR

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

ARA[14]

NC_6

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

A_RVREF2

A_RVREF3

+1.5V_DDR

+1.5V_DDR

IC703-*1

NT5CB128M16BP-DI

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

NC_6

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

DDR_NANYA

C735

R720

0.1uF
1K
1%

R721
1K

C736

1%

0.1uF

C733

R718

0.1uF
1K
1%

R719
1K

C734

1%

0.1uF

IC703-*2

K4B2G1646C-HCK0

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_7

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

L8

R8

ZQ

A6

R2

A7

T8

A8

B2

R3

VDD_1

A9

D9

L7

VDD_2

A10/AP

G7

R7

VDD_3

A11

K2

N7

VDD_4

A12/BC

K8

T3

VDD_5

A13

N1

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

C7

A9

DQSU

VSS_1

B3

B7

DQSU

VSS_2

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

DDR_SS

+1.5V_DDR

C707

C705

C718

0.1uF

C720

0.1uF

C722

0.1uF

C724

0.1uF

C726

0.1uF

C728

0.1uF

10uF

1uF

10V

+1.5V_DDR

C708

C727

0.1uF

BRCLK1

/BRCLK1

C706
1uF

BRDQ[16-23]

BRDQ[24-31]

10uF
10V

IC704

BRA[0-13]

R715

100

5%

/BRRAS
/BRCAS

BRREST

BRDQS2

/BRDQS2

BRDQS3

/BRDQS3

BRDQM2

BRDQM3
BRDQ[16]
BRDQ[17]
BRDQ[18]
BRDQ[19]
BRDQ[20]
BRDQ[21]
BRDQ[22]
BRDQ[23]

BRDQ[24]
BRDQ[25]
BRDQ[26]
BRDQ[27]
BRDQ[28]
BRDQ[29]
BRDQ[30]
BRDQ[31]

BRBA0
BRBA1
BRBA2

BRCKE

/BRCS
BRODT

/BRWE

BRA[0]
BRA[1]
BRA[2]
BRA[3]
BRA[4]
BRA[5]
BRA[6]
BRA[7]
BRA[8]
BRA[9]
BRA[10]
BRA[11]
BRA[12]
BRA[13]

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

H5TQ2G63BFR-PBC

B_RVREF8

M8

B_RVREF7

H1

1%

240

R717

L8

ZQ

+1.5V_DDR

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

BRA[14]

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

DDR_HYNIX

B_RVREF7

B_RVREF8

+1.5V_DDR

+1.5V_DDR

NT5CB128M16BP-DI

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

NC_6

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

DDR_NANYA

IC704-*1

C739

R724

0.1uF
1K
1%

R725
1K

C740

1%

0.1uF

C737

R722

0.1uF
1K
1%

R723
1K

C738

1%

0.1uF

IC704-*2

K4B2G1646C-HCK0

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

L8

R8

ZQ

A6

R2

A7

T8

A8

B2

R3

VDD_1

A9

D9

L7

VDD_2

A10/AP

G7

R7

VDD_3

A11

K2

N7

VDD_4

A12/BC

K8

T3

VDD_5

A13

N1

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_7

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

DDR_SS

+1.5V_DDR

RVREF_C

C741

R726

0.1uF
1K
1%

R727
1K

C742

1%

0.1uF

+1.5V_DDR

RVREF_D

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

C743

R728

0.1uF
1K
1%

R729
1K

C744

1%

0.1uF

BRA[0-14]

RVREF_D

RVREF_C

BRCLK0

/BRCLK0

BRCLK1

/BRCLK1

BRCKE

BRODT
/BRRAS
/BRCAS

/BRCS

BRBA0

BRBA1

BRBA2

/BRWE
BRA[14]
BRA[13]
BRA[12]
BRA[11]
BRA[10]
BRA[9]
BRA[8]
BRA[7]
BRA[6]
BRA[5]
BRA[4]
BRA[3]
BRA[2]
BRA[1]
BRA[0]

+1.5V_DDR

IC105

LGE2112

P13

RVREF_C

V7

RVREF_D

F4

BRCLK0

F3

BRCLK0

V4

BRCLK1

V3

BRCLK1

P6

BRCKE

H6

BRODT

H4

BRRAS

H5

BRCAS

K3

BRCS

N1

BRBA0

P5

BRBA1

K4

BRBA2

L4

BRWE

L5

BRA14

M4

BRA13

N5

BRA12

M5

BRA11

P4

BRA10

M3

BRA9

L6

BRA8

L3

BRA7

N4

BRA6

K5

BRA5

N6

BRA4

N2

BRA3

M1

BRA2

N3

BRA1

K6

BRA0

G5

BRCSX

D5

DDRV_11

E5

DDRV_13

T5

DDRV_38

V5

DDRV_42

U5

DDRV_40

E6

DDRV_14

F6

DDRV_18

G6

DDRV_23

U6

DDRV_41

T6

DDRV_39

AC5

DDRV_48

F7

DDRV_19

G7

DDRV_24

AC6

DDRV_49

N7

DDRV_36

P7

DDRV_37

V6

DDRV_43

J10

DDRV_35

H10

DDRV_32

H13

DDRV_33

E20

DDRV_15

F20

DDRV_20

G20

DDRV_27

G15

DDRV_25

G18

DDRV_26

D25

DDRV_12

C25

DDRV_9

B25

DDRV_6

A25

DDRV_3

H7

DDRV_30

H8

DDRV_31

J8

DDRV_34

BRDQM0
BRDQS0
BRDQS0

BRDQ0
BRDQ1
BRDQ2
BRDQ3
BRDQ4
BRDQ5
BRDQ6
BRDQ7

BRDQM1
BRDQS1
BRDQS1

BRDQ8

BRDQ9
BRDQ10
BRDQ11
BRDQ12
BRDQ13
BRDQ14
BRDQ15

BRDQM2
BRDQS2
BRDQS2
BRDQ16
BRDQ17
BRDQ18
BRDQ19
BRDQ20
BRDQ21
BRDQ22
BRDQ23

BRDQM3
BRDQS3
BRDQS3
BRDQ24
BRDQ25
BRDQ26
BRDQ27
BRDQ28
BRDQ29
BRDQ30
BRDQ31

BRRESET

DDRV_16
DDRV_22
DDRV_29
DDRV_21
DDRV_28
DDRV_17
DVSS_15
DVSS_23

DVSS_1
DVSS_3
DVSS_5
DVSS_9

DVSS_16
DVSS_24
DVSS_31
DVSS_32
DVSS_19

DVSS_2
DVSS_4
DVSS_6

DVSS_10

G2

BRDQM0

E4

BRDQS0

E3

/BRDQS0

A1
J1
B2
J2
C2
K1
A2
K2

D1

BRDQM1

F1

BRDQS1

F2

/BRDQS1

J3
B1
H3
D3
G3
C1
G4
D2

Y1

BRDQM2

V2

BRDQS2

V1

/BRDQS2

T4
AB4
P2
AB3
P3
AB1
P1
AB2

U1

BRDQM3

W3

BRDQS3

W4

/BRDQS3

AA3
U4
AA4
T3
Y3
U3
Y2
U2

M2

BRREST

E23
F24
G24
F23
G23
E24
E12
F12
A18
B18
C18
D18
E19
F19
G19
G22
E25
A26
B26
C26
D26

BRDQ[0-7]

BRDQ[8-15]

BRDQ[16-23]

BRDQ[24-31]

+1.5V_DDR

K4B2G1646C-HCK0

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

IC702-*2

C719

0.1uF

BRA[0-13]

R713
100
5%

C721

0.1uF

BRDQ[0-7]

BRDQ[8-15]

0.1uF

BRCLK0

/BRCLK0

C725

0.1uF

C717

0.1uF

IC702

+1.5V_DDR

M8

H1

1%
240

L8

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

H5TQ2G63BFR-PBC

VREFCA

VREFDQ

ZQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

DDR_HYNIX

A10/AP

A12/BC

RESET

BRA[0]

N3

A0

BRA[1]

P7

A1

BRA[2]

P3

A2

BRA[3]

N2

A3

BRA[4]

P8

A4

BRA[5]

P2

A5

BRA[6]

R8

A6

BRA[7]

R2

A7

BRA[8]

T8

A8

BRA[9]

R3

A9

BRA[10]

L7

BRA[11]

R7

A11

BRA[12]

N7

BRA[13]

T3

A13

M7

A15

M2

BA0
BA1
BA2

CK
CK

CKE

CS
ODT
RAS
CAS

WE

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BRBA0

N8

BRBA1

M3

BRBA2

J7
K7
K9

BRCKE

L2

/BRCS

K1

BRODT

J3

/BRRAS

K3

/BRCAS

L3

/BRWE

T2

BRREST

F3

BRDQS0

G3

/BRDQS0

C7

BRDQS1

B7

/BRDQS1

E7

BRDQM0

D3

BRDQM1

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B_RVREF6

B_RVREF5

R711

B_RVREF5

+1.5V_DDR

C709

R702

0.1uF
1K
1%

R703
1K

C710

1%

0.1uF

+1.5V_DDR

B_RVREF6

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

DDR_SS

R704
1K
1%

R705
1K
1%

IC702-*1

NT5CB128M16BP-DI

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_7

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

DDR_NANYA

C711

0.1uF

C712

0.1uF

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

NC_6

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

BRA[14]

C723

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

2011.12.09

DDR ONE SIDE 12

FROM LIPS & POWER B/D

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

+3.5V_ST

+12V

C2401

0.1uF

+3.5V_ST

RL_ON

L2402

CIS21J121

C2406

0.1uF
16V

L2401

CIS21J121

50V

#16/#20/#23
LD - GND OR USE
LE(N.L.D.) - OPEN
LE(L.D.) - USE

R2401

10K

R2408

10K

MMBT3906(NXP)

Q2401

3

1

2

PWM_DIM2

PWR ON

3.5V

3.5V

GND/P.DIM2

24V
GND
GND

GND
GND
12V
12V
12V

OPT
P2400
FW20020-24S

1

1
3

3
5

5
7

7
9

9
11

11
13

13
15

15
17

17
19

19
21

21 22
23

23 24

25

SMAW200-H24S2

P2401

2

2
4

4
6

6
8

8

10

10
12

12
14

14
16

16
18

18
20

20
22
24

24V
24V
GND
GND

3.5V

3.5V
GND
GND/V-sync
INV ON
A.DIM
P.DIM1
Err OUT

L2403

CIS21J121

R2420

0

POWER_16_GND

C2413

0.1uF

R2423 0

POWER_16_VSYNC

0

R2422

50V

L/DIM0_VS

POWER_24_GND

R2405

POWER_24_ERROR_OUT

+24V

+3.3V_NORMAL

22

R2425
100

A_DIM

PWM_DIM1

R2424

4.7K
OPT

ERROR_OUT

+3.3V_NORMAL

R2426
1K

INV_CTL

+12V

L2408

BLM18SG121TN1D

C2432

0.01uF
50V

PANEL_CTL

PANEL_POWER

C2433

0.1uF
50V

R2437
10K

33K

R2442-*1

5.6K

R2441-*1

10K

R2442

MTK_NON_EPI

1.8K

R2441

C

MTK_NON_EPI

B

E

MTK_EPI

C2435

4.7uF
50V

MTK_EPI

Q2406
MMBT3904(NXP)

Q2407

AO3407A

S

TYP 1450mA

PANEL_VCC

D

G

C2440

1uF
25V
OPT

R2451

PANEL_DISCHARGE_REG

C2443

2K

2K

0.1uF

1/8W

1/8W

R2452

50V

PANEL_DISCHARGE_REG

Power_DET

On-semi

+12V

L2400

BLM18PG121SN1D

Placed on SMD-TOP

C2400

C2402

10uF

10uF

16V

16V

C2403

0.1uF
16V
OPT

+12V

+3.5V_ST

OPT

+24V

IC2400

AOZ1038PI

1

2

3

4

THERMAL

R2412

8.2K
5%
OPT

R2411

1.5K
1%

OPT

9

R2413
0
5%

[EP]LX

*NOTE 17

NC_2

8

OPT

R24000

NC_1

7

EN

6

R2402

3.3K

COMP

5

C2404

0.1uF
16V

R2410

2.7K
1%

R2409

1.2K
1%

PGND

VIN

AGND

FB

Vout=0.8*(1+R1/R2)

C2411

0.1uF
16V

C2410

0.1uF
50V
OPT

C2405

4700pF

50V

R2403

VCC

VCC

10K

R2417
100K

IC2402

NCP803SN293

3

GND

R2416
100K

IC2401

NCP803SN293

3

GND

L2404

2uH

POWER_ON/OFF1

+3.5V_ST

R2421
10K
OPT

R2419

RESET

2

1

OPT

OPT

RESET

2

1

100

R2418
100

OPT

POWER_DET

C2412

0.1uF
16V

not to RESET at 8kV ESD

24V-->3.48V
12V-->3.58V

ST_3.5V-->3.5V

+12V

L2407
BLM18PG121SN1D

C2415
10uF
16V

+5V_Normal

POWER_ON/OFF2_3

1%

R1

R2415

56K

C2416
100pF

50V

R2439

10K

R2

1%

DEV_DCDC_TPS54327

IC2404

VREG5

C2428
3300pF
50V

VFB

TPS54327DDAR

EN

1

2

3

SS

4

3A

R2435

10K

C24001

0.1uF
16V

C2417
1uF
10V

9

THERMAL

8

7

6

5

[EP]GND

VIN

VBST

SW

GND

C2429

0.1uF
16V

L2409

3.6uH

NR8040T3R6N

+5V_NORMAL

C2430
22uF
10V

+3.3V_NORMAL

+3.5V_ST

L2413

BLM18PG121SN1D

CN

L2412

BLM18PG121SN1D

NON_CN

+3.3V_TU_IN

C2436

0.1uF
16V

POWER_ON/OFF1

POWER_ON/OFF2_1
POWER_ON/OFF2_2
POWER_ON/OFF2_3
POWER_ON/OFF2_4

DDR MAIN 1.5V

C2407
10uF
10V

C2408
10uF
10V

C2409
10uF
10V

C2414
10uF
10V

C2441
3300pF
50V
OPT

R2404

R2406

10K

1%

5.6K

1%

R2

+1.2V_MTK_CORE

R1

10K

R2430

+3.5V_ST

L2405

C2448
10uF
10V

BLM18PG121SN1D

C2418

C2419

10uF

0.1uF

10V

16V

VIN_1

VIN_2

GND_1

GND_2

VIN_3

EP[GND]

1

THERMAL

2

3

TPS54319TRE

4

3A

5

AGND

15EN16

17

IC2403

6

VSENSE

3A

Vout=0.827*(1+R1/R2)=1.521V

C2420

0.1uF
16V

7

COMP

BOOT14PWRGD

13

12

11

10

9

8

RT/CLK

1/16W 5%

$ 0.145

POWER_ON/OFF2_1

C2423

0.1uF

16V

PH_3

PH_2

PH_1

C2422

SS/TR

0.01uF
50V

R2432

330K1/16W 5%

C2421

R2431

4700pF

15K

L2406

3.6uH

NR8040T3R6N

50V

C2424
10uF
10V

C2425
10uF

10V

C2446
10uF

10V

C2447
10uF
10V

R2433
56K
1/16W
1%

R2434

R1

47K 1%

R2

+1.5V_DDR

C2426
100pF
50V

C2427

0.1uF
16V

+12V

L2410

BLM18PG121SN1D

C2431
10uF
16V

+3.3V_NORMAL

VIN2

VIN1

VBST

PGND2

PGND1

SW2

SW1

IC2405

TPS54425PWPR

14

13

12

4A

11

10

9

8

THERMAL

15

C2434

0.1uF
50V

[EP]PGND

1

2

3

4

5

6

7

+3.3V_NORMAL

VO

VFB

VREG5

SS

GND

PG

EN

R2407
100K

Vout=(0.763+0.0017*Vout.set)*(1+R1/R2)

C2438
1uF
10V

R2414 10K
C2437

0.1uF

R1

C2439
3300pF
50V

POWER_ON/OFF2_2

L2411

2uH

C2442
22uF
10V

MAX 3.4 A

R2

R2427
33K
1%

C2444
22uF
10V

R2428
10K

1%

C2445
22pF
50V

+3.3V_NORMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

MID_POWER

2011.11.25

24

Renesas MICOM

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

For Debug

+3.5V_ST

MICOM_DEBUG

P3000

12507WS-12L

1

2

3

4

5

6

7

8

9

10

11

12

13

GP4 High/MID Power SEQUENCE

POWER_ON/OFF!

POWER_ON/OFF2_1

POWER_ON/OFF2_2

POWER_ON/OFF2_3

POWER_ON/OFF2_4

SOC_RESET

MICOM MODEL OPTION

MICOM_MHL

MICOM_GED

R3016 10K

R3020 10K

MICOM_GP4_10PIN

R3030 10K

Don’t remove R3014,
not making float P40

R3014 1K

R3011 10K

MICOM_DEBUG

+3.5V_ST

MICOM_PDP

R3007 10K

R3005 10K

MICOM_JAPAN

MICOM_TOUCH_KEY

R3009 10K

R3012 10K

MICOM_DIIVA

MICOM_DEBUG

MICOM_RESET

R3005-*1

56K

R3005-*2

22K

MICOM_OLED_FRC

MICOM_OLED_MAIN

MODEL1_OPT_0
MODEL1_OPT_1
MODEL1_OPT_2
MODEL1_OPT_3
MODEL1_OPT_4

MODEL1_OPT_5
MODEL1_OPT_6

MICOM MODEL OPTION

10

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

NON DIVA

NON JAPAN

TACT_KEY

LCD

/ OLED

IR Wafer
12/15Pin

(GP3_Soft touch)

NON_MHL

NON_GED

DIVA

JAPAN

TOUCH_KEY

PDP

IR Wafer

10Pin

(GP4_TOOL)

MHLMODEL_OPT_5

GEDMODEL_OPT_6

POWER_ON/OFF2_3

For China

For JAPAN

For Sample Set

GP4_HIGH

I2C_SCL3

I2C_SDA3

AMP_RESET_N

PANEL_CTL

MODEL1_OPT_5

HDMI_CEC

POWER_ON/OFF2_2

POWER_ON/OFF2_3

EEPROM_SDA

EEPROM_SCL

MODEL1_OPT_6

AMP_RESET_BY_MICOM

IR

+3.5V_ST

R3018

3.3K

+3.3V_NORMAL

R3032

10K

R3033

10K

R3003 22

AMP_RESET_BY_MICOM

P31/TI03/TO03/INTP4

P75/KR5/INTP9/SCK01/SCL01

P74/KR4/INTP8/SI01/SDA01

P71/KR1/SI21/SDA21

P70/KR0/SCK21/SCL21

P30/INTP3/RTC1HZ/SCK11/SCL11

R3019

3.3K

FLG_POD_DR

POD_WAKEUP_N

/RST_DIIVA

/RST_DIIVA

POD_WAKEUP_N

FLG_POD_DR

for DiiVA

+3.5V_ST

C3000

0.1uF

P60/SCLA0
P61/SDAA0

P62
P63

P73/KR3/SO01
P72/KR2/SO21

+3.3V_NORMAL

R3035

4.7K
OPT

8pF

C3002

X3000

32.768KHz

R3002 22

MICOM_DIIVA

R3001 22

MICOM_DIIVA

GND

C3001 0.47uF

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

VSS

VDD

43

44

45

46

47

48

1
2
3
4
5
6
7
8

IC3000

R5F100GEAFB

MICOM

9
10
11
12

13

14

15

16

17

18

P17/TI02/TO02

P51/INTP2/SO11

P16/TI01/TO01/INTP5

P50/INTP1/SI11/SDA11

P14/RXD2/SI20/SDA20

P15/PCLBUZ1/SCK20/SCL20

R30 22 10 K

10K

R3000

C3003 8pF

MICOM_DEBUG

R3023

4.7M
OPT

MICOM_RESET

R3024 22

P40/TOOL0

RESET

P124/XT2/EXCLKS

P123/XT1

39

40

41

42

19

20

21

22

COMMERCIAL_12V_CTL

P41/TI07/TO07

38

23

+3.5V_ST

10K

C3004

0.1uF
16V

R3026

R3027

R3025 22

MICOM_DIIVA

P120/ANI19

37

P140/PCLBUZ0/INTP6

36

P00/TI00/TXD1

35

P01/TO00/RXD1

34

P130

33

P20/ANI0/AVREFP

32

P21/ANI1/AVREFM

31

P22/ANI2

30

P23/ANI3

29

P24/ANI4

28

P25/ANI5

27

P26/ANI6

26

P27/ANI7

25

24

P146

P147/ANI18

P13/TXD2/SO20

P10/SCK00/SCL00

P12/SO00/TXD0/TOOLTXD

P11/SI00/RXD0/TOOLRXD/SDA00

12V_EXT_PWR_DET

HDMI_WAUP:HDMI_INIT

MICOM_RESET_SW

SW3000

JTP-1127WEM

12

4 3

270K

OPT

POWER_ON/OFF2_4

RL_ON





SCART_MUTE

POWER_ON/OFF2_4

KEY2

KEY1

MODEL1_OPT_2

MODEL1_OPT_1

MODEL1_OPT_0

MODEL1_OPT_4

MODEL1_OPT_3

For Japan:LNB_INIT

EXT_AMP_MUTE

EXT_AMP_RESET

COMMERCIAL_12V_CTL

12V_EXT_PWR_DET

SCART_MUTE

+3.3V_NORMAL

+3.3V_NORMAL

R3036

10K
OPT

R3037

10K

OPT

POWER_ON/OFF2_1

SIDE_HP_MUTE

R3006 10K

R3008 10K

R3010 10K

R3021 10K

R3017 10K

MICOM_NON_MHL

MICOM_NON_GED

R3031 10K

MICOM_LCD/OLED

MICOM_GP3_12/15PIN

MICOM_TACT_KEY

R3013 10K

MICOM_NON_JAPAN

MICOM_NON_DIIVA

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Eye Sensor Option

MODEL_OPT_4

MODEL_OPT_2

0

1

0

N/A

CM3231_CAPELLA

(GP3 Soft touch) (GP4 Soft touch)

1

MC8101_ABOV

(TACT_KEY)

CM3231_CAPELLA

POWER_ON/OFF1

+3.3V_NORMAL

R3034

4.7K
OPT

LOGO_LIGHT

LOGO_LIGHT

POWER_DET

SOC_RESET

LED_B/GP4_LED_R

C

B

E

INV_CTL

SOC_TX

Q3000
MMBT3904(NXP)

EDID_WP

SOC_RX

AMP_MUTE

EXT_AMP_MUTE

EDID_WP

EXT_AMP_RESET

CEC_REMOTE

MICOM

D3000

BAT54_SUZHO

D

For CEC

R3028
27K

G

Q3001-*1
SI1012CR-T1-GE3

S

HDMI_CEC_FET_VISHAY

+3.5V_ST

G

D

Q3001
RUE003N02

HDMI_CEC_FET_ROHM

R3029
120K

S

HDMI_CEC

2011.12.12

30

BODY_SHIELD

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

GND

20

19

18

17

16

15

14

13

12

11
10

EAG62611201

RSD-105156-100

JK3301

9

8

7

6

5

4

3

2

1

HP_DET

5V

GND

DDC_DATA

DDC_CLK

ARC

CE_REMOTE

CK-

CK_GND

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

R33 00

0

CK-_HDMI4_JACK

CK+_HDMI4_JACK

D0-_HDMI4_JACK

D0+_HDMI4_JACK

D1-_HDMI4_JACK

D1+_HDMI4_JACK

D2-_HDMI4_JACK

D2+_HDMI4_JACK

5V_HDMI_4_JACK

R3308 100

R3309 100

CEC_REMOTE

Q3301

R3307
100K

MMBT3904(NXP)

R3310

1K

C

B

E

DDC_SDA_4_JACK

DDC_SCL_4_JACK

R3312

4.7K

R3311
1K

HDMI_ARC

UI : HDMI1

HDMI_HPD_4_JACK

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11
10

EAG62611201

JK3303

RSD-105156-100

9

8

7

6

5

4

3

2

1

HP_DET

5V

GND

DDC_DATA

DDC_CLK

NC

CE_REMOTE

CK-

CK_GND

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

5V_HDMI_3_JACK

R3327

100K

MMBT3904(NXP)

R3328 100

R3329 100

C

Q3303

E

DDC_SDA_3_JACK

DDC_SCL_3_JACK

CEC_REMOTE

CK-_HDMI3_JACK

CK+_HDMI3_JACK

D0-_HDMI3_JACK

D0+_HDMI3_JACK

D1-_HDMI3_JACK

D1+_HDMI3_JACK

D2-_HDMI3_JACK

D2+_HDMI3_JACK

R3330

1K

R3331
1K

B

UI : HDMI3

R3336

4.7K

HDMI_HPD_3_JACK

E0

E1

E2

VSS

IC3300

M24C02-RMN6T

1

2

HDMI_EXT_EDID

3

4

5V_HDMI_1_SOC

VCC

8

WC

7

SCL

6

SDA

5

EDID_WP

R3319
22

HDMI_EXT_EDID

R3320
22

HDMI_EXT_EDID

C3300

0.1uF
16V

R3323
47K

+5V_NORMAL

A2CA1
MMBD6100
D3300

R3325
47K

DDC_SCL_1_SOC

DDC_SDA_1_SOC

5V_HDMI_3_JACK

C3302

0.1uF
16V

R3337
47K

+5V_NORMAL

A2CA1
MMBD6100
D3302

R3339
47K

DDC_SCL_3_JACK

DDC_SDA_3_JACK

BODY_SHIELD

20

EAG62611201

JK3302

RSD-105156-100

19

18

17

16

15

14

13

12

11
10

9

8

7

6

5

4

3

2

1

HP_DET

5V

GND

DDC_DATA

DDC_CLK

NC

CE_REMOTE

CK-

CK_GND

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

5V_HDMI_2_JACK

R3313

MMBT3904(NXP)

100K

R3314 100

R3315 100

CEC_REMOTE

CK-_HDMI2_JACK

CK+_HDMI2_JACK

D0-_HDMI2_JACK

D0+_HDMI2_JACK

D1-_HDMI2_JACK

D1+_HDMI2_JACK

D2-_HDMI2_JACK

D2+_HDMI2_JACK

C

Q3302

E

DDC_SCL_2_JACK

R3316

R3317
1K

R3318

1K

B

UI : HDMI2

4.7K

HDMI_HPD_2_JACK

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11
10

EAG62611201

JK3300

RSD-105156-100

9

8

7

6

5

4

3

2

1

HP_DET

5V

GND

DDC_DATA

DDC_CLK

NC
CE_REMOTE

CK-

CK_GND

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

5V_HDMI_1_SOC

R3301

MMBT3904(NXP)

100K

R3302 100

R3303 100

CEC_REMOTE

CK-_HDMI1_SOC

CK+_HDMI1_SOC

D0-_HDMI1_SOC

D0+_HDMI1_SOC

D1-_HDMI1_SOC

D1+_HDMI1_SOC

D2-_HDMI1_SOC

D2+_HDMI1_SOC

C

Q3300

E

DDC_SDA_1_SOCDDC_SDA_2_JACK

DDC_SCL_1_SOC

R3304

1K

R3306

4.7K
HDMI_INTERNAL_EDID

R3305
1K

B

R3321

4.7K
HDMI_EXT_EDID

UI : HDMI4

HDMI_HPD_1_SOC

5V_HDMI_2_JACK

C3301

0.1uF
16V

R3324
47K

+5V_NORMAL

A2CA1
MMBD6100
D3301

R3326
47K

DDC_SCL_2_JACK

DDC_SDA_2_JACK

5V_HDMI_4_JACK

C3303

0.1uF
16V

R3338
47K

+5V_NORMAL

A2CA1
MMBD6100
D3303

R3340
47K

DDC_SCL_4_JACK

DDC_SDA_4_JACK

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

HDMI 4

2011.10.29

33

RGB/ PC AUDIO/ SPDIF

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

RGB PC

DSUB_VSYNC

DSUB_HSYNC

DSUB_R+

DSUB_B+

DSUB_G+

M24C02-RMN6T

E0

E1

E2

VSS

1

RGB_EDID

2

3

4

IC3600

D3615
30V
OPT

D3616
30V

OPT

RGB_5V

VCC

8

WC

7

SCL

6

SDA

5

Closed to JACK

C3633

18pF

50V

RGB_5V

R3641

R3642

2.7K

2.7K

C3634
18pF

50V

111112121313141415

6677889

112233445

A1

C

A2

MMBD6100

D3620

R3645
10K

RGB_EDID

D3621
ADUC 5S 02 0R5L

5.5V

JK3603

SLIM-15F-D-2

OPT

91010

15

5

+5V_NORMAL

R3643 22

R3644 22

D3622
ADUC 5S 02 0R5L

5.5V
OPT

NON_RGB_DEBUG

16

16

R3600

0

EDID_WP

RGB_DDC_SCL

RGB_DDC_SDA

+3.3V_NORMAL

R3646
10K

D3623

5.6V
OPT

D3600

20V
OPT

R3601

NON_RGB_DEBUG

DSUB_DET

+3.3V_NORMAL

SPDIF OUT

SPDIF_OUT

D3613-*1

5.5V

ADUC 5S 02 0R5L

ESD_MTK

RGB_DEBUG

R3602
100

SOC_RX

RGB_DEBUG

R3647
100

SOC_TX

D3601

20V

0

OPT

PC AUDIO

JK3601

KJA-PH-0-0177

5 GND

4 L

3 DETECT

1 R

R3615

33

ADUC 5S 02 0R5L

D3611

5.6V
OPT

D3612

5.6V
OPT

R3620

2.7K
OPT

D3613

5.5V

OPT

D3611-*1

ESD_MTK

D3612-*1

ESD_MTK

C3615

0.1uF
16V

PC_L_IN

5.6V

PC_R_IN

5.6V

JK3602

2F11TC1-EM52-4F

VIN

A

VCC

B

GND

C

Fiber Optic

4

SHIELD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

JACK HIGH / MID

2011.11.21

36

HP_LOUT

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

HP_ROUT

HP_DET

+3.3V_NORMAL

R3700

10K

HP_OUT

VA3700

5.6V

OPT

JK3700

KJA-PH-0-0177
5GND

4L

3DETECT

1R

EAG61030001

HP_OUT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

ESD for MTK

VA3700-*1

5.6V

ESD_MTK_HP_OUT

ESD for LG1152

VA3700-*2

5.6V

ESD_LG1152_HP_OUT

JACK_COMMON

2011.11.21

37

RS232C

Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

0.1uF

0.1uF

RS232

RS232

RS232

RS232

C38000.1uF

C3801

C38020.1uF

C3803

DOUT2

12V_COMMERCIAL_OUT

12V 1A FOR COMMERCIAL(RS-232C POWER)

12V_COMMERCIAL_OUT

IC3800

+3.5V_ST

MAX3232CDR

C1+

V+

C1-

C2+

C2-

V-

RIN2

1

2

3

4

RS232

5

6

7

8

EAN41348201

VCC

16

GND

15

DOUT1

14

RIN1

13

ROUT1

12

DIN1

11

DIN2

10

ROUT2

9

+3.5V_ST

R3811

IR_OUT

RS232

100

R3820

RS232

100

R3821

+3.5V_ST

OPT_RS232

R3834

10K

FOR COMMERCIAL

R3814

D3805
20V

OPT

4.7K
OPT

D3804

20V
OPT

4.7K
OPT

SOC_RX

SOC_TX

9

8

7

6

RS232

SPG09-DB-009

JK3803

+3.5V_ST

10

5

4

3

2

1

UART_4PIN_STRAIGHT

P3800

12507WS-04L

1

2

3

4

5

UART_4PIN_ANGLE

P3801

12507WR-04L

1

2

3

4

5

CVBS 1 PHONE JACK

AV_JACK_BLACK

JK3800

KJA-PH-1-0177

5 M5_GND

4 M4

3 M3_DETECT

1 M1

6 M6

AV_JACK_YELLOW

JK3800-*1

KJA-PH-1-0177-1

5 M5_GND

4 M4

3 M3_DETECT

1 M1

6 M6

D3800

5.6V
OPT

D3801

5.6V

D3802

5.6V

+3.3V_NORMAL

R3810
10K

OPT

OPT

AV1_CVBS_DET

AV1_CVBS_IN

AV1_L_IN

AV1_R_IN

COMPONENT 1 PHONE JACK

COMP_JACK_BLACK

JK3801

KJA-PH-1-0177

5 M5_GND

4 M4

3 M3_DETECT

1 M1

6 M6

COMP_JACK_GREEN

JK3801-*1

KJA-PH-1-0177-2

5 M5_GND

4 M4

3 M3_DETECT

1 M1

6 M6

D3803

5.6V
OPT

+3.3V_NORMAL

R3806
10K

COMP1_DET

COMP1_Y

COMP1_Pb

COMP1_Pr

ESD For MTK ESD For LG1152

D3803-*1

5.6V

ESD_MTK

D3800-*1

5.6V

ESD_MTK

D3801-*1

5.6V

ESD_MTK

D3802-*1

5.6V

ESD_MTK

D3803-*2

5.6V
ESD_LG1152

D3800-*2
ESD_LG1152

D3801-*2

5.6V

ESD_LG1152

D3802-*2

5.6V

ESD_LG1152

5.6V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

JACK_COMMON

2011.11.21

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