LG 60LA8600-CA Schematic

Printed in KoreaP/NO : MFL67696803 (1304-REV00)

CHASSIS : LC34D

MODEL : 60LA8600 60LA8600-CA

CAUTION

BEFORE SERVICING THE CHASSIS,

READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

LED TV

SERVICE MANUAL

North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com

Asia/Oceania http://biz.lgservice.com

Internal Use Only

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 12

EXPLODED VIEW .................................................................................. 21

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the

Schematic Diagram and Exploded View.

It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent

Shock, Fire, or other Hazards.

Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the

servicing of a receiver whose chassis is not isolated from the AC

power line. Use a transformer of adequate power rating as this

protects the technician from accidents resulting in personal injury

from electrical shocks.

It will also protect the receiver and it's components from being

damaged by accidental shorts of th e cir cuitry that may be

inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,

replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,

over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to

be sure the set is safe to operate without damage of electrical

shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an

electrical jumper across the two AC plug prongs. Place the AC

switch in the on position, connect one lead of ohm-meter to the AC

plug prongs tied together and touch other ohm-meter lead in turn to

each exposed metallic parts such as antenna terminals, phone

jacks, etc.

If the exposed metallic part has a return path to the chassis, the

measured resistance should be between 1 MΩ and 5.2 MΩ.

When the exposed metal has no return path to the chassis the

reading must be infinite.

An other abnormality exists that must be corrected before the

receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.

Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor

between a known good earth ground (Water Pipe, Conduit, etc.)

and the exposed metallic parts.

Measure the AC voltage across the resistor using AC voltmeter

with 1000 ohms/volt or more sensitivity.

Reverse plug the AC cord into the AC outlet and repeat AC voltage

measurements for each exp ose d metallic par t. Any voltage

measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.

In case any measurement is out of the limits specified, there is

possibility of shock hazard and the set must be checked and

repaired before it is returned to the customer.

Leakage Current Hot Check circuit

IMPORTANT SAFETY NOTICE

SAFETY PRECAUTIONS

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service

manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication.

NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions

on page 3 of this publication, always follow the safety precau-

tions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power

source before;

a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug

or other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver.

CAUTION: A wrong part substitution or incorrect polarity

installation of electrolytic capacitors may result in an explo-

sion hazard.

2. Test high voltage only by measuring it with an appropriate

high voltage meter or other voltage measuring device (DVM,

FETVOM, etc) equipped with a suitable high voltage probe.

Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its

assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the

contacts with a pipe cleaner, cotton-tipped stick or comparable

non-abrasive applicator; 10 % (by volume) Acetone and 90 %

(by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture.

Unless specied otherwise in this service manual, lubrication

of contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which

receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its

electrical assemblies unless all solid-state device heat sinks

are correctly installed.

7. Always connect the test receiver ground lead to the receiver

chassis ground before connecting the test receiver positive

lead.

Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged eas-

ily by static electricity. Such components commonly are called

Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques

should be used to help reduce the incidence of component dam-

age caused by static by static electricity.

1. Immediately before handling any semiconductor component or

semiconductor-equipped assembly, drain off any electrostatic

charge on your body by touching a known earth ground. Alter-

natively, obtain and wear a commercially available discharg-

ing wrist strap device, which should be removed to prevent

potential shock reasons prior to applying power to the unit

under test.

2. After removing an electrical assembly equipped with ES

devices, place the assembly on a conductive surface such as

aluminum foil, to prevent electrostatic charge buildup or expo-

sure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder

ES devices.

4. Use only an anti-static type solder removal device. Some sol-

der removal devices not classied as “anti-static” can generate

electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective

package until immediately before you are ready to install it.

(Most replacement ES devices are packaged with leads elec-

trically shorted together by conductive foam, aluminum foil or

comparable conductive material).

7. Immediately before removing the protective material from the

leads of a replacement ES device, touch the protective mate-

rial to the chassis or circuit assembly into which the device will

be installed.

CAUTION: Be sure no power is applied to the chassis or cir-

cuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replace-

ment ES devices. (Otherwise harmless motion such as the

brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity suf-

cient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropri-

ate tip size and shape that will maintain tip temperature within

the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed

of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wire-

bristle (0.5 inch, or 1.25 cm) brush with a metal handle.

Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F)

b. Heat the component lead until the solder melts.

c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique.

a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand

against the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there

only until the solder ows onto and around both the compo-

nent lead and the foil.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through

which the IC leads are inserted and then bent at against the cir-

cuit foil. When holes are the slotted type, the following technique

should be used to remove and replace the IC. When working with

boards using the familiar round hole, use the standard technique

as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by

gently prying up on the lead with the soldering iron tip as the

solder melts.

2. Draw away the melted solder with an anti-static suction-type

solder removal device (or with solder braid) before removing

the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and

solder it.

3. Clean the soldered areas with a small wire-bristle brush.

(It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor

Removal/Replacement

1. Remove the defective transistor by clipping its leads as close

as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remain-

ing on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding

leads extending from the circuit board and crimp the "U" with

long nose pliers to insure metal to metal contact then solder

each connection.

Power Output, Transistor Device

Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit

board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as pos-

sible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit

board.

3. Observing diode polarity, wrap each lead of the new diode

around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of

the two "original" leads. If they are not shiny, reheat them and

if necessary, apply additional solder.

Fuse and Conventional Resistor

Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow

stake.

2. Securely crimp the leads of replacement component around

notch at stake top.

3. Solder the connections.

CAUTION: Maintain original spacing between the replaced

component and adjacent components and the circuit board to

prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit

board will weaken the adhesive that bonds the foil to the circuit

board causing the foil to separate from or "lift-off" the board. The

following guidelines and procedures should be followed when-

ever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the

following procedure to install a jumper wire on the copper pattern

side of the circuit board. (Use this technique only on IC connec-

tions).

1. Carefully remove the damaged copper pattern with a sharp

knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if

used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and

carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper

pattern and let it overlap the previously scraped end of the

good copper pattern. Solder the overlapped area and clip off

any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern

at connections other than IC Pins. This technique involves the

installation of a jumper wire on the component side of the circuit

board.

1. Remove the defective copper pattern with a sharp knife.

Remove at least 1/4 inch of copper, to ensure that a hazardous

condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern

break and locate the nearest component that is directly con-

nected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the

nearest component on one side of the pattern break to the

lead of the nearest component on the other side.

Carefully crimp and solder the connections.

CAUTION: Be sure the insulated jumper wire is dressed so the

it does not touch components or sharp edges.

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This specification is applied to the LED TV used LC34D

chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage

: Standard input voltage (AC 100-240 V~, 50/60 Hz)

* Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

ea ch drawing and s pe cificatio n b y p art number in

accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

- Wireless : Wireless HD Specification (Option)

4. Model General Specification

No. Item Specication Remarks

1 Market China/HONGKONG

2 Broadcasting system

[HONGKONG]

PAL D/K : VHF/UHF 1 to 69, Cable 1 to 47

PAL I : VHF/UHF 1 to 69, Cable 1 to 47

NTSC M : VHF/UHF 2 to 78, Cable 1 to 71

DTMB : 21 to 69

DTMB : DMB-T (Multi Carrier) + ADTB-T (Single Carrier)

3 Receiving system

Analog : Upper Heterodyne

Digital : COFDM, QAM

► DTMB

(Carrier, Code Rate, Constellation, Frame Header, Interleaving)

* Hong Kong

- 3780, 0.4/0.6, 4/16/64QAM, PN945, 720

► DVB-C

- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s

- Modulation : 16QAM, 32-QAM, 64-QAM, 128-QAM and 256-QAM

4 Video Input (1EA) PAL, NTSC AV gender jack 1EA

5

Component Input

(1EA)

Y/Cb/Cr

Y/Pb/Pr

Component Gender 1EA

6 RGB Input RGB-PC → Spec out Analog (D-SUB 15PIN)

7 HDMI Input (4EA)

HDMI1-DTV/ARC

HDMI2-DTV

HDMI3-DTV

HDMI4-DTV/MHL

PC(HDMI version 1.3)

Support HDCP

8 Audio Input (2EA)

DVI Audio

Component/AV common

L/R Input

9 SDPIF out (1EA) SPDIF out

10 USB (3EA)

EMF, DivX HD, For SVC (down-

load)

JPEG, MP3, DivX HD

(USB 2.0 : 2EA, USB 3.0 : 1EA)

11 Ethernet Lan Jack

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

5. External input format

5.1. 2D Mode

(1) Component input(Y, CB/PB, CR/PR)

(2) HDMI Input (PC/DTV)

No. Resolution H-freq(kHz) V-freq(Hz)

1. 720×480 15.73 60.00 SDTV, DVD 480i

2. 720×480 15.63 59.94 SDTV, DVD 480i

3. 720×480 31.47 59.94 480p

4. 720×480 31.50 60.00 480p

5. 720×576 15.625 50.00 SDTV 576i

6. 720×576 31.25 50.00 SDTV 576p

7. 1280×720 45.00 50.00 HDTV 720p

8. 1280×720 44.96 59.94 HDTV 720p

9. 1280×720 45.00 60.00 HDTV 720p

10. 1920×1080 31.25 50.00 HDTV 1080i

11. 1920×1080 33.75 60.00 HDTV 1080i

12. 1920×1080 33.72 59.94 HDTV 1080i

13. 1920×1080 56.250 50 HDTV 1080p

14. 1920×1080 67.5 60 HDTV 1080p

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC Proposed

HDMI-PC DDC

1 640*350 31.468 70.09 25.17 EGA Х

2 720*400 31.469 70.08 28.32 DOS O

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1152*864 54.348 60.053 80 VESA

7 1280*1024 63.981 60.020 108 VESA(SXGA) O

8 1360*768 47.712 60.015 85.5 VESA(WXGA) O

9 1920*1080 67.5 60.00 148.5 WUXGA(CEA861D) O

HDMI-DTV

1 640*480 31.469 / 31.5 59.94/ 60 25.125 1 SDTV 480P

2 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3 SDTV 480P

3 720*576 31.25 50 27 17,18 SDTV 576P

4 720*576 15.625 50 27 21 SDTV 576I

5 1280*720 37.500 50 74.25 19 HDTV 720P

6 1280*720 44.96 / 45 59.94 / 60 74.17/74.25 4 HDTV 720P

7 1920*1080 33.72 / 33.75 59.94 / 60 74.17/74.25 5 HDTV 1080I

8 1920*1080 28.125 50.00 74.25 20 HDTV 1080I

9 1920*1080 26.97 / 27 23.97 / 24 74.17/74.25 32 HDTV 1080P

10 1920*1080 25 33 HDTV 1080P

11 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 34 HDTV 1080P

12 1920*1080 56.250 50 148.5 31 HDTV 1080P

13 1920*1080 67.43 / 67.5 59.94 / 60 148.35/148.50 16 HDTV 1080P

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

5.2. 3D Mode

(1) RF Input(3D supported mode manually)

No. Resolution Proposed 3D input proposed mode

1 HD

1080I

720P

2D to 3D

Side by Side(Half)

Top & Bottom

2 SD

576P

576I

2D to 3D

(3) HDMI 1.3 (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P 2D to 3D

Side by Side(half),

Top & Bottom,

Single Frame Sequential

2 1280*720 37.500 50 74.25 HDTV 720P

3 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D,

Side by Side(Half),

Top & Bottom

4 1920*1080 28.125 50.00 74.25 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P 2D to 3D,

Side by Side(Half),

Top & Bottom,

Checker Board

6 1920*1080 28.12 25 74.25 HDTV 1080P

7 1920*1080 33.75 30.00 74.25 HDTV 1080P

8 1920*1080 56.250 50 148.5 HDTV 1080P

2D to 3D,

Side by Side(Half),

Top & Bottom,

Checker Board,

Single Frame Sequential,

Row Interleaving,

Column Interleaving

9 1920*1080 67.50 60.00 148.5 HDTV 1080P

(2) RF Input(3D supported mode automatically)

No. Signal 3D input proposed mode

1 Frame Compatible

Side by Side(Half),

Top & Bottom

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

(4) HDMI 1.4b (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed

1

640*480

31.469 / 31.5 59.94/ 60 25.125/25.2 1

Top-and-Bottom

Side-by-side(half)

Secondary(SDTV 480P)

Secondary(SDTV 480P)

2 62.938/63 59.94/ 60 50.35/50.4 1

Frame packing

Line alternative

Secondary(SDTV 480P)

(SDTV 480P)

3 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)

4

720*480

31.469 / 31.5 59.94 / 60 27.00/27.03 2,3

Top-and-Bottom

Side-by-side(half)

Secondary(SDTV 480P)

Secondary(SDTV 480P)

5 62.938/63 59.94 / 60 54/54.06 2,3

Frame packing

Line alternative

Secondary(SDTV 480P)

(SDTV 480P)

6 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)

7

720*576

31.25 50 27 17,18

Top-and-Bottom

Side-by-side(half)

Secondary(SDTV 576P)

Secondary(SDTV 576P)

8 62.5 50 54 17,18

Frame packing

Line alternative

Secondary(SDTV 576P)

(SDTV 576P)

9 31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)

10 15.625 50 27 21

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 720P)

Primary(HDTV 720P)

11 31.25 50 54 21

Frame packing

Field alternative

Primary(HDTV 720P)

(HDTV 720P)

12 15.625 50 54 21 Side-by-side(Full) (HDTV 720P)

13

1280*720

37.500 50 74.25 19

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 720P)

Primary(HDTV 720P)

14 75 50 148.5 19

Frame packing

Line alternative

Primary(HDTV 720P)

(HDTV 720P)

15 37.500 50 148.5 19 Side-by-side(Full) (HDTV 720P)

16 44.96 / 45 59.94 / 60 74.18/74.25 4

Top-and-Bottom

Side-by-side(half)

Secondary(HDTV 1080I)

Primary(HDTV 1080I)

17 89.91/90 59.94 / 60 148.35/148.5 4

Frame packing

Line alternative

Primary(HDTV 1080I)

(HDTV 1080I)

18 44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 1080I)

19

1920*1080

33.72 / 33.75 59.94 / 60 74.18/74.25 5

Top-and-Bottom

Side-by-side(half)

Secondary(HDTV 1080I)

Primary(HDTV 1080I)

20 67.432/67.50 59.94 / 60 148.35/148.5 5

Frame packing

Field alternative

Primary(HDTV 1080I)

(HDTV 1080I)

21 33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)

22 28.125 50.00 74.25 20

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

Primary(HDTV 1080P)

23 56.25 50.00 148.5 20

Frame packing

Field alternative

Primary(HDTV 1080P)

(HDTV 1080P)

24 28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080P)

25 26.97 / 27 23.97 / 24 74.18/74.25 32

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

Primary(HDTV 1080P)

26 43.94/54 23.97 / 24 148.35/148.5 32

Frame packing

Line alternative

Primary(HDTV 1080P)

(HDTV 1080P)

27 26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)

28 28.12 25 74.25 33

Top-and-Bottom

Side-by-side(half)

Secondary(HDTV 1080P)

Secondary(HDTV 1080P)

29 56.24 25 148.5 33

Frame packing

Line alternative

Secondary(HDTV 1080P)

(HDTV 1080P)

30 28.12 25 148.5 33 Side-by-side(Full) (HDTV 1080P)

31 33.716 / 33.75 29.976 / 30.00 74.18/74.25 34

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

32 67.432 / 67.5 29.976 / 30.00 148.35/148.5 34

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

(HDTV 1080P)

33 33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)

34 56.250 50 148.5 31

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

35 67.43 / 67.5 59.94 / 60 148.35/148.50 16

Top-and-Bottom

Side-by-side(half)

Primary(HDTV 1080P)

Secondary(HDTV 1080P)

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1024*768 48.36 60 65

2D to 3D, Side by Side(half)

Top & Bottom

HDTV 768P

2 1360*768 47.71 60 85.5

2D to 3D, Side by Side(half)

Top & Bottom

HDTV 768P

3 1920*1080 67.500 60 148.50

2D to 3D, Side by Side(half)

Top & Bottom, Checker Board,

Single Frame Sequential,

Row Interleaving,

Column Interleaving

HDTV 1080P

4 Others - - - 2D to 3D

640*350

720*400

640*480

800*600

1152*864

(5) HDMI-PC Input (3D) (3D supported mode manually)

(6) Component Input ( 3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock 3D input proposed mode Proposed

1 1280*720 37.5 50 74.25 2D to 3D, Side by Side, Top & Bottom HDTV 720P

2 1280*720 45.00 60.00 74.25 2D to 3D, Side by Side, Top & Bottom HDTV 720P

3 1280*720 44.96 59.94 74.176 2D to 3D, Side by Side, Top & Bottom HDTV 720P

4 1920*1080 33.75 60.00 74.25 2D to 3D, Side by Side, Top & Bottom HDTV 1080I

5 1920*1080 33.72 59.94 74.176 2D to 3D, Side by Side, Top & Bottom HDTV 1080I

6 1920*1080 28.12 50 74.25 2D to 3D, Side by Side, Top & Bottom HDTV 1080I

7 1920*1080 67.500 60 148.50 2D to 3D, Side by Side, Top & Bottom HDTV 1080P

8 1920*1080 67.432 59.94 148.352 2D to 3D, Side by Side, Top & Bottom HDTV 1080P

9 1920*1080 27.000 24.000 74.25 2D to 3D, Side by Side, Top & Bottom HDTV 1080P

10 1920*1080 28.12 25 74.25 2D to 3D, Side by Side, Top & Bottom HDTV 1080P

11 1920*1080 56.25 50 74.25 2D to 3D, Side by Side, Top & Bottom HDTV 1080P

12 1920*1080 26.97 23.976 74.176 2D to 3D, Side by Side, Top & Bottom HDTV 1080P

13 1920*1080 33.75 30.000 74.25 2D to 3D, Side by Side, Top & Bottom HDTV 1080P

14 1920*1080 33.71 29.97 74.176 2D to 3D, Side by Side, Top & Bottom HDTV 1080P

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

(8) USB / DLNA Input(3D) (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1920*1080 33.75 30 74.25

2D to 3D

Side by Side(Half),

Top & Bottom,

Checkerboard,

Row Interleaving,

Column Interleaving

(Photo : side by Side(half), Top & Bottom)

HDTV 1080P

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1920*1080 33.75 30 74.25

Side by Side(Half),

Top & Bottom,

Checkerboard,

MPO(photo)

HDTV 1080P

(7) USB / DLNA Input(3D) (3D supported mode manually)

■ Remark: 3D Input mode

No. Side by Side Top & Bottom Checker board

Single Frame

Sequential

Frame Packing

Line

Interleaving

Column

Interleaving

1

R

L

R

L

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied to all of the LED TV with

LC34D chassis.

2. Designation

(1) Because this is not a hot chassis, it is not necessary to

use an isolation transformer. However, the use of isolation

transformer will help protect test instrument.

(2) Adjustment must be done in the correct order.

(3) The adjustment must be performed in the circumstance of

25 °C ± 5 °C of temperature and 65 % ± 10 % of relative

humidity if there is no specific designation.

(4) The input voltage of the receiver must keep AC 100-240

V~, 50/60 Hz.

(5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15.

In case of keeping module is in the circumstance of 0 °C, it

should be placed in the circumstance of above 15 °C for 2

hours.

In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15

°C for 3 hours.

[Caution]

When still image is displayed for a period of 20 minutes or

longer (Especially where W/B scale is strong. Digital pattern

13ch and/or Cross hatch pattern 09ch), there can some

afterimage in the black level area.

3. Automatic Adjustment

3.1. ADC Adjustment

■ Enter Service Mode by pushing “ADJ” key,

■ Enter ADC mode by pushing “► key at “8. ADC Calibration”

■ There are 2 ways for ADC Calibration. (Internal, External)

3.1.1. Internal mode

: Automatic ADC Calibration.(Internal ADC Calibration) On the

manufacture line, it is used for ADC Calibration automatically.

(1) Change the ADC type “internal” by using “►”key.

(2) Enter “Start” key.

(3) Check the sign “OK” below ADC type.

3.1.2. External mode

(1) Equipment & Condition

1) USB to RS-232C Jig

2) MSPG-925 Series Pattern Generator(MSPG-925FA,

pattern - 65)

- Resolution : 480i Comp1

1080P Comp1

1920*1080P SCART RGB

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level : 0.7 ± 0.1 Vp-p

- Image

(2) Adjustment

1) Adjustment method

- Using RS-232, adjust items in the other shown in

"3.1.2.(3).3)"

2) Adj. protocol

Ref.) ADC Adj. RS232C Protocol_Ver1.0

3) Adj. order

- aa 00 00 [Enter ADC adj. mode]

- xb 00 04 [Change input source to Component1 (480i&

1080p)]

- ad 00 10 [Adjust 480i&1080p Comp1]

- xb 00 06 [Change input source to RGB(1024*768)]

- ad 00 10 [Adjust 1920*1080 SCART RGB]

- ad 00 90 End adj.

3.2. MAC address D/L, Widevine key D/L,

ESN key D/L, HDCP key D/L

Connect: PCBA Jig → RS-232C Port== PC → RS-232C Port

Communication Prot connection

▪ Com 1,2,3,4 and 115200(Baudrate)

Mode check: Online Only

▪ Check the test process: DETECT → MAC → CI → Widevine

→ ESN

▪ Play: START

▪ Result: Ready, Test, OK or NG

▪ Printer Out (MAC Address Label)

Protocol Command Set ACK

Enter adj. mode aa 00 00 a 00 OK00x

Source change

xb 00 04

xb 00 06

b 00 OK04x (Adjust 480i, 1080p Comp1 )

b 00 OK06x (Adjust 1920*1080 SCART RGB)

Begin adj. ad 00 10

Return adj. result

OKx (Case of Success)

NGx (Case of Fail)

Read adj. data

(main)

ad 00 20

(main)

000000000000000000000000007c007b006dx

(sub )

ad 00 21

(Sub)

000000070000000000000000007c00830077x

Conrm adj. ad 00 99

NG 03 00x (Fail)

NG 03 01x (Fail)

NG 03 02x (Fail)

OK 03 03x (Success)

End adj. aa 00 90 a 00 OK90x

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

3.3. LAN Inspection

3.3.1. Equipment & Condition

▪ Each other connection to LAN Port of IP Hub and Jig

3.3.2. LAN inspection solution

▪ LAN Port connection with PCB

▪ Network setting at MENU Mode of TV

▪ Setting automatic IP

▪ Setting state confirmation

→ If automatic setting is finished, you confirm IP and MAC

Address.

3.3.3. WIDEVINE key Inspection

- Confirm key input data at the "IN START" MENU Mode.

3.4. LAN PORT INSPECTION(PING TEST)

Connect SET → LAN port == PC → LAN Port

3.4.1. Equipment setting

(1) Play the LAN Port Test PROGRAM.

(2) Input IP set up for an inspection to Test Program.

*IP Number : 12.12.2.2

3.4.2. LAN PORT inspection(PING TEST)

(1) Play the LAN Port Test Program.

(2) Connect each other LAN Port Jack.

(3) Play Test (F9) button and confirm OK Message.

(4) Remove LAN cable.

SET PC

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

3.5. Model name & Serial number Download

3.5.1. Model name & Serial number D/L

▪ Press "Power on" key of service remote control.

(Baud rate : 115200 bps)

▪ Connect RS-232C Signal to USB Cable to USB.

▪ Write Serial number by use USB port.

▪ Must check the serial number at Instart menu.

3.5.2. Method & notice

(1) Serial number D/L is using of scan equipment.

(2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory

by D-book 4.0.

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded by OTA or service man, sometimes

model name or serial number is initialized.(Not always)

It is impossible to download by bar code scan, so It need

Manual download.

1) Press the "Instart" key of Adjustment remote control.

2) Go to the menu "7.Model Number D/L" like below photo.

3) Input the Factory model name(ex 47LM960V-ZB) or Serial

number like photo.

4) Check the model name Instart menu. → Factory name

displayed. (ex 47LA8600-CA)

5) Check the Diagnost ics.(DTV country only) → Buyer

model displayed. (ex 47LA8600-CA)

3.6. WIFI MAC ADDRESS CHECK

(1) Using RS232 Command

(2) Check the menu on in-start

4. Manual Adjustment

* ADC adjustment is not needed because of OTP(Auto ADC

adjustment)

4.1. EDID(The Extended Display Identification

Data)/DDC(Display Data Channel) download

4.1.1. Overview

It is a VESA regulation. A PC or a MNT will display an optimal

resolution through information sharing without any necessity

of user input. It is a realization of "Plug and Play".

4.1.2. Equipment

- Since embedded EDID data is used, EDID download JIG,

HDMI cable and D-sub cable are not need.

- Adjustment remote control

4.1.3. Download method

(1) Press "ADJ" key on the Adjustment remote control then

select "10.EDID D/L", By pressing "Enter" key, enter EDID

D/L menu.

(2) Select "Start" button by pressing "Enter" key, HDMI1/

HDMI2/ HDMI3/ HDMI4/ RGB are writing and display OK

or NG.

4.1.4. EDID DATA

# HDMI 1(C/S : E8 81)

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

H-freq(kHz) V-freq.(Hz)

Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]

For Analog For HDMI EDID

D-sub to D-sub DVI-D to HDMI or HDMI to HDMI

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 0 0 1E 6D 01 00 01 01 01 01

10 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 5 0 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3 A 80 18 71 38 2D 40 58 2C

40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 0 0 3A

60 3 E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E 8

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 29 3D 06 C0 15 07 50 09 57 07 78 03 0C

20 00 10 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10

30 06 10 16 10 28 10 E3 05 03 01 02 3A 80 18 71 38

40 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18

50 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D

60 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 81

- 15 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

# HDMI 2(C/S : E8 71)

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

# HDMI 3(C/S : E8 61)

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

# HDMI 4(C/S : E8 51)

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

4.1.5. Camera Port Inspection

(1) Objective : To check PCBA’s CAMERA Port.

(2) How-it-works

1) Connect the PCBA like below Picture.

2) Send speci fic RS -232C Command for display ing

Camera Preview.

3) RS-232C Command

4.2. White Balance Adjustment

4.2.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel's W/B deviation

(2) How-it-works : When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to

prevent saturation of Full Dynamic range and data, one

of R/G/B is fixed at 192, and the other two is lowered to

find the desired value.

(3) Adjustment condition : normal temperature

1) Surrounding Temperature : 25 °C ± 5 °C

2) Warm-up time: About 5 Min

3) Surrounding Humidity : 20 % ~ 80 %

4.2.2. Equipment

(1) Color Analyzer: CA-210 (LED Module : CH 14)

(2) Adjustment Computer(During auto adj., RS-232C protocol

is needed)

(3) Adjustment Remote control

(4) Video Signal Generator MSPG-925F 720p/216-Gray

(Model: 217, Pattern: 78)

→ Only when internal pattern is not available

▪ Color Analyzer Matrix should be calibrated using CS-100.

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8

0 1 2 3 4 5 6 7 8 9 A B C D E F

00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 29 3D 06 C0 15 07 50 09 57 07 78 03 0C

20 00 10 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10

30 06 10 16 10 28 10 E3 05 03 01 02 3A 80 18 71 38

40 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18

50 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D

60 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 81

0 0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8

0 0 1 2 3 4 5 6 7 8 9 A B C D E F

00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 29 3D 06 C0 15 07 50 09 57 07 78 03 0C

20 00 30 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10

30 06 10 16 10 28 10 E3 05 03 01 02 3A 80 18 71 38

40 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18

50 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D

60 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61

0 0 1 2 3 4 5 6 7 8 9 A B C D E F

00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8

0 0 1 2 3 4 5 6 7 8 9 A B C D E F

00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 29 3D 06 C0 15 07 50 09 57 07 78 03 0C

20 00 40 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10

30 06 10 16 10 28 10 E3 05 03 01 02 3A 80 18 71 38

40 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18

50 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D

60 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 51

RS-232C COMMAND

[CMD ID DATA]

Explantion

ai 00 23 Camera Function Start

ai 00 24 Camera Function End

- 16 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

4.2.3. Equipment connection MAP

4.2.4. Adj. Command (Protocol)

<Command Format>

- LEN: Number of Data Byte to be sent

- CMD: Command

- VAL: FOS Data value

- CS: Checksum of sent data

- A: Acknowledge

Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]

▪ RS-232C Command used during auto-adjustment.

Ex) wb 00 00 -> Begin white balance auto-adj.

wb 00 10 -> Gain adj.

ja 00 ff -> Adj. data

jb 00 c0

...

...

wb 00 1f → Gain adj. completed

*(wb 00 20(Start), wb 00 2f(end)) → Off-set adj.

wb 00 ff → End white balance auto-adj.

▪ Adj. Map

4.2.5. Adj. method

(1) Auto adj. method

1) Set TV in adj. mode using POWER ON key.

2) Zero calibrate probe then place it on the center of the

Display.

3) Connect Cable.(RS-232C to USB)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sign), check adj. status pre

mode. (Warm, Medium, Cool)

6) Remove probe and RS-232C cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need.

(2) Manual adjustment. method

1) Set TV in Adj. mode using POWER ON.

2) Zero Calibrate the probe of Color Analyzer, then place it

on the cente r of LCD module wi thin 10 cm of the

surface.

3) Press ADJ key → EZ adjust using adj. R/C → 9. White-

Balance then press the cursor to the right(key ►). When

right key(►) is pressed 216 Gray internal pattern will be

displayed

4) Adjust Cool modes

a. Fix the one of R/G/B gain to 192 (default data) and

decrease the others. ( If G gain is adjusted over 172

and R and B gain less than 192 , Adjust is O.K.)

b. If G gain is less than 172, Increase G gain by up to

172, and then increase R gain and G gain same

amount of increasing G gain.

c. If R gain or B gain is over 255, Readjust G gain less

than 172, Conform to R gain is 255 or B gain is 255

5) Adjust two modes(Medium/Warm) Fix the one of R/G/B

gain to 192(default data) and decrease the others.

6) Adj. is completed, Exit adjust mode using “EXIT” key on

Remote controller.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 6.White Balance, you can select one of 2 Test-

pattern: ON, OFF. Default is inner(ON). By selecting OFF,

you can adjust using RF signal in 206 Gray pattern.

* CASE Cool

First adjust the coordinate far away from the target

value(x, y).

1. x, y > target

i) Decrease the R, G.

2. x, y < target

i) First decrease the B gain,

ii) Decrease the one of the others.

3. x > target, y < target

i) First decrease B, so make y a little more than the target.

ii) Adjust x value by decreasing the R

4. x < target, y > target

i) First decrease B, so make x a little more than the target.

ii) Adjust x value by decreasing the G

How to adjust

1. If G gain is adjusted over 172 and R gain and B gain

less than 192 , Adjust is O.K.

2. If G gain is less than 172 , increase G gain by up to

172, and then increase R gain and B gain same

amount of increasing G gain.

3. If R gain or B gain is over 255 , Readjust G gain less

than 172, Conform to R gain is 255 or B gain is 255

START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP

Co lor Anal yze r

Co mp ute r

Pattern Gen era to r

RS -232 C

RS- 232 C

RS- 232 C

Pro be

Sig nal Sou rce

* If TV internal pattern is used, not needed

RS-232C COMMAND

[CMD ID DATA]

Explantion

wb 00 00 Begin White Balance adjustment

wb 00 10 Gain adjustment(internal white pattern)

wb 00 1f Gain adjustment completed

wb 00 20 Offset adjustment(internal white pattern)

wb 00 2f Offset adjustment completed

wb 00 ff

End White Balance adjustment

(internal pattern disappears )

Adj. item

Command

(lower caseASCII)

Data Range

(Hex.)

Default

(Decimal)

CMD1 CMD2 MIN MAX

Cool

R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

R Cut

G Cut

B Cut

Medium

R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

R Cut

G Cut

B Cut

Warm

R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

R Cut

G Cut

- 17 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

* CASE Medium / Warm

First adjust the coordinate far away from the target

value(x, y).

1. x, y > target

i) Decrease the R, G.

2. x, y < target

i) First decrease the B gain,

ii) Decrease the one of the others.

3. x > target, y < target

i) First decrease B, so make y a little more than the target.

ii) Adjust x value by decreasing the R

4. x < target, y > target

i) First decrease B, so make x a little more than the target.

ii) Adjust y value by decreasing the G

*Ascended method of Adjusting W/B

- CASE Cool

First adjust the coordinate far away from the target

value(x, y).B

1. x, y > target

2. x, y < target

3. x > target , y < target

4. x < target , y >target

- Every 4 case have to fit y value by adjusting B Gain

and then fit x value by adjusting R-Gain

- In this case, increasing/decreasing of B Gain and R

Gain can be adjusted.

- How to adjust

1. Fix G gain to 172

Adjust R Gain and B Gain ( In Case of Mostly Blue

Gain Saturation )

2. When B Gain > 255, Release Fixed G Gain and

Readjust

- CASE Medium / Warm

First adjust the coordinate far away from the target

value(x, y).

1. x, y > target

i) Decrease the R, G.

2. x, y < target

i) First decrease the B gain,

ii) The one value is bigger than the target then the other

one should be not much more bigger than target.

iii) In case that we take x off, we also take R(G-gain fix)

In other case that we take y off, we also take G

(R-gain fix)

3. x > target , y < target

i) First decrease B, so make y a little more than the

target.

ii) Adjust x value by decreasing the R

4. x < target , y > target

i) First decrease B, so make x a little more than the

target.

ii) Adjust y value by decreasing the G

▪ Adjustment condition and cautionary items

1) Lighting condition in surrounding area

Surrounding lighting should be lower 10 lux. Try to

isolate adj. area into dark surrounding.

2) Probe location

: Color Analyzer(CA-210) probe should be within 10 cm

and perpendicular of the module surface (80° ~ 100°)

3) Aging time

- After Aging Start, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked

using no signal or Full-white pattern.

4.2.6. Reference (White balance Adj. coordinate and

color temperature)

▪ Luminance : 206 Gray

▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

▪ Standard color coordinate and temperature using CA-210(CH 18)

4.2.7. EDGE LED White balance table

(1) EDGE LED module change color coordinate because of

aging time.

(2) Apply under the color coordinate table, for compensated

aging time.

(3) Normal line

Mode

Coordinate

Temp ∆uv

x y

Cool 0.271 0.270 13000 K 0.0000

Medium 0.285 0.293 9300 K 0.0000

Warm 0.310 0.325 6500 K 0.0000

Mode

Coordinate

Temp ∆uv

x y

Cool 0.271±0.002 0.270±0.002 13000K 0.0000

Medium 0.285±0.002 0.293±0.002 9300K 0.0000

Warm 0.310±0.002 0.325±0.002 6500K 0.0000

GP4

Aging

time

(Min)

Cool Medium Warm

X y x y x y

271 270 286 289 314 318

1 0-2 281 287 296 306 321 331

2 3-5 280 285 295 304 320 329

3 6-9 278 284 293 303 318 328

4 10-19 276 281 291 300 316 325

5 20-35 275 277 290 296 315 321

6 36-49 274 274 289 293 314 318

7 50-79 273 272 288 291 313 316

8 80-119 272 271 287 290 312 315

9 Over 120 271 270 286 289 311 314

- 18 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

- Gumi winter table(Jan, Fab)- Gumi producing model use only

4.3. EYE-Q function check

Step 1) Turn on TV.

Step 2) Press EYE key of Adj. R/C.

Step 3) Cover the Eye Q II sensor on the front of the using your

hand and wait for 6 seconds.

Step 4) Confirm that Sensor Data is lower than 100 of the “Raw

Data (Sensor data, Back light )”. If after 6 seconds,

Sensor Data is not lower than 100, replace Eye Q II

sensor.

Step 5) Remove your hand from the Eye Q II sensor and wait for

6 seconds.

Step 6) Confirm that “ok” pop up. If change is not seen, replace

Eye Q II sensor.

4.4. Local Dimming Function Check

Step 1) Turn on TV.

Step 2) At the Local Dimming mode, module Edge Backlight

moving right to left Back light of IOP module moving.

Step 3) Confirm the Local Dimming mode.

Step 4) Press "exit" key.

4.5. Magic Motion Remote control test

(1) Equipment : RF Remote control for test, IR-KEY-Code

Remote control for test

(2) You must confirm the battery power of RF-Remote control

before test(recommend that change the battery per every lot)

(3) Sequence (test)

1) if you select the "Start(Mute)" key on the Adjustment

remote control, you can pairing with the TV SET.

2) You can check the cursor on the TV Screen, when select

the "OK" key on the Adjustment remote control.

3) You must remove the pairing with the TV Set by select

"OK" key + "Mute" key on the Adjustment remote control

for 5 seconds.

4.6. 3D function test

(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])

* HDMI mode NO. 872 , pattern No.83

(1) Please input 3D test pattern like below.

(2) When 3D OSD appear automatically, then select OK key.

(3) Don't wear a 3D Glasses, check the picture like below.

GP4

Aging

time

(Min)

Cool Medium Warm

X y x y x y

271 270 286 289 314 318

1 0-5 280 285 295 304 320 329

2 6-10 276 280 291 299 316 324

3 11-20 272 275 287 294 312 319

4 21-30 269 272 284 291 309 316

5 31-40 267 268 282 287 307 312

6 41-50 266 265 281 284 306 309

7 51-80 265 263 280 282 305 307

8 81-119 264 261 279 280 304 305

9 Over 120 264 260 279 279 304 304

G

- 19 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

4.7. Wi-Fi Test

Step 1) Turn on TV

Step 2) Select Network Connection option in Network Menu.

Step 3) Select Start Connection button in Network Connection.

Step 4) If the system finds any AP like blow PIC, it is working

well.

4.8. LNB voltage and 22KHz tone check

(only for DVB-S/S2 model)

▪ Test method

(1) Set TV in Adj. mode using POWER ON.

(2) Connect cable between satellite ANT and test JIG.

(3) Press Yellow key(ETC+SWAP) in Adj Remote control to

make LNB on.

(4) Check LED light ‘ON’ at 18 V menu.

(5) Check LED light ‘ON’ at 22 KHz tone menu.

(6) Press Blue key(ETC+PIP INPUT) in Adjustment Remote

control to make LNB off.

(7) Check LED light ‘OFF’ at 18 V menu.

(8) Check LED light ‘OFF’ at 22 KHz tone menu.

▪ Test result

(1) After press LNB On key, ‘18 V LED’ and ‘22 KHz tone

LED’ should be ON.

(2) After press LNB OFF key, ‘18 V LED’ and ‘22 KHz tone

LED’ should be OFF.

4.9. Inspection of light scattering

▪ Test Method

(1) Push “Power only” key.

(2) Push “HDMI” hot key.

(3) Inspect whether light scattering is occurred in internal

black pattern or not.

(4) Push “Power only” key.

4.10. Option selection per country

4.10.1. Overview

- Option selection is only done for models in Non-EU.

4.10.2. Method

(1) Press ADJ key on the Adjustment Remote Control, then

select Country Group Meun

(2) Depending on destination, select Country Group Code 04

or Country Group EU then on the lower Country option,

select US, CA, MX. Selection is done using +, - or ►◄

key.

4.11. MHL Test

(1) Turn on TV

(2) Select HDMI4 mode using input Menu.

(3) Set MHL Zig(M1S0D3617) using MHL input, output and

power cord.

(4) Connect HDMI cable between MHL Zig and HDMI4 port.

(5) Check LED light of Zig and Module of Set.

Result) If, the LED light is green and the Module sho ws

normal stream → OK, Else → NG

- 20 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

5. Tool Option selection

▪ Method : Press "ADJ" key on the Adjustment remote control,

then select Tool option.

6. Ship-out mode check(In-stop)

▪ After final inspection, press "IN-STOP" key of the Adjustment

remote control and check that the unit goes to Stand-by

mode.

7. GND and Internal Pressure check

7.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power cord is fully inserted to the SET.

(If loose, re-insert)

(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord, Antenna cable and A/V

arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER(GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically.

(Remove CORD, A/V form AV JACK BOX.)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the

pallet to move on to next process.

7.2. Checkpoint

▪ TEST voltage

- GND: 1.5 KV / min at 100 mA

- SIGNAL: 3 KV / min at 100 mA

▪ TEST time: 1 second

▪ TEST POINT

- GND TEST = POWER CORD GND & SIGNAL CABLE

METAL GND

- Internal Pressure TEST = POWER CORD GND & LIVE &

NEUTRAL

▪ LEAKAGE CURRENT: At 0.5 mArms

8. Audio

Measurement condition:

(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation

(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms

(3) RGB PC: 1 KHz sine wave signal 0.7 Vrms

9. USB S/W Download(Service only)

(1) Put the USB Stick to the USB socket.

(2) Automatically detecting update file in USB Stick.

- If your downloaded program version in USB Stick is Low,

it didn't work. But your downloaded version is High, USB

data is automatically detecting.(Download Version High &

Power only mode, Set is automatically Download)

(3) Show the message "Copying files from memory".

(4) Updating is starting.

(5) Updating Completed, The TV will restart automatically.

(6) If your TV is turned on, check your updated version and

Tool option. (explain the Tool option, next stage)

* If downloading version is more high than your TV have, TV

can lost all channel data. In this case, you have to channel

recover. if all channel data is cleared, you didn’t have a DTV/

ATV test on production line.

* After downloading, have to adjust Tool Option again.

(1) Push "IN-START" key in service remote control.

(2) Select "Tool Option 1" and push "OK" key.

(3) Punch in the number. (Each model has their number)

No. Item Min Typ Max Unit Remark

1.

Audio practical

max Output, L/R

(Distortion=10%

max Output)

9.0 10.0 12.0 W

Measurement condition

Auto Volume :Off

Audio EQ : Off

Clear Voice : Off

Virtual Surround:Off

8.5 8.9 9.8 Vrms

2.

Speaker (8Ω

Impedance)

10.0 15.0 W

- 21 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Only for training and service purposes

A22

A10

AT1

AG1

900

200

310

CAM1

400

420

410

540

530

120

570

560

300

510

121

820

LV1

* Set + Stand

LV2

A2

EXPLODED VIEW

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These

parts are identified by in the Schematic Diagram and EXPLODED VIEW.

It is essenti al that these special safet y parts shoul d be replac ed with the same compo nents as

recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.

Do not modify the original design without permission of manufacturer.

IMPORTANT SAFETY NOTICE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

EB_ADDR[13]

EMMC_DATA[5]

EB_ADDR[0]

EB_ADDR[14]

EB_ADDR[8]

EB_DATA[2]

EMMC_DATA[1]

EB_DATA[4]

EB_ADDR[11]

EB_DATA[3]

EB_DATA[5]

EB_ADDR[10]

EB_ADDR[12]

EMMC_DATA[7]

EB_ADDR[1]

EB_DATA[6]

EMMC_DATA[4]

EB_ADDR[6]

EB_ADDR[2]

EB_ADDR[4]

EB_DATA[0]

EMMC_DATA[0]

EMMC_DATA[6]

EMMC_DATA[3]

EB_ADDR[5]

EB_ADDR[3]

EB_ADDR[7]

EMMC_DATA[2]

EB_DATA[7]

EB_ADDR[9]

EB_DATA[1]

EMMC_RST

I2C_SCL_MICOM_SOC

R142

3.3K

TMS0

R174 33

X100

24MHz

4

GND_2

1

X-TAL_1

2

GND_1

3

X-TAL_2

TCK0

EMMC_CLK

WIFI_DM

RF_SWITCH_CTL

EPHY_EN

+3.3V_NORMAL

I2C_SDA_MICOM_SOC

TCK0

I2C_SCL1

/S2_RESET

HW_OPT_9

SMARTCARD_DATA/SD_EMMC_CLK

USB3_TX0M

UART2_RX

R155

10K

CI

EPHY_RXD1

EPHY_INT

I2C_SDA5

HDMI_S/W_RESET

PLLSET1

SMARTCARD_CLK/SD_EMMC_DATA[0]

+3.3V_NORMAL

HW_OPT_4

HDMI_CLK+

R159

200

1%

/PCM_CE1

SOC_RESET

R169 3.3K

SW100

JTP-1127WEM

DEBUG

12

4 3

HW_OPT_10

R125 10K

NON_DVB_T2_TUNER

R150

3.3K

OPT

+3.3V_NORMAL

R130 10K

NON_AJ_JA

XIN_MAIN

M_REMOTE_RTS

I2C_SDA1

R154

10K

CI

HW_OPT_1

R112

10K

INTERNAL_FRC

I2C_SCL6

R134 33

OPT

TDO0

R170 3.3K

HDMI_RX2-

+3.3V_NORMAL

+3.3V_NORMAL

I2C_SDA6

+3.3V_NORMAL

I2C_SDA5

PLLSET0

IRB_SPI_SS

TMS0

I2C_SDA4

INSTANT_BOOT

R118

3.3K

UART2_TX

+3.3V_NORMAL

R144

3.3K

IRB_SPI_CK

R148

3.3K

HDMI_RX0-

USB3_TX0P

+3.3V_NORMAL

I2C_SDA5

IRB_SPI_MOSI

SOC_TX

C105 0.1uF

UART2_TX

R101 33

OPT

R143

3.3K

OPM1

EB_ADDR[0-14]

R162

200

1%

C101

10pF

CAM_INPACK_N

R123 10K

NON_CP_BOX

+3.3V_NORMAL

R122 10K

OPT

EMMC_DATA[0-7]

I2C_SDA4

R135-*1

1.5K

KR_PIP

M_REMOTE_RX

M_RFModule_RESET

+3.3V_TU

+3.3V_NORMAL

FE_LNA_Ctrl2

HW_OPT_7

PLLSET0

TRST_N0

SMARTCARD_VCC/SD_EMMC_CMD

HW_OPT_5

HP_DET

FRC_RESET

R120 10K

V13_MODULE

I2C_SCL5

PLLSET1

WIFI_DP

I2C_SCL5

SOC_RX

SPDIF_OUT_ARC

SMARTCARD_DET/SD_EMMC_DATA[3]

R137

3.3K

I2C_SCL4

EPHY_MDC

R135

3.3K

KR_PIP_NOT

BOOT_MODE

OPM0

R121 10K

I2C_SCL6

USB3_RX0P

R138

3.3K

CAM_REG_N

R151 33

FE_LNA_Ctrl1

XIN_MAIN

USB2_HUB_IC_IN_DM

CAM_WAIT_N

EPHY_TXD0

R146

3.3K

R117

3.3K

OPT

TDO0

USB3_RX0M

USB3_DP

R129 10K

AJ_JA

R157

200

1%

R103

3.3K

DEBUG

I2C_SDA_MICOM_SOC

I2C_SCL4

R114 10K

FHD

/RST_PHY

HW_OPT_6

R116 10K

OLED

C100

10pF

USB3_DM

HDMI_RX1-

HDMI_RX2+

USB_DM2

R126 10K

DVB_T2_TUNER

HW_OPT_0

R139 33

/RST_HUB

+3.3V_NORMAL

TDI0

I2C_SCL1

R110 10K

TAIWAN

TRST_N0

C103

0.1uF

I2C_SDA6

R140 33

R147

3.3K

VCOM_DYN

INSTANT_BOOT

R106

33

HDMI_RX1+

CAM_CD2_N

CAM_CD1_N

R141

3.3K

R149 33

R165

3.3K

COMP1_DET

R109 10K

NON_TAIWAN

EB_DATA[0-7]

+3.3V_TU

R152

560

I2C_SCL2_SOC

R113 10K

UD

USB_CTL1

EMMC_CMD

+3.3V_NORMAL

EPHY_MDIO

SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]

HW_OPT_2

R153

10K

CI

XO_MAIN

R136

3.3K

KR_PIP_NOT

R131 10K

EPI

SOC_RESET

HDMI_INT

CAM_IREQ_N

SMARTCARD_RST/SD_EMMC_DATA[2]

AMP_RESET_N

I2C_SDA1

USB2_HUB_IC_IN_DP

/TU_RESET1

BOOT_MODE

R133 33

OPT

P101

12507WS-04L

DEBUG

1

2

3

4

5

R132 10K

NON_EPI

OPM1

H13A_SCL

R100 33

OPT

UART2_RX

C104 0.1uF

HDMI_RX0+

OPM0

PMIC_RESET

USB_DP2

M_REMOTE_CTS

R128 10K

DVB_S_TUNER

R108

1M

I2C_SCL2_SOC

R119 10K

V12_MODULE

R145

3.3K

AV1_CVBS_DET

R136-*1

1.5K

KR_PIP

R161 200 1%

I2C_SDA2_SOC

R115 10K

NON_OLED

R127 10K

NON_DVB_S_TUNER

HW_OPT_8

M_REMOTE_TX

R164

33

1/16W

5%

TDI0

I2C_SCL_MICOM_SOC

PCM_5V_CTL

EPHY_RXD0

H13A_SDA

XO_MAIN

R124 10K

CP_BOX

HDMI_CLK-

R10533

CAM_SLIDE_DET

HW_OPT_3

IRB_SPI_MISO

/TU_RESET2

I2C_SCL5

EPHY_TXD1

PCM_RESET

/PCM_CE2

SC_DET

EPHY_REFCLK

R111

10K

NO_FRC

I2C_SDA2_SOC

EPHY_CRS_DV

/USB_OCD1

/USB_OCD2

EB_WE_N

USB_CTL2

USB_CTL3

EB_BE_N1

EB_OE_N

/USB_OCD3

EB_BE_N0

IR_B_RESET

IC102

R1EX24256BSAS0A

EEPROM_RENESAS

3

A2

2

A1

4

VSS

1

A0

5

SDA

6

SCL

7

WP

8

VCC

IC102-*1

M24256-BRMN6TP

EEPROM_ST

3

E2

2

E1

4

VSS

1

E0

5

SDA

6

SCL

7

WC

8

VCC

I2C_SCL_MICOM

I2C_SCL_MICOM_SOC

I2C_SDA_MICOM_SOC

I2C_SDA2_SOC

I2C_SCL2_SOC

R104

33

R10233

I2C_SDA_MICOM

I2C_SCL2

I2C_SDA2

IC100

LG1154D_H13D

XIN

A26

XOUT

B26

XTAL_BYPASS

B27

H13DA_XTAL

AT37

PORES_N

AU16

OPM1

AD34

OPM0

AD33

H13DA_SCL

AT26

H13DA_SDA

AU26

TRST_N0

AP9

TMS0

AN9

TCK0

AP11

TDI0

AN11

TDO0

AN10

TRST_N1

AM10

TMS1

AM9

TCK1

AM11

TDI1

AM12

TDO1

AL11

PLLSET1

AL9

PLLSET0

AL10

BOOT_MODE

AE34

EXT_INTR3/GPIO70

Y33

EXT_INTR2/GPIO69

W32

EXT_INTR1/GPIO68

W33

EXT_INTR0/GPIO67

W34

UART0_RXD

AU12

UART0_TXD

AT12

UART1_RXD

AU13

UART1_TXD

AT13

UART1_RTS

AP12

UART1_CTS

AR12

SPI_CS0/GPIO36

AE35

SPI_DO0/GPIO38

AE36

SPI_DI0/GPIO39

AF36

SPI_SCLK0/GPIO37

AF35

SPI_CS1

AG34

SPI_DO1

AF33

SPI_DI1

AG33

SPI_SCLK1

AG32

SCL0/GPIO66

AR15

SDA0/GPIO65

AP15

SCL1/GPIO64

AR16

SDA1/GPIO79

AP16

SCL2/GPIO78

AP17

SDA2/GPIO77

AR17

SCL3

AP6

SDA3

AR6

SCL4

AH32

SDA4

AJ33

SCL5

AH34

SDA5

AH33

CAM_CE1_N

F33

CAM_CE2_N

F34

CAM_CD1_N/GPIO76

D32

CAM_CD2_N/GPIO75

E32

CAM_VS1_N/GPIO86

G32

CAM_VS2_N/GPIO85

G33

CAM_IREQ_N/GPIO73

F32

CAM_RESET

G34

CAM_INPACK/GPIO74

D33

CAM_VCCEN_N/GPIO87

H32

CAM_WAIT_N/GPIO84

E33

CAM_REG_N/GPIO72

D34

CAM_IOIS16_N/GPIO83

H33

SC_CLK/GPIO130

T33

SC_DETECT/GPIO133

U33

SC_VCCEN/GPIO129

T32

SC_VCC_SEL/GPIO128

V32

SC_RST/GPIO131

V33

SC_DATA/GPIO132

V34

SD_CLK/GPIO125

A25

SD_CMD/GPIO124

C25

SD_CD_N/GPIO123

B25

SD_WP_N/GPIO122

E25

SD_DATA3/GPIO121

D25

SD_DATA2/GPIO120

E24

SD_DATA1/GPIO135

D24

SD_DATA0/GPIO134

C24

USB2_2_DP0

L37

USB2_2_DM0

L36

USB2_2_TXRTUNE

K34

USB2_1_DP0

M37

USB2_1_DM0

M36

USB2_1_TXRTUNE

K33

USB2_0_DP

AU7

USB2_0_DM

AT7

USB2_0_TXRTUNE

AP7

USB3_DP0

P37

USB3_DM0

P36

USB3_RX0P

N36

USB3_RX0M

N37

USB3_TX0P

R36

USB3_TX0M

R37

USB3_RESREF

N34

USB3_REFPADCLKM

P33

USB3_REFPADCLKP

P32

NC_1

L32

NC_2

L33

NC_3

M31

NC_4

AJ31

GPIO136

J32

GPIO137

J33

GPIO138

K32

GPIO139

J34

GPIO31

AL34

GPIO30

AM33

GPIO29

AM32

GPIO28

AF30

GPIO27

AN34

GPIO26

AK34

GPIO25

AL33

GPIO24

AL32

GPIO23/UART2_TX

AR9

GPIO22/UART2_RX

AM5

GPIO21

AM6

GPIO20

AM7

GPIO19

AL6

GPIO18

AK7

GPIO17

AK6

GPIO16

AK5

GPIO15

AJ5

GPIO14

AJ6

GPIO13

AJ7

GPIO12

AH6

GPIO11

AG7

GPIO10

AG6

GPIO9

AG5

GPIO8

AF5

GPIO7

AH30

GPIO6

AG30

GPIO5

AN33

GPIO4

AK33

GPIO3

AE30

GPIO2

AD30

GPIO1

AN32

GPIO0

AK32

DDCD0_CK

AC32

DDCD0_DA

AC33

HPD0

AB33

PHY0_ARC_OUT_0

AE37

PHY0_RX0N_0

AC36

PHY0_RX0P_0

AC37

PHY0_RX1N_0

AB36

PHY0_RX1P_0

AB37

PHY0_RX2N_0

AA36

PHY0_RX2P_0

AA37

PHY0_RXCN_0

AD36

PHY0_RXCP_0

AD37

HUB_PORT_OVER0

R32

HUB_VBUS_CTRL0

R33

EB_CS3/GPIO93

K35

EB_CS2/GPIO92

K36

EB_CS1/GPIO91

K37

EB_CS0/GPIO90

L35

EB_WE_N/GPIO95

H35

EB_BE_N1/GPIO81

H36

EB_WAIT/GPIO94

J35

EB_OE_N/GPIO82

J36

EB_BE_N0/GPIO80

H37

EB_ADDR15/GPIO89

G37

EB_ADDR14/GPIO88

G36

EB_ADDR13/GPIO103

G35

EB_ADDR12/GPIO102

F36

EB_ADDR11/GPIO101

F35

EB_ADDR10/GPIO100

E36

EB_ADDR9/GPIO99

E37

EB_ADDR8/GPIO98

E35

EB_ADDR7/GPIO97

D37

EB_ADDR6/GPIO96

D36

EB_ADDR5/GPIO111

D35

EB_ADDR4/GPIO110

C36

EB_ADDR3/GPIO109

C35

EB_ADDR2/GPIO108

B37

EB_ADDR1/GPIO107

B36

EB_ADDR0/GPIO106

B35

EB_DATA7/GPIO105

C32

EB_DATA6/GPIO104

B33

EB_DATA5/GPIO119

A33

EB_DATA4/GPIO118

C33

EB_DATA3/GPIO117

A34

EB_DATA2/GPIO116

B34

EB_DATA1/GPIO115

C34

EB_DATA0/GPIO114

A36

EMMC_CLK

Y37

EMMC_CMD

Y36

EMMC_RESETN

W35

EMMC_DATA7

T36

EMMC_DATA6

W36

EMMC_DATA5

V35

EMMC_DATA4

V37

EMMC_DATA3

V36

EMMC_DATA2

U35

EMMC_DATA1

U36

EMMC_DATA0

U37

RMII_REF_CLK

AU11

RMII_CRS_DV

AU8

RMII_MDIO

AT8

RMII_MDC

AR8

RMII_TXEN

AR10

RMII_TXD1

AT10

RMII_TXD0

AU10

RMII_RXD1

AT11

RMII_RXD0

AR11

TP102

TP103

TP104

TP105

TP106

TP101

TP108

TP109

TP100

IRB_SPI_SS

TP107

IRB_SPI_MOSI

TP111

TP110

IRB_SPI_CK

IRB_SPI_MISO

IR_B_RESET

TP112

C106

33pF

50V

interface

local dimming

I2C port

BOOT MODE

"0 : EMMC

"1 : TEST MODE

OLED option

T2 support

AREA option1

NVRAM

Debug

satellite support

INSTANT_MODE0

EPI PANEL version

INSTANT boot MODE

"1 : Instant boot

"0 : normal

(internal pull down)

AREA option2

System Configuration

AC-coupling CAP

reserved

A0’h

Clock for LG1154D

Jtag I/F For Main

Place near by LG1154D

OP MODE[1:0]

"00" : Normal Mode

"01/10/11" : Internal Test mode

Write Protection

- Low : Normal Operation

- High : Write Protection

BOOT_MODE0

I2C for tuner

PLL SET[1:0] : internal pull up

"00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz)

"01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz)

"10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz)

"11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)

FRC option

System Clock for Analog block(24Mhz)

Model Option

MAIN Clock(24Mhz)

Pannel Resol

I2C PULL UP

CP BOX

EPI selection

For ISP

I2C for tuner

Only SMART CARD

Not Support

Panel

Area1

Not Support

No FRC(60Hz)

Disable

MODEL_OPT_5

MODEL_OPT_6

OLED

FRCMODEL_OPT_1

CP BOX

LOW

AJ_JA

NON OLED

Enable

MODEL_OPT_3

S Tuner

Support

Default

Area2

V12

HIGH

non Taiwan

MODEL_OPT_4

UD

MODEL_OPT_8

Module

Support

Reserved

OLED

MODEL_OPT_7

V13

FRC(120Hz)

MODEL_OPT_0

EPI

MODEL_OPT_2

Support

MODEL_OPT_10

MODEL_OPT_9

T2 Tuner

FHD

Not Support

Taiwan

BSD-NC4_H001-HD

2012-11-14

H13 D CHIP

non AJ_JA

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

L222

BLM18PG121SN1D

+1.1V_VDD

L225

BLM15BD121SN1

4.7uF

C200

R202

1K 1%

4.7uFC241

L216

BLM18PG121SN1D

VREF_M0_0

4.7uFC239

R300

1K 1%

C283 0.1uF

L228

BLM18PG121SN1D

4.7uFC378

VDDC11_XTAL

VDDC15_M0

4.7uFC201

C274 0.1uF

+3.3V_NORMAL

L238

BLM18PG121SN1D

+1.1V_VDD

4.7uFC211

+1.0V_VDD

+2.5V_Normal

L203

BLM18PG121SN1D

VDD25_XTAL

C208 0.1uF

OPT

AVDD33

AVDD33

L201

BLM18PG121SN1D

VDD25_LTX

VDD10_XTAL

+1.0V_VDD

AVDD25

C206 0.1uF

4.7uFC214

C308

0.1uF

C344

0.1uF

OPT

VDD25_REF

AVDD33_XTAL

VDDC10

C204 0.1uF

4.7uFC209

OPT

C251 0.1uF

+3.3V_NORMAL

VDD25_AUD

+2.5V_Normal

C218 0.1uF

L220

BLM18PG121SN1D

+1.5V_DDR

VDDC15_M1

L207

BLM18PG121SN1D

VDDC15_M0

22uF

C303

+1.5V_DDR

L211

BLM18PG121SN1D

L226

BLM15BD121SN1

+1.1V_VDD

+3.3V_NORMAL

R201

1K 1%

4.7uFC270

C306

0.1uF

R303

1K 1%

4.7uFC216

AVDD33_CVBS

C300 0.1uF

VDDC11_XTAL

R203

1K 1%

4.7uFC279

L200

BLM18PG121SN1D

L234

BLM18PG121SN1D

VDD10_XTAL

VDDC15_M1

C381 0.1uF

VREF_M1_1

VDDC15_M0

C259 0.1uF

AVDD33_CVBS

4.7uFC297

VDD25_LVDS

+2.5V_Normal

VREF_M1_0

+1.1V_VDD

AVDD33_XTAL

C223 0.1uF

AVDD25

4.7uFC298

VREF_M0_1

VSS25_REF

4.7uFC364

VDD25_LVDS

4.7uF

C202

R301

1K 1%

C301 0.1uF

VSS25_REF

C203 0.1uF

VREF_M0_0

C310

0.1uF

OPT

VREF_M1_0

C288

0.1uF

VDD10_XTAL

4.7uFC242

+2.5V_Normal

4.7uFC255

C207 0.1uF

OPT

22uFC299

VDDC15_M1

4.7uFC351

VDD25_XTAL

VDD25_XTAL

C307

0.1uF

C296

0.1uF

OPT

VREF_M0_1

VDDC15_M0

VDDC10

L227

BLM18PG121SN1D

VDD25_LTX

4.7uFC275

C302

0.1uF

VREF_M1_1

VDD25_LTX

VDD11_VTXPHY

R200

1K 1%

L230

BLM18PG121SN1D

L209

BLM18PG121SN1D

C246 0.1uF

VDD33

L206

BLM18PG121SN1D

VDDC15_M1

R302

1K 1%

+2.5V_Normal

VDD25_REF

+3.3V_NORMAL

4.7uFC205

C304

0.1uF

OPT

VDD25_AUD

C368 0.1uF

VDD33

+1.1V_VDD

VDD11_VTXPHY

VDDC11_XTAL

JP202

JP204

JP205

JP203

MDS62110209

M200

GASKET_8.0X6.0X8.5H

NON_LA8600

IC101

LG1154AN_H13A

H13A_NON_BRAZIL

VDD33_1

E11

VDD33_2

F5

VDD33_3

F6

VDD33_4

F11

VDD33_5

G5

VDD33_6

H13

VDD33_7

J13

VDD33_8

P12

VDD33_9

P13

VDD33_10

R5

VDD33_11

R6

VDD33_XTAL

N16

AVDD33_CVBS_1

T13

AVDD33_CVBS_2

T14

VDD25_CVBS_1

N10

VDD25_CVBS_2

N11

VDD25_VSB_1

N12

VDD25_VSB_2

N13

VDD25_REF

U5

VDD25_COMP_1

N7

VDD25_COMP_2

N8

VDD25_COMP_3

N9

VDD25_APLL

F14

VDD25_AUD_1

M6

VDD25_AUD_2

N6

VDD25_AAD

M13

LTX_LVDD_1

F15

LTX_LVDD_2

F16

SDRAM_VDDQ_1

H15

SDRAM_VDDQ_2

J15

SDRAM_VDDQ_3

J16

SDRAM_VDDQ_4

K15

SDRAM_VDDQ_5

K16

VDD10_XTAL

R18

VDDC10_1

G7

VDDC10_2

G8

VDDC10_3

G9

VDDC10_4

H7

VDDC10_5

H12

VDDC10_6

J7

VDDC10_7

J12

VDDC10_8

K7

VDDC10_9

K12

VDDC10_10

L7

VDDC10_11

L12

VDDC10_12

M7

VDDC10_13

M12

AVDD10_CVBS

T17

AVDD10_VSB

T18

AVDD10_LLPLL

M8

DVDD10_APLL_1

G10

DVDD10_APLL_2

G11

LTX_VDD

G12

VSS25_REF

V5

GND_1

C3

GND_2

D3

GND_3

D4

GND_4

D17

GND_5

E4

GND_6

F4

GND_7

F7

GND_8

F8

GND_9

F9

GND_10

F10

GND_11

F12

GND_12

F13

GND_13

F17

GND_14

F18

GND_15

G4

GND_16

G6

GND_17

G13

GND_18

G14

GND_19

G15

GND_20

G16

GND_21

G17

GND_22

G18

GND_23

H4

GND_24

H5

GND_25

H6

GND_26

H8

GND_27

H9

GND_28

H10

GND_29

H11

GND_30

H14

GND_31

J4

GND_32

J5

GND_33

J6

GND_34

J8

GND_35

J9

GND_36

J10

GND_37

J11

GND_38

J14

GND_39

K4

GND_40

K5

GND_41

K6

GND_42

K8

GND_43

K9

GND_44

K10

GND_45

K11

GND_46

K13

GND_47

K14

GND_48

L1

GND_49

L2

GND_50

L3

GND_51

L4

GND_52

L5

GND_53

L6

GND_54

L8

GND_55

L9

GND_56

L10

GND_57

L11

GND_58

L13

GND_59

L14

GND_60

L15

GND_61

L16

GND_62

L17

GND_63

L18

GND_64

M1

GND_65

M2

GND_66

M3

GND_67

M4

GND_68

M5

GND_69

M9

GND_70

M10

GND_71

M11

GND_72

M14

GND_73

M15

GND_74

M16

GND_75

N4

GND_76

N5

GND_77

N14

GND_78

N15

GND_79

N17

GND_80

P4

GND_81

P5

GND_82

P6

GND_83

P7

GND_84

P8

GND_85

P9

GND_86

P10

GND_87

P11

GND_88

P14

GND_89

P15

GND_90

P16

GND_91

R4

GND_92

R7

GND_93

R8

GND_94

R9

GND_95

R10

GND_96

R11

GND_97

R12

GND_98

R13

GND_99

R14

GND_100

R15

GND_101

R16

GND_102

R17

GND_103

T4

GND_104

T7

GND_105

T8

GND_106

T9

GND_107

T10

GND_108

T11

GND_109

T12

GND_110

T15

GND_111

T16

GND_112

U4

GND_113

U6

GND_114

U18

GND_115

V4

GND_116

V16

IC100

LG1154D_H13D

M0_DDR_VREF1

A24

M0_DDR_VREF2

A4

M1_DDR_VREF1

A2

M1_DDR_VREF2

Y1

XTAL_VDD

P26

XTAL_VDDP

N26

VDD33_1

M21

VDD33_2

Y30

VDD33_3

AA30

VDD33_4

AE8

VDD33_5

AF8

VDD33_6

AK13

VDD33_7

AK24

VDD33_8

AK25

AVDD33_USB_1

M22

AVDD33_USB_2

M23

AVDD33_BT_USB_1

AK11

AVDD33_BT_USB_2

AK12

AVDD33_HDMI_1

AF25

AVDD33_HDMI_2

AF26

SP_VQPS

R31

VDD25_LVRX_1

AE23

VDD25_LVRX_2

AF23

VTXPHY_VDD25_1

AE14

VTXPHY_VDD25_2

AF14

VDD25_DR3PLL

N25

GPLL_AVDD25

AD26

VDD15_M0_1

H10

VDD15_M0_2

H11

VDD15_M0_3

H12

VDD15_M0_4

H13

VDD15_M0_5

H14

VDD15_M0_6

H15

VDD15_M0_7

H16

VDD15_M0_8

H17

VDD15_M0_9

H18

VDD15_M0_10

H19

VDD15_M0_11

H20

VDD15_M0_12

H21

VDD15_M0_13

H22

VDD15_M0_14

H23

VDD15_M0_15

H24

VDD15_M0_16

H25

VDD15_M1_1

H7

VDD15_M1_2

H8

VDD15_M1_3

J8

VDD15_M1_4

K8

VDD15_M1_5

L7

VDD15_M1_6

L8

VDD15_M1_7

M8

VDD15_M1_8

N7

VDD15_M1_9

N8

VDD15_M1_10

P8

VDD15_M1_11

R7

VDD15_M1_12

R8

VDD15_M1_13

T8

VDD15_M1_14

U8

VDD15_M1_15

V8

VDD15_M1_16

W8

VDDC11_1

N21

VDDC11_2

N22

VDDC11_3

N23

VDDC11_4

P15

VDDC11_5

P16

VDDC11_6

P17

VDDC11_7

P18

VDDC11_8

R15

VDDC11_9

T15

VDDC11_10

T22

VDDC11_11

T23

VDDC11_12

T24

VDDC11_13

U15

VDDC11_14

U22

VDDC11_15

U23

VDDC11_16

U24

VDDC11_17

V15

VDDC11_18

V22

VDDC11_19

V23

VDDC11_20

V24

VDDC11_21

W22

VDDC11_22

W23

VDDC11_23

W24

VDDC11_24

AB15

VDDC11_25

AB24

VDDC11_26

AC15

VDDC11_27

AC24

VDDC11_28

AD15

VDDC11_29

AD16

VDDC11_30

AD17

VDDC11_31

AD18

VDDC11_32

AD21

VDDC11_33

AD22

VDDC11_34

AD23

VDDC11_35

AD24

VTXPHY_VDD11_1

AB14

VTXPHY_VDD11_2

AC14

VTXPHY_VDD11_3

AD14

AVDD11_DR3PLL

P25

AVDD11_DCO

AA15

GPLL_VDD11

AC26

IC100

LG1154D_H13D

GND_1

A27

GND_2

B5

GND_3

C5

GND_4

C26

GND_5

C27

GND_6

D5

GND_7

D26

GND_8

E5

GND_9

E6

GND_10

E7

GND_11

E8

GND_12

E22

GND_13

E23

GND_14

E26

GND_15

F7

GND_16

F8

GND_17

F22

GND_18

F23

GND_19

F24

GND_20

F25

GND_21

F26

GND_22

F27

GND_23

F31

GND_24

G7

GND_25

G8

GND_26

G9

GND_27

G10

GND_28

G11

GND_29

G12

GND_30

G13

GND_31

G14

GND_32

G15

GND_33

G16

GND_34

G17

GND_35

G18

GND_36

G19

GND_37

G20

GND_38

G21

GND_39

G22

GND_40

G23

GND_41

G24

GND_42

G25

GND_43

G26

GND_44

G27

GND_45

G28

GND_46

G29

GND_47

G30

GND_48

G31

GND_49

H9

GND_50

H26

GND_51

H27

GND_52

H28

GND_53

H29

GND_54

H30

GND_55

H31

GND_56

J7

GND_57

J30

GND_58

J31

GND_59

K7

GND_60

K30

GND_61

K31

GND_62

L30

GND_63

L31

GND_64

M7

GND_65

M12

GND_66

M13

GND_67

M14

GND_68

M15

GND_69

M16

GND_70

M17

GND_71

M18

GND_72

M19

GND_73

M20

GND_74

M24

GND_75

M25

GND_76

M26

GND_77

M30

GND_78

M32

GND_79

M33

GND_80

M34

GND_81

N12

GND_82

N13

GND_83

N14

GND_84

N15

GND_85

N16

GND_86

N17

GND_87

N18

GND_88

N19

GND_89

N20

GND_90

N24

GND_91

N30

GND_92

N31

GND_93

N32

GND_94

N33

GND_95

P7

GND_96

P12

GND_97

P13

GND_98

P14

GND_99

P19

GND_100

P20

GND_101

P21

GND_102

P22

GND_103

P23

GND_104

P24

GND_105

P30

GND_106

P31

GND_107

R12

GND_108

R13

GND_109

R14

GND_110

R16

GND_111

R17

GND_112

R18

GND_113

R19

GND_114

R20

GND_115

R21

GND_116

R22

GND_117

R23

GND_118

R24

GND_119

R25

GND_120

R26

GND_121

R30

GND_122

R34

GND_123

T7

GND_124

T12

GND_125

T13

GND_126

T14

GND_127

T16

GND_128

T17

GND_129

T18

GND_130

T19

GND_131

T20

GND_132

T21

GND_133

T25

GND_134

T26

GND_135

T30

GND_136

T31

GND_137

T34

GND_138

U7

GND_139

U12

GND_140

U13

GND_141

U14

GND_142

U16

GND_143

U17

GND_144

U18

GND_145

U19

GND_146

U20

GND_147

U21

GND_148

U25

GND_149

U26

GND_150

U30

GND_151

U31

GND_152

V7

GND_153

V12

GND_154

V13

GND_155

V14

GND_156

V16

GND_157

V17

GND_158

V18

GND_159

V19

GND_160

V20

GND_161

V21

GND_162

V25

GND_163

V26

GND_164

V30

GND_165

V31

GND_166

W5

GND_167

W6

GND_168

W7

GND_169

W12

GND_170

W13

GND_171

W14

GND_172

W15

GND_173

W16

GND_174

W17

GND_175

W18

GND_176

W19

GND_177

W20

GND_178

W21

GND_179

W25

GND_180

W26

GND_181

W30

GND_182

W31

GND_183

Y3

GND_184

Y4

GND_185

Y5

GND_186

Y8

GND_187

Y12

GND_188

Y13

GND_189

Y14

GND_190

Y15

GND_191

Y16

GND_192

Y17

GND_193

Y18

GND_194

Y19

GND_195

Y20

GND_196

Y21

GND_197

Y22

GND_198

Y23

GND_199

Y24

GND_200

Y25

GND_201

Y26

GND_202

Y31

GND_203

Y35

GND_204

AA8

GND_205

AA12

GND_206

AA13

GND_207

AA14

GND_208

AA16

GND_209

AA17

GND_210

AA18

GND_211

AA19

GND_212

AA20

GND_213

AA21

GND_214

AA22

GND_215

AA23

GND_216

AA24

GND_217

AA25

GND_218

AA26

GND_219

AA31

GND_220

AB6

GND_221

AB8

GND_222

AB12

GND_223

AB13

GND_224

AB16

GND_225

AB17

GND_226

AB18

GND_227

AB19

GND_228

AB20

GND_229

AB21

GND_230

AB22

GND_231

AB23

GND_232

AB25

GND_233

AB26

GND_234

AB30

GND_235

AB31

GND_236

AC8

GND_237

AC12

GND_238

AC13

GND_239

AC16

GND_240

AC17

GND_241

AC18

GND_242

AC19

GND_243

AC20

GND_244

AC21

GND_245

AC22

GND_246

AC23

GND_247

AC25

GND_248

AC30

GND_249

AC31

GND_250

AD8

GND_251

AD12

GND_252

AD13

GND_253

AD19

GND_254

AD20

GND_255

AD25

GND_256

AD31

GND_257

AE12

GND_258

AE13

GND_259

AE15

GND_260

AE16

GND_261

AE17

GND_262

AE18

GND_263

AE19

GND_264

AE20

GND_265

AE21

GND_266

AE22

GND_267

AE24

GND_268

AE25

GND_269

AE26

GND_270

AE31

GND_271

AF12

GND_272

AF13

GND_273

AF15

GND_274

AF16

GND_275

AF17

GND_276

AF18

GND_277

AF19

GND_278

AF20

GND_279

AF21

GND_280

AF22

GND_281

AF24

GND_282

AF31

GND_283

AG8

GND_284

AG31

GND_285

AH8

GND_286

AH31

GND_287

AJ8

GND_288

AJ30

GND_289

AK8

GND_290

AK9

GND_291

AK10

GND_292

AK14

GND_293

AK15

GND_294

AK16

GND_295

AK17

GND_296

AK18

GND_297

AK19

GND_298

AK20

GND_299

AK21

GND_300

AK22

GND_301

AK23

GND_302

AK26

GND_303

AK27

GND_304

AK28

GND_305

AK29

GND_306

AK30

GND_307

AK31

GND_308

AL8

GND_309

AL12

GND_310

AL13

GND_311

AL14

GND_312

AL15

GND_313

AL16

GND_314

AL17

GND_315

AL18

GND_316

AL19

GND_317

AL20

GND_318

AL21

GND_319

AL22

GND_320

AL23

GND_321

AL24

GND_322

AL25

GND_323

AL26

GND_324

AL27

GND_325

AL28

GND_326

AL29

GND_327

AL30

GND_328

AL31

GND_329

AM8

GND_330

AM13

GND_331

AM14

GND_332

AM15

GND_333

AM16

GND_334

AM17

GND_335

AM18

GND_336

AM19

GND_337

AM20

GND_338

AM21

GND_339

AM22

GND_340

AM23

GND_341

AM24

GND_342

AM25

GND_343

AM26

GND_344

AM27

GND_345

AM28

GND_346

AM29

GND_347

AM30

GND_348

AM31

GND_349

AN6

GND_350

AN12

GND_351

AN13

GND_352

AN15

GND_353

AN16

GND_354

AN17

GND_355

AN18

GND_356

AN19

GND_357

AN20

GND_358

AN21

GND_359

AN22

GND_360

AN23

GND_361

AN24

GND_362

AN25

GND_363

AN26

GND_364

AN27

GND_365

AN28

GND_366

AN29

GND_367

AN30

GND_368

AN31

IC101-*1

LG1154AN_H13A_ISDB-T (LG1154AN-IT)

H13A_BRAZIL

XIN_SUB

P17

XO_SUB

P18

VSB_AUX_XIN

J17

XTAL_BYPASS

N18

CLK_24M

D18

XTAL_SEL0

M18

XTAL_SEL1

M17

PORES_N

E3

OPM0

K3

OPM1

K2

H13A_SCL

A8

H13A_SDA

B8

CVBS_IN3

U13

CVBS_IN2

V14

CVBS_IN1

V15

CVBS_VCM

V13

BUF_OUT1

U15

BUF_OUT2

U14

REFT

U7

REFB

V6

ADC1_COM

V7

ADC2_COM

U10

ADC3_COM

V12

SC1_SID

T5

SC1_FB

T6

PB1_IN

U8

Y1_IN

V8

SOY1_IN

V9

PR1_IN

U9

PB2_IN

V10

Y2_IN

U11

SOY2_IN

V11

PR2_IN

U12

AAD_ADC_SIF

H18

AAD_ADC_SIFM

H17

AUDA_VBG_EXT

P2

AUDA_OUTL

N1

AUDA_OUTR

N2

AUD_SCART_OUTL

N3

AUD_SCART_OUTR

P1

AUAD_L_CH4_IN

P3

AUAD_R_CH4_IN

R1

AUAD_L_CH3_IN

R2

AUAD_R_CH3_IN

T1

AUAD_L_CH2_IN

U2

AUAD_R_CH2_IN

U3

AUAD_L_CH1_IN

V2

AUAD_R_CH1_IN

V3

AUAD_R_REF

U1

AUAD_M_REF

T3

AUAD_L_REF

T2

AUAD_REF_PO

R3

ANTCON

K17

RFAGC

K18

IFAGC

J18

ADC_I_INCOM

U16

ADC_I_INP

U17

ADC_I_INN

V17

GPIO0

F3

GPIO1

F2

GPIO2

F1

GPIO3

G3

GPIO4

G2

GPIO5

G1

GPIO6

H3

GPIO7

H2

GPIO8

H1

GPIO9

J3

GPIO10

E18

GPIO11

E17

GPIO12

H16

GPIO13

J2

GPIO14

J1

GPIO15

K1

MAIN POWER

+2.5V_Bypass Cap

+1.0V_Bypass Cap

1005 size bead

Bottom side of chip

+3.3V

+1.5V

LG1154A

(1)

(2)

AFE 3CH Power

+2.5V

+3.3V_Bypass Cap

+3.3V_Bypass Cap

+1.5V_Bypass Cap

(1)

(4)

LG1154A

+1.1V_Bypass Cap

(2)

+0.75V

+2.5V_Bypass Cap

+1.1V

LG1154D

BSD-NC4_H002-HD

2012-12-24

GND JIG POINT

SMD TOP for EMI

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

TPO_DATA[0]

TPO_DATA[2]

TPO_DATA[3]

FE_DEMOD1_TS_DATA[1]

TPO_DATA[7]

FE_DEMOD1_TS_DATA[7]

FE_DEMOD1_TS_DATA[3]

FE_DEMOD1_TS_DATA[5]

FE_DEMOD1_TS_DATA[2]

FE_DEMOD1_TS_DATA[6]

TPI_DATA[0]

FE_DEMOD1_TS_DATA[0]

TPI_DATA[7]

TPI_DATA[1]

TPI_DATA[5]

TPO_DATA[6]

TPI_DATA[3]

TPO_DATA[5]

TPI_DATA[6]

TPO_DATA[1]

TPI_DATA[4]

TPI_DATA[2]

FE_DEMOD1_TS_DATA[4]

TPO_DATA[4]

TPO_DATA[0-7]

AUAD_R_REF

R434

100

R404

100K

EU

AUAD_R_CH3_IN

R408

100K

EU

D406

5.5V

D401

5.5V

TXB0P/TX5P

TXA0P/TX11P

R432

100

C402

150pF

50V

OPT

COMP1_Y_IN_SOC_SOY

DTV/MNT_V_OUT_SOC

HW_OPT_2

SC_B

AUAD_REF_PO

COMP2_Y_IN_SOC_SOY

H13A_SDA

C423 0.047uF

C400

0.01uF

COMP2_Y_IN_SOC

TPO_ERR

TPO_SOP

R49433

SCART_Lout

R422

75

SCART_FB_DIRECT

TXC1N

TPO_ERR

R440 10K 1%

C405

150pF

50V

D403

5.5V

C454 0.1uF

H13A_SCL

FE_DEMOD2_TS_CLK

R453 330

R409

100K

EU

COMP2_PR_IN_SOC

R419 27K

1%

SCART_AMP_L_FB

R431

33

COMP2_PB_IN_SOC

AUD_SCK

GST_SOC

SCART_Rout_SOC

R454

2

1/10W

5%

OPT

BPL_IN

R427

33

XOUT_SUB

X400

24MHz

4

GND_2

1

X-TAL_1

2

GND_1

3

X-TAL_2

R445

22K

C403

2.2uF

10V

EU

C447

1uF

25V

OPT

AV1_CVBS_IN

+3.3V_NORMAL

R481

10K

OPT

SC_CVBS_IN

C420 0.047uF

COMP1/AV1/DVI_L_IN

C424 0.047uF

R439 10K 1%

ADC_I_INP

TXB4N/TX0N

SC_FB

TXA2N/TX9N

SC_R

TPI_DATA[0-7]

TU_CVBS

OPM[1]

C6006

1uF25V

EU

C429 1000pF

PWM_DIM2

TPI_CLK

FE_DEMOD1_TS_DATA[0-7]

SC_CVBS_IN_SOY

R429

33

R416

75

1%

EU

TXBCLKN/TX2N

C406

2.2uF

10V

EU

COMP1_PR_IN_SOC

TXA1N/TX10N

R447 68

R448 68

C425 0.047uF

COMP1_Y_IN_SOC_SOY

R425

33

C458 0.01uF

EU

SC_CVBS_IN_SOY

EO_SOC

FE_DEMOD2_TS_ERROR

COMP2_PR_IN_SOC

L408

1uH

HW_OPT_7

TP400

COMP1_Y_IN_SOC

TXACLKP/TX8P

R435

10K

EU

C435 4.7uF

HW_OPT_8

AUAD_M_REF

DPM

TXB0N/TX5N

R438 10K 1%

XTAL_SEL[0]

+12V

COMP1_PR_IN_SOC

FE_DEMOD1_TS_SYNC

FE_DEMOD1_TS_CLK

TPI_SOP

XTAL_SEL[0]

R498 100

C460 0.01uF

EU

XTAL_SEL[1]

AUAD_R_CH2_IN

TXB3N/TX1N

HW_OPT_4

DPM

TXB1N/TX4N

C442 0.047uF

R490

100

R450

68

R49333

COMP2_Y_IN_SOC_SOY

AUAD_L_CH2_IN

TXCCLKP

R482

10K

OPT

R430

22K

TXA3N/TX7N

TXA3P/TX7P

AUAD_R_REF

HW_OPT_10

FE_DEMOD3_TS_CLK

C426

10pF

TUNER_SIF

C450 0.1uF

R480100

EU

R426

22K

EU

C446

0.1uF

C441 0.047uF

SCART_Lout_SOC

C451 0.1uF

TXACLKN/TX8N

SCART_Rout

R420 27K

1%

HW_OPT_6

GCLK_SOC

TXC4P

+2.5V_Normal

FE_DEMOD1_TS_VAL

FE_DEMOD3_TS_ERROR

TPO_CLK

C419

0.047uF

R411

75

1%

EU

C470

10pF

50V

TXB2N/TX3N

SC_FB_SOC

OPM[0]

SC_G

COMP1_PB_IN_SOC

R436

2.7K

EU

C408

150pF

50V

EU

HW_OPT_0

PWM1

COMP1/AV1/DVI_R_IN

C6001

1uF 25V

EU

PWM2

FE_DEMOD2_TS_DATA

HW_OPT_9

OPM[0]

C427

10pF

C432 4.7uF

R417

75

1%

TXC1P

R483

10K

OPT

R462

100

FRC_FLASH_WP

R418 27K

1%

HW_OPT_3

R487

0

NON_TU_W_BR/TW/CO

FE_DEMOD3_TS_DATA

SC_ID_SOC

R437 10K 1%

C440 0.047uF

AUDA_OUTR

REFB

XIN_SUB

FE_DEMOD3_TS_VAL

SC_R_IN

AUD_LRCK

TXA1P/TX10P

C421 0.047uF

TXB1P/TX4P

C443 0.047uF

PWM_DIM

COMP2_PB_IN_SOC

HW_OPT_1

COMP1_Y

AUAD_R_CH3_IN

AUAD_L_REF

C473

10pF

50V

OPT

R495 100

C422 0.047uF

C456

4.7uF

10V

AUD_LRCH

C439

100pF

50V

OPT

SPDIF_OUT

AV1_CVBS_IN_SOC

C430

10pF

50V

TXCCLKN

R442

22K

EU

C417 0.047uF

C431

10pF

50V

HP_LOUT_MAIN

SC_L_IN

XOUT_SUB

TXC2N

HP_ROUT_MAIN

TXC2P

C410

150pF

AV1_CVBS_IN_SOC

R424

33

SC_CVBS_IN_SOC

C474

10pF

50V

OPT

R428

33

XTAL_SEL[1]

C472

10pF

50V

OPT

R403

100K

EU

TPI_ERR

MCLK_SOC

XIN_SUB

C448

4.7uF

10V

OPT

AUAD_REF_PO

L409

EU

1uH

REFT

C453 2.2uF

R412

75

1%

EU

TU_CVBS_SOC

R45 5

51K

1%

COMP2_Y_IN_SOC

R433

100

AUAD_R_CH2_IN

TXC0P

R496 100

TXA2P/TX9P

C4494.7uF

AUAD_L_REF

R436-*1

0

NON_EU

R484

10K

OPT

OPM[1]

HW_OPT_5

C445

0.1uF

TXB2P/TX3P

TXC4N

R6005

10K

EU

C462

150pF

EU

SCART_Rout_SOC

R460

100

FE_DEMOD2_TS_SYNC

R422-*1

0

NON_EU

TPI_ERR

R449 68

C401

0.01uF

COMP1_Pb

AUAD_M_REF

TXC3P

COMP1_Pr

+3.3V_NORMAL

R441

1M

TXB3P/TX1P

PWM2

REFT

SC_FB_SOC

C428 1000pF

R461

100

R459

100

AUDA_OUTL

TXC3N

COMP1_Y_IN_SOC

D404

5.5V

SCART_AMP_R_FB

R421 27K

1%

R423 100

SCART_FB_DIRECT

R410

75

1%

10uFC452

AUAD_L_CH2_IN

C459

0.1uF

TU_W_BR/TW/CO

SC_ID

FE_DEMOD1_TS_ERROR

R479100

EU

AUAD_L_CH3_IN

R45 7

51K

1%

AUDA_OUTL

TXA4N/TX6N

AUAD_L_CH3_IN

L/DIM0_MOSI

TXB4P/TX0P

TPI_VAL

R415

75

1%

REFB

TPO_VAL

C433 4.7uF

FE_DEMOD3_TS_SYNC

R6450

100

SC_CVBS_IN_SOC

SC_ID_SOC

SCART_Lout_SOC

C418 0.047uF

R60 06

10K

EU

SOC_RESET

L/DIM0_VS

AUD_MASTER_CLK

10uF

C455

L407

R497 100

ADC_I_INN

FE_DEMOD2_TS_VAL

R6451

100

R489

100

TXA4P/TX6P

C444

0.1uF

PWM1

TU_CVBS_SOC

COMP1_PB_IN_SOC

TXC0N

R413

75

1%

TXBCLKP/TX2P

TP402

AUDA_OUTR

IF_AGC

L/DIM0_SCLK

R414

75

1%

EU

C457

1000pF

OPT

TXA0N/TX11N

C434 4.7uF

R407 330

R492 330

CLK_54M_VTT

DAC_START_PULLDOWN

R466

82

1/16W

1%

+3.3V_NORMAL

DAC_START_PULLDOWN

CLK_54M_VTT

R464

1K

1/16W

1%

R465

390

1/16W

1%

R467 82

1/16W1%

TXB0P

TXB0N

TXB1N

TXB1P

TXACLKN

TXA4N

TXA4P

TXACLKP

TXB2N

TXA1P

TXA1N

TXB2P

L401

BLM18PG121SN1D

HP_OUT

HP_ROUT

C436

22pF

NON_TU_W_BR/TW

L400

BLM18PG121SN1D

HP_OUT

IF_P

HP_LOUT_AMP

IF_N

C407

0.22uF

10V

HP_OUT

L406

OPT

ADC_I_INP

R443

51

NON_TU_W_BR/TW

HP_LOUT

C437

0.01uF

HP_ROUT_AMP

C438

0.01uF

R444

51

NON_TU_W_BR/TW

ADC_I_INN

C409

0.22uF

10V

HP_OUT

C411

10pF

50V

OPT

R402 33

R405 33

R400 33

4.7uF

C413

EU

IC400

MM1756DURE

EU

3

BIAS

2

GND

4

OUT

1

IN

6

VCC

5

PS

DTV/MNT_V_OUT_SOC

C414

0.1uF

EU

+3.3V_NORMAL

C412

0.1uF

EU

DTV/MNT_V_OUT

Q400

MMBT3904(NXP)

SCART_FB_BUFFER

E

B

C

R446

4.7K

SCART_FB_BUFFER

SC_FB_BUF

R4061K

1/16W

1%

SCART_FB_BUFFER

SC_FB

+3.3V_NORMAL

SC_FB_BUF

C404

0.01uF

50V

EPI_LOCK6

R401

470

1/16W

5%

SCART_FB_BUFFER

R45 647K 1 %

R45 8

47K

1%

IC101

LG1154AN_H13A

H13A_NON_BRAZIL

XIN_SUB

P17

XO_SUB

P18

VSB_AUX_XIN

J17

XTAL_BYPASS

N18

CLK_24M

D18

XTAL_SEL0

M18

XTAL_SEL1

M17

PORES_N

E3

OPM0

K3

OPM1

K2

H13A_SCL

A8

H13A_SDA

B8

CVBS_IN3

U13

CVBS_IN2

V14

CVBS_IN1

V15

CVBS_VCM

V13

BUF_OUT1

U15

BUF_OUT2

U14

REFT

U7

REFB

V6

ADC1_COM

V7

ADC2_COM

U10

ADC3_COM

V12

SC1_SID

T5

SC1_FB

T6

PB1_IN

U8

Y1_IN

V8

SOY1_IN

V9

PR1_IN

U9

PB2_IN

V10

Y2_IN

U11

SOY2_IN

V11

PR2_IN

U12

AAD_ADC_SIF

H18

AAD_ADC_SIFM

H17

AUDA_VBG_EXT

P2

AUDA_OUTL

N1

AUDA_OUTR

N2

AUD_SCART_OUTL

N3

AUD_SCART_OUTR

P1

AUAD_L_CH4_IN

P3

AUAD_R_CH4_IN

R1

AUAD_L_CH3_IN

R2

AUAD_R_CH3_IN

T1

AUAD_L_CH2_IN

U2

AUAD_R_CH2_IN

U3

AUAD_L_CH1_IN

V2

AUAD_R_CH1_IN

V3

AUAD_R_REF

U1

AUAD_M_REF

T3

AUAD_L_REF

T2

AUAD_REF_PO

R3

ANTCON

K17

RFAGC

K18

IFAGC

J18

ADC_I_INCOM

U16

ADC_I_INP

U17

ADC_I_INN

V17

GPIO0

F3

GPIO1

F2

GPIO2

F1

GPIO3

G3

GPIO4

G2

GPIO5

G1

GPIO6

H3

GPIO7

H2

GPIO8

H1

GPIO9

J3

GPIO10

E18

GPIO11

E17

GPIO12

H16

GPIO13

J2

GPIO14

J1

GPIO15

K1

IC101

LG1154AN_H13A

H13A_NON_BRAZIL

INTR_GBB

E1

INTR_AFE3CH

E2

INTR_AGPIO

D1

AUD_FS20CLK

A6

AUD_FS21CLK

B6

AUD_FS23CLK

A5

AUD_FS24CLK

B5

AUD_FS25CLK

A4

AUDCLK_OUT_SUB

C4

AUD_HDMI_MCLK

C18

AUD_DAC1_LRCK

A2

AUD_DAC1_SCK

B2

AUD_DAC1_LRCH

B1

AUD_DAC0_LRCK

C2

AUD_DAC0_SCK

C1

AUD_DAC0_LRCH

D2

AUD_ADC_LRCK

B4

AUD_ADC_SCK

A3

AUD_ADC_LRCH

B3

BB_SCL

A7

BB_SDA

B7

BB_TP_CLK

E8

BB_TP_ERR

D8

BB_TP_SOP

C8

BB_TP_VAL

E7

BB_TP_DATA7

D7

BB_TP_DATA6

C7

BB_TP_DATA5

E6

BB_TP_DATA4

D6

BB_TP_DATA3

C6

BB_TP_DATA2

E5

BB_TP_DATA1

D5

BB_TP_DATA0

C5

CLK_F54M

B10

CVBS_GC2

C9

CVBS_GC1

B9

CVBS_GC0

A9

CVBS_UP

D9

CVBS_DN

E9

FS00CLK

B11

AUDCLK_OUT

A11

DAC_START

D11

DAC_DATA4

C11

DAC_DATA3

E10

DAC_DATA2

D10

DAC_DATA1

C10

DAC_DATA0

A10

AAD_GC4

D13

AAD_GC3

C13

AAD_GC2

E12

AAD_GC1

D12

AAD_GC0

C12

AAD_DATA9

C17

AAD_DATA8

E16

AAD_DATA7

D16

AAD_DATA6

C16

AAD_DATA5

E15

AAD_DATA4

D15

AAD_DATA3

C15

AAD_DATA2

E14

AAD_DATA1

D14

AAD_DATA0

C14

AAD_DATAEN

E13

ADCO_OUT_CLK

B18

HSR_AP0

A12

HSR_AM0

B12

HSR_BP0

A13

HSR_BM0

B13

HSR_CP0

A14

HSR_CM0

B14

HSR_CLKP0

A15

HSR_CLKM0

B15

HSR_DP0

A16

HSR_DM0

B16

HSR_EP0

A17

HSR_EM0

B17

IC100

LG1154D_H13D

INTR_GBB

AT16

INTR_AFE3CH

AU17

INTR_AGPIO

AT17

AUD_FS20CLK

AT24

AUD_FS21CLK

AU24

AUD_FS23CLK

AT23

AUD_FS24CLK

AU23

AUD_FS25CLK

AT22

AUD_HDMI_MCLK

AU36

AUD_DAC1_LRCK

AT20

AUD_DAC1_SCK

AU20

AUD_DAC1_LRCH

AT19

AUD_DAC0_LRCK

AU19

AUD_DAC0_SCK

AT18

AUD_DAC0_LRCH

AU18

AUD_ADC_LRCK

AU22

AUD_ADC_SCK

AT21

AUD_ADC_LRCH

AU21

BB_SCL

AT25

BB_SDA

AU25

BB_TPI_CLK

AP23

BB_TPI_ERR

AR23

BB_TPI_SOP

AP22

BB_TPI_VAL

AR22

BB_TPI_DATA7

AP21

BB_TPI_DATA6

AR21

BB_TPI_DATA5

AP20

BB_TPI_DATA4

AR20

BB_TPI_DATA3

AP19

BB_TPI_DATA2

AR19

BB_TPI_DATA1

AP18

BB_TPI_DATA0

AR18

CLK_54M

AU28

CVBS_GC2

AR24

CVBS_GC1

AU27

CVBS_GC0

AT27

CVBS_UP

AP24

CVBS_DN

AR25

FS00CLK

AU29

H13A_AUDCLK_OUT

AT29

DAC_START

AP27

DAC_DATA4

AR27

DAC_DATA3

AP26

DAC_DATA2

AR26

DAC_DATA1

AP25

DAC_DATA0

AT28

AAD_GC4

AR30

AAD_GC3

AP29

AAD_GC2

AR29

AAD_GC1

AP28

AAD_GC0

AR28

AAD_DATA9

AP35

AAD_DATA8

AR35

AAD_DATA7

AP34

AAD_DATA6

AR34

AAD_DATA5

AP33

AAD_DATA4

AR33

AAD_DATA3

AP32

AAD_DATA2

AR32

AAD_DATA1

AP31

AAD_DATA0

AR31

AAD_DATAEN

AP30

ADCO_OUT_CLK

AT36

HSR_AP

AT30

HSR_AM

AU30

HSR_BP

AT31

HSR_BM

AU31

HSR_CP

AT32

HSR_CM

AU32

HSR_CLKP

AT33

HSR_CLKM

AU33

HSR_DP

AT34

HSR_DM

AU34

HSR_EP

AT35

HSR_EM

AU35

AUD_HPDRV_LRCH

AT14

AUD_HPDRV_LRCK

AT15

AUD_HPDRV_SCK

AU15

FRC_LR_O_SYNC_FLAG

AC7

L_VSOUT_LD

AN5

DIM0_SCLK

AR14

DIM0_MOSI

AP14

DIM1_SCLK

AN14

DIM1_MOSI

AP13

PWM0

AF6

PWM1

AF7

PWM2

AD7

PWM_IN

AE6

EPI_EO

AP5

EPI_VST

AN8

EPI_DPM

AP8

EPI_MCLK

AR7

EPI_GCLK

AN7

STPI0_CLK/GPIO47

AK35

STPI0_SOP/GPIO46

AK36

STPI0_VAL/GPIO45

AK37

STPI0_ERR/GPIO44

AJ35

STPI0_DATA/GPIO43

AJ36

STPI1_CLK/GPIO42

AH35

STPI1_SOP/GPIO41

AH37

STPI1_VAL/GPIO40

AH36

STPI1_ERR/GPIO55

AG35

STPI1_DATA/GPIO54

AG36

TP_DVB_CLK

AM36

TP_DVB_SOP

AL36

TP_DVB_VAL

AL35

TP_DVB_ERR

AL37

TP_DVB_DATA0

AM35

TP_DVB_DATA1

AN36

TP_DVB_DATA2

AN37

TP_DVB_DATA3

AN35

TP_DVB_DATA4

AP37

TP_DVB_DATA5

AP36

TP_DVB_DATA6

AR37

TP_DVB_DATA7

AR36

TPI_CLK

A28

TPI_SOP

B29

TPI_VAL

B28

TPI_ERR

C28

TPI_DATA0

B32

TPI_DATA1

C31

TPI_DATA2

B31

TPI_DATA3

A31

TPI_DATA4

C30

TPI_DATA5

A30

TPI_DATA6

B30

TPI_DATA7

C29

TPIO_CLK/GPIO53

D30

TPIO_SOP/GPIO52

D31

TPIO_VAL/GPIO51

F30

TPIO_ERR/GPIO50

E31

TPIO_DATA0/GPIO58

E30

TPIO_DATA1/GPIO59

F29

TPIO_DATA2/GPIO60

E29

TPIO_DATA3/GPIO61

F28

TPIO_DATA4/GPIO62

E28

TPIO_DATA5/GPIO63

D28

TPIO_DATA6/GPIO48

E27

TPIO_DATA7/GPIO49

D27

AUDCLK_OUT

AD5

DACLRCH

AD6

DACSLRCH/GPIO127

Y6

PCMI3SCK/GPIO112

Y7

DACSCK

AC6

DACLRCK

AC5

PCMI3LRCK/GPIO113

AA6

PCMI3LRCH

AB7

DACCLFCH/GPIO126

AB5

IEC958OUT

AU14

DACSUBMCLK

AA32

DACSUBLRCH

AA34

DACSUBSCK

AA33

DACSUBLRCK

AB34

TEST1

AE32

TEST2

AE33

TX0N

AT6

TX0P

AU6

TX1N

AT5

TX1P

AU5

TX2N

AT4

TX2P

AU4

TX3N

AU3

TX3P

AU2

TX4N

AT2

TX4P

AT1

TX5N

AR4

TX5P

AR3

TX6N

AP1

TX6P

AP2

TX7N

AP4

TX7P

AP3

TX8N

AN4

TX8P

AN3

TX9N

AM4

TX9P

AM3

TX10N

AL4

TX10P

AL3

TX11N

AK1

TX11P

AK2

TX12N

AK4

TX12P

AK3

TX13N

AJ4

TX13P

AJ3

TX14N

AH4

TX14P

AH3

TX15N

AG4

TX15P

AG3

TX16N

AF1

TX16P

AF2

TX17N

AF4

TX17P

AF3

TX18N

AE4

TX18P

AE3

TX19N

AD4

TX19P

AD3

TX20N

AC4

TX20P

AC3

TX21N

AB1

TX21P

AB2

TX22N

AB4

TX22P

AB3

TX23N

AA4

TX23P

AA3

TX_LOCKN

AR5

R451 330

MHL_ON_OFF

R443-*1

220

TU_W_BR/TW

R444-*1

220

TU_W_BR/TW

C436-*1

100pF

TU_W_BR/TW

R487-*1

10K

TU_W_BR/TW/CO

MAIN AUDIO/VIDEO

Near Place Scart AMP

Placed as close as possible to SOC

Must be used

Close to IC4300

OP MODE[0:1] : SW[2:1]

00 => Normal Operaiton Mode

/T32 Debug Mode

01 => Internal Test Purpose

10 => Internal Test Purpose

11 => Internal Test Purpose

XTAL SEL[1:0] : SW[4:3]

00 => Xtal Input

01 => CLK 24M from H13D

10 => XTAL Bypass from H13D

OP MODE Setting

& Select XTAL Input

AFE 3CH REF Setting

Place JACK Side

Placed as close as possible to IC4300

MAIN Clock(24Mhz)

Placed as close as possible to IC4300

Clock for H13A

NC

I2S_I/F

DIMMING

Place SOC Side

Close to LG1154A

AUDIO IN

LG1154DLG1154A

FOR EMI

TXDCLKP/TX14P

TXD3N/TX13N

TXD4N/TX12N

TXD1N/TX16N

TXD2P/TX15P

TXD3P/TX13P

TXDCLKN/TX14N

TXD4P/TX12P

TXD2N/TX15N

TXD1P/TX16P

TXD0N/TX17N

TXD0P/TX17P

2012-11-13

BSD-NC4_H004-HD

EPI Output

H13 Ball Name

Placed as close as possible to IC100

To ADC

Tuner IF Filter

Place at JACK SIDE

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M1_DDR_A5

M0_DDR_DQ10

M0_DDR_CASN

M1_DDR_DM1

M1_DDR_WEN

C535

0.1uF

M1_DDR_DQ30

M0_DDR_DQ14

M0_DDR_VREFDQ

M1_DDR_DQ19

M1_DDR_DQS_N1

M1_DDR_DQS0

M1_DDR_A13

M0_DDR_DQ25

M1_DDR_RESET_N

M1_DDR_DQ28

M1_DDR_DQ29

M1_DDR_DQ4

M0_DDR_DQ4

M0_DDR_ODT

M0_DDR_DQ11

M0_DDR_DQ26

C561

0.1uF

M1_DDR_CKE

M1_DDR_A6

M0_DDR_A4

VDDC15_M1

M0_DDR_DQ10

M0_DDR_A3

M1_DDR_DQ18

M1_DDR_RASN

M1_DDR_DQ20

R544

240

1%

M0_DDR_RESET_N

M0_DDR_DQS2

M1_DDR_DQ7

M0_DDR_DQ26

M0_DDR_DQ25

R513

1K 1%

M1_DDR_DQ3

M0_DDR_A6

C501

0.1uF

M0_DDR_DM2

M1_DDR_DQ14

M1_DDR_DQ28

M1_DDR_DQS_N0

M0_DDR_A6

M0_DDR_DQ27

M0_DDR_A11

M1_DDR_DQ5

M1_DDR_DQ10

M1_DDR_DQ6

M1_DDR_A14

M0_DDR_A2

R541

10K

M1_DDR_DQ12

M0_U_CLKN

M0_DDR_VREFCA

M1_DDR_DQ15

M0_DDR_DQ23

M1_DDR_DQ13

M0_DDR_DQ3

VDDC15_M0

M1_DDR_DM3

M1_1_DDR_VREFCA

M1_DDR_A11

M1_DDR_CKE

M1_D_CLKN

M0_DDR_A7

M0_DDR_A12

M0_1_DDR_VREFDQ

M0_DDR_DQS1

R516

1K 1%

C509

0.1uF

M0_DDR_A11

VDDC15_M1

R518

100

R514

1K 1%

M1_DDR_DQS1

M1_DDR_DQS3

M1_DDR_CKE

M0_DDR_CASN

M1_DDR_A7

M0_DDR_DQS3

M0_DDR_BA0

M0_DDR_DQS_N0

R520

10K

M0_DDR_A1

M1_DDR_DQ11

M1_DDR_A1

M1_DDR_BA2

M0_DDR_DQS_N2

C504

0.1uF

M0_DDR_DM1

M1_DDR_A11

M1_DDR_DQ22

M0_D_CLKN

M1_DDR_A0

M0_DDR_DQ30

M1_DDR_A15

M1_1_DDR_VREFDQ

R538

1K 1%

M0_DDR_DQ18

M0_DDR_DQ0

M1_DDR_A8

M1_DDR_DQ25

M0_DDR_BA2

VDDC15_M1

M0_DDR_DQ24

R532

1K 1%

M1_DDR_BA0

M1_DDR_DQ26

M0_DDR_A8

M0_DDR_RASN

M1_DDR_A2

M1_DDR_A6

M0_U_CLK

R533

1K 1%

M0_DDR_VREFDQ

M1_DDR_VREFDQ

VDDC15_M0

M1_DDR_A9

M1_DDR_DQ16

M0_DDR_DQ29

M1_DDR_A12

M1_DDR_A5

VDDC15_M0

M1_DDR_DQ12

M1_U_CLKN

M1_DDR_RASN

M0_DDR_DM0

M0_DDR_DQ15

M0_DDR_DQ6

C566

0.1uF

M0_DDR_A2

M1_DDR_A3

M1_DDR_DQ8

M0_DDR_DQ9

M0_DDR_DQ20

R501

240

1%

M1_D_CLK

M0_DDR_BA0

M1_DDR_DM2

M0_DDR_DQ30

M0_DDR_DQ27

M1_DDR_VREFCA

M0_D_CLK

C530

0.1uF

M0_DDR_DQ22

M0_DDR_A2

M1_DDR_A13

M0_DDR_BA0

C505

0.1uF

M1_DDR_CASN

M0_1_DDR_VREFCA

C512

0.1uF

R545

240

M0_DDR_DQ17

M0_DDR_DQ15

M1_DDR_DQ0

M1_DDR_A1

M0_DDR_ODT

M1_DDR_BA1

M1_DDR_DQ25

M0_DDR_WEN

M1_DDR_DQ29

M1_DDR_VREFDQ

M1_DDR_DQ9

M0_DDR_DM1

M0_DDR_DQ0

M0_DDR_DQ2

M1_DDR_A7

M1_DDR_DQ21

M0_1_DDR_VREFCA

M0_DDR_A4

M1_DDR_DQ13

M0_DDR_CASN

M1_DDR_A11

C529

0.1uF

M1_DDR_DQ16

C567

0.1uF

M0_DDR_DQ5

M0_DDR_DQ14

M1_DDR_DM2

M1_DDR_DM0

M1_DDR_A0

M0_DDR_A0

M0_DDR_DQS_N1

M1_DDR_DQ10

M1_DDR_A5

M1_U_CLK

M0_DDR_DM0

M1_DDR_DQ18

M0_DDR_DQS_N0

M0_DDR_VREFCA

R535

100

M0_DDR_DQ6

M1_DDR_A7

M1_D_CLKN

M0_DDR_DQ21

VDDC15_M1

M0_DDR_A10

M1_DDR_DQ7

C513

0.1uF

M1_U_CLK

M1_DDR_DQ2

VDDC15_M0

M1_DDR_A10

M0_DDR_A8

M1_DDR_DQ14

M1_DDR_RESET_N

M0_DDR_DQ1

M0_DDR_DQ29

M0_DDR_DQS2

M0_DDR_A13

M1_DDR_A15

M0_DDR_DQS1

M1_DDR_DQ17

R537

1K 1%

M1_DDR_DQ1

M0_DDR_RESET_N

M1_DDR_A10

M1_DDR_A8

M1_DDR_BA1

M1_DDR_DQS_N2

M1_U_CLKN

M0_DDR_A5

M1_DDR_DQ23

M0_DDR_DM3

M0_DDR_DQ19

VDDC15_M0

R512

1K 1%

M1_DDR_CASN

M0_DDR_DQ8

M0_U_CLKN

M0_DDR_DQ22

M1_DDR_A13

M1_DDR_BA2

M0_DDR_BA1

M0_DDR_A15

M0_DDR_DM2

M0_DDR_A9

M1_DDR_DQS_N2

M0_DDR_DQ1

M1_DDR_WEN

M0_DDR_A4

M1_DDR_A4

M1_DDR_DQ5

M1_DDR_A9

M0_DDR_CKE

M0_DDR_DQ16

M0_DDR_A9

M1_DDR_DM1

M0_DDR_DQ5

M1_DDR_A1

R539

1K 1%

C508

0.1uF

M1_DDR_DQ24

M0_DDR_DQ18

M0_U_CLKN

VDDC15_M0

M0_1_DDR_VREFDQ

M1_DDR_DQ31

M1_DDR_DQ21

M0_DDR_CKE

M0_DDR_DQ31

M0_DDR_A15

M0_DDR_DQ8

M0_DDR_DQ13

M0_DDR_A15

M0_DDR_DQ19

M1_1_DDR_VREFCA

M0_D_CLK

M0_DDR_DQ7

M1_DDR_A3

M0_DDR_RASN

M1_DDR_A14

M1_DDR_DQS_N1

M1_DDR_ODT

M1_DDR_DQS2

R511

1K 1%

M0_DDR_WEN

M1_DDR_DQ4

M1_DDR_A2

M0_DDR_DQ12

M0_DDR_A14

M1_DDR_A8

M0_DDR_DQ28

M0_DDR_DQS_N3

R521

10K

R536

1K 1%

M1_DDR_DQ11

M1_DDR_DQ6

M0_DDR_A6

M1_DDR_VREFCA

M0_DDR_DQ3

M1_DDR_DQ27

M0_DDR_A5

M0_DDR_DQ4

M1_DDR_BA0

M0_DDR_DQ7

M0_DDR_A14

M1_DDR_DQ15

R510

1K 1%

M1_DDR_DQ26

M1_DDR_A0

M0_D_CLKN

M1_DDR_A4

M0_DDR_A1

VDDC15_M1

M0_DDR_A0

M1_DDR_DQ22

M0_DDR_CKE

M0_DDR_WEN

VDDC15_M1

M1_DDR_A2

M1_DDR_A3

M1_DDR_DQ17

M1_D_CLK

M1_DDR_DM3

M1_DDR_DQS3

M0_DDR_A12

M0_U_CLK

M1_DDR_DQ30

M1_D_CLK

M0_DDR_A10

R515

1K 1%

M1_DDR_CKE

M0_DDR_DQ31

M0_DDR_ODT

M0_DDR_RESET_N

M0_DDR_A0

M1_DDR_DQS_N3

M0_DDR_DQ24

M1_DDR_DQ2

M0_DDR_CKE

M1_DDR_RESET_N

M1_DDR_A15

M1_DDR_ODT

M1_DDR_DQ19

R517

1K 1%

M1_DDR_CASN

M0_DDR_A13

M0_D_CLK

M0_DDR_DQS0

M0_DDR_DQS_N3

M0_DDR_DQS3

R531

1K 1%

M1_DDR_DQ1

M1_DDR_A12

M0_DDR_DQS_N2

M0_DDR_DQ13

M1_DDR_A9

M0_DDR_A13

M1_DDR_DM0

M0_DDR_BA2

M1_DDR_BA1

M1_DDR_DQ9

M0_DDR_A5

C562

0.1uF

M0_DDR_A9

M0_DDR_DQ2

M1_DDR_DQ3

M0_DDR_DQ11

M1_D_CLKN

M0_DDR_DQS0

M1_DDR_DQ0

M1_DDR_BA2

R519

100

C500

0.1uF

M1_DDR_DQ23

M1_DDR_ODT

M1_DDR_DQ27

M1_DDR_DQ8

M0_U_CLK

M1_DDR_DQS1

M0_DDR_A1

M0_DDR_BA1

M1_DDR_A10

M1_DDR_DQ24

M0_DDR_A10

R530

100

M0_DDR_DQ20

M1_DDR_A14

VDDC15_M0

M0_DDR_A3

M1_DDR_BA0

M1_DDR_DQS_N3

M0_DDR_DM3

M1_DDR_A6

M1_DDR_RESET_N

M0_DDR_RASN

M0_DDR_A7

M0_DDR_DQ28

M0_DDR_RESET_N

R540

10K

M0_DDR_DQ23

R500

240

1%

M0_DDR_BA1

M0_DDR_DQ21

M0_DDR_DQ9

M1_DDR_DQS0

M0_DDR_DQS_N1

M1_DDR_DQ20

M0_DDR_DQ16

M1_U_CLK

M1_1_DDR_VREFDQ

M1_DDR_DQ31

M1_DDR_A12

R543

240

M0_DDR_A8

M0_DDR_A7

M0_DDR_DQ12

VDDC15_M1

M1_U_CLKN

M1_DDR_DQS2

M1_DDR_DQS_N0

M1_DDR_WEN

M0_DDR_A12

M0_DDR_A14

M1_DDR_RASN

M0_DDR_DQ17

R534

1K 1%

M0_D_CLKN

M1_DDR_A4

R542

240

1%

M0_DDR_BA2

M0_DDR_A11

M0_DDR_A3

C534

0.1uF

K4B4G1646B-HCK0

IC500

DDR_SAMSUNG

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

K4B4G1646B-HCK0

IC501

DDR_SAMSUNG

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

K4B4G1646B-HCK0

IC503

DDR_SAMSUNG

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

K4B4G1646B-HCK0

IC502

DDR_SAMSUNG

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

H5TQ4G63AFR-PBC

IC500-*1

DDR_HYNIX

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

H5TQ4G63AFR-PBC

IC502-*1

DDR_HYNIX

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

H5TQ4G63AFR-PBC

IC503-*1

DDR_HYNIX

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

H5TQ4G63AFR-PBC

IC501-*1

DDR_HYNIX

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

IC100

LG1154D_H13D

M0_DDR_A[0]

F15

M0_DDR_A[1]

F13

M0_DDR_A[2]

F17

M0_DDR_A[3]

F19

M0_DDR_A[4]

E10

M0_DDR_A[5]

E18

M0_DDR_A[6]

E11

M0_DDR_A[7]

F18

M0_DDR_A[8]

F11

M0_DDR_A[9]

F16

M0_DDR_A[10]

E9

M0_DDR_A[11]

E12

M0_DDR_A[12]

E13

M0_DDR_A[13]

E16

M0_DDR_A[14]

F12

M0_DDR_A[15]

F14

M0_DDR_BA[0]

E19

M0_DDR_BA[1]

F10

M0_DDR_BA[2]

E15

M0_DDR_U_CLK

B10

M0_DDR_U_CLKN

A10

M0_DDR_D_CLK

A19

M0_DDR_D_CLKN

B19

M0_DDR_CKE

E14

M0_DDR_ODT

F21

M0_DDR_RASN

E21

M0_DDR_CASN

E20

M0_DDR_WEN

F20

M0_DDR_RESET_N

E17

M0_DDR_ZQCAL

F9

M0_DDR_DQS[0]

B20

M0_DDR_DQS_N[0]

A20

M0_DDR_DQS[1]

C19

M0_DDR_DQS_N[1]

D19

M0_DDR_DQS[2]

A11

M0_DDR_DQS_N[2]

B11

M0_DDR_DQS[3]

C10

M0_DDR_DQS_N[3]

D10

M0_DDR_DM[0]

D18

M0_DDR_DM[1]

C20

M0_DDR_DM[2]

D9

M0_DDR_DM[3]

C11

M0_DDR_DQ[0]

D22

M0_DDR_DQ[1]

C15

M0_DDR_DQ[2]

C23

M0_DDR_DQ[3]

D16

M0_DDR_DQ[4]

B24

M0_DDR_DQ[5]

B15

M0_DDR_DQ[6]

D23

M0_DDR_DQ[7]

A15

M0_DDR_DQ[8]

C16

M0_DDR_DQ[9]

D21

M0_DDR_DQ[10]

D17

M0_DDR_DQ[11]

C22

M0_DDR_DQ[12]

C18

M0_DDR_DQ[13]

C21

M0_DDR_DQ[14]

C17

M0_DDR_DQ[15]

D20

M0_DDR_DQ[16]

C13

M0_DDR_DQ[17]

D7

M0_DDR_DQ[18]

D13

M0_DDR_DQ[19]

C6

M0_DDR_DQ[20]

D14

M0_DDR_DQ[21]

D6

M0_DDR_DQ[22]

C14

M0_DDR_DQ[23]

A5

M0_DDR_DQ[24]

C7

M0_DDR_DQ[25]

D12

M0_DDR_DQ[26]

D8

M0_DDR_DQ[27]

B13

M0_DDR_DQ[28]

C9

M0_DDR_DQ[29]

C12

M0_DDR_DQ[30]

C8

M0_DDR_DQ[31]

D11

IC100

LG1154D_H13D

M1_DDR_A[0]

N6

M1_DDR_A[1]

R6

M1_DDR_A[2]

L6

M1_DDR_A[3]

J6

M1_DDR_A[4]

U5

M1_DDR_A[5]

J5

M1_DDR_A[6]

T5

M1_DDR_A[7]

K6

M1_DDR_A[8]

U6

M1_DDR_A[9]

M6

M1_DDR_A[10]

V5

M1_DDR_A[11]

R5

M1_DDR_A[12]

P5

M1_DDR_A[13]

L5

M1_DDR_A[14]

T6

M1_DDR_A[15]

P6

M1_DDR_BA[0]

H5

M1_DDR_BA[1]

V6

M1_DDR_BA[2]

M5

M1_DDR_U_CLK

R2

M1_DDR_U_CLKN

R1

M1_DDR_D_CLK

F1

M1_DDR_D_CLKN

F2

M1_DDR_CKE

N5

M1_DDR_ODT

G6

M1_DDR_RASN

F5

M1_DDR_CASN

G5

M1_DDR_WEN

H6

M1_DDR_RESET_N

K5

M1_DDR_ZQCAL

F6

M1_DDR_DQS[0]

E2

M1_DDR_DQS_N[0]

E1

M1_DDR_DQS[1]

F3

M1_DDR_DQS_N[1]

F4

M1_DDR_DQS[2]

P1

M1_DDR_DQS_N[2]

P2

M1_DDR_DQS[3]

R3

M1_DDR_DQS_N[3]

R4

M1_DDR_DM[0]

G4

M1_DDR_DM[1]

E3

M1_DDR_DM[2]

T4

M1_DDR_DM[3]

P3

M1_DDR_DQ[0]

C4

M1_DDR_DQ[1]

K3

M1_DDR_DQ[2]

B3

M1_DDR_DQ[3]

J4

M1_DDR_DQ[4]

A3

M1_DDR_DQ[5]

K2

M1_DDR_DQ[6]

B4

M1_DDR_DQ[7]

K1

M1_DDR_DQ[8]

J3

M1_DDR_DQ[9]

D4

M1_DDR_DQ[10]

H4

M1_DDR_DQ[11]

C3

M1_DDR_DQ[12]

G3

M1_DDR_DQ[13]

D3

M1_DDR_DQ[14]

H3

M1_DDR_DQ[15]

E4

M1_DDR_DQ[16]

M3

M1_DDR_DQ[17]

V4

M1_DDR_DQ[18]

M4

M1_DDR_DQ[19]

W3

M1_DDR_DQ[20]

L4

M1_DDR_DQ[21]

W4

M1_DDR_DQ[22]

L3

M1_DDR_DQ[23]

Y2

M1_DDR_DQ[24]

V3

M1_DDR_DQ[25]

N4

M1_DDR_DQ[26]

U4

M1_DDR_DQ[27]

M2

M1_DDR_DQ[28]

T3

M1_DDR_DQ[29]

N3

M1_DDR_DQ[30]

U3

M1_DDR_DQ[31]

P4

MAIN DDR

H5TQ1G63DFR-PBC(x16)

DDR3

4Gbit

(x16)

DDR3

4Gbit

(x16)

4Gbit : T7(A14)

DDR3 1.5V bypass Cap - Place these caps near Memory

1Gbit : T7(NC_6)

Real USE : 1Gbit

DDR3 1.5V bypass Cap - Place these caps near Memory

DDR3

4Gbit

(x16)

DDR3

4Gbit

(x16)

2012-09-14

BSD-NC4_H005-HD

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

CI_DATA[7]

CI_DATA[1]

CI_DATA[5]

CI_DATA[3]

CI_DATA[2]

CI_DATA[6]

CI_DATA[0]

EB_DATA[0-7]

CI_DATA[4]

TPO_DATA[3]

TPO_DATA[4]

TPO_DATA[0]

TPO_DATA[7]

TPO_DATA[1]

TPO_DATA[5]

TPO_DATA[6]

TPO_DATA[2]

CI_ADDR[9]

CI_DATA[1]

CI_IN_TS_DATA[6]

CI_ADDR[1]

CI_DATA[6]

CI_IN_TS_DATA[3]

CI_ADDR[5]

CI_ADDR[13]

CI_IN_TS_DATA[2]

CI_ADDR[8]

CI_ADDR[2]

CI_ADDR[3]

CI_ADDR[4]

CI_DATA[0]

CI_DATA[7]

CI_DATA[4]

CI_ADDR[12]

CI_ADDR[11]

CI_IN_TS_DATA[0]

CI_DATA[5]

CI_ADDR[14]

CI_DATA[3]

CI_DATA[2]

CI_ADDR[10]

CI_ADDR[0]

CI_IN_TS_DATA[1]

CI_ADDR[7]

CI_IN_TS_DATA[7]

CI_ADDR[6]

CI_IN_TS_DATA[4]

CI_IN_TS_DATA[5]

EB_DATA[0]

EB_DATA[1]

EB_DATA[2]

EB_DATA[3]

EB_DATA[4]

EB_DATA[5]

EB_DATA[6]

EB_DATA[7]

CI_DATA[0-7]

CI_ADDR[13]

CI_ADDR[8]

CI_ADDR[7]

EB_ADDR[12]

/PCM_IOWR

EB_ADDR[0]

CI_ADDR[1]

EB_BE_N1

EB_ADDR[1]

CI_ADDR[11]

EB_ADDR[13]

CI_ADDR[9]

AR708

33

CI

AR709

33

CI

CI_ADDR[5]

CI_ADDR[2]

EB_OE_N

/PCM_OE

EB_ADDR[2]

EB_ADDR[10]

AR711

33

CI

AR712

33

CI

EB_DATA[0-7]

CI_DATA[0-7]

EB_ADDR[6]

CI_ADDR[4]

/PCM_WE

EB_ADDR[5]

EB_ADDR[4]

EB_ADDR[8]

AR707

33

CI

EB_ADDR[11]

EB_WE_N

EB_ADDR[3]

/PCM_IORD

CI_ADDR[0]

CI_ADDR[6]

CI_ADDR[14]

EB_ADDR[14]

EB_BE_N0

EB_ADDR[7]

CI_ADDR[12]

CI_ADDR[3]

CAM_REG_N

EB_ADDR[9]

CI_ADDR[10]

AR710

33

CI

AR713

33

CI

/PCM_REG

TPO_CLK

TPO_VAL

TPO_DATA[0-7]

TPO_SOP

/PCM_WE

/PCM_OE

PCM_INPACK

+5V_CI_ON

CI_TS_CLK

CI_ADDR[0]

CI_ADDR[10]

/PCM_IORD

/PCM_CE1

CI_ADDR[8]

CI_ADDR[14]

R706

10K

OPT

/PCM_REG

CI_TS_DATA[1]

R715

0

OPT

R713

0

OPT

/PCM_IOWR

CI_ADDR[4]

R704

10K

OPT

CI_TS_DATA[0]

/PCM_IRQA

/CI_CD1

CI_IN_TS_VAL

CI_TS_VAL

CI_ADDR[1]

CI_ADDR[11]

PCM_INPACK

CI_VS1

CI_TS_DATA[3]

+5V_CI_ON

CI_TS_DATA[5]

R710

0

OPT

CI_ADDR[9]

R709

10K

CI

R718

0

OPT

CI_TS_DATA[7]

+5V_CI_ON

/CI_CD2

R711

10K

OPT

C706 0.1uF

CI

CI_DATA[0-7]

R707

10K

OPT

CI_TS_DATA[6]

R708

10K

OPT

CI_TS_DATA[4]

CI_TS_SYNC

C702

0.1uF

CI

R712

10K

OPT

CI_TS_DATA[2]

CI_VS1

+5V_CI_ON

R719

10K

OPT

CI_IN_TS_DATA[0-7]

CI_ADDR[7]

R720

10K

OPT

+5V_CI_ON

CI_ADDR[3]

/PCM_CE2

R724

10K

OPT

CI_ADDR[13]

+5V_CI_ON

R714 0

CI

R716

100

CI

R725

10K

OPT

R723

10K

CI

CI_ADDR[5]

/PCM_WAIT

CI_ADDR[2]

CI_ADDR[6]

R717 100

CI

/PCM_CE2

CI_IN_TS_SYNC

PCM_RESET

C707

0.1uF

16V

CI

CI_IN_TS_CLK

CI_ADDR[12]

AR706

33

CI

AR705

33

CI

AR701

33

CI

CI_IN_TS_DATA[7]

CI_IN_TS_DATA[6]

CI_IN_TS_DATA[0]

CI_IN_TS_DATA[1]

CI_IN_TS_DATA[5]

CI_IN_TS_DATA[2]

CI_IN_TS_DATA[4]

CI_IN_TS_DATA[3]

CI_IN_TS_SYNC

CI_IN_TS_VAL

CI_IN_TS_CLK

TPI_DATA[7]

AR700

100

CI

CAM_CD1_N

CAM_INPACK_N

C700

0.1uF

16V

CI

CI_TS_DATA[7]

AR703

100

CI

PCM_INPACK

CI_TS_DATA[2]

CI_TS_SYNC

TPI_VAL

CAM_IREQ_N

TPI_DATA[4]

TPI_DATA[5]

TPI_DATA[2]

CAM_WAIT_N

/PCM_WAIT

TPI_DATA[0]

TPI_SOP

/CI_CD1

TPI_DATA[3]

CI_TS_DATA[1]

/CI_CD2

CI_TS_CLK

CI_TS_DATA[5]

R703

10K

/PCM_IRQA

CI_TS_VAL

CI_TS_DATA[4]

CI_TS_DATA[0]

CAM_CD2_N

TPI_DATA[6]

TPI_CLK

R705

10K

TPI_DATA[1]

C701

0.1uF

16V

CI

+5V_NORMAL

CI_TS_DATA[6]

AR704

100

CI

CI_TS_DATA[3]

AR702

100

R701

33

CI

R702

33

CI

R700

33

OPT

R721 33

CI

R722 33

OPT

C705

12pF

50V

OPT

C704

12pF

50V

OPT

JK700

10120698-015LF

CI

G1G2

57

21

52

16

10

47

41

5

36

59

23

45

54

18

49

43

13

7

38

2

25

56

20

51

15

9

46

40

4

35

58

22

53

17

11

48

42

12

6

37

1

24

55

19

50

44

14

8

39

3

2660

2761

2862

2963

3064

31

32

33

34

65

66

67

68

69

C703

4.7uF

10V

CI

BSD-NC4_H007-HD

2012-10-20

PCMCIA

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only

THERMAL

THERMAL

THERMAL

THERMAL

THERMAL

THERMAL

THERMAL

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

L2311

BLM18PG121SN1D

NON_OLED

IC2302

AP7173-SPG-13 HF(DIODES)

3

VCC

2

PG

4

EN

1

IN

5

GND

6

SS

7

FB

8

OUT

9

[EP]

L2308

1uH

+24V

POWER_ON/OFF2_2

C2338

0.1uF

50V

C2316

0.1uF

50V

L2300

BLM18PG121SN1D

R2305

15K

1/16W

1%

C2343

22uF

10V

OPT

C2329

150pF

50V

C2307

0.1uF

16V

C2361

22uF

10V

+5V_NORMAL

C2347

0.1uF

50V

R2335

330K1/16W 5%

C2354

0.1uF

16V

C2348

0.1uF

16V

R2331

10K

C2336

10uF

10V

R2300

10K

R2306

33K

1%

C2301

10uF

16V

C2318

0.1uF

16V

R2310

1K

R2340

56K

1/16W

1%

R2301

10K

C2312

3300pF

50V

+24V

R2343

16K

1%

R2304

10K

C2355

0.1uF

16V

Q2301

MMBT3904(NXP)

E

B

C

C2310

1uF

10V

C2303

10uF

16V

R2315 0

1/16W

5%

IC2300

TPS54327DDAR

DCDC_TI

3

VREG5

2

VFB

4

SS

1

EN

5

GND

6

SW

7

VBST

8

VIN

9

[EP]GND

R2312

10K

R2309

100

C2308

100pF

50V

DCDC_TI

+3.5V_ST

C2350

10uF

10V

+3.3V_NORMAL

Q2302

AO3407A

G

D

S

R2328

1.5K

1%

PD_24V

C2319

22uF

10V

R2336

100K

PD_20_24V

C2356

0.1uF

16V

PD_20_24V

C2315

4700pF 50V

C2333

10uF

16V

R2322

4.3K

1%

IC2307

NCP803SN293

1

GND

3

VCC

2

RESET

R2337

100K

+12V

POWER_ON/OFF2_1

C2324

0.01uF

50V

10uF

C2327

10V

+12V

+12V

R2330

0

5%

PD_+3.5V

POWER_DET

R2328-*1

1.3K

1%

PD_20V

P2300

SMAW200-H18S1

POWER_WAFER_18PIN

14

12V

9

24V

4

PDIM#1

18

GND

13

12V

8

GND

3

3.5V

17

GND

12

GND

7

GND

2

INV ON

16

24V

11

GND

6

PDIM#2

1

PWR ON

15

12V

10

24V

5

3.5V

19

+1.1V_VDD

L2307

2.2uH

NR5040T2R2N

C2322

22uF

10V

+2.5V_Normal

POWER_ON/OFF1

R2318

5.6K

C2364

100pF

50V

DCDC_TI

C2334

22uF

10V

IC2308

NCP803SN293

PD_20_24V

1

GND

3

VCC

2

RESET

+12V

R2339

47K 1%

C2311

0.1uF

50V

+1.5V_DDR

R2327

8.2K

1%

PD_24V

INV_CTL

L2312

4.7uH

2200pF

C2337

50V

L2318

L2301

IC2303

TPS54821RHL

3

GND_2

2

GND_1

4

PVIN_1

1

RT/CLK

6

VIN

5

PVIN_2

7

VSENSE

8

COMP

9

SS/TR

10

EN

11

PH_1

12

PH_2

13

BOOT

14

PWRGD

15

[EP]GND

C2359

0.01uF

50V

POWER_ON/OFF2_3

R2325

2.7K

1%

PD_+12V

C2323

22uF

10V

L2314

OLED

C2360

4700pF

50V

C2365

0.1uF

16V

+5V_NORMAL

+3.3V_NORMAL

C2317

22uF

10V

C2335

0.1uF

16V

R2338

10K

OPT

C2362

22uF

10V

C2302

180pF

50V

IC2305

TPS54319TRE

DCDC_TI

1

VIN_1

3

GND_1

7

COMP

9

SS/TR

10

PH_1

11

PH_2

12

PH_3

13

BOOT

14

PWRGD

15

EN

16

VIN_3

5

AGND

8

RT/CLK

6

VSENSE

4

GND_2

2

VIN_2

17

EP[GND]

+3.5V_ST

+3.5V_ST

R2314

10K

+24V

PANEL_CTL

R2313

1.3K

+12V

L2320

3.3uH

NR5040T3R3N

D2300

40V

B540C

PANEL_VCC

PWM_DIM2

+1.0V_VDD

R2327-*1

5.6K

1%

PD_20V

RL_ON

C2306

0.1uF

50V

R2326

1.2K

1%

PD_+12V

C2330

22uF

10V

POWER_ON/OFF2_2

C2320

47pF 50V

C2331

0.1uF

50V

C2346

10uF

10V

+3.5V_ST

R2302

11K

1%

PWM_DIM

Q2300 MMBT3906(NXP)

1

2

3

R2344

51K

1%

C2313

4.7uF

16V

+1.1V_VDD

C2358

0.1uF

16V

+3.5V_ST

R2321

2K

1%

R2345

10K

R2317

33K

C2321

22000pF 50V

C2314

0.1uF

16V

R2334

15K

1/16W 5%

+12V

R2316 1K

C2305

0.1uF

16V

+3.3V_NORMAL

L2302

BLM18PG121SN1D

3.3V_EMMC

C2300

22uF

10V

C2309

10uF

35V

IC2304

RT8289GSP

3

NC_2

2

NC_1

4

FB

1

BOOT

5

EN

6

GND

7

VIN

8

SW

9

[EP]GND

C2339

22uF

10V

L2305

BLM18PG121SN1D

R2308

51K

1% C2332

0.1uF

16V

+3.3V_NORMAL

R2311

10K

C2325

100pF

50V

OPT

IC2301

TPS54327DDAR

3

VREG5

2

VFB

4

SS

1

EN

5

GND

6

SW

7

VBST

8

VIN

9

[EP]GND

R2319

15K

1%

C2304

10uF

16V

C2326

1uF

10V

+12V

C2328

3300pF

50V

C2340

22uF

10V

POWER_ON/OFF1

P2301

SMAW200-H24S2

POWER_WAFER_24PIN

19

14

9

4

18

13

8

3

17

12

7

2

16

11

6

1

20

15

10

5

21 22

23 24

25

L/DIM0_VS

L/DIM0_SCLK

L/DIM0_MOSI

L2309

3.6uH

SM-8040

IC2300-*1

RT7266ZSP

DCDC_RT

3

PVCC

2

FB

4

SS

1

EN

5

GND

6

SW

7

BOOT

8

VIN

9

[EP]GND

IC2305-*1

RT8079AGQW

DCDC_RT

3

GND_1

2

VIN_2

4

GND_2

1

VIN_1

5

AGND

6

FB

7

COMP

8

RT/SYNC

9

SS/TR

10

SW_1

11

SW_2

12

SW_3

13

BOOT

14

PGOOD

15

EN

16

VIN_3

17

[EP]GND

ZD2303

5V

OPT

ZD2302

5V

OPT

ZD2301

5V

OPT

ZD2300

5V

OPT

C2341

22uF

10V

L2303

UBW2012-121F

L2304

UBW2012-121F

L2306

UBW2012-121F

L2313

UBW2012-121F

R2303

16K

1/16W

1%

L2310

4.7uH

R2347

5.6K

LVDS_DISCHARGE

R2346

5.6K

LVDS_DISCHARGE

R2307

120K

1/16W

1%

POWER

LG1154

24V-->3.48V

5A

12V-->3.58V

R1

not to RESET at 8kV ESD

R1

8A

Vout=0.765*(1+R1/R2)

+1.1V_CORE

+1.0V_VDD

Vout=0.6*(1+R1/R2)

1.5A

LG1154AN : 3.3V->2.5V->1.0V

LG1154D : 3.3V->2.5V->1.5V->1.1V

Switching freq: 700K

R2

DDR MAIN 1.5V

eMMC POWER

5V/3.3V->2.5V->1.5V/1.1V->1.0V

Vout=0.827*(1+R1/R2)=1.521V

3A

POWER UP SEQUENCE

LG1154A

Vout=0.8*(1+R1/R2)

R2

3A

+2.5V

PANEL_POWER

R1

R1

Vout=1.222*(1+R1/R2)

3A

R2

+5.0V normal & USB

LG1154D

Vout(1.24V)=0.6*(1+16k/15k)

R2

20V-->3.51V

Power_DET

$ 0.145

R2

R1

ST_3.5V-->3.5V

2012-12-07

BSD-NC4_H023-HD

Vout=0.765*(1+R1/R2)

Switching freq: 700K

R1

3A

+3.3V_NORMAL

R2

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

WOL/WIFI_POWER_ON

POWER_ON/OFF1

R3005 10K

MICOM_LCD/OLED

R3004 10K

MICOM_GP3_12/15PIN

I2C_SDA_MICOM

MODEL1_OPT_5

RUE003N02

Q3001

HDMI_CEC_FET_ROHM

S

D

G

+3.5V_ST

R3030

10K

R3014 10K

MICOM_DEBUG

+3.5V_ST

WOL_CTL

C3003 8pF

P3000

12507WS-04L

MICOM_DEBUG

1

2

3

4

5

SCART_MUTE

CAM_CTL

KEY1

MODEL1_OPT_5

CEC_REMOTE

R3012 10K

MICOM_NON_LOGO_LIGHT

POWER_ON/OFF2_4

C3001 0.47uF

SOC_TX

MODEL1_OPT_3

R3013 10K

MICOM_LOGO_LIGHT

R3008 10K

MICOM_TACT_KEY

EDID_WP

CAM_PWR_ON_CMD

LOGO_LIGHT

MODEL1_OPT_1

RL_ON

MODEL1_OPT_2

R3007-*2

22K

MICOM_OLED_FRC

SOC_RX

POWER_DET

R3007-*1

56K

MICOM_OLED_MAIN

R3001 10K

MICOM_M13

MHL_DET

MICOM_RESET

CAM_CTL

MODEL1_OPT_4

R3031

270K

OPT

R3010 10K

MICOM_TOUCH_KEY

R3021

10K

EDID_WP

LED_R

MODEL1_OPT_2

C3004

0.1uF

16V

R3028

4.7M

OPT

POWER_ON/OFF2_4

LED_R

R3007 10K

MICOM_PDP

POWER_ON/OFF2_1

LOGO_LIGHT

MICOM_DEBUG

I2C_SCL_MICOM

R3032

10K

R3033

27K

HDMI_CEC

MODEL1_OPT_1

X3000

32.768KHz

C3002

8pF

+3.5V_ST

PANEL_CTL

MODEL1_OPT_3

MHL_DET

C3000

0.1uF

POWER_ON/OFF2_2

AMP_MUTE

R3034

120K

KEY2

CAM_PWR_ON_CMD

IR

SCART_MUTE

D3000

BAT54_SUZHO

POWER_ON/OFF2_3

SI1012CR-T1-GE3

Q3001-*1

HDMI_CEC_FET_VISHAY

S

D

G

SW3000

JTP-1127WEM

MICOM_RESET_SW

12

4 3

R3002 10K

MICOM_GED

MODEL1_OPT_0

MICOM_DEBUG

MODEL1_OPT_4

R3029 22

MICOM_RESET_22OHM

INV_CTL

+3.5V_ST

SOC_RESET

MODEL1_OPT_0

MICOM_RESET

R3016 1K

+3.5V_ST

GND

SIDE_HP_MUTE

R3003 10K

MICOM_H13

HDMI_CEC

R3000 10K

MICOM_NON_GED

R3006 10K

MICOM_NC4_8PIN

R3029-*1 33

MICOM_RESET_33OHM

ST_BY_DET_CAM

ST_BY_DET_CAM

+3.5V_ST

WOL/ETH_POWER_ON

IC3000

R5F100GEAFB

MICOM_LEAD_Au

1

P60/SCLA0

2

P61/SDAA0

3

P62

4

P63

5

P31/TI03/TO03/INTP4

6

P75/KR5/INTP9/SCK01/SCL01

7

P74/KR4/INTP8/SI01/SDA01

8

P73/KR3/SO01

9

P72/KR2/SO21

10

P71/KR1/SI21/SDA21

11

P70/KR0/SCK21/SCL21

12

P30/INTP3/RTC1HZ/SCK11/SCL11

13

P50/INTP1/SI11/SDA11

14

P51/INTP2/SO11

15

P17/TI02/TO02

16

P16/TI01/TO01/INTP5

17

P15/PCLBUZ1/SCK20/SCL20

18

P14/RXD2/SI20/SDA20

19

P13/TXD2/SO20

20

P12/SO00/TXD0/TOOLTXD

21

P11/SI00/RXD0/TOOLRXD/SDA00

22

P10/SCK00/SCL00

23

P146

24

P147/ANI18

25

P27/ANI7

26

P26/ANI6

27

P25/ANI5

28

P24/ANI4

29

P23/ANI3

30

P22/ANI2

31

P21/ANI1/AVREFM

32

P20/ANI0/AVREFP

33

P130

34

P01/TO00/RXD1

35

P00/TI00/TXD1

36

P140/PCLBUZ0/INTP6

37

P120/ANI19

38

P41/TI07/TO07

39

P40/TOOL0

40

RESET

41

P124/XT2/EXCLKS

42

P123/XT1

43

P137/INTP0

44

P122/X2/EXCLK

45

P121/X1

46

REGC

47

VSS

48

VDD

IC3000-*1

R5F100GEAFB#30

MICOM_LEAD_Cu

1

P60/SCLA0

2

P61/SDAA0

3

P62

4

P63

5

P31/TI03/TO03/INTP4

6

P75/KR5/INTP9/SCK01/SCL01

7

P74/KR4/INTP8/SI01/SDA01

8

P73/KR3/SO01

9

P72/KR2/SO21

10

P71/KR1/SI21/SDA21

11

P70/KR0/SCK21/SCL21

12

P30/INTP3/RTC1HZ/SCK11/SCL11

13

P50/INTP1/SI11/SDA11

14

P51/INTP2/SO11

15

P17/TI02/TO02

16

P16/TI01/TO01/INTP5

17

P15/PCLBUZ1/SCK20/SCL20

18

P14/RXD2/SI20/SDA20

19

P13/TXD2/SO20

20

P12/SO00/TXD0/TOOLTXD

21

P11/SI00/RXD0/TOOLRXD/SDA00

22

P10/SCK00/SCL00

23

P146

24

P147/ANI18

25

P27/ANI7

26

P26/ANI6

27

P25/ANI5

28

P24/ANI4

29

P23/ANI3

30

P22/ANI2

31

P21/ANI1/AVREFM

32

P20/ANI0/AVREFP

33

P130

34

P01/TO00/RXD1

35

P00/TI00/TXD1

36

P140/PCLBUZ0/INTP6

37

P120/ANI19

38

P41/TI07/TO07

39

P40/TOOL0

40

RESET

41

P124/XT2/EXCLKS

42

P123/XT1

43

P137/INTP0

44

P122/X2/EXCLK

45

P121/X1

46

REGC

47

VSS

48

VDD

EYE_SCL

EYE_SDA

R3035

3.3K

EYE_Q_10P

R3036

3.3K

EYE_Q_10P

+3.5V_ST

MICOM

30

2012.02.22

For CEC

HDMI_WAUP:HDMI_INIT

NON_GED

For Debug

Commercial

POWER_ON/OFF2_4

LCD

MICOM MODEL OPTION

/ OLED

Ready for sample set

PDP

0

H13

TACT_KEY

IR_wafer(12/15)

GP4 High/MID Power SEQUENCE

Ready for sample set

1

POWER_ON/OFF2_3

MODEL_OPT_3

M13MODEL_OPT_4

Renesas MICOM

POWER_ON/OFF!

MODEL_OPT_2

MODEL_OPT_0

For LOGO LIGHT

Need to Assign ADC port

MODEL_OPT_5

LOGO

SOC_RESET

POWER_ON/OFF2_2

GED

IR_wafer(10pin)

MODEL_OPT_1

Don’t remove R3014,

not making float P40

MICOM MODEL OPTION

Ready For

NON LOGO

POWER_ON/OFF2_1





TOUCH_KEY

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only

THERMAL

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

DDC_SDA_4

R3246

10K

CK+_HDMI1

C3214

1uF

D3202

A2

C

A1

HDMI_CLK+

DDC_SDA_2

D2+_HDMI1

+5V_NORMAL

R3240

10

D3207

5.6V

DDC_SCL_4

C3209

0.1uF

16V

HDMI_S/W_RESET

D0+_HDMI4

VA3207

ESD_HDMI

D0-_HDMI2

L3202

JK3202

51U019S-312HFN-E-R-B-LG

EAG62611204

HDMI_FREEPORT

14

ARC

13

CE_REMOTE

5

D1_GND

20

BODY_SHIELD

12

CK-

11

CK_GND

2

D2_GND

19

HP_DET

18

5V

10

CK+

4

D1+

1

D2+

17

GND

9

D0-

8

D0_GND

3

D2-

16

DDC_DATA

7

D0+

6

D1-

15

DDC_CLK

VA3216

ESD_HDMI

L3203

CK-_HDMI2

D1-_HDMI4

IC3201-*1

SII9587CNUC-3

UD

1

R1XCN

2

R1XCP

3

R1X0N

4

R1X0P

5

R1X1N

6

R1X1P

7

R1X2N

8

R1X2P

9

AVDD12_1

10

VDD12_1

11

R3XCN

12

R3XCP

13

R3X0N

14

R3X0P

15

R3X1N

16

R3X1P

17

R3X2N

18

R3X2P

19

AVDD12_2

20

VDD33_1

21

R4XCN

22

R4XCP

23

R4X0N

24

R4X0P

25

R4X1N

26

R4X1P

27

R4X2N

28

R4X2P

29

VDD12_2

30

DSDA0

31

DSCL0

32

CBUS_HPD0

33

R0PWR5V

34

DSDA1

35

DSCL1

36

CBUS_HPD1

37

R1PWR5V

38

DSDA3

39

DSCL3

40

CBUS_HPD3

41

R3PWR5V

42

DSDA4

43

DSCL4

44

CBUS_HPD4

45

R4PWR5V

46

DSDA5[VGA]

47

DSCL5[VGA]

48

R5PWR5V[VGA]

49

SBVCC5

50

PWRMUX_OUT

51

LPSBV

52

WKUP

53

CD_SENSE0

54

CD_SENSE1

55

GPIO2

56

CD_SENSE3

57

CD-SENSE4

58

GPIO0

59

GPIO1

60

TPWR

61

RESET_N

62

CSDA

63

CSCL

64

INT

65

SPDIF_IN

66

RSVDL

67

VDD12_3

68

ARC

69

TX2P

70

TX2N

71

TX1P

72

TX1N

73

TX0P

74

TX0N

75

TXCP

76

TXCN

77

TCVDD12

78

TPVDD12

79

R0XCN

80

R0XCP

81

R0X0N

82

R0X0P

83

R0X1N

84

R0X1P

85

R0X2N

86

R0X2P

87

AVDD12_3

88

VDD33_2

89

[EP]GND

5V_HDMI_2

DDC_SDA_1

DDC_SDA_2

D3204

A2

C

A1

R3219

47K

D0-_HDMI4

DDC_SDA_3

DDC_SCL_4

C3222

10uF

10V

C3213

1uF

+5V_NORMAL

R3237 33

C3220

1uF

R3228

47K

DDC_SDA_4

CEC_REMOTE

R3234

5.1K

5%

1/16W

MHL_DET

DDC_SCL_1

HDMI_RX0+

CK-_HDMI2

+5V_NORMAL

HDMI_INT

DDC_SDA_3

DDC_SCL_2

D2-_HDMI1

5V_HDMI_4

C3225

0.1uF

16V

R3231

10

C3206

0.1uF

16V

VA3201

ESD_HDMI

CK+_HDMI4

JK3200

51U019S-312HFN-E-R-B-LG

EAG62611204

HDMI_FREEPORT

14

NC

13

CE_REMOTE

5

D1_GND

20

BODY_SHIELD

12

CK-

11

CK_GND

2

D2_GND

19

HP_DET

18

5V

10

CK+

4

D1+

1

D2+

17

GND

9

D0-

8

D0_GND

3

D2-

16

DDC_DATA

7

D0+

6

D1-

15

DDC_CLK

R3241

5.1K

5%

1/16W

HDMI_RX2+

CK-_HDMI3

C3208

0.1uF

CK+_HDMI1

HDMI_HPD_1

HDMI_HPD_4

DDC_SCL_1

R3236 33

D0+_HDMI2

D2+_HDMI4

D2-_HDMI4

R3216

10

5V_HDMI_1

R3247

10K Q3201

MMBT3906(NXP)

E

B

C

DDC_SCL_1

+3.5V_ST

C3218

10uF

10V

D0-_HDMI1

SPDIF_OUT_ARC

VA3206

ESD_HDMI

CK+_HDMI4

D1+_HDMI4

D2+_HDMI2

5V_HDMI_1

CK-_HDMI1

+5V_NORMAL

HDMI_RX0-

DDC_SCL_4

C3223

0.047uF

25V

5V_HDMI_2

CEC_REMOTE

D2-_HDMI4

R3217

47K

R3212

1

1/16W

5%

C3207

0.1uF

16V

+5V_NORMAL

5V_HDMI_4

C3202

1uF

10V

CK-_HDMI4

DDC_SCL_3

HDMI_HPD_1

5V_HDMI_4

VA3215

ESD_HDMI

HDMI_HPD_2

5V_HDMI_3

Q3202

AO3438

G

D

S

D1+_HDMI4

VA3211

ESD_HDMI

D0-_HDMI3

VA3210

ESD_HDMI

DDC_SDA_4

MHL_DET

+5V_NORMAL

C3224

0.1uF

16V

D0+_HDMI1

D2+_HDMI3

HDMI_HPD_2

+3.3V_NORMAL

DDC_SDA_2

+5V_NORMAL

CEC_REMOTE

R3206

220K

1/16W

5%

CK+_HDMI3

D1-_HDMI3

D0-_HDMI3

CK+_HDMI2

I2C_SDA5

D0-_HDMI1

IC3201

SII9587CNUC

FHD

1

R1XCN

2

R1XCP

3

R1X0N

4

R1X0P

5

R1X1N

6

R1X1P

7

R1X2N

8

R1X2P

9

AVDD12_1

10

VDD12_1

11

R3XCN

12

R3XCP

13

R3X0N

14

R3X0P

15

R3X1N

16

R3X1P

17

R3X2N

18

R3X2P

19

AVDD12_2

20

VDD33_1

21

R4XCN

22

R4XCP

23

R4X0N

24

R4X0P

25

R4X1N

26

R4X1P

27

R4X2N

28

R4X2P

29

VDD12_2

30

DSDA0

31

DSCL0

32

CBUS_HPD0

33

R0PWR5V

34

DSDA1

35

DSCL1

36

CBUS_HPD1

37

R1PWR5V

38

DSDA3

39

DSCL3

40

CBUS_HPD3

41

R3PWR5V

42

DSDA4

43

DSCL4

44

CBUS_HPD4

45

R4PWR5V

46

DSDA5[VGA]

47

DSCL5[VGA]

48

R5PWR5V[VGA]

49

SBVCC5

50

PWRMUX_OUT

51

LPSBV

52

WKUP

53

CD_SENSE0

54

CD_SENSE1

55

GPIO2

56

CD_SENSE3

57

CD-SENSE4

58

GPIO0

59

GPIO1

60

TPWR

61

RESET_N

62

CSDA

63

CSCL

64

INT

65

SPDIF_IN

66

RSVDL

67

VDD12_3

68

ARC

69

TX2P

70

TX2N

71

TX1P

72

TX1N

73

TX0P

74

TX0N

75

TXCP

76

TXCN

77

TCVDD12

78

TPVDD12

79

R0XCN

80

R0XCP

81

R0X0N

82

R0X0P

83

R0X1N

84

R0X1P

85

R0X2N

86

R0X2P

87

AVDD12_3

88

VDD33_2

89

[EP]GND

VA3214

ESD_HDMI

R3204

10K

C3217

0.1uF

16V

VA3203

ESD_HDMI

R3226

47K

HDMI_CLK-

HDMI_RX1+

I2C_SCL5

IC3200

AZ1117BH-1.2TRE1

1

GND/ADJ

2

OUT

3

IN

CEC_REMOTE

D1+_HDMI3

HDMI_RX2-

D3203

A2

C

A1

C3211

0.1uF

16V

CK-_HDMI1

C3212

1uF

10V

D2-_HDMI3

5V_HDMI_2

R3214 33

D1-_HDMI1

D3206

30V

MBR230LSFT1G

Q3200

MMBT3904(NXP)

E

B

C

5V_HDMI_3

C3226

0.1uF

16V

OPT

D1-_HDMI1

R3220

47K

R3233

5.1K

5%

1/16W

R3238

10

D2-_HDMI2

D0+_HDMI3

JK3203

51U019S-312HFN-E-R-B-LG

EAG62611204

HDMI_FREEPORT

14

NC

13

CE_REMOTE

5

D1_GND

20

BODY_SHIELD

GND

12

CK-

11

CK_GND

2

D2_GND

19

HP_DET

18

5V

10

CK+

4

D1+

1

D2+

17

GND

9

D0-

8

D0_GND

3

D2-

16

DDC_DATA

7

D0+

6

D1-

15

DDC_CLK

DDC_SDA_1

5V_HDMI_3

D2+_HDMI3

D2+_HDMI4

D2-_HDMI1

+3.5V_ST

D0+_HDMI2

DDC_SCL_3

D1-_HDMI2

D3200

A2

C

A1

VA3204

ESD_HDMI

R3249

3.9K

OPT

R3229

47K

DDC_SDA_1

D0+_HDMI3

CK-_HDMI4

VA3200

ESD_HDMI

C3210

0.1uF

16V

D2+_HDMI1

D2-_HDMI2

D1+_HDMI2

VA3209

ESD_HDMI

D1+_HDMI1

HDMI_HPD_3

D1+_HDMI1

5V_HDMI_4

DDC_SDA_3

R3211 33

D1+_HDMI3

C3219

1uF

C3201

10uF

10V

R3225

47K

D1-_HDMI2

R3232

10

D3205

A2

C

A1

VA3213

ESD_HDMI

D2+_HDMI2

R3213

5.1K

5%

1/16W

D1-_HDMI4

R3248

1K

OPT

R3244

10K

C3215

0.1uF

16V

D0+_HDMI1

C3200

10uF

10V

MHL_DET

5V_HDMI_1

+3.5V_ST

D0-_HDMI2

HDMI_HPD_3

D0+_HDMI4

R3243

1K

1/16W

5%

CK+_HDMI3

R3202

10K

D3201

A2

C

A1

C3203

10uF

10V

HDMI_HPD_4

D0-_HDMI4

+3.3V_NORMAL

DDC_SCL_2

D1+_HDMI2

R3245

10K

1/16W

5%

R3218

47K

D2-_HDMI3

CK-_HDMI3

HDMI_RX1-

D1-_HDMI3

DDC_SCL_3

R3239

5.1K

5%

1/16W

DDC_SCL_2

JK3201

51U019S-312HFN-E-R-B-LG

EAG62611204

HDMI_FREEPORT

14

NC

13

CE_REMOTE

5

D1_GND

20

BODY_SHIELD

12

CK-

11

CK_GND

2

D2_GND

19

HP_DET

18

5V

10

CK+

4

D1+

1

D2+

17

GND

9

D0-

8

D0_GND

3

D2-

16

DDC_DATA

7

D0+

6

D1-

15

DDC_CLK

CK+_HDMI2

C3204

0.1uF

16V

R3250

33

R3251

33

R3252

33

R3253

33

IC3202

TPS2051BDBVR

3

OC

2

GND

4

EN

1

OUT

5

IN

C3205

10uF

10V

R3215

100K

D3210

RCLAMP0524PA

HDMI_ESD_SEMTEK

1

8

2

7

3

6

4

5

9

10

D3211

RCLAMP0524PA

HDMI_ESD_SEMTEK

1

8

2

7

3

6

4

5

9

10

D3212

RCLAMP0524PA

HDMI_ESD_SEMTEK

1

8

2

7

3

6

4

5

9

10

D3213

RCLAMP0524PA

HDMI_ESD_SEMTEK

1

8

2

7

3

6

4

5

9

10

D3208

RCLAMP0524PA

HDMI_ESD_SEMTEK

1

8

2

7

3

6

4

5

9

10

D3209

RCLAMP0524PA

HDMI_ESD_SEMTEK

1

8

2

7

3

6

4

5

9

10

D3215

RCLAMP0524PA

HDMI_ESD_SEMTEK

1

8

2

7

3

6

4

5

9

10

D3214

RCLAMP0524PA

HDMI_ESD_SEMTEK

1

8

2

7

3

6

4

5

9

10

R3210

22

R3222

22

R3223

22

R3208 22

R3207 22

R3205

22

R3209

22

R3203

22

VA3205

ESD_HDMI

VA3212

ESD_HDMI

VA3202

ESD_HDMI

VA3208

ESD_HDMI

D3210-*1

IP4283CZ10-TBA

HDMI_ESD_NXP

3

GND_1

2

TMDS_CH1+

4

TMDS_CH2-

1

TMDS_CH1-

5

TMDS_CH2+

6

NC_1

7

NC_2

8

GND_2

9

NC_3

10

NC_4

D3211-*1

IP4283CZ10-TBA

HDMI_ESD_NXP

3

GND_1

2

TMDS_CH1+

4

TMDS_CH2-

1

TMDS_CH1-

5

TMDS_CH2+

6

NC_1

7

NC_2

8

GND_2

9

NC_3

10

NC_4

D3212-*1

IP4283CZ10-TBA

HDMI_ESD_NXP

3

GND_1

2

TMDS_CH1+

4

TMDS_CH2-

1

TMDS_CH1-

5

TMDS_CH2+

6

NC_1

7

NC_2

8

GND_2

9

NC_3

10

NC_4

D3213-*1

IP4283CZ10-TBA

HDMI_ESD_NXP

3

GND_1

2

TMDS_CH1+

4

TMDS_CH2-

1

TMDS_CH1-

5

TMDS_CH2+

6

NC_1

7

NC_2

8

GND_2

9

NC_3

10

NC_4

D3209-*1

IP4283CZ10-TBA

HDMI_ESD_NXP

3

GND_1

2

TMDS_CH1+

4

TMDS_CH2-

1

TMDS_CH1-

5

TMDS_CH2+

6

NC_1

7

NC_2

8

GND_2

9

NC_3

10

NC_4

D3208-*1

IP4283CZ10-TBA

HDMI_ESD_NXP

3

GND_1

2

TMDS_CH1+

4

TMDS_CH2-

1

TMDS_CH1-

5

TMDS_CH2+

6

NC_1

7

NC_2

8

GND_2

9

NC_3

10

NC_4

D3215-*1

IP4283CZ10-TBA

HDMI_ESD_NXP

3

GND_1

2

TMDS_CH1+

4

TMDS_CH2-

1

TMDS_CH1-

5

TMDS_CH2+

6

NC_1

7

NC_2

8

GND_2

9

NC_3

10

NC_4

D3214-*1

IP4283CZ10-TBA

HDMI_ESD_NXP

3

GND_1

2

TMDS_CH1+

4

TMDS_CH2-

1

TMDS_CH1-

5

TMDS_CH2+

6

NC_1

7

NC_2

8

GND_2

9

NC_3

10

NC_4

MHL_ON_OFF

R3254

100

1/16W

5%

OPT

JK3200-*1

DAADR019A

HDMI_FOOSUNG

14

RESERVED

13

CEC

5

TMDS_DATA1_SHIELD

20

BODY_SHIELD

12

TMDS_CLK-

11

TMDS_CLK_SHIELD

2

TMDS_DATA2_SHIELD

19

HOT_PLUG_DETECT

18

VDD[+5V]

10

TMDS_CLK+

4

TMDS_DATA1+

1

TMDS_DATA2+

17

DDC/CEC_GND

9

TMDS_DATA0-

8

TMDS_DATA0_SHIELD

3

TMDS_DATA2-

16

SDA

7

TMDS_DATA0+

6

TMDS_DATA1-

15

SCL

JK3201-*1

DAADR019A

HDMI_FOOSUNG

14

RESERVED

13

CEC

5

TMDS_DATA1_SHIELD

20

BODY_SHIELD

12

TMDS_CLK-

11

TMDS_CLK_SHIELD

2

TMDS_DATA2_SHIELD

19

HOT_PLUG_DETECT

18

VDD[+5V]

10

TMDS_CLK+

4

TMDS_DATA1+

1

TMDS_DATA2+

17

DDC/CEC_GND

9

TMDS_DATA0-

8

TMDS_DATA0_SHIELD

3

TMDS_DATA2-

16

SDA

7

TMDS_DATA0+

6

TMDS_DATA1-

15

SCL

JK3202-*1

DAADR019A

HDMI_FOOSUNG

14

RESERVED

13

CEC

5

TMDS_DATA1_SHIELD

20

BODY_SHIELD

12

TMDS_CLK-

11

TMDS_CLK_SHIELD

2

TMDS_DATA2_SHIELD

19

HOT_PLUG_DETECT

18

VDD[+5V]

10

TMDS_CLK+

4

TMDS_DATA1+

1

TMDS_DATA2+

17

DDC/CEC_GND

9

TMDS_DATA0-

8

TMDS_DATA0_SHIELD

3

TMDS_DATA2-

16

SDA

7

TMDS_DATA0+

6

TMDS_DATA1-

15

SCL

JK3203-*1

DAADR019A

HDMI_FOOSUNG

14

RESERVED

13

CEC

5

TMDS_DATA1_SHIELD

20

BODY_SHIELD

12

TMDS_CLK-

11

TMDS_CLK_SHIELD

2

TMDS_DATA2_SHIELD

19

HOT_PLUG_DETECT

18

VDD[+5V]

10

TMDS_CLK+

4

TMDS_DATA1+

1

TMDS_DATA2+

17

DDC/CEC_GND

9

TMDS_DATA0-

8

TMDS_DATA0_SHIELD

3

TMDS_DATA2-

16

SDA

7

TMDS_DATA0+

6

TMDS_DATA1-

15

SCL

HDMI 32

GP4

HDMI2

HDMI S/W OUTPUT

HDMI3

HDMI1 With ARC

HDMI1

HDMI2

ARC

Device Address : 0XB0

HDMI4

HDMI3

HDMI4 With MHL

Vout=0.8*(1+R1/R2)

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only

Fiber Optic

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+3.3V_NORMAL

COMP1/AV1/DVI_R_IN

COMP1/AV1/DVI_L_IN

HP_DET

R3402

10K

VA3405

5.6V

VA3402

5.6V

R3401

10K

+3.3V_NORMAL

VA3404

5.6V

+3.5V_ST

AV1_CVBS_DET

P3400

12507WS-04L

1

2

3

4

5

HP_LOUT

COMP1_Pr

R3406

10K

HP_OUT

COMP1_Y

COMP1_Pb

+3.3V_NORMAL

VA3403

5.6V

R3400

33

+3.3V_NORMAL

COMP1_DET

AV1_CVBS_IN

VA3401

5.6V

VA3400

5.5V

ADUC 5S 02 0R5L

OPT

SOC_RX

SPDIF_OUT

HP_ROUT

C3400

0.1uF

16V

SOC_TX

C3401

18pF

OPT

R3407

100

1/16W

5%

R3408

100

1/16W

5%

R3409

100

1/16W

5%

HP_OUT

R3403

330K

R3404

150

1/10W

5%

R3405

150

1/10W

5%

C3402

47pF

50V

JK3400

PEJ038-4G6

JACK_PARK

EAG61030012

3 M3_DETECT

4 M4

5 M5_GND

1 M1

6 M6

JK3403

PEJ038-3B6

EAG61030009

JACK_PARK

3DETECT

4L

5GND

1R

JK3402

PEJ038-4Y6

JACK_PARK

EAG61030011

3 M3_DETECT

4 M4

5 M5_GND

1 M1

6 M6

JK3401

JSTIB15

C

GND

B

VCC

A

VIN

4

SHIELD

C3403

0.1uF

16V

JK3400-*1

KJA-PH-1-0177-2

JACK_KSD

EAG61030007

3 M3_DETECT

4 M4

5 M5_GND

1 M1

6 M6

JK3402-*1

KJA-PH-1-0177-1

JACK_KSD

EAG61030006

3 M3_DETECT

4 M4

5 M5_GND

1 M1

6 M6

JK3403-*1

KJA-PH-0-0177

JACK_KSD

EAG61030001

3DETECT

4L

5GND

1R

JACK HIGH/MID

2012.10.09

COMPONENT 1 PHONE JACK

SPDIF OUT

CVBS 1 PHONE JACK

BSD-NC4_H034-HD

for audio Hum noise (L)

Copyright © 2013 LG Electronics. Inc. All rights reserved.

Only for training and service purposes

LGE Internal Use Only