LG 566LM THEOREM

566LM Service Manual

7. WORKING THEOREM

A. DC-DC CONVERTER

This block provides adjustable output voltages of 9.2V, -6V, 18V and 3 to 4V for the panel.

It consists of a PWM IC I119 (AIC 1341CS) and power switch IC I118 (AIC 1526-1).
When DC_EN signal is high, then I118 is activated and sends one signal to activate I119. At this
time, I119 will send 200KHz 12V PWM to Q109 , which is connected with L177, Q109. D116
and C323, to boost 5V to 9.2V. And I119 offers the adjustable voltage of 3V to 4V. By sending
out pulses from pin 2 and pin 16 of I119 to double voltage circuit consisting of C313, D112,
D111and C316, leaner regulator with Q105 would output –6V. 18V output is created , according
to the rule of –6V creation.

For protection portion, I118 offers OCP protection and I119 offers OPP and OCP protections.
F101 and F102 will be open as soon as short-circuit protection occurs of 3V to 4V and 18V.

B. A/D converter

The ADC is to convert RGB analog signal to digital signal that scaling chip can acknowledge.
The AD9883A is a complete 8-bit 110 MSPS monolithic analog interface optimized for capturing
RGB graphic signal, a +3.3V power supply is necessary. Its 110 MSPS encode rate capability
and full-power analog Bandwidth 300MHz supports display resolutions of up to 1280x1024 at
60Hz.
A clamp signa l is generated inter nally or may be pro vided through the CLAM P input pin. This
device is fully programmable via a two-wire serial port.
The HSYNC input receives a logic signal and provides the frequency reference for pixel clock
generation.
The clock gene rator CO AST i nput may b e used to st op sync hronizi ng wit h HSYNC and conti nue
producing a clock at its present frequency and phase.
The CLAMP logic input may be used to define the time during which the input signal is clamped
to GND, establishing a black reference.
When the Power Down control input is bringing to low, AD9883A is put into a very low power
dissipation mode, all the output buffers are placed in a high-impedance state.

C. Scaling controller

The scaling IC is to converts the input signal rangi ng fro m VGA to XGA into XG A resol ution t hat
panel can acknowledge. ZiproTC-T0946 is a highly integrated system on a chip that contains an
OSD logic and a timing control circuit for source/gate drivers of XGA panel. Including an
embedded hardware for display mode detection and an auto adjustment function provides
automatic frequency, phase, H/V position and white balance tuning at any screen condition.

The analog input RGB signals are first sampled by three channels of 8-bit A/D converters, and the
24-bit RGB data are then fed into the ZiproTC-T0946. The chip T0946 is capable of performing
automatic detection of the display resolution and timi ng of input signals generated from various
PC graphic cards. No special driver is required for the timing detection, nor any manual
adjustment. The T0946 then automatically scales t he input image to fill the full screen o f the LCD
monitor. The T0946 can interface with TFT LCD panels from various manufacturers by
generating either 24-bit or 48-bit RGB signal to the LCD panel based upon the timing parameters
saved in the EEPROM.

The T0946 implements four advanced display technologies:

1. Advanced mode detection and auto-calibration without any external CPU assist

2. Advanced programmable interpolation algorithm

3. Stand-alone mode support, and

4. Advanced true color support with both dithering and frame modulation.

The T0946 also provides “plug-and-play” features to the TFT LCD monitor solution. To be truly

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566LM Service Manual

plug-and-display, the T0946 performs automatic input mode detection and auto phase calibration,
so the LCD monitor can ensure that the A/D converters’ sample clock is precisely synchronized
with the input video data, and to preserve the highest image bandwidth for the highest image
quality. Furthermore, the T0946 can generate output video even when the input signal is beyond
the specifications or no input signal is fed.

The panel interface consists of 48-bit panel data bus, Start pulse(STH1) and Clock (CLKH),
Polarity(POL)/Latch pulse(LP) for source driver IC ,Start pulse(STV1) and Clock(CLKV) for gate
driver IC, and Data inversion control (HMSO/HMSE) for odd/even pixel bus and the power supply
(+3.3V,+3.45V<adjustable>,+9.2V,+18Vand-6V) for panel driver IC use.

The chip enters into power down stat us by setting POW ERDN pi ns to Hig h. The syste m returns to
normal after POWERDN to Low. In power down status, all circuits are set to off except the mode
detection circuit which is always working. The mode detection circuit detects the presences,
polarity, and frequencies of HS, VS, and DE.

The

BRI signal (pin121 of T0946) is for inverter output current control and the VOLUME signal

(pin 119 of T0946) is to control the output amplitude of the audio .

D. Inverter

In order to drive the CCFLs embedded in the panel module, there is a ROYE R inverter to convert
the input 12V up to hundreds of AC vo ltage output.
The inverter is formed by symmetric circuitry, in order to drive the separate lamp modules.
The input stage consists of a PWM controller, buck choke, and switching MOSFET to convert DC
input into AC output.
The output stage consists of a tuning capacitor, transformer, push-pull transistor pair to boost ac
output up to hundreds of voltage.
And one resister is serial to lamp for output current feedback.
A 5-pin connector is the only interface to control the inverter.
Pin 1 is 12V input, pin 2/4 is the returns, pin 3 is the control of output current, and pin 5 is the
enable/disable control.

E. Audio amplifier

The TDA7057AQ is a stereo BTL output amplifier with two DC volume control stages, designed
for TV and monitors, but also suitable for batter-fed portable recorders and radios.
In conventional DC volume control circuits the control or input stage is AC coupled to the output
stage via external capacitors to keep the offset voltage low.
In the TDA7057AQ the two DC volume control stages are integrated into the input stages so that
no coupling capacitors are required and ye t a low offset voltage is maintained. Also the minimum
supply voltage remains low.
The BTL principle offers the following advantages:

! Lower peak value of the supply current
! The frequency of the ripple on the supply voltage is twice the signal frequency.

Consequently, a reduced power supply with smaller capacitors can be used which results in cost
reductions.
For portable applications there is a trend to decrease the supply voltage, resulting in a reduction of
output power at conventional output stages. Using the BTL principle increases the output power.
The maximum gain of the amplifier is fixed at 40.5dB.
The DC volume control stages have a logarithmic control characteristic. Therefore, the total gain
can be controlled from 40.5dBto –33 dB.
If the DC volume control voltage falls below 0.4V, the device will switch to the mute mode.
The amplifier is short-circuit proof to ground, Vp and across the load. Also a thermal protection
circuits is implemented. If the crystal temperature rises above +150℃ the gain will be reduced,

thereby reducing the output power.
Special attention is given to switch-on and switch-off clicks, low HF radiation and a good overall
stability.

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