LG 50PY2DR Service Manual

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LG TRAINING MANUAL

50PY2DR Training Manual Addendum - Fall 2007

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Published August 2007 by LG USA Training Center Customer Service (and Part Sales): 1-800-243-0000 Technical Support (and Part Sales): 1-800-847-7597 USA Website: www.lgusa.com Customer Service Website: us.lgservice.com B2B Service Website: aic.lgservice.com Training Website: www.LGCSAcademy.com

IMPORTANT SAFETY NOTICE

This manual was prepared for use only by properly trained audio-visual service technicians. When servicing this product, under no circumstances should the original design be modiﬁed or altered without permission from LG Electronics. Unauthorized modiﬁcations will not only void the warranty, but may lead to property damage or user injury. All components should be replaced only with types identical to those in the original circuit and their physical location, wiring, and lead dress must conform to original layout upon completion of repairs. If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it only with the factory speciﬁed fuse type and rating. When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1W), keep the resistor 10mm away from PCB. Always keep wires away from high voltage or high temperature parts. Do not attempt to modify this product in any way.

Special components are also used to prevent shock and ﬁre hazard and are required to maintain safe performance. No deviations are allowed without prior approval by LG Electronics. Service work should be performed only after you are thoroughly familiar with these safety checks and servicing guidelines. Circuit diagrams may occasionally differ from the actual circuit used. This way, implementation of the latest safety and performance improvement changes into the set is not delayed until the new service literature is printed.

GENERAl SAFETY GuIdANCE

An lsolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating to protect against personal injury from electrical shocks. It will also protect the receiver and its components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation. Before returning the receiver to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock.

With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should

be between 1MΩ and 5.2MΩ. When the exposed metal has no return path to the chassis the reading must be inﬁnite. Any other abnormality that exists must be corrected before the receiver is returned to the customer.

ElECTROSTATICAllY SENSITIvE dEvICES

Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive (ES) Devices. Examples of typical ES devices are integrated circuits and some ﬁeld-effect transistors and semiconductor “chip” components. The following techniques should be used to help reduce the incidence of component damage caused by static electricity.

Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on the body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed for potential shock reasons prior to applying power to the unit under test. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as an ESD mat, to prevent electrostatic charge buildup or exposure of the assembly. Use only a grounded-tip soldering iron to solder or unsolder ES devices. Use only an anti-static solder removal device. Some solder removal devices not classiﬁed as “antistatic” can generate electrical charges sufﬁcient to damage ES devices. Do not use freon-propelled chemicals which can generate electrical charge sufﬁcient to damage ES devices. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. Minimize bodily motions when handling unpackaged replacement ES devices (Otherwise, seemingly harmless motion, such as the brushing together of your clothing or the lifting of your foot from a carpeted ﬂoor, can generate static electricity sufﬁcient to damage an ES device).

REGulATORY INFORMATION

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna; Increase the separation between the equipment and receiver; Connect the equipment into an outlet on a circuit different from that to which the receiver is connected; Consult the dealer or an experienced radio/TV technician for help.

The responsible party for this device’s compliance is:

LG Electronics of Alabama, Inc. 201 James Record Road Huntsville, AL 35813, USA

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Table of ConTenTs

INTRODUCTION .............................................................................................5

PCB LAYOUT .................................................................................................5

SIGNAL AND VOLTAGE DISTRIBUTION ................................................................6

SIGNAL AND VOLTAGE DISTRIBUTION (CONT.) .....................................................7

SWITCH MODE POWER SUPPLY ..........................................................................8

Y-SUSTAIN BOARD ........................................................................................9

DUAL SCAN Y-SUSTAIN DISTRIBUTION ............................................................. 10

Y-SUSTAIN TEST POINTS ................................................................................ 11

WAVEFORMS ................................................................................................ 12

Y-DRIVE BOARDS ......................................................................................... 19

50PY2DR Training Addendum 3 Contents

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- 4 -

Page 5

INTROduCTION

HDD

SMPS

Analog

Digital

Control

Y SUS

Z SUS

Top X Drive

Bottom X Drive

Y Drive

This addendum to the 50PY2DR Dual Scan Plasma Display Panel manual will discuss Layout, Circuit Board Identiﬁcation, and Troubleshooting. Upon completion of this section the Technician will have a better understanding of the disassembly procedures, the layout of the printed circuit boards and be able to identify each board.

PCB lAYOuT

TRoUblesHooTInG

50PY2DR Training Addendum 5 Troubleshooting

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TRoUblesHooTInG

Z SUS

Board

Top X Drive Boards

5v, VA, VS

VA, VS

5v, VA

Switch Mode

Power Supply

Y SUS

Board

Control

Board

5v, VA

Logic Signals

RGB Logic Signals

RGB

Logic Signals

RGB

Logic Signals

5v, VA

Y Drive Top

5V, VA

Y Drive Bottom

Drive Signal

5V, VA 5V, VA

5v, VA

RGB

Logic Signals

SIGNAl ANd vOlTAGE dISTRIBuTION

50PY2DR Training Addendum 6 Troubleshooting

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TRoUblesHooTInG

Control Board

LVDS Cable

Digital Board

Analog Board

Antenna Input

Cable Input

Power Supply

Digital Video Signal

(includes OSD)

P801 P803 P802

CN1700

P402

P201

For voltages see interconnect Diagram

Clock, Data,

Analog Audio and Video signals

SIGNAl ANd vOlTAGE dISTRIBuTION (CONT.)

50PY2DR Training Addendum 7 Troubleshooting

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TRoUblesHooTInG

VCC

Standby

SwITCh MOdE POwER SuPPlY

50PY2DR Training Addendum 8 Troubleshooting

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Y-SuSTAIN BOARd

V-SET UP

Ramp UP

V- SET DN

VSC

-VY

VSC TP (L3)

VSC Floating Ground

V SET UP Ground

Scope TP

-VY TP (R95)

V SET UP TP

TRoUblesHooTInG

50PY2DR Training Addendum 9 Troubleshooting

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TRoUblesHooTInG

Dual Scan Y SUS Board

Voltage Distribution

15v

VS_2

SUS_OUT

ER_HIGH

ER_ LOW

VS_2

ER_ LOW

ER_ HIGH

SUS_ OUT

15v

SUS_UP

SUS_DN

ER_UP

ER_DN

SUS_UP

SUS_DN

ER_UP

ER_DN

FL1

FS2

FS1

R95

-VY TP

IC7

IC2

PS5

PS3

VSC

IC303

IC17

Logic

Signals

From

Control

Bd.

Logic signals

from the

Control BD

for IPMs and

Y Drive

-VY

R27

R17

VSC TP

Q16

Q26

B41

P115vVA VS VA 5v

V SET UP

FS3

GND

-VY

ER_l0

GND

ER_I0

HS7

HS5

R88

R100

VSET UP

VSET GND

Q25

IC8

IC3

IC1

IC10

IC19

R132

15v IPM

HS4

IC303

IC302

VSET DN

Circuits

PS1

Oscilloscope

Waveform

Y Drive

D21

D12

D11

VSC Floating

Ground

VSC Floating Ground

Q12

Q17

Q18

Q19

Q11

Q15

Q14

Q10

Q13

5V VA

GND

duAl SCAN Y-SuSTAIN dISTRIBuTION

50PY2DR Training Addendum 10 Troubleshooting

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Y-SuSTAIN TEST POINTS

-Vy test point, Adjustment

Waveform

Test point

Vsc test point, Adjustment

Variations in the PCB design will result in variations in

The signal driving the PDP panel. Refer to the label on the

Y-SUS PCB match this number to the correct signal

in this manual.

TRoUblesHooTInG

50PY2DR Training Addendum 11 Troubleshooting

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TRoUblesHooTInG

Normal Y-SUS PCB #038C

DUAL SCAN PDP 50PX2

wAvEFORMS

50PY2DR Training Addendum 12 Troubleshooting

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TRoUblesHooTInG

V-Set DN too low

All of the center washes out due to decreased Vset_DN time.

V-Set DN too low

V-Set DN too high

All of the center washes out due to decreased Vset_DN time.

The center begins to wash out and arc due to decreased Vset_DN time.

50PY2DR Training Addendum 13 Troubleshooting

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TRoUblesHooTInG

V-Set UP too Low

The center begins to wash out and ark due to Vset_UP Peeking too late and alters the start of the Vset_DN phase.

V-Set UP too High

V-Set UP too Low

The center begins to wash out and ark due to Vset_UP Peeking too late and alters the start of the Vset_DN phase.

Very little alteration to the picture, the wave form indicates a distorted Vset_UP. The peek widens due to the Vset_UP peeking too quickly.

50PY2DR Training Addendum 14 Troubleshooting

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TRoUblesHooTInG

Ramp-UP too High

Noticeable low level color distortion with the Ramp_up too low.

Ramp-UP too Low

Noticeable low level color distortion with the Ramp_up too high.

Ramp-UP too High

Noticeable low level color distortion with the Ramp_up too low.

Normal Y-SUS PCB #038B

50PY2DR Training Addendum 15 Troubleshooting

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TRoUblesHooTInG

Vset-DN too low

All of the center washes out due to decreased Vset_DN time.

Vset-DN too low

Vset-DN too high

The center begins to wash out and arc due to decreased Vset_DN time.

All of the center washes out due to decreased Vset_DN time.

50PY2DR Training Addendum 16 Troubleshooting

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TRoUblesHooTInG

Vset-UP too low

The center begins to wash out and ark due to Vset_UP Peeking too late and alters the start of the Vset_DN phase.

Vset-UP too low

Vset-UP too High

Very little alteration to the picture, the wave form indicates a distorted Vset_UP. The peek widens due to the Vset_UP peeking too quickly.

The center begins to wash out and ark due to Vset_UP Peeking too late and alters the start of the Vset_DN phase.

50PY2DR Training Addendum 17 Troubleshooting

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TRoUblesHooTInG

Ramp-UP too High

Noticeable low level color distortion with the Ramp_up too low.

Ramp-UP too High

Ramp-UP too Low

Noticeable low level color distortion with the Ramp_up too high.

Noticeable low level color distortion with the Ramp_up too low.

50PY2DR Training Addendum 18 Troubleshooting

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TRoUblesHooTInG

Y-Drive Board works as a path supplying Sustain waveform and Reset

waveform which are made in Y SUSTAIN B/D and sent to the Panel through SCAN DRIVER IC’s.

The Y Drive Boards supply a waveform which selects the horizontal

electrodes sequentially.

* 50PY2DR uses 12 DRIVER ICs (TOP, BOTTOM: 6 each)

Y DRIVE Boards

Troubleshooting

Y Drive Signal Input

Floating Ground

Y Drive Signals to the PDP

Y Drive Board Voltage Distribution

Q101

Q102

Q103

IC107

IC101IC102IC103IC104IC105IC106

Troubleshooting

D104

Q105

P101

Logic Signals

from the Control

Board

P102P103P104P105

P106

P107

Y-dRIvE BOARdS

Y-Drive Board works as a path supplying Sustain waveform and Reset waveform which are made in Y SUSTAIN B/D and sent to the Panel through SCAN DRIVER IC’s. The Y Drive Boards supply a waveform which selects the horizontal electrodes sequentially. The 50PY2DR uses 12 DRIVER ICs (TOP, BOTTOM: 6 each).

50PY2DR Training Addendum 19 Troubleshooting

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Page 21

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2007 Info Center Refrigerator Training

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50PY2DR InteRconnect

P504 P505 P506 P507

P10

P100

P501

P502

P503

P509 P510 P511

P401

P402

P403

P401 P402

P403

P404

P1 P425

P404 P403

P402

CN1300

CN1700

CN1703

CN1702

CN1501

CN1500

CN1707

CN701

N/C

CN1704

CN901

LED170

LED901

P200

P300

P101

P102 P103

P4V

P104 P105 P106

D15

D16

D17

D18

TP45 – 76 Color Bar Pattern For this connector ONLY.

TP1

P805

P804

P806 N/C

P801 P803 P802

VS Adj

VA Adj

IPM

P1P12

IPM

VR1

Vsetup

VR2

Vsetdn

VSC

-VY

P5 P11

Vsetup TP

TP0 & TP779(a-d)

(Y-SUS & Z-SUS)

P402P201

P202

P203

P204

P205

Tuner’s

P101

P406

P403

P301

P100

Vsetup

GND

HDD

P600

P200

CN1705

CN1706

CN701

CN1700

1 GND 2 GND 3 12V 4 12V 5 GND 6 GND 7 9V 8 9V

9 GND 10 GND 11 3.4V 12 3.4V

CN1700

LED150

LED301

LED302

L L

Woofer Speaker

IC206

IC208

IC205

IC209

IC203

IC207

IC1706

IC802

IC1707

IC605

IC1703IC1702

Memory Card Reader

LOC IC Pin 1 Pin 2 Pin 3 Pin 4 Pin 5

IC205 SC1565 Input GND Output IC209 IC802 IC206 IC208 IC203 IC207 IC1706 IC1707

IC605 IC1702 IC1703

KA78R09F Input

I/O

control

Output

GND Output

05DZ11 Input

I/O

control

Output

N/C GND

EZ1117 GND Output Input

N/C GND

KA7809R Input

Keyboard PCB

1 GND 2 GND 3 5V 4 N/C 5 VA

P100

1 GND 2 GND 3 5V 4 N/C 5 V A

P9, P7, P3

1 GND 2 GND 3 5V 4 N/C 5 VA

P100

1 GND 2 GND 3 5V 4 N/C 5 VA

P1, P7

ER_DN (TP32)

ER_UP (TP31)

SYS_UP (TP33)

SYS_DN (TP34)

Z_BIAS (TP35)

Stby Run Stby Run Stby Run Stby Run Stby Run IC605 12.2v 12.2v 12.2v 12.2v 9.0v 9.0v 52mv 9mv 0 0 IC802 0 0 3.3v 3.3v 5.0v 5.0v N/A N/A N/A N/A IC1702 12.3v 12.3v 0 0 0 6.6v 2mv 30mv 0 0 IC1703 12.3v 12.3v 0 4.7v 0 9.0v 2mv 2mv 0 0 IC1706 5.8v 5.8v 5.8v 5.8v 5.0v 5.0v 2mv 2mv 0 0 IC1707 5.8v 5.8v 5.8v 5.8v 5.0v 5.0v 2mv 2mv 0 0

Pin 5Pin 1 Pin 2 Pin 3 Pin 4

(TP25) LE_Top

(TP26) NSC

(TP27) Data_Top

15VT

(TP28) CLK_Top

15VB

CLK_Btm Data_Btm

NSC

5VB

LE_Btm

Y_SUS Waveform

TP19

TP20 & 21

(Pin 60)

TP22 - (Pin 3) TP23 – (Pin 1) TP24 – (Pin 2)

TP20 & 21

(Pin 60)

TP20 & 21

TP22 - (Pin 58) TP23 – (Pin 60) TP24 – (Pin 59)

TP20 & 21

(

)

(Pin 1)

(

)

TP22 - (Pin 3) TP23 – (Pin 1) TP24 – (Pin 2)

TP20 & 21

(Pin 60)

TP20 & 21

(Pin 60)

TP22 - (Pin 3) TP23 – (Pin 1) TP24 – (Pin 2)

(

)

Stby Run Stby Run Stby Run Stby Run Stby Run IC203 5.7v 5. 7v 5.7v 5.7v 5.0v 5.0v 1mv 1mv 0 0 IC205 3.4v 3. 4v 0 0 1.8v 1.8v N/A N/A N/A N/A IC206 12.2v 12.2v 0 0 9.0v 9.0v N/A N/A N/A N/A IC207 5.7v 5. 7v 5.7v 5.7v 5.0v 5.0v 1mv 1mv 0 0 IC208 12.2v 12.2v 0 1 9.0v 9.0v N/A N/A N/A N/A IC209 0 1 3.0v 3.0v 5.0v 5.0v N/A N/A N/A N/A

Pin 5Pin 1 Pin 2 Pin 3 P in 4

1 GND 1 138.0mV 1 4.91V 2 12V 2 1.2V 2 5.0V 3 GND 3 10.1mV 3 4. 91V 4 3.4V 4 GND 4 GND 5 GND 5 5.0V 5 5.0V 6 6V 6 4.9V 6 4.9V 7 GND 7 4.3V 7 4.3V 8 GND

9 19V

10 19V

STBY RUN

P402 P201

1 GND 1 GND 1 GND 1 VA 1 3.4V 1 138.0mV 1 4.91V 2 12V 2 GND 2 GND 2 VA 2 3.4V 2 1.2V 2 5.0V 3 GND 3 12V 3 V CC 5V 3 GND 3 3.4V 3 10.1mV 3 4.91V 4 3.4V 4 12V 4 VCC 5V 4 GND 4 3.4V 4 GND 4 GND 5 GND 5 GND 5 GND 5 GND 5 5.0V 5 5.0V 6 6V 6 GND 6 GND 6 GND 6 4.9V 6 4.9V 7 GND 7 9V 7 VS 7 GND 7 4.3V 7 4.3V 8 GND 8 9V 8 VS 8 GND

9 19V 9 GND 9 VS

10 19V 10 GND 10 VS

11 3. 4V 12 3. 4V

P806P805P804

STBY

P801

RUN

P802 P803

1 5V 2 5V 3 GND 4 GND 5 GND 6 GND 7 GND 8 N/C

9 VA 10 VA 11 VS 12 VS

P12

1 VS 1 GND 1 GND 1 5V 1 GND 1 5V 2 VS 2 GND 2 GND 2 5V 2 GND 2 5V 3 VS 3 5V 3 5V 3 5V 3 5V 3 GND 4 N/C 4 5V 4 N/C 4 5V 4 N/C 4 GND 5 GND 5 VA 5 GND 5 VA 5 GND 6 GND 6 GND 6 GND 7 GND 7 GND 7 GND 8 GND 8 GND 8 N/C 9 VA 9 VA

10 VA 10 VA

11 5V 12 5V

P7 P11P3 P4 P5 P6

IC24

IC44

IC46

IC45

Pin 1 Pin 2 Pin 3 IC24 5v 2.5v 0 IC42 5v 2.5v 0 IC44 5v 3.3v 0 IC45 5v 3.3v 0 IC46 5v 3.3v 0

IC42

(TP30)

(TP29)

(TP44) After resister array

(TP76) Before resister array

1 GND 1 0V Z Dummy (TP42) 2 GND 2 0V 3 5V 3 1.5V Z-sus dn (TP41) 4 N/C 4 0V 5 VA 5 3.0V Z-sus up (TP39)

6 0V Z-ramp up (TP38) 7 0V 8 0V V A Con (TP37)

9 .7V Z-er dn (TP36) 10 .4V Z-er up (TP35) 11 3V - . 3V 12 0V

P1, P4, P6 P5, P2

1 GND 2 GND 3 5V 4 N/C 5 VA

P5, P7

B11 TP43 & TP77(a-d) (Y-SUS & Z-SUS)

(TP29)

(

TP29

)

(

TP29

)

Ramp_dn (TP78) Ramp_up (TP79)

SW Er_up (TP80) Er_dn (TP81)

Sus_up (TP82) Sus_dn (TP83)

B12

A/C Input

P504

P401

P100

Front display PCB

Side AV input PCB

TP22 - (Pin 3) TP23 – (Pin 1) TP24 – (Pin 2)

Y-SUS Voltages

50PY2DR Training Addendum 23 Schematics

Page 24

50PY2DR WavefoRms

TP0

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

*TP18

*TP19

*NOTE 18 and 19 are the same signal #19 is

a closer view of the signal.

TP20

TP21

NOTE: 21 is a closer view of 20

TP22

TP23

TP24

TP25

TP26

TP27 TP28

TP29

TP30

50PY2DR Training Addendum 24 Schematics

Page 25

50PY2DR WavefoRms

TP31

TP32

TP33

TP34

TP35

TP36

TP37

TP38

TP39

TP40

TP41

TP42

TP43

TP44

TP45

TP46

TP47

TP48

TP49

TP50

TP51

TP52

TP53

TP54

TP55

TP56

TP57

TP58

TP59

TP60

50PY2DR Training Addendum 25 Schematics

Page 26

50PY2DR WavefoRms

TP64

TP65

TP66

TP67

TP68

TP69

TP70

TP63

TP62

TP61 TP71

TP72

TP73

TP74

TP75

TP77

TP76

Z-SUS

Y-SUS

TP77a

TP77b

TP77c

TP77d

TP78

TP79

TP80

TP81

TP82

TP83

Z-SUS

Y-SUS

At varied time per division

50PY2DR Training Addendum 26 Schematics