LG 50pq30 Diagram

Training Manual

50PQ30 Plasma Display

50PQ30 Plasma Display

Advanced Single Scan Troubleshooting

720p

720p

Published November 05

th

, 2009

OUTLINE

OUTLINE

Section 1

Contact Information, Preliminary Matters, Specifications,
Plasma Overview, General Troubleshooting Steps,
Disassembly Instructions, Voltage and Signal Distribution

Section 2

Circuit Board Operation, Troubleshooting and Alignment of :

• Switch mode Power Supply

Overview of Topics to be Discussed

• Y-SUS Board

Delivers Logic Signals and FG5V to both upper and lower boards.

• Y-Drive Boards (2) Upper and Lower. Lower board delivers Scan to Upper

• Z-SUS Output Board (Also uses one Z-SUB board for bottom panel connector)

• Control Board

• X Drive Boards (3)

• Main Board

• Main Power Switch (Version 3). Shuts off stand by 5V.

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November 2009 50PQ30 Plasma

Overview of Topics to be Discussed

Overview of Topics to be Discussed

50PQ30 Plasma Display

Section 1

This Section will cover Contact Information and remind the Technician of
Important Safety Precautions for the Customers Safety as well as the Technician
and the Equipment.

Basic Troubleshooting Techniques which can save time and money sometimes
can be overlooked. These techniques will also be presented.

This Section will get the Technician familiar with the Disassembly, Identification and
Layout of the Plasma Display Panel.

At the end of this Section the Technician should be able to Identify the Circuit
Boards and have the ability and knowledge necessary to safely remove and
replace any Circuit Board or Assembly.

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November 2009 50PQ30 Plasma

Preliminary Matters (The Fine Print)

Preliminary Matters (The Fine Print)

IMPORTANT SAFETY NOTICE

IMPORTANT SAFETY NOTICE

The information in this training manual is intended for use by persons possessing an adequate
background in electrical equipment, electronic devices, and mechanical systems. In any attempt
to repair a major Product, personal injury and property damage can result. The manufacturer or
seller maintains no liability for the interpretation of this information, nor can it assume any
liability in conjunction with its use. When servicing this product, under no circumstances should
the original design be modified or altered without permission from LG Electronics. Unauthorized
modifications will not only void the warranty, but may lead to property damage or user injury.
If wires, screws, clips, straps, nuts, or washers used to complete a ground path are removed for
service, they must be returned to their original positions and properly fastened.

CAUTION

CAUTION

To avoid personal injury, disconnect the power before servicing this product. If electrical power
is required for diagnosis or test purposes, disconnect the power immediately after performing
the necessary checks. Also be aware that many household products present a weight hazard.
At least two people should be involved in the installation or servicing of such devices.
Failure to consider the weight of an product could result in physical injury.

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November 2009 50PQ30 Plasma

LG CONTACT INFORMATION

LG CONTACT INFORMATION

Customer Service (and Part Sales) [phone]

Technical Support (and Part Sales) [phone]

USA Website (GCSC) aic.lgservice.com

Customer Service Website us.lgservice.com

LG Web Training lge.webex.com

LG CS Academy lgcsacademy.com

LCD-DV:

PLASMA:

Also available on

Also available on

the Plasma page

the Plasma page

Published November 2009 by LG Technical Support and Training

http://136.166.4.200

LG Learning Academy

32LG40, 32LH30, 37LH55, 42LG60, 42LG70, 42LH20, 42LH40, 42LH50, 47LG90
42PG20, 42PQ20, 50PQ30, 50PG20, 50PS80, 50PS60

Plasma Panel

Alignment Handbook

LG Electronics Alabama, Inc.

201 James Record Road, Huntsville, AL, 35813.

New Training Materials on

New Training Materials on

the Learning Academy site

the Learning Academy site

Page 5

Page 5

(Electrostatic Static Discharge)

ESD Notice

ESD Notice

Today’s sophisticated electronics are electrostatic discharge (ESD) sensitive. ESD can weaken or damage
the electronics in a manner that renders them inoperative or reduces the time until their next failure.
Connect an ESD wrist strap to a ground connection point or unpainted metal in the product. Alternatively,
you can touch your finger repeatedly to a ground connection point or unpainted metal in the product. Before
removing a replacement part from its package, touch the anti-static bag to a ground connection point or
unpainted metal in the product. Handle the electronic control
repackaging a failed electronic control assembly in an anti-static bag, observe these same precautions.

Regulatory Information

Regulatory Information

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference when the equipment is operated in a residential installation. This equipment generates, uses,
and can radiate radio frequency energy, and, if not installed and used in accordance with the instruction
manual, may cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful interference to
radio or television reception, which can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate
the receiving antenna; Increase the separation between the equipment and the receiver; Connect the
equipment to an outlet on a different circuit than that to which the receiver is connected; or consult the
dealer or an experienced radio/TV technician for help.

(Electrostatic Static Discharge)

assembly by its edges only. When

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November 2009 50PQ30 Plasma

Safety and Handling, Checking Points

Safety and Handling, Checking Points

Safety & Handling Regulations

1. Approximately 10 minute pre-run time is required before any adjustments are performed.

2. Refer to the Voltage Sticker inside the Panel when making adjustments on the Power Supply, Y-SUS and Z-SUS Boards.

3. Always adjust to the specified voltage level (+/- ½ volt) unless otherwise specified.

4. Be cautious of electric shock from the PDP module since the PDP module uses high voltage, check that the Power Supply
and Drive Circuits are completely discharged because of residual current stored before Circuit Board removal.

4. C-MOS circuits are used extensively for processing the Drive Signals and should be protected from static electricity.

5. The PDP Module must be carried by two people. Always carry vertical NOT horizontal.

6. The Plasma television should be transported vertically NOT horizontally.

7. Exercise care when making voltage and waveform checks to prevent costly short circuits from damaging the unit.

8. Be cautious of lost screws and other metal objects to prevent a possible short in the circuitry.

9. New Panels and Frames are much thinner than previous models. Be Careful with flexing these panels. Be careful
with lifting Panels from a horizontal position. Damage to the Frame mounts or panel can occur.

10. New Plasma models have much thinner cabinet assemblies and mounts.
Be extremely careful when moving the set around as damage can occur.

Checking Points to be Considered

1. Check the appearance of the Replacement Panel and Circuit Boards for both physical damage and part number accuracy.

2. Check the model label. Verify model names and board model matches.

3. Check details of defective condition and history. Example: Y Board Failure, Mal-discharge on screen, etc.

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November 2009 50PQ30 Plasma

Basic Troubleshooting Steps

Basic Troubleshooting Steps

Define, Localize, Isolate and Correct

• Define
failure. Use your senses Sight, Smell, Touch and Hearing. Look for burned parts and check
for possible overheated components. Capacitors will sometimes leak dielectric material and
give off a distinct odor. Frequency of power supplies will change with the load, or listen for
relay closing etc. Observation of the front Power LEDs may give some clues.

• Localize
and after giving a thorough examination using your senses the first check should always be
the DC Supply Voltages to those circuits under test. Always confirm the supplies are not
only the proper level but be sure they are noise free. If the supplies are missing check the
resistance for possible short circuits.

• Isolate
to make a final determination of the failure. Look for correct Amplitude Phasing and Timing
of the signals also check for the proper Duty Cycle of the signals. Sometimes “glitches” or
“road bumps” will be an indication of an imminent failure.

Look at the symptom carefully and determine what circuits could be causing the

After carefully checking the symptom and determining the circuits to be checked

To further isolate the failure, check for the proper waveforms with the Oscilloscope

• Correct
check the DC Supplies for proper levels. Make all necessary adjustments and lastly always
perform a Safety AC Leakage Test before returning the product back to the Customer.

The final step is to correct the problem. Be careful of ESD and make sure to

8

November 2009 50PQ30 Plasma

50PQ30 PRODUCT INFORMATION SECTION

50PQ30 PRODUCT INFORMATION SECTION

This section of the manual will discuss the specifications of the
50PQ30 Advanced Single Scan Plasma Display Television.

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November 2009 50PQ30 Plasma

50PQ30 Specifications

50PQ30 Specifications

• 720p HD Resolution

• 600 Hz sub field driving

• 1,500 cd/m2 Brightness

• Dual XD Engine™

• 2000,000:1 Dynamic Contrast Ratio

• Smart Energy Saving

• 3x HDMI™ V.1.3 with Deep Color (2 Rear, 1 side).

720P PLASMA HDTV

50” Class (50” diagonal)

• AV Mode (Cinema, Sports, Game)

• Clear Voice

• LG SimpLink™ Connectivity

• Invisible Speaker System

• 100,000 Hours to Half Brightness (Typical)

• PC Input

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November 2009 50PQ30 Plasma

600Hz Sub Field Driving

600Hz Sub Field Driving

(600 Hz Sub Field Driving)

• 600 Hz Sub Field Driving is achieved by using 10 sub-fields per frame process
(vs. Comp. 8 sub-field/frame)

• No smeared images during fast motion scenes

Original Image 10 Sub Fields Per Frame

Sub Field firing occurs using wall charge and polarity differences between Y-SUS and Z-SUS signals.

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November 2009 50PQ30 Plasma

Specifications Logo Familiarization (Picture Wizard)

Specifications Logo Familiarization (Picture Wizard)

Picture Wizard

consumers through the
calibration process using
on-screen reference
points.

Customers can customize

picture performance
without the need for
additional expense.

easily guides

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November 2009 50PQ30 Plasma

50PQ30 Logo Familiarization Page 1 of 2

50PQ30 Logo Familiarization Page 1 of 2

HD RESOLUTION 720p HD Resolution Pixels: 1365 (H) × 768 (V)
High definition television is the highest performance segment of the
DTV system used in the US. It’s a wide screen, high-resolution video
image, coupled with multi-channel, compact-disc quality sound.

HDMI (1.3 Deep Color) Digital multi-connectivity

HDMI (1.3 Deep color) provides a wider bandwidth (340MHz,

10.2Gbps) than that of HDMI 1.2, delivering a broader range of colors,
and also drastically improves the data-transmission speed.

Invisible Speaker
Personally tuned by Mr. Mark Levinson for LG

TAKE IT TO THE EDGE newly introduces ‘Invisible Speaker’ system,
guaranteeing first class audio quality personally tuned by Mr. Mark
Levinson, world renowned as an audio authority. It provides Full Sweet
Spot and realistic sound equal to that of theaters with its Invisible
Speaker.

Dual XD Engine
Realizing optimal quality for all images

One XD Engine optimizes the images from RF signals as another XD
Engine optimizes them from External inputs. Dual XD Engine presents
images with optimal quality two times higher than those of previous
models.

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November 2009 50PQ30 Plasma

50PQ30 Logo Familiarization Page 2 of 2

50PQ30 Logo Familiarization Page 2 of 2

AV Mode "One click" Cinema,

TAKE IT TO THE EDGE is a true multimedia TV with an AV Mode
which allows you to choose from 4 different modes of Cinema, Sports
and Game by a single click of a remote control.

Clear Voice Clearer dialogue sound

Automatically enhances and amplifies the sound of the human voice
frequency range to provide high-quality dialogue when background
noise swells.

Save Energy, Save Money

It reduces the plasma display’s power consumption.
The default factory setting complies with the Energy Star requirements
and is adjusted to the comfortable level to be viewed at home.
(Turns on Intelligent Sensor).

THX

Cinema, Sport, Game mode.

Save Energy, Save Money

Home electronic products use energy when they're off to power features like clock
displays and remote controls. Those that have earned the ENERGY STAR use as much
as 60% less energy to perform these functions, while providing the same performance at
the same price as less-efficient models. Less energy means you pay less on your energy
bill. Draws less than 1 Watt in stand by.

14

November 2009 50PQ30 Plasma

50PQ30 Remote Control

50PQ30 Remote Control

TOP PORTION

BOTTOM PORTION

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November 2009 50PQ30 Plasma

50PQ30 Rear and Side Input Jacks

50PQ30 Rear and Side Input Jacks

AC In

REAR

INPUTS

Software

Upgrades

SIDE

INPUTS

Music and

Photos

USB

HDMI 3

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November 2009 50PQ30 Plasma

Power:

279W (Typical)

0.13W (Stand-By)

50PQ30 Dimensions

There must be at least 4 inches of Clearance on all sides

47-7/8"

1216.66mm

6-3/16"

157mm

15-3/4"

15-5/16"

405mm

400mm

3-5/16"

83.82mm

32-3/16"

817.9mm

759.46mm

Weight:

29-7/8"

2-5/16"

58.74mm

74.3 lbs with Stand

68.8 lbs without Stand

15-3/4"

400mm

7-7/8"

200mm

Remove 4 screws to

remove stand for

wall mount

25-5/8"

651mm

15-3/4"

400mm

Model No.

Serial No.

Label

4-15/16"

125mm

7-1/4"

183.74mm

13-7/8"

353mm

17 Published November 2009 50PQ30 Plasma

DISASSEMBLY SECTION

DISASSEMBLY SECTION

This section of the manual will discuss Disassembly, Layout and Circuit
Board Identification, of the 50PQ30 Advanced Single Scan Plasma Display Panel.

Upon completion of this section the Technician will have a better
understanding of the disassembly procedures, the layout of the printed
circuit boards and be able to identify each board.

18

November 2009 50PQ30 Plasma

Removing the Back Cover

Removing the Back Cover

To remove the back cover, remove the 26 screws

(The Stand does not need to be removed).

PAY CLOSE ATTENTION TO THE TYPE, SIZE AND LENGTH

Of the screws when replacing the back cover.

Improper type can damage the front.

Indicated by the arrows.

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November 2009 50PQ30 Plasma

Circuit Board Layout

Circuit Board Layout

Panel Voltage Label

Y-Drive

Upper

FPC

FPC FPC FPC

Identify the Circuit Boards

Identify the Circuit Boards

Power Supply

(SMPS)

Panel ID Label

FPC

Z-SUS

FPC

FPC

IR/

LED

Y-Drive

Lower

Power

Main

Y-SUS

TCP

Heat Sink

Keyboard

Left “X”

Control

AC In

Center “X”

Invisible Speakers

Right “X”

Conductive Tape Under Main Board

Z-SUB

Side Input

(part of main)

Main Board

FPC

FPC

20

November 2009 50PQ30 Plasma

Disassembly Procedure for Circuit Board Removal

Disassembly Procedure for Circuit Board Removal

Notes: 1) All Plugs listed are from left to right Pin 1,2, 3, ETC.

2) Remember to be cautious of ESD as some semiconductors are CMOS and prone to static failure.

Switch Mode Power Supply Board Removal

Disconnect the following connectors: P811, P813, SC101.
Remove the 8 screws holding the SMPS in place.
Remove the board.
When replacing, be sure to readjust the Va/Vs voltages in accordance with the Panel Label.
Also, re-confirm VSC, -Vy and Z-Bias as well.

After replacing the Y-Drive,

Y-SUS Board Removal

Disconnect the following connectors: P201, P206, P101, P202.
Remove the 8 screws holding the Y-SUS in place.
Remove the Y-SUS by lifting slightly to clear standoff and slid it to the right.
When replacing, be sure to readjust the Va/Vs voltages in accordance with the Panel Label.
Confirm VSC, -Vy and Z-bias as well.

After replacing the Y-Drive,

Y-Drive Boards Removal

check the connectors for solder breaks.

check the connectors for solder break.

Board Standoff

Disconnect the following Flexible Ribbon Connectors: P101~P103 and/or P201~P203.
Disconnect the following connectors: P209 and/or P108.
Remove the 3 screws holding either of the Y-Drive boards in place.
Remove the Y-Drive by lifting slightly and sliding the board to the left unseating P106,
P107, P109 and/or P205, P206 and P208 from the Y-SUS Board.

Note: Y, Z-SUS and Y-Drive boards are mounted on board stand-offs that have a small collar.
The board must be lifted slightly to clear these collars.

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November 2009 50PQ30 Plasma

Collar

Disassembly Procedure for Circuit Board Removal (2)

Disassembly Procedure for Circuit Board Removal (2)

Z-SUS Board Removal

Disconnect the following connectors: P100, P101.
Disconnect the following connectors: P104, P105 and P302. These are the FPC cables. Pull the locking
caps to the right. Lift carefully the Flexible Printed Circuits (FPCs) and slide them out to the right.
Remove the 5 screws holding the Z-SUS in place and the one holding the Z-SUB in place.
Lift the Z-SUS up and remove the board. Remove the Z-SUB by pulling it off the Z-SUS.
When replacing, be sure to readjust the Va/Vs voltages in accordance with the Panel Label.
Confirm VS, -Vy and Z-bias as well.

Main Board Removal

Disconnect the following connectors: P1001, P1003, P1005 and P1006.
Remove the 1screws holding on the decorative plastic piece on the right side.
Remove the 4 screws holding the Main board in place and Remove the board.

Control Board Removal

Disconnect the following connectors: P121 LVDS, P101, P161 Ribbon, P162 Ribbon by lifting up the
locking tab. Remove the 4 screws holding the Control board in place Remove the board.

Front Key and LED Board Removal

Remove the 2 screws holding the Key board in place. Remove the board by releasing the two black
tabs and lifting the board upward. Disconnect P101.
(Note: LED board is behind the Key board. Remove it’s 2 screws and remove.
Disconnect J1 and J2.

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November 2009 50PQ30 Plasma

X Drive Circuit Board Removal Continued

X Drive Circuit Board Removal Continued

Lay the Plasma down carefully on a padded surface.
Make sure AC is removed and remove the Back Cover and the Stand.
Carefully remove the LVDS Cable P121 from the Control Board by pressing the Locking Tabs together and
pull the connector straight back to remove the cable. (This prevents possible damage). See illustration below.

Press

Inward

LVDS Cable Connector

(A) Remove the Stand (4 Screws removed during back removal).
(B) Remove the Stand Metal Support Bracket (5 Screws).
(C) Remove connector P1001 to Front IR board and P1005 to the Speakers.
(D) Remove the 4 screws from the Main Board Mounting Bracket. Carefully reposition the Main Board and Mounting

Bracket up and off to the right side.
(E) Remove the metal support Braces marked “E”. Note: There is a Left and a Right brace. (3 Screws per/bracket).
(F) Remove the 9 screws holding the Heat Sink. (Warning: Never run the set with this heat sink removed).

X-DRIVE LEFT, CENTER AND RIGHT REMOVAL:

Disconnect all TCP ribbon cables from the defective X-Drive board. Remove the 3 screws in either the Left or Right X-Drive
board or the 4 screws holding the Center X-Drive in place.
Remove the board. Reassemble in reverse order. Recheck Va / Vs / VScan / -VY / Z-Drive.

Press

Inward

23

November 2009 50PQ30 Plasma

Getting to the X Circuit Boards

Getting to the X Circuit Boards

Warning: Never run the TV with the TCP Heat Sink removed

A

LVDS Cable

B

Stand should have already be removed

F

Heat Sink

E

Left

B

A

Warning Shorting Hazard: Conductive Tape. Do not allow to touch energized circuits.

24

November 2009 50PQ30 Plasma

E

Right

C

D

Left and Right X Drive Removal

Left and Right X Drive Removal

After removing the back cover, the Main board is lifted out of the way, the 9 screws removed from heat sink
covering the TCPs and connectors to the TCPs are removed, the X-Drive boards can be removed.

There may be tape on the connectors P231 or P232

P231 P232

Peel the tape off the connectors

Remove tape (if present) and Gently

locking mechanism upward and remove the ribbon

cable from the connector.

Removing Connectors to the TCPs.

Gently lift the locking mechanism

upward on all TCP connectors

Left X: P101~105

Center X: P201~206

Right X: P301~305

Cushion (Chocolate)

pry the

Disconnect connector P122

P122

Va from the Y-SUS

Carefully lift the TCP ribbon up and off.

It may stick, be careful not to crack TCP.

(See next page for precautions)

TCP

25

Flexible ribbon cable connector

November 2009 50PQ30 Plasma

TCP (Tape

TCP (Tape

Carrier

Carrier

Package) Generic Removal Precautions

Package) Generic Removal Precautions

TCP Connector Removal

Lift up the lock as shown by arrows.

(The Lock can be easily broken.

It needs to be handled carefully.)

The TCP has two small tab on each
side which have to be lifted up
slightly to pull the connector out.
Note: TCP is usually stuck down
to the heat transfer material, be
Very careful when lifting up on
the TCP ribbon cable.

26

Pull TCP apart as shown by arrow.

(TCP Film can be easily damaged.

Handle with care.)

November 2009 50PQ30 Plasma

Left and Right X Drive Removal

Left and Right X Drive Removal

Remove the 3 screws for either left or right board or 4 for the center. 8 total for all three.

(The screws between the boards, secures both boards)

The Left X Board drives the right side of the screen vertical electrodes

The Center X Board drives the Center of the screen vertical electrodes

The Right X Board drives the left side of the screen vertical electrodes

27

November 2009 50PQ30 Plasma

CIRCUIT OPERATION, TROUBLESHOOTING AND CIRCUIT

CIRCUIT OPERATION, TROUBLESHOOTING AND CIRCUIT

ALIGNMENT SECTION

ALIGNMENT SECTION

50PQ30 Plasma Display

This Section will cover Circuit Operation, Troubleshooting and
Alignment of the Power Supply, Y-SUS Board, Y-Drive Boards, Z-SUS
Board, Control Board, Main Board and the X Drive Boards.

At the end of this Section the technician should understand the operation
of each circuit board and how to adjust the controls. The technician
should be able with confidence to troubleshoot a circuit board failure,
replace the defective circuit and perform all necessary adjustments.

28

November 2009 50PQ30 Plasma

50PQ30 SIGNAL and VOLTAGE DISTRIBUTION DIAGRAM

Y Drive

FPCs

P101

P102

P103

FPCs

P201

P202

P203

Upper

P109

P101

P103

P106

P107

P106

(V Scan)

P209

P208

P206

P207

5VFG indicates
measured from

Floating Ground

Floating
Ground

5VFG

Drive Data
Clock (i2c)

5VFG

Drive Data
Clock (i2c)

Y Drive

Lower

Display Panel
Horizontal Electrodes

P209
(5VFG) (FG)

P204
(FG)

P203
(FG)

Y-SUS

Board

P208
(FG)

P208
(FG)

P207
(V Scan)
(5VFG) (FG)

VSC

DC/DC

-Vy

DC/DC

5VFG

DC/DC

P206

P201

P101

17V

DC/DC

P202

Va

P122

SMPS OUTPUT VOLTAGES IN STBY

STB +5V (also AC Voltage Det)

P811

Power

M5V, Vs, Va

Note:

Va not used

by Y-SUS

Drive Signals for

Y-SUS and Y-Drive

M5V, 17V

Note: 17V not used

by Control

Signals

3.3V

P121

P212

Supply

Board

SK101

AC
Input
Filter

M5V

P200

P111

3.3V

P121

P101

CONTROL

Board

P161

P162

RGB

Logic

P231

P232

P211 P311 P331

X-Board-Center

P813

Z Drive Signals

3.3V

RGB

Logic

Signals

3.3V

P232

SMPS OUTPUT VOLTAGES IN RUN

STB5V, +5V, 17V, 12V to Main PWB
Vs, Va and M5V to Y-SUS

SMPS

M5V, Vs, Error-Com

Turn On

Commands

Relay On
M5 On
VS On

+5V, 12V
M5V
Audio 17V,
Va, Vs

LVDS

Z Drive

17V

Set in

Signals

LVDS

Stand By:
STB +5

AC Voltage
Det

5V

STBY

P1006

P1001

P1005

P1003

MAIN Board

IR, Power LED,

3.3V

P211 P331

Intelligent Sensor

X-Board-RightX-Board-Left

Horizontal

Display Panel

Electrodes

P101

Z SUS
Board

17V

P100

Speakers

Control Keys

3.3V

Power Button

FPCs

P101

P102

P103

P302

P301

FPCs

3.3V

Key Board

Pull Up

Va

P101 P102 P103 P104 P105 P201 P301 P302 P304 P305

P202 P203 P204 P205 P206 P303

Va

Display Panel Vertical Address (RGB Cell Address)

29 Published November 2009 50PQ30 Plasma

Panel Label Explanation

Panel Label Explanation

(1)

(2)

(3)
(4)

(5)
(6) (7)

(9) (10)

(8)

(11)
(12)

(13)
(14)
(15)

(1) Panel Model Name
(2) Bar Code
(3) Manufacture No.
(4) Adjusting Voltage DC, Va, Vs
(5) Adjusting Voltage (Set Up / -Vy / Vsc / Ve / Vzb)
(6) Trade name of LG Electronics
(7) Manufactured date (Year & Month)
(8) Warning

30

(9) TUV Approval Mark
(10) UL Approval Mark
(11) UL Approval No.
(12) Panel Model Name
(13) Max. Watt (Full White)
(14) Max. Volts
(15) Max. Amps

November 2009 50PQ30 Plasma

Adjustment Notice

Adjustment Notice

All adjustments (DC or Waveform) are adjusted in WHITE WASH.

Customer’s Menu, Select “Options”, select “ISM” select “WHITE WASH”.

It is critical that the DC Voltage adjustments be checked when;

1) SMPS, Y-SUS or Z-SUS board is replaced.

2) Panel is replaced, Check Va/Vs since the SMPS does not come with new panel

3) A Picture issue is encountered

4) As a general rule of thumb when ever the back is removed

ADJUSTMENT ORDER “IMPORTANT”
DC VOLTAGE ADJUSTMENTS

1) POWER SUPPLY: Va Vs (Always do first)

2) Y-SUS: Adjust –Vy, Vscan,

Remember, the Voltage Label MUST be followed,

3) Z-SUS: Adjust Z-Bias (VZB)

it is specific to the panel’s needs.

WAVEFORM ADJUSTMENTS

1) Y-SUS: Set-Up, Set-Down

Manufacturer

Bar Code

The Waveform adjustment is only necessary

1) When the Y-SUS board is replaced

2) When a “Mal-Discharge” problem is encountered

3) When an abnormal picture issues is encountered

Set-

Up

31

-VY

Vscan

All label references are from a specific panel.

They are not the same for every panel encountered.

Ve

Z_BIAS

“Rear View”

November 2009 50PQ30 Plasma

Panel

SWITCH MODE POWER SUPPLY SECTION

SWITCH MODE POWER SUPPLY SECTION

This Section of the Presentation will cover troubleshooting the Switch Mode Power Supply for

the Single Scan Plasma. Upon completion of the section the technician will have a
better understanding of the operation of the Power Supply Circuit and will be able to
locate voltage and test points needed for troubleshooting and alignments.

• DC Voltages developed on the SMPS

• Adjustments VA and VS.

• Always refer to the Voltage Sticker located on the back of the panel, in the upper Left
Hand side for the correct voltage levels for the VA, VS, -VY, Vscan, and Z Bias as these
voltages will vary from Panel to Panel even in the same size category.

• Set-Up and Ve are just for Label location identification and are not adjusted in this panel.

SMPS P/N EAY58316301

Check the silk screen label on the top center of the Power Supply board to identify the correct part
number. (It may vary in your specific model number).

On the following pages, we will examine the Operation of this Power Supply.

32

November 2009 50PQ30 Plasma

50PQ30 50G2 (SMPS) POWER SUPPLY BOARD

50PQ30 50G2 (SMPS) POWER SUPPLY BOARD

P811

10

1

Hot Ground

C107

L102

L602L601

10) M5V

9) M5V

8) Gnd

7) VA

6) VA

5) Gnd

4) Gnd

3) N/C

2) VS

1) VS

C106

EXAMPLE: Voltage Label. Use the voltage
label off your specific panel for adjustments.

Hot Ground Symbol represents a SHOCK Hazard

T901

F801

4A/250V

VR502

Va

17V turns on

1

2

Hot Ground

RL101

RL103

STBY 123V

RUN 382V

F801

STBY 160V

RUN 382V

F302

1A/

250V

1

0

1

F

SC101

VR901

Hot Ground

F101

10A/250V

AC In

Vs

1,2) 17V
3,4) Gnd
5,6) 12V
7,8) Gnd
9,10,11) +5V

12) Stby 5V
13,14) Gnd

T301

15) n/c

16) Gnd

17) 5V Det

18) AC Det

19) RL_On

20) VS_On

21) M5_On

22) Auto Gnd

23) Stby 5V

24) Key_On

Model : PDP 50G2####
Voltage Setting:5V / Va:60V / Vs:193V
N.A. / -185 / 133 / N.A. / 80
Max Watt : 350 W (Full White)

with Vs On

command

IC701

P813

23

24

VA Adjust

VR502

17V

1

3

Gnd

5

12V

7

Gnd

9

5V

11

5V

13

Gnd

15

Gnd

17

5V Det

19

RL ON

M5 ON

21

Stby5V

23

VS Adjust

P813

2

4

6

8

10

12

14

16

18

20

22

24

VR901

17V

Gnd

12V

Gnd

5V

STBY 5V

Gnd

N/C

AC Det

VS ON

Auto Gnd

Key On

33

Published November 2009 50PQ30 Plasma

Switch Mode Power Supply Overview

Switch Mode Power Supply Overview

The Switch Mode Power Supply Board Outputs to the :

Y-SUS Board

Main Board

Adjustments

VS

VA

M5V

STBY 5V Microprocessor Circuits

17V Audio B+ Supply

12V Tuner B+ Circuits

5V Signal Processing Circuits

There are 2 adjustments located on the Power Supply Board VA and VS. The
5V VCC is pre-adjusted and fixed. All adjustments are made with relation to
Chassis Ground. Use “Full White Raster” 100 IRE

Drives the Display Panel’s Horizontal Electrodes

Primarily responsible for Display Panel Vertical Electrodes

Used to develop Bias Voltages on the Y-SUS,
X Drive, and Control Boards

VA

VS

RV502

RV901

34

November 2009 50PQ30 Plasma

Power Supply Circuit Layout

Power Supply Circuit Layout

P811

To Y-SUS

Main Bridge
Rectifier

123V Stby

382V Run

Fuse F801

4Amp/250V

160V Stby

382V Run

Fuse F302

1Amp/250V

Bridge

Rectifier

PFC

Circuit

Primary

Source

VS VR901

STBY 5V

5V, 12V

Source

VA Source

VS Source

17V Source

VA VR502

IC701

Sub Micon

Main Fuse

F101

10Amp/250V

35

AC Input

SC 101

P813

To MAIN

November 2009 50PQ30 Plasma

Power Supply Basic Operation

Power Supply Basic Operation

AC Voltage is supplied to the SMPS Board at Connector SC101 from the AC Input assembly. Standby 5V is developed from
160V source supply (which during run measures 380V measured from the primary fuse F302).
This supply is also used to generate all other voltages on the SMPS.

The STBY5V (standby) is B+ for the Controller (IC701) on the SMPS and output at P813 pins 11 and 23 then sent to the
Main board for Microprocessor (IC1) operation. AC Detect is generated on the SMPS, by rectifying a small sample of the
A/C Line at D102 and associated circuitry and routed to the Controller (IC701) where it outputs at pin 15 and sent to P813
pin 18 to the Main Board where it is sensed and monitored by the Main Microprocessor (IC1). The AC Det in this set works
differently than most. If AC Det is missing the Microprocessor will turn off the television in about 10 seconds after turn on.
This will happen each time turn on is attempted.
A new feature included on the side keypad is called a Main Power Switch which opens a ground allowing the “Key On” line
of P813 Pin 24 to go high, turning off the 5V STB line defeating the Micro Processor (IC1) on the Main Board and Remote
Control Operation.

When the Microprocessor (IC1) on the Main Board receives an “ON“ Command from either the Power button or the
Remote IR Signal, it outputs a high called RL ON at Pin 19 of P813. This command causes the RelaY-Drive Circuit to
close both Relays RL102 and RL103 bringing the PFC source up to full power by increasing the 160V standby to 380V
run which can be read measuring voltage at Fuse F302 and F801 from “Hot” Ground. At this time the run voltages 12V,
and +5V sources become active and are sent to the Main Board via P813 (12V at pins 5 and 6 and 5V at pins 9,10, and

12). The 5V detect line from the SMPS Board to the Main Board can be measured at pin 17 of P813. It is not used.
The next step is for the Microprocessor (IC1) on the Main Board to output a high on M5V ON Line to the SMPS at P813 Pin

21 which is sensed by the Controller (IC701) turning on the M5V line and output at P811 pins 9 and 10 to the
Y-SUS board P201 pins 9, 10. Then it is routed to the Control and Z-SUS boards.

Full Power occurs when the Microprocessor (IC1) on the Main Board brings the VS-ON line high at Pin 20 of P813 of the
SMPS Board. VS-ON is routed to the Controller (IC701) which turns on the 17V Audio, VA, and the VS supplies. VA and
VS output at P811 to the Y-SUS board. (VA pins 6 and 7 and VS pins 1 and 2). The 17V Audio supply outputs to the Main
board at P814 pins 1 and 2 and used for Audio processing and amplification.

AUTO GND Pin 22 of P813: This pin is grounded on the Main board. When it is grounded, the Controller IC701 works in
the normal mode, meaning it turns on the power supply via commands sent from the Main board. When this pin is floated
(opened), it pulls up and turns the Controller IC701 on in the Auto mode. In this state, the Controller turns on the power
supply in stages automatically. A load is necessary to perform a good test of the SMPS if the Main board is suspect.

36

November 2009 50PQ30 Plasma

50PQ30 POWER SUPPLY START UP SEQUENCE

50PQ30 POWER SUPPLY START UP SEQUENCE

1

Standby 5V will not

be output if the Main

Power Switch is off.

AC In

Stand

By 5V Reg

AC

Det.

Stand

By 5V

3

AC Det.

If missing,

the set
will turn
off in 10

seconds.

3.3V Reg

IC301

3

5V Mnt.

2

+5V
HDMI
EDID

AC-Det

6

Relay

5V

Mnt

2

6

Microprocessor

(BCM)

In Stand-By Primary side is 160V/123V
In Run (Relay On) Primary side is 386V

POWER SUPPLY

8

(SMPS)

5V/12V

Regulators

5

17V

RL

Reg

On

5V

12V

14

17V

M5V

On

7

On

5

8

17V Audio

PWR

On

Relay

On

5

IC1

Power On

12V Tuner
B+ stepped
down to 5V

Video
Processing

At point TV is in

Stand-By state.

It is Energy Star

Less than 1 Watt

3

Compliant.

M5-On

8

Vs/Va-On

13

4

Power On IR

13

On

13

Vs

MAIN

Board

M5V

Reg

Vs

Reg

Va

Reg

8

16

Vs

Va

15

Va

Y-SUS

Va

15

15

STBY 5V

Vs

M5V

16 8

Va

2

4

5VFG

10

M5V

17V

9

X PWB

Left

FG5V

Floating Gnd 5V

10

16

Vs

1615

Vs

16

Z-SUS

17V

11

12

3.3V

15 15

Va Va

Front IR

Board

Remote

Or Key

11

3.3V

X PWB

Center

Y DRIVE

Upper

Y DRIVE

Lower

CONTROL

11

9

17V M5V 3.3V

12

12

3.3V

X PWB

Right

Power Button

Off

On

12

37 Published November 2009 50PQ30 Plasma

Power Supply Va and Vs Adjustments

Power Supply Va and Vs Adjustments

Important: Use the Panel Label

Example Voltage Label

Va TP

P811

Pin 6 or 7

Vs TP

P811

Pin 1 or 2

Not this book for all voltage adjustments.

Use Full White Raster “White Wash”

Vs Adjust:
Place voltmeter on pin 1 or 2
of P811. Adjust VR901 until
the reading matches your
label.

38

Va Adjust:
Place voltmeter on pin 6 or 7
of P811. Adjust VR502 until
the reading matches your
label.

November 2009 50PQ30 Plasma

50PQ30 SMPS STATIC TEST UNDER LOAD

Using two 100 Watt light bulbs, attach one end to Vs and the other end to ground. Apply AC to SC101. If the light bulbs
turn on and VS is the correct voltage, allow the SMPS to run for several minutes to be sure it will operate under load. If
this test is successful and all other voltages are generated, you can be fairly assured the power supply is OK.
Note: To be 100% sure, you would need to read the current handling capabilities of each power supply listed on the silk
screen on the SMPS and place each supply voltage under the appropriate load.

or

4

100W

or

5

8

Gnd

100W

Vs

Pins

Check Pins 1 or 2

for Vs voltage

Check Pins 6 or 7

for Va voltage

You can even pre-

align the Vs and Va

voltage to the

panel’s label.
But you must

recheck when you

can get a white

Check Pins 1~4

For M5V

or

1 2

P811

raster.

P811

1

4A/250V

Hot Ground

C107

L102

L602L601

F801

C106

Hot Ground

RL101

RL103

STBY 123V

RUN 382V

F801

STBY 160V

RUN 382V

F302

1A/

250V

1

0

1

F

SC101

Hot Ground

10A/250V

AC In

T901

VR901

Vs

T301

F101

1,2) 17V
3,4) Gnd
5,6) 12V
7,8) Gnd
9,10,11) +5V

12) Stby 5V
13,14) Gnd

15) n/c

16) Gnd

17) 5V Det

18) AC Det

19) RL_On

20) VS_On

21) M5_On

22) Auto Gnd

23) Stby 5V

24) Key_On

VR502

Va

17V turns on

with Vs On

command

IC701

P813

1

2

23

24

Provided the Power Button is
closed, any time AC is applied to
the SMPS, STBY 5V and AC DET
should be present.

If AC Det is missing,
the TV will come on then shut
off within 10 Sec.
This will happen each time the
TV is turned on.

P813

Check Pins 11 or 23 for

5V SBY

Check Pin 18 for

AC Det (5V)

Check Pin 9,10,12 for

(+5V)

Check Pins 1 or 2 for

17V

Check Pins 5 or 6 for

12V

Note: This SMPS will run without a load, however if the Vs is not loaded,
the 17V may pulsate up and down.
It is always best to test the SMPS under a load using the 2 light bulbs.

39 Published November 2009 50PQ30 Plasma

Power Supply Static Test (Forcing on the SMPS in stages)

Power Supply Static Test (Forcing on the SMPS in stages)

WARNING: Remove AC when

adding or removing any

plug or resistor.

(A) Ground the Auto Ground (Pin 22) on P813.

(B) When AC Power is applied, Check AC_Det (Pin 18) and 5V Stand-By (Pins 12 and 23) are 5V.

P811 disconnected from

the Y-SUS or the SMPS.

P1006 disconnected from

the Main board.

Use the holes in the

connector P1006 side to

insert the resistor or

jumper leads.

(C) 100Ω ¼ watt resistor added from STBY 5V (Pins 12 or 23) (Note pins 9~11 are not on yet).

to RL_ON (Pin 19) closes relay RL101 and RL103 turning on the 5V and 12V Supplies.

(D) 100Ω ¼ watt resistor added from 5V (Pins 9 ~ 11) to M5 ON (Pin 21) brings the M5V (P811 pins 9,

10) line high.

(E) 100Ω ¼ watt resistor added from STBY 5V (Pins 9 ~ 11) to VS ON (Pin 20) brings the

• 17V (P813 pins 1 and 2) lines high.

• VA and VS (P811 pins 1 and 2 Vs and Pins 6 and 7 Va) lines high.

40

November 2009 50PQ30 Plasma

Connector P813 Identification, Voltages and Diode Check

Connector P813 Identification, Voltages and Diode Check

P813 CONNECTOR “SMPS" to “Main" P1006

Diode ModeRun STBYLabelPin

a

17V1

2.2V17.3V0V

a

17V2

GndGndGndGnd3

b

12V5

Open12V0V

b

12V6

GndGndGndGnd7

b

5V9

b

5V11

1.1V5V5V

1.1V5V5V

b

5V10

GndGndGndGnd13

GndGndGndGnd15

Open5V.15V5V Det17

Open3.73V0VRL On19

Open3.24V0VM5 ON21

22

Open5V5VStby 5V23

Auto Gnd

c

Key On24

Diode ModeRun STBYLabelPin

2.2V17.3V0V

GndGndGndGnd4

Open12V0V

GndGndGndGnd8

1.1V5V5V

1.13V5V5VStby 5V12

GndGndGndGnd14

Not UsedGndGndGnd16

Open5V5VAC Det18

Open3.2V0VVS On20

OpenGndGnd

Open0V0V

a

Note: The 17V turns on when the

VS On command arrives.

b

Note: The 5V/12V turns on when the

RL On command arrives.

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

41

c

Note: If the Key On line is 4.39V, the

Main Power Switch is open.
Stand-By 5V will shut off.

November 2009 50PQ30 Plasma

Connector SC101 and P811 Identification, Voltages and Diode Checkk

Connector SC101 and P811 Identification, Voltages and Diode Chec

SC101 AC INPUT

Standby Run Diode ModeConnector Pin Number

SC101 120VAC 120VAC Open

P811 CONNECTOR "Power Supply“ to Y-SUS “P201”

* Note: This voltage will vary in accordance with Panel Label

1 and 3

Diode ModeRun STBYLabelPin

Open*194V0VVs1, 2

n/cn/cn/cn/c3

Gnd0V0VGnd4, 5

Open*60V0VVa6, 7

Gnd0V0VGnd8

0.86V5V0VM5V9, 10

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

42

November 2009 50PQ30 Plasma

SUS BOARD SECTION

YY--SUS BOARD SECTION

(Overview)

(Overview)

Y-SUS Board develops the V-Scan drive signal to the Y-Drive boards.

This Section of the Presentation will cover troubleshooting the Y-SUS Board for the Single
Scan Plasma. Upon completion of the Section the technician will have a better
understanding of the operation of the circuit and will be able to locate voltage and
Diode mode test points needed for troubleshooting and alignments.

• Adjustments

• DC Voltage and Waveform Checks

• Diode Mode Measurements

Operating

Operating

SMPS Supplied VA

Y-SUS Developed -VY VR502

Floating Ground FG 5V

Voltages

Voltages

VS
M5V

VSC VR501
V SET UP VR601
V SET DN VR602
15V

FG 15V

VA supplies the Panel Vertical Electrodes (Routed to the Left X-Board)
VS Supplies the Panel Horizontal Electrodes (Also routed to the Z-SUS board)
5V Supplies Bias to Y-SUS (Then Routed to the Control board and Z-SUS board)

-VY Sets the Negative excursion of the Y-SUS Drive Waveform
VSC Set the amplitude of the complex waveform.
SET UP sets amplitude of the Top Ramp of the Drive Waveform
SET DOWN sets the Pitch of the Bottom Ramp of the Drive Waveform
To the Control Board then routed to the Z-SUS board

Used on the Y-Drive boards (Measured from Floating Gnd)
Used in the Development of the V-Scan signal (Measured from Floating Gnd)

43

November 2009 50PQ30 Plasma

SUS Block Diagram

YY--SUS Block Diagram

Distributes Vs and M5V

Power Supply Board - SMPS

Z-SUS Board

Left X Board

Simplified Block Diagram of

Y-Sustain Board

Distributes VA

Circuits generate

Y-Sustain Waveform

Receive M5V, Va, Vs

FETs amplify Y-Sustain

Waveform

Distributes Vs, Va and M5V

from SMPS

from M5V by DC/DC Converters

Distributes 15V

Distributes 15V and 5V

Control Board

Generates Vsc and -Vy

Also controls Set Up/Down

Generates Floating Ground

5V by DC/DC Converters

Logic signals needed to scan the panel

Y-Drive Boards

Receive Scan Waveform

Logic signals needed to generate drive waveform

44

November 2009 50PQ30 Plasma

Display Panel

SUS Board Layout

YY--SUS Board Layout

P209

Pins 8 ~12 Logic (Drive)

Signals to the Y-Drive

Upper board

Floating Gnd 5V

Pins 4 and 5

P204, P203, P205 and

P208 All Pins are

Floating Ground

P204

SET UP

VR 601

FS202 (Vs)

4A 250V

P206

P201

VS to and Error
Com from Z-SUS

VS, VA and M5V
Input from the
SMPS

P209, P204 and P203

Plugs into Y-Drive upper

P205, P208 and P207

Plugs into Y-Drive lower

P207 Pins 11 and 12

Y-Drive signal (V Scan)

Floating Gnd 5V

Pins 8 and 9

Pins 2 ~5 Logic (Drive)

Signals to the Y-Drive

Lower board

P203

P205

P208

P207

VSC ADJ

VR501

c

VSC TP

R202

P202

-VY TP
R201

V SET DN

VR 401

-VY ADJ
VR502

FS501 (17V)

4A/125V

P101

FS201 (Va)

10A/125V

FS201 (M5V)

10A/125V

M5V and 17V

Ribbon

Logic Signals from
the Control Board

P202

Va to Left X Board

Pins 5~7

45

November 2009 50PQ30 Plasma

VSC and --

VSC and

VY Adjustments

VY Adjustments

These are DC level Voltage Adjustments

VSC TP

R202

-

+

Voltage Reads

Positive

-

+

-Vy TP R201

VR502

VR501

Set should run for 15 minutes, this is the “Heat Run” mode.
Set screen to “White Wash”.
Adjust –Vy to Panel Label voltage (+/- 1V)
Adjust VSC to Panel Label voltage (+/- 1V)

46

Lower Center of board
Just below Heat Sinks

November 2009 50PQ30 Plasma

Y-Drive Upper Test Point

(Bottom of Board)

VR108

VR209

c Overall signal observed 4mS/div

There are several other test points on either the
Upper or Lower Y-Drive boards that can be used.
Basically any output pin on any of the FPC
to the panel are OK to use.

d Highlighted signal from waveform

above observed 400uS/div

e Highlighted signal from

Y-Drive Lower Test Point

(Top of Board)

NOTE: The Waveform Test Points are fragile. If by
accident the land is torn and the run lifted, make sure
there are no lines left to right in the screen picture.

waveforms above observed

100uS/div

47

80VRms

100uS

516V p/p

November 2009 50PQ30 Plasma

Observing (Capturing) the Y--

Observing (Capturing) the Y

Drive Signal for Set Up Adjustment

Drive Signal for Set Up Adjustment

Set must be in “WHITE WASH”

All other DC Voltage adjustments should have already been made.

Fig 1:

As an example of how to lock in to the Y-Drive Waveform.
Fig 1 shows the signal locked in at 4ms per/div.
Note the 2 blanking sections.
The signal for SET-UP is outlined within the Waveform

Fig 2:

At 2mSec per/division, the waveform to use for
SET-UP Is now becoming clear.
Now, the two blanking signal are still present.

Fig 3:

At 400us per/div. the signal for SET-UP is now easier to
recognize. It is outlined within the Waveform.
Remember, this is the first large signal to the right of blanking.

Outlined

Area

Area to

be adjusted

Area to

be adjusted

Blanking

Blanking

Blanking

Blanking

FIG1
4mS

FIG2
2mS

FIG3
400uS

Fig 4:

At 40uSec per/division, the adjustment for SET-UP
can be made.
It will make this adjustment easier if you use
the “Expanded” mode of your scope.

48

Area to

be adjusted

FIG4
40uS

November 2009 50PQ30 Plasma

Observing (Capturing) the Y--

Observing (Capturing) the Y

Drive Signal for Set Up Adjustment

Drive Signal for Set Up Adjustment

Set must be in “WHITE WASH”

All other DC Voltage adjustments should have already been made.

Fig 1:

As an example of how to lock in to the Y-Drive Waveform.
Fig 1 shows the signal locked in at 4ms per/div.
Note the 2 blanking sections.
The signal for SET-DN is outlined within the Waveform

Fig 2:

At 2mSec per/division, the waveform to use for
SET-DN is now becoming clear.
Now the two blanking signals are still present.

Fig 3:

At 400us per/div. the signal for SET-DN is now easier to
recognize. It is outlined within the Waveform.
Remember, this is the first large signal to the right of blanking.

Outlined

Area

Area to

be adjusted

Area to

be adjusted

Blanking

Blanking

Blanking

Blanking

FIG1
4mS

FIG2
2mS

FIG3
400uS

Fig 4:

At 20uSec per/division, the adjustment for
SET-DN can be made.
It will make this adjustment easier if you use the
“Expanded” mode of your scope.

49

Area to

be adjusted

FIG4
20uS

November 2009 50PQ30 Plasma

Set Up and Set Down Adjustments

Set Up and Set Down Adjustments

Observe the Picture while making these adjustments. Normally, they do not have to be done.

Y-Drive Test Point

Set must be in “WHITE WASH”

All other DC Voltage adjustments should have already been made.

ADJUSTMENT LOCATIONS:
Top Left and Center Right

50

SET-UP ADJUST:

1) Adjust VR601 and set the (A) portion of the
signal to match the waveform above. (150V ± 5V)

SET-DN ADJUST:

2) Adjust VR401 and set the (B) time of the
signal to match the waveform above. (100uSec 5uSec)

November 2009 50PQ30 Plasma

Set Up Adjustment Too High or Low

Set Up Adjustment Too High or Low

Set Up swing is Minimum 80V Max 200V

Ramp (SET UP) Too High (200V)

Full Counter Clock Wise

Panel Waveform Adjustment

The center begins to wash out and arc due to SET UP

Ramp (SET UP) Too Low (80V)

Full Clock Wise

Very little alteration to the picture, the wave form indicates a
distorted SET UP. The peek widens due to the SET UP
peeking too quickly.

51

November 2009 50PQ30 Plasma

Set Down Adjustment Too High or Low

Set Down Adjustment Too High or Low

Set Dn swing is Minimum 73uS Max 166uS+

(SET DN) Too High 166uSec

Full Clock Wise

100V off

the Floor

Floor

Panel Waveform Adjustment

NOTE: If Set DN too high, this set

may go excessive bright,

then shutdown.

If this happens, remove the LVDS

from Control board and make

necessary adjustments. Then

reconnect LVDS select White Wash

and adjust correctly.

All of the center washes out due to increased SET_DN time.

(SET DN) Too Low

Counter Clock Wise

The center begins to wash out and arc due to decreased
SET DN time.

52

November 2009 50PQ30 Plasma

SUS How to Check the Output FETs (1 of 2)

YY--SUS How to Check the Output FETs (1 of 2)

Name is printed on the components. Readings “In Circuit”.

45F122
Q34

RJP4584
Q32

K3667
*Q18

Q31

Shown: 0.6V

Reverse: 1.64V

Shown: 0.69V

Reverse: 0.67V

Shown: 0.59V~0.6V

Reverse: Open
*Reversed: 2.18V

Shown: 0.38V

Reverse: Open

Blk RedBlk Red BlkRed

Shown: 0.483V

Reverse: Open

Blk RedBlk Red

Shown: 0.5V

Reverse: Open

Blk RedBlk Red

Shown: 2.02V

Reverse: Open

Shown: 1.09V

Reverse: Open

BlkRed

Shown: Open
*Shown: 2.2V

Reverse: Open

BlkRed

RF2001
D31
D32
D33
D34
D36
D717

Blk Red

Shown: Shorted

Reverse: Shorted

0.3 Ohms

Blk Red

Shown: 0.37V~0.38V

Reverse: Open

53

November 2009 50PQ30 Plasma

Shown: 0.37~0.38V

Reverse: Open

BlkRed

SUS How to Check the Output FETs (2 of 2)

YY--SUS How to Check the Output FETs (2 of 2)

Name is printed on the components. Readings “In Circuit”.

I4F14229
Q16
Q17

30J124
Q11
Q12
Q13

RF020
D11

Shown: 0.876V

Reverse: 1.56V

Shown: 0.668V

Reverse: 0.6V

Shown: Shorted

Reverse: Shorted

(0.3 Ohm)

Shown: 0.46V

Reverse: Open

Blk RedBlk Red BlkRed

Shown: 0.392V

Reverse: Open

Blk RedBlk Red BlkRed

Shown: 0.392V

Reverse: Open

Shown: 1.95V

Reverse: Open

Shown: 0.998V

Reverse: Open

Shown: 0.392V

Reverse: Open

Blk RedBlk Red BlkRed

54

November 2009 50PQ30 Plasma

SUS Board P207 (Bottom Connector) Explained

YY--SUS Board P207 (Bottom Connector) Explained

TIP: Use P207 pins 1 or 2 or the Right Side of C213 to test

for Y Scan signal if the Y-Drive boards are removed

C213

FL201

11) V Scan

10) V Scan

9) n/c

8) 5V VF

P205

c

Y-Drive Lower

Board

Bottom Connector P207

P207

Y-SUS Board

7) 5V VF

6) Ground (F)

5) STB

4) OC1

3) DATA

2) OC2

1) Ground (F)

P207 Pins 1 and 2

Y Scan signal

400V p/p (No Y-Drives)

440V p/p (With Y-Drives)

FG5V measured from

Pins 7 or 8

Floating Gnd

Pins 1 or 6

P207 Pins 2, 3, 4, and 5 are

Logic (Drive) Signals to the

Y-Drive lower.

P209 carries the Y-Drive signals

to the upper via P108.

55

November 2009 50PQ30 Plasma

SUS P207 (Drive Output Plug) Diode Mode Testing

YY--SUS P207 (Drive Output Plug) Diode Mode Testing

P205 of the

Y-Drive

Lower Board

c

P207 of the

Y-SUS Board

C213

P207

Checking the Y--

Checking the Y

NOTE: Disconnected from the Y--

NOTE: Disconnected from the Y

SUS Board P207

SUS Board P207

Readings from Floating Ground (Pin 1)

RED LEAD

Blk Lead FG

Y-Drive Sig
Y-Drive Sig

Floating Gnd

Floating Gnd

12) V Scan

11) V Scan

10) n/c

9) 5V VF

8) 5V VF

7) Ground (F)

6) CLK

5) STB

4) OC1

3) DATA

2) OC2

1) Ground (F)

Open
Open
Open

1.9V

1.9V
0V

1.43V

1.43V

1.43V

1.53V

1.53V
0V

DRIVE boards

DRIVE boards

BLACK LEAD

Red Lead FG

Open
Open
Open

0.557V

0.557V
0V

0.66V

0.66V

0.68V

0.66V

0.68V
0V

Y-Drive Board should be

disconnected for this test.

56

Meter in the Diode Mode

November 2009 50PQ30 Plasma

SUS Board P209 (Top Connector) Explained

YY--SUS Board P209 (Top Connector) Explained

Y-Drive Upper

Board

P109

FL101

c

Y-SUS Board

P209

Top Connector P209

P209 Pins 7, 8, 9, and 10 are Logic Signals
from the Control board routed through the

Y-SUS to the Y-Drive upper.

Between the Y-Drive upper and lower is

P209, P108 which carries the Y-Drive (Scan)

signals from the lower to the upper.

11) Ground (F)

10) DATA

9) OC1

8) STB

7) CLK

6) Ground (F)

5) 5V VF

4) 5V Vf

3) Ground (F)

2) Ground (F)

1) Ground (F)

FG5V (+5V F) measured

from Pins 4 or 5 to

Floating Gnd

Pins 1~3, 6 or 11

57

November 2009 50PQ30 Plasma

SUS P209 Diode Mode Testing

YY--SUS P209 Diode Mode Testing

P109 of the

Y-Drive

Upper Board

c

P209 of the

Y-SUS Board

Checking the Y--

Checking the Y

NOTE: Disconnected from the Y--

NOTE: Disconnected from the Y

SUS Board P209

SUS Board P209

Readings from Floating Ground (Pin 1~3)

RED LEAD

Blk Lead FG

Floating Gnd

Floating Gnd

Floating Gnd
Floating Gnd
Floating Gnd

12) Ground (F)

11) DATA

10) OC1

9) STB

8) CLK

7) STB

6) Ground (F)

5) 5V VF

4) 5V VF

3) Ground (F)

2) Ground (F)

1) Ground (F)

0

1.53V

1.43V

1.53V

1.43V

1.43V
0V

1.94V

1.94V
0V
0V
0V

DRIVE boards

DRIVE boards

BLACK LEAD

Red Lead FG

0V

0.68V

0.66V

0.68V

0.66V

0.66V
0V

0.68V

0.68V
0V
0V
0V

P209

Y-Drive Board should be

disconnected for this test.

Meter in the Diode Mode

58

November 2009 50PQ30 Plasma

SUS P201 to SMPS P812 Plug Information

YY––SUS P201 to SMPS P812 Plug Information

Voltage and Diode Mode Measurement

P201 CONNECTOR "Y-SUS" to "Power Supply" P811

Diode ModeRun STBYLabelPin

Open*193V0VVs1

Open*193V0VVs2

NCNCNCNC3

GndGndGndGnd4

GndGndGndGnd5

Open*60V0VVa6

* Note: This voltage will vary in accordance with Panel Label

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

59

November 2009 50PQ30 Plasma

Open*60V0VVa7

GndGndGndGnd8

0.86V5V0VM5V9

0.86V5V0VM5V10

SUS P202 to X Drive P122 Plug Information

YY--SUS P202 to X Drive P122 Plug Information

Voltage and Diode Mode Measurements for the Y-SUS Board

P202 CONNECTOR "Y-SUS" to "X-Drive” Left P122

Diode ModeRun STBYLabelPin

GndGndGndGnd1

GndGndGndGnd2

GndGndGndGnd3

ncncncnc4

Open*60V0VVA5

Open*60V0VVA6

* Note: This voltage will vary in accordance with Panel Label

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

60

November 2009 50PQ30 Plasma

Open*60V0VVA7

SUS P206 to Z Drive P101 Plug Information

YY--SUS P206 to Z Drive P101 Plug Information

Voltage and Diode Mode Measurements for the Y-SUS Board

P206 Connector Y-SUS to Z Drive P101 Plug Information

Diode ModeRun STBYLabelPin

0.86V5V0VM5V1, 2

GndGndGndGnd3~6

ncncncnc7

Gnd*89V0VEr Com8, 9

ncncncnc10

Open*193V0VVS11, 12

* Note: This voltage will vary in accordance with Panel Label

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

61

November 2009 50PQ30 Plasma

P101 Y--

P101 Y

SUS 15V and 5V to Control board P111 Information

SUS 15V and 5V to Control board P111 Information

Voltage Measurements for the Y-SUS Board

Y-SUS Board B+ checks for the P101 connector.

FS201

5V to run the Control Board.

Leaves the Control Board on P101

pins 4~7.

Can also be checked at J843 M5V TP.

Run: 5VStandby: 0V

Diode Check: 0.86V

FS501 and 15V Test Point

15V to run the Z-SUS Board.

Routed out P101 to the Control

Board.

Leaves the Control Board on

P101 pins 11 and 12.

Can also be checked at J642 15V TP.

Location: Just below P201

Location

Run: 15VStandby: 0V

Diode Check: Open

Location: Bottom Center Right

62

November 2009 50PQ30 Plasma

SUS Floating Ground (15V) and (5V) Checks

YY--SUS Floating Ground (15V) and (5V) Checks

Voltage Measurements for the Y-SUS Board

Floating Ground checks must be made from Floating
Ground. Use any pin on P204, P203, P205 or P208.

FG5V Test Point

Floating Ground referenced 5V. Used for low

voltage signal processing on the Y-Drive

board. Leaves the Y-SUS board on P207 pins 8

and 9. AND P209 pins 5 and 5.

Checked at J795 (+5V (F) Test Point.

Run: 5VStandby: 0V Diode Check: 1.94V

FG15V Test Point

FG15V to develop the Y-Drive signal.

Location

Location: Bottom Left

Checked at J644 (+15V (F) Test Point.

Run: 15.2VStandby: 0V Diode Check: 1.5V

Floating Ground J643

Location: Bottom Center of the

two large black heat sinks.

63

November 2009 50PQ30 Plasma

SUS P101 to Control P111 Plug Information (Tip)

YY--SUS P101 to Control P111 Plug Information (Tip)

“Y-SUS" P101 CONNECTOR to “Control board" P111

(30 Pin Connector)

See next page

For Voltage readings

Pin 1

Only Odd pins

are easily

accessible with

Ribbon Cable

inserted

With Ribbon Cable Without Ribbon Cable

TIP:

For Voltage

readings,

Check Odd pins on

Y-SUS board

Check Even pins on

Control board

P101

Connector Label

Pin 29

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

64

November 2009 50PQ30 Plasma

SUS P101 to Control P111 Plug Voltage Checks

YY--SUS P101 to Control P111 Plug Voltage Checks

“Y-SUS" P101 CONNECTOR to “Control" P111

TIP: For Voltage readings,

Check Odd pins on Y-SUS board

Check Even pins on Control board

Run LabelPin

Diode

Mode

1.37V17.04V15V1

1.37V17.04V15V3

2V5V5V5

2V5V5V7

1.30.1VCTRL_OE9

1.78V0VGnd (Y Enable)11

GndGndGnd13

0.9V1.99VDelta VY Det15

0.9V0.5VSet On17

0.9V1.29VDet Level Sel19

0.9V0.17VSlope Rate Sel21

0.9V0.114VER DN23

Run LabelPin

Diode
Mode

1.37V17.04V15V2

2V4.95V5V4

2V4.95V5V6

GndGndGnd8

GndGndOE10

GndGndGnd12

0.9V1.82VOC214

0.9V0VData16

0.9V1.44VOC118

0.9V1.45VSTB20

0.9V0.6VCLK22

0.9V024VSET UP24

0.9V2.6VSUS DN25

0.9V0.14VER UP27

0.9V0.11VYSUS UP29

There are No Stand By Voltages on this Connector

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

65

November 2009 50PQ30 Plasma

0.9V3.12VRamp Slope OPT 126

0.9V1.1VBlocking28

GndGndGnd30

DRIVE BOARD SECTION

YY--DRIVE BOARD SECTION

Y-Drive Boards work as a path supplying the Sustain and Reset waveforms which are

made in the Y-Sustain board and sent to the Panel through Scan Driver IC’s.

The Y-Drive Boards supply a waveform which selects the horizontal electrodes

sequentially starting at the top and scanning down the panel.

* 50PQ30 uses 8 Driver ICs on 2 Y-Drive Boards

Drive Explained)

(Y(Y--Drive Explained)

TIP:
See additional Service Tips
beginning on page 131.

Y-Drive (V Scan) WAVEFORM

Y-Drive WAVEFORM TEST POINTS

Warning: To facilitate scope attachment, solder a small wire (Stand Off) at this point.
Be very careful, these are fragile and can peal off with excessive heat or stress.

66

November 2009 50PQ30 Plasma

Upper Y--

Upper Y

Drive Layout

Drive Layout

TIP:
The connectors
to the Y-SUS
board are very
easy to
misalign and
plugged in.
The Connector
will be below
the actual pins
on the Y-SUS.
Look carefully.
See Tip section
page 133-134.

FG5V Volts from the
Y-SUS board and Logic
Signals from the Control
through the Y-SUS
board are supplied to
the Upper Y-Drive
Board on Connector
P109.

Y-Drive signal (VSC)
from the Y-SUS board
through the Y-Drive
lower is supplied to the
Upper Y-Drive Board on
Connector P108.

PANEL

SIDE

Y-SUS

SIDE

67

November 2009 50PQ30 Plasma

Upper Y--

Upper Y

P109 Pins 7, 8, 9, and 10 are Logic Signals
from the Control board routed through the

Between the Y-Drive upper and lower is

P108/P209 which carries the Y-Drive (Scan)

FG5V (+5V F) measured

from Pins 4 or 5 to

Floating Gnd

Pins 1~3, 6 or 11

Drive P109 (Top Connector) Explained

Drive P109 (Top Connector) Explained

Y-SUS to the Y-Drive upper.

signal from the lower to the upper.

11) Ground (F)

10) DATA

9) OC1

8) STB

7) CLK

6) Ground (F)

5) 5V VF

4) 5V VF

3) Ground (F)

2) Ground (F)

1) Ground (F)

Y-Drive Upper

Board

Y-SUS

Board

c

FL101

68

P109

Top Connector P109

November 2009 50PQ30 Plasma

P209

Upper Y--

Upper Y

Checking the Upper Y--

Checking the Upper Y

NOTE: Disconnected from the Y--

NOTE: Disconnected from the Y

All Readings from Floating Ground (Pin 1~3, 6 or 12)

Drive Upper P109 Diode Mode Testing

Drive Upper P109 Diode Mode Testing

Drive BOARD P109

Drive BOARD P109

SUS Board

SUS Board

TIP: This test will check “All”

scan buffers Low Voltage input

side on the Y-Drive Upper board.

Y-Drive

Upper
Board

Y-SUS

Board

Floating Gnd

Floating Gnd

Floating Gnd
Floating Gnd
Floating Gnd

12) Ground (F)

11) OC2

10) DATA

9) OC1

8) STB

7) CLK

6) Ground (F)

5) 5V VF

4) 5V VF

3) Ground (F)

2) Ground (F)

1) Ground (F)

Meter in the Diode Mode

RED LEAD

Blk Lead FG

0V
Open
Open
Open
Open
Open
0V

1.94V

1.94V
0V
0V
0V

BLACK LEAD

Red Lead FG

0V

0.52V

0.67V

0.54V

0.54V

0.54V
0V

0.43V

0.43V
0V
0V
0V

FL101

c

P109

Y-SUS Board should be

disconnected for this test.

P209

69

November 2009 50PQ30 Plasma

Drive Lower Layout

YY--Drive Lower Layout

PANEL

SIDE

TIP:
The connectors
to the Y-SUS
board are very
easy to
misalign and
plugged in.
The Connector
will be below
the actual pins
on the Y-SUS.
Look carefully.
See Tip section
page 133-134.

Y-SUS

SIDE

FG5V Volts from the
Y-SUS board and Logic
Signals from the Control
through the Y-SUS
board are supplied to
the Lower Y-Drive
Board on connector
P205.

Y-Drive signal (VSC)
from the Y-SUS board is
supplied to the Lower
Y-Drive Board on
connector P205 pins 11
and 12. Then the Lower
Y-Drive delivers the
V-Scan signal to the
upper via P209 to P108.

70

November 2009 50PQ30 Plasma

Drive Lower P205 (Bottom Connector) Explained

YY--Drive Lower P205 (Bottom Connector) Explained

TIP: Use P207 pins 1 or 2 or the Right Side of C213 to test

for Y Scan signal if the Y-Drive boards are removed

Blanking

Reset

FL201

c

P205

Y-Drive Board

P207

C213

Y-SUS Board

11) V Scan

10) V Scan

9) n/c

8) 5V VF

7) 5V VF

6) Ground (F)

5) STB

4) OC1

3) DATA

2) OC2

1) Ground (F)

P207 Pins 1 and 2

Y Scan signal

516V p/p

FG5V measured from

Pins 7 or 8

Floating Gnd

Pins 1 or 6

P207 Pins 2, 3, 4, and 5 are

Logic (Drive) Signals to the

Y-Drive lower P209 carries the

Y-Drive signals to the Upper

Y-Drive board

Sustain

Bottom Connector P205

71

November 2009 50PQ30 Plasma

Lower Y--

Lower Y

Drive P205 Diode Mode Testing

Drive P205 Diode Mode Testing

TIP: This test will check “All”

scan buffers Low Voltage input

side on the Y-Drive lower board.

Checking the Lower Y--

Checking the Lower Y

NOTE: Disconnected from the Y--

NOTE: Disconnected from the Y

All Readings from Floating Ground (Pin 1 or 7)

Y-Drive Sig
Y-Drive Sig

Floating Gnd

Floating Gnd

12) V Scan

11) V Scan

10) n/c

9) 5V VF

8) 5V VF

7) Ground (F)

6) CLK

5) STB

4) OC1

3) DATA

2) OC2

1) Ground (F)

Drive Board P205

Drive Board P205

RED LEAD

Blk Lead FG

Open
Open
Open
Open
Open
0V
Open
Open
Open
Open
Open
Open

SUS board

SUS board

BLACK LEAD

Red Lead FG

1.0V

1.0V
Open

0.425V

0.425V
0V

0.538V

0.538V

0.538V
Open

0.521V
0V

P205 of the

Y-DRIVE Lower

FL201

P205

c

P207 of the

Y-SUS Board

C213

P207

Meter in the Diode Mode

72

Y-SUS Board should be

disconnected for this test.

November 2009 50PQ30 Plasma

Drive P108 and P209 Voltage and Diode Mode Check

YY--Drive P108 and P209 Voltage and Diode Mode Check

TIP: This test will check “All” scan buffers Input side on the board.

Voltage and Diode Mode Measurements (Taken from Floating Ground)

P108 CONNECTOR “Y-Drive Upper to Lower”

Y-Drive Upper

P108

P209

Y-Drive Lower

Run LabelPin

P209 CONNECTOR “Y-Drive Lower to Upper”

Run LabelPin

Diode Mode

Diode Mode

Red Lead

0V0VFGnd1

0V0VFGnd2

Open*134VY Scan3

Open*134VY Scan4

Open*134VY Scan5

Red Lead

0V0VFGnd1

0V0VFGnd2

Open*134VY Scan3

Diode Mode

Black Lead

0V

0V

1.2V

1.2V

1.2V

Diode Mode

Black Lead

0V

0V

1.0V

Diode Mode Readings taken with all
connectors Disconnected. DVM in Diode
Mode.

Open*134VY Scan4

Open*134VY Scan5

Note: This voltage will vary in accordance with Panel Label

73

November 2009 50PQ30 Plasma

1.0V

1.0V

Removing (Panel) Flexible Ribbon Cables from Y--

Removing (Panel) Flexible Ribbon Cables from Y

Drive Upper or Lower

Drive Upper or Lower

Flexible Ribbon Cables shown are from a different model, but pro

Flexible Ribbon Cables shown are from a different model, but pro

To remove the Ribbon Cable from the connector first carefully lift the Locking Tab from

the back and tilt it forward ( lift from under the tab as shown in Fig 1).
The locking tab must be standing straight up as shown in Fig 2.
Lift up the entire Ribbon Cable gently to release the Tabs on each end. (See Fig 3)
Gently slide the Ribbon Cable free from the connector.

Be sure ribbon tab is released

By lifting the ribbon up slightly,

Gently Pry

Up Here

Locking tab in

upright position

cess is the same.

cess is the same.

before removing ribbon.

Fig 1

To reinstall the Ribbon Cable, carefully slide it back into the slot see ( Fig 3 ), be sure the Tab is seated
securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1).

Fig 2

74

November 2009 50PQ30 Plasma

Fig 3

Incorrectly Seated Y--

Incorrectly Seated Y

The Ribbon Cable is clearly improperly seated
into the connector. You can tell by observing the
line of the connector compared to the FPC, they
should be parallel.

The Locking Tab will offer a greater resistance to
closing in the case.

Note the cable is crooked. In this case the Tab on
the Ribbon cable was improperly seated at the

Drive Flexible Ribbon Cables

Drive Flexible Ribbon Cables

top. This can cause bars, lines, intermittent lines
abnormalities in the picture.

Remove the ribbon cable and re-seat it correctly.

75

November 2009 50PQ30 Plasma

Drive Buffer Troubleshooting

YY--Drive Buffer Troubleshooting

YOU CAN CHECK ALL 8 BUFFER ICs USING THIS PROCEDURE

YOU CAN CHECK ALL 8 BUFFER ICs USING THIS PROCEDURE

BACK SIDE OF Y-DRIVE BOARD

BUFFER IC FLOATING GROUND (FGnd)

128

Output

Pins

Using the “Diode Test” on the DVM, check
the pins for shorts or abnormal loads.

RED LEAD ON

BUFFER IC FGnd

Indicated by white outline

BLACK LEAD ON

BLACK LEAD ON “ANY”

OUTPUT LUG.

READING 0.798 V

RED LEAD ON “ANY”

42 43 43

• Any of these output lugs can be tested.

• Look for shorts indicating a defective Buffer IC

BUFFER IC FGnd

Indicated by white outline

128 Output Pins per/FPC (Flexible Printed Circuit)

6 Ribbon cables (Horizontal Electrodes)

768 Total Horizontal Electrodes controlling Vertical resolution

76

OUTPUT LUG.

READING “OPEN”

November 2009 50PQ30 Plasma

SUS SECTION

ZZ--SUS SECTION

This Section of the Presentation will cover troubleshooting the ZZ--

This Section of the Presentation will cover troubleshooting the

Upon completion of this section the Technician will have a bette

Upon completion of this section the Technician will have a bette

able to locate voltage and diode mode test points needed for tro

able to locate voltage and diode mode test points needed for tro

Locations

Locations

• DC Voltage and Waveform Test Points

• Z BIAS Alignment

• Diode Mode Test Points

Operating Voltages

Operating Voltages

Power Supply Supplied VS

SUS Board Assembly.

SUS Board Assembly.

r understanding of the circuit and be

r understanding of the circuit and be

ubleshooting and all alignments.

ubleshooting and all alignments.

M5V

Control Board Supplied

But developed on the Y-SUS 17V

Developed on Z-SUS Z Bias

77

November 2009 50PQ30 Plasma

SUS Block Diagram

ZZ--SUS Block Diagram

POWER SUPPLY Board

M5V and VS

Control Board

Receives

Logic

Signals

17V

Circuits generate erase,

sustain waveforms

NO IPMs

Y-SUS Board

5V, 17V

M5V and VS

Z-SUS board receives VS and

M5V from Y-SUS and 17V from

the Control board

Generates Z Bias 100V

Via 3 FPC

Flexible

Printed

Circuits

PDP

FET Makes Drive waveform

Simplified Block Diagram of Z-SUStain Board

78

November 2009 50PQ30 Plasma

Z-SUB

Display

Panel

SUS SECTION

ZZ--SUS SECTION

FS100

M5V

10A/125V

P101

VS and M5V

Input from

the Y-SUS

P101

FS102

VS

4A/250V

No IPMs

Z-Bias TP

Top of R271 or R272

P104

FPC

Z-Bias
VR200

No IPMs

Logic Signals from

the Control board

Also +15V generated

on the Y-SUS and routed

through the Control

board.

P100

Z-SUS

Waveform

Development

ICs

Z-SUS

Output

ICs

Z-SUS
Waveform
Test Point

J27

P105

FPC

To Z-SUB

P103

79

November 2009 50PQ30 Plasma

SUS Waveform

ZZ--SUS Waveform

The Z-SUS (in combination with the Y-SUS) generates a
SUSTAIN Signal and an ERASE PULSE for generating
SUSTAIN and DISCHARGE in the Panel.

This waveform is supplied to the panel through FPC (Flexible
Printed Circuit) P104, P105 and also P103 to the Z-SUB which
connects to the panel via P302.

TIP: The Z-Bias (VZB) Adjustment is a

DC level adjustment.

This is only to show the effects

of Z-Bias on the waveform.

Z Drive
Waveform

(Vzb) Z Bias VR200

Vzb voltage

+

1V80 V

-

400uS/div50V/div

This Waveform is just for reference to observe the effects of Zbz adjustment

80

November 2009 50PQ30 Plasma

Oscilloscope Connection Point.

J27 to check Z Output waveform.

Right Hand side Center.

VZB

VZB

(Z--

Bias) Adjustment

(Z

Bias) Adjustment

Read the Label on the back of the upper left hand

side of the panel when adjusting VR200.

Top of Z-SUS

Board

VZB (Z Bias)

VR200

VZB (Z-Bias) TP Top

Side R271 or R272

Z Bias

Chassis Ground or

the Top of C239

or J125

Note: You can also

measure across C239

for the VZB (Zbias)

adjustment.

Set should run for 15 minutes, this is the “Heat Run” mode.
Set screen to “White Wash” mode or 100 IRE White input.

Adjust VZ (Z-Bias) to Panel Label (± 1V)

81

Measured from Chassis Ground

November 2009 50PQ30 Plasma

Connector P101 to Y--

Connector P101 to Y

Voltage and Diode Mode Measurements

P101 CONNECTOR “Z-SUS" to “Y-SUS" P206

SUS P206 Voltages and Diode Checks

SUS P206 Voltages and Diode Checks

Diode ModeRun LabelPin

Open5VM5V1, 2

GndGndGnd3~6

n/cn/cn/c7

Open*94.9VER COM8, 9

Openn/cn/c10

Open*193VVS11, 12

* Note: This voltage will vary in accordance with Panel Label

There are no Stand-By voltages on this connector

Location: Top Left

Pin 1

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

82

November 2009 50PQ30 Plasma

Connector P100 to Control P101 Voltages and Diode Checks

Connector P100 to Control P101 Voltages and Diode Checks

Voltage and Diode Mode Measurements

P100 CONNECTOR “Z-SUS" to “Control" P101

Diode ModeRun LabelPin

GndGndGnd1

Open0.05VZ Enable2

Open1.8VZ Bias3

Open1.7VZ Ramp4

GndGndGnd5

Open0.3VZ ER UP6

Open0.4VZ ER DN7

Open0.2VZ-SUS UP8

Open0.8VZ-SUS DN9

GndGndGnd10

Open17V+15V11

Open17V+15V12

Location: Bottom
Left hand side

Pin 1

There are no Stand-By voltages on this connector

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

83

November 2009 50PQ30 Plasma

SUS How to Check the Output FETs 1 of 2

ZZ--SUS How to Check the Output FETs 1 of 2

Name is printed on the components. Readings “In Circuit”.

20NF20
Q311

33N25T
Q312

RF2001

D301
D302
D303
D304

D305
D306
D311
D312

Shown: Short

Reverse: Short

0.1 Ohms

Shown: 0.678V

Reverse: Open

Shown: Short

Reverse: Short

0.1 Ohms

Shown: Open

Reverse: Open

Blk RedBlk Red Blk Red

Shown: Open

Reverse: Open

Blk RedBlk Red Blk Red

Shown: 0.36V

Reverse: Open

Shown: 0.52V

Reverse: Open

Shown: 0.52V

Reverse: Open

Shown: 0.36V

Reverse: Open

Blk RedBlk Red Blk Red

84

November 2009 50PQ30 Plasma

SUS How to Check the Output FETs 2 of 2

ZZ--SUS How to Check the Output FETs 2 of 2

Name is printed on the components. Readings “In Circuit”.

45F122

A

Q302

A

Q304

B

Q313

B

Q314

5N50C
Q321

Q315
Q317
Q318

Shown: 1.496V

A

0.6V

Reverse: 0.782V

Shown: 1.22V

Reverse: Open

Shown: Open
Reverse: 1.14V

B

0.95V

Blk RedBlk Red Blk Red

Shown: Open

Reverse: Open

Blk RedBlk Red Blk Red

Shown: 0.364V

A

0.49V

Reverse: Open

Shown: 0.536V

Reverse: Open

85

November 2009 50PQ30 Plasma

SUS How to Check the Z--

ZZ--SUS How to Check the Z

Jump STBY

5V to any 5V

location

SUS if the Y--

SUS if the Y

SUS Has Failed

SUS Has Failed

Jump M5V to

Pin 1 or 1

Jump 17V to

any FS101

Jump Vs to

Pin 11 or 12

All this assumes

the Power

supply and

Control board

are working

correctly.

86

Leave P101 to

P100 Connected

November 2009 50PQ30 Plasma

When you apply AC to the

SMPS, check the Z-Bias

waveform TP for 100V P/P

signal

CONTROL BOARD SECTION

CONTROL BOARD SECTION

This Section of the Presentation will cover troubleshooting the Control Board Assembly. Upon
completion of this section the Technician will have a better understanding of the circuit and be
able to locate voltage and diode mode test points needed for troubleshooting.

• DC Voltage and Waveform Test Points

• Diode Mode Test Points

Signals

Signals

Control Board Generated Y-SUS and Z-SUS Drive Signals (Sustain)

Main Board Supplied Panel Control and LVDS Signals

X Board Drive Signals (RGB Address)

Operating Voltages

Operating Voltages

Y-SUS Supplied

Developed on the Control Board

+5V (M5V) Developed on the SMPS
+17V (Routed to the Z-SUS)

+1.8V for internal use
+3.3V for internal use
+3.3V for the X-Boars (TCPs)

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November 2009 50PQ30 Plasma

Control Board Component Identification

Control Board Component Identification

Waveform Generation Software

Download Connection

M5V

FL111
FL112

17V

Pins 1~3

M5V

Pins 4~7

Pin 1

5V

Gnd

P111

To P101

Y-SUS

IC241

1) 0.8V

2) Gnd

3) 4.96V

4) 5.74V

5) 4.91V

6) Gnd

7) Gnd

8) 4.95V

3.3V

IC221

IC231

5V

IC241

n/c

P131

Gnd

EEPROM

IC101

P161

3.3V

To P1003 Main

P121 LVDS

Pin 1

X101

Crystal 25Meg

IC201

MCM

AUTO GEN TEST

PATTERN

4.8V

1.8V

IC211

DRAM

IC251

Vs DA

3.2V

Temp LED

P162

Gnd

D201

L

VD

S

C

P101

a

b

l

Pin 1

3.3V

IC141

1) 3.3V

2) 0V

3) 3.3V

4) Gnd

5) 3.3V

6) 0V

7) 3.3V

8) 0V

17V

Pins 11, 12

e

To P100

Z-SUS

To X Drive Cent

Part Number

Label

88

To X Drive Cent

November 2009 50PQ30 Plasma

50PQ30 CONTROL BOARD (Troubleshooting Tips)

50PQ30 CONTROL BOARD (Troubleshooting Tips)

Unplug all connectors. Jump 5V from SMPS (P813 pins 9~12) to pin 1 of IC211. Observe LED. If it blinks, most likely
Control PWB is OK. FL111 and FL112 should be checked.

Disconnect P201 from the Y SUS Board and connect a Jumper from Pin 10 of P812 (M5V) to Pin 10 P201 (5V). The 5V will
be routed to the Control Board via FS201, Ribbon Cable P101 on the Y SUS Board to P111 on the Control board. Then
through FL111 and FL112 to all regulators on the Control Board. For Control Board operation verification, watch D201 for
blinking.

Note: IC221

(3.3V Regulator)

routed out P162

(56~60)to X-PWBs

M5V

GndGnd

M5V

Pin 1~3 (17V)

Pin 4~7 (M5V)

P111 Ribbon Cable

Data and Clocks to

Y-SUS and Y-Drive

IC221

Pin 1 (Gnd)
Pin 2 (3.3V)
Pin 3 (4.95V)

FL111 FL112

M5V Fuses

(EMI Filters)

Used for ROM Updates

No Connection

P131

IC221

2

CONTROL BOARD

IC231

Pin 1 (Gnd)
Pin 2 (3.3V)
Pin 3 (4.95V)

P111

LVDS

P121

IC201

* If the complaint is no video and if shorting the
two points (AutoGen) causes video to appear
suspect the Main board or LVDS cable.

IC141

X101

25 Meg

IC211

IC141

Pin 1 (5V)
Pin 2 (1.8V)
Pin 3 (Gnd)

Pin 1 (3.3V)
Pin 2 (0V)
Pin 3 (3.3V)
Pin 4 (Gnd)
Pin 5 (3.3V)
Pin 6 (0V)
Pin 7 (3.3V)

MCM

Auto Gen

P101

Pin 8 (0V)

P101

Pin 1 (3.3V)
Pin 2 (3.3V)
Pin 3 (Gnd)
Pin 4 (3.3V)

IC241

Pin 8 (3.3V)

IC241

P161 P162

Pin 7 (3.3V)
Pin 6 (Gnd)
Pin 5 (3.3V)

To Left X Board To Right X Board

With the unit on, if D201 does not blink
on/off, check 5V supply.
If present replace the Control PCB

D201

From Pin 2 IC221 (3.3V)

P162 Pins 56~60

Short across the two points labeled Auto Gen

to generate a test pattern.

(LVDS Cable Must Be Removed)

To Z-SUS

Pin 11/12 (17V)

89

Published November 2009 50PQ30 Plasma

Control Board Additional Troubleshooting Tips

Control Board Additional Troubleshooting Tips

For quick Control board test. (All connectors Disconnected).

Jump 5V from Power
Supply to IC201 Pin 3.
(Bottom Pin)
If the LED blinks,
Pretty much
guaranteed,
Control Board is OK.

Confirm B+ to Control the
Control Board
VS_DA
3V ~ 3.3V
(Note, this TP can also be
Used as an External Trigger
For scope when locking onto
the Y-Drive signal).

Quick observation

When the Television has a problem related to;

1) Shutdown caused by Main Board.

2) No Video (No Picture) Sound OK.
This can be checked by the following.
(1) Disconnect the Main board from all connectors. Apply AC power.
Since P813 is not connected to the SMPS, the set will come on.
Short the two pins on the Auto Test Pattern lands.
If there is a picture of cycling colors and patters, the Y-SUS, Y-Drive, Z-SUS, Power Supply, Control board,
X-Boards, TCPs and Panel are all OK.
Use the same test for problem (2) above to tell if the No Video is caused by the Main board or failed LVDS cable.

90

November 2009 50PQ30 Plasma

Of LED blinking
Tell if the Control
Board is running.

Checking the Crystal X101““

Checking the Crystal X101

Clock””

Clock

on the Control Board

on the Control Board

X101

CONTROL

BOARD

CRYSTAL

LOCATION

DC Voltage Check

1.5V ~ 1.8V

Check the output of the Oscillator (Crystal).
The frequency of the sine wave is 25 MHZ.
Missing this clock signal will halt operation of
the panel drive signals.

Osc. Check: 25Mhz

91

November 2009 50PQ30 Plasma

Control Board LVDS Signals

Control Board LVDS Signals

Pins are close together,
Use Main board side.

On Main Board

Connector P1002 Configuration

- indicates signal pins.

2

4

6

8

10

12

14

16

1

3

5

7

9

11

13

15

LVDS Cable
P121 on Control board shown.
Press two outside tabs inward
to release.

LVDS

Video Signals from the Main Board to the Control Board are referred to as Low
Voltage Differential Signals or LVDS. Their presence can be confirmed with the
Oscilloscope by monitoring the LVDS signals with no input signal selected while
pressing the Menu Button “on” and “off” with the Remote Control or Keypad.
Loss of these Signals would confirm the failure is on the Main Board!

Pin c

Menu Off

Menu ON

18

20

22

24

26

17

19

21

23

25

Main board P1002

Example of Normal Signals measured at 200mv/cm at 5µs/cm.

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November 2009 50PQ30 Plasma

Control Board Signal (Simplified Block Diagram)

Control Board Signal (Simplified Block Diagram)

The Control Board supplies Video Signals to the TCP (Tape Carrier Package) ICs.

If there is a bar defect on the screen, it could be a Control Board problem.

Control Board to X Board

Address Signal Flow

This Picture shows Signal Flow Distribution to help determine the

failure depending on where the it shows on the screen.

MCM

EEPROM

To Center X-Board

IC201

DRAM

Basic Diagram of Control Board

IC201

CONTROL BOARD

MCM

Resistor Array

16 bit words

2 Buffer
Outputs
per TCP

128 Lines per Buffer

256 Lines output Total

X-DRIVE BOARD

There are 16 total TCPs.

4096 Vertical Electrodes

1365 Total Pixels (H)

PANEL

93

November 2009 50PQ30 Plasma

Removing the LVDS Cable from the Control Board

Removing the LVDS Cable from the Control Board

The LVDS Cable has two “Interlocks” that must be disengaged to remove the LVDS Cable.

To Disengage, press the two Locking Tabs Inward and pull the plug out.

Press

Inward

94

Press

Inward

November 2009 50PQ30 Plasma

Control Board Connector P111 to Y--

Control Board Connector P111 to Y

P111 These pins are very close together. When taking Voltage measurements use Caution.

FL111 and FL112 +5V Fuse

SUS P101 Voltages and Diode Mode Checks

SUS P101 Voltages and Diode Mode Checks

Pin c

Pins 1, and 2
Receive +15V from the Y-SUS.

Pins 3, 4, 5, 6, and 7
Receive +5V from the Y-SUS.

Pins 9, 10, 11 and 30
Are Ground

All the rest are delivering
Y-SUS Waveform development and
Y-Drive logic signals to the Y-SUS
Board (Y-Drive logic signals are simply
routed right through the Y-SUS to the
Y-Drive boards).

Odd
Pins

The +17V is not used by the
Control board, it is routed to the
Z-SUS leaving on P101 Pins 11
and 12.

Tip: For Checking Voltages,
Check the Odd pins on the Control
board and the Even pins on the
Y-SUS board.

Even

Pins

95

November 2009 50PQ30 Plasma

Control Board Connector P111 Silkscreen Can Be Misleading

Control Board Connector P111 Silkscreen Can Be Misleading

P111 The silkscreen indicates
that taking voltage or signal
readings on P111 show Odd
pins on the Left and Even pins
on the Right.

Odd

Pins

Even

Pins

P111 Example:

If there were room

for Labeling

Silkscreen Label:

The pin numbers are

correct. Remember
Odd pins on the left

and even pins are on

the right.

96

Silkscreen Label:

The pin numbers are correct.

Remember Odd pins on the left

and even pins are on the right.

November 2009 50PQ30 Plasma

Control P111 to Y--

Control P111 to Y

P111 CONNECTOR “Control Board" to “Y-SUS" P101

SUS P101 Plug Information

SUS P101 Plug Information

Tip: For Checking Voltages, Check the
Odd pins on the Control board and the
Even pins on the Y-SUS board.

Diode ModeRun LabelPin

Open17.04V+15V01

Open17.04V+15V03

0.97V5V+5V05

0.97V5V+5V07

Open0.1VGND09

1.76V0VY_ENABLE11

GndGndGND13

Open1.99VSET_ON15

Open0.57VDELTA_VY17

Open1.29VDET_LEVEL_SEL19

Open0.17VSLOPE_RATE_SEL21

Open0.114VY_ER_DN23

Open2.6VYO_SYS_DN25

Diode ModeRun LabelPin

Open17.04V+15V02

0.97V4.95V+5V04

0.97V4.95V+5V06

GndGndGND08

GndGndGND10

GndGndGND12

Open1.82VOC214

Open0VDATA16

Open1.44VOC118

Open1.45VSTB20

Open0.6VCLK22

Open024VSLOPE_OPT24

Open3.12VSET_UP26

Open0.14VY_ER)_UP27

Open0.11VY_SUS_UP29

There are no Stand-By voltages on this connector

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

97

November 2009 50PQ30 Plasma

Open1.1VY_PASS_TOP28

GndGndGND30

Control Board P101 to Z--

Control Board P101 to Z

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

P101 CONNECTOR “Control Board" to “Z-SUS" P100

SUS P100 Plug Information

SUS P100 Plug Information

Diode ModeRun LabelPin

GndGndGnd1

Open0.05VZ_ENABLE2

Open1.8VZ_Bias3

Open1.7VSLOPE_CTRL4

GndGndGnd5

Open0.3VZO_ER_Up6

98

Open0.4VZO_ER_Dn7

Open0.2VZO_SUS_Up8

Open0.8VZO_SUS_Dn9

GndGndGnd10

Open17V15V11

Open17V15V12

Pin 1 at the bottom

of the connector

November 2009 50PQ30 Plasma

Control Board Connector P161 and P162 to X--

Control Board Connector P161 and P162 to X

P161 and P162 Connectors from the "Control Board" to "X Drive Center”.

These pins may be covered with tape for transportation issues. (Tape can be removed).

Drive Boards

Drive Boards

P161 P162

Delivers only

RGB drive

signals

Note: In this set, both

Tape removed

Delivers only RGB

3.3V TP

3.3V created by IC221

drive signals and

3.3V

3.3V
TP

connectors go to the

Center X-Board

99

The rest of the pins are much too

close together for a safe test.

November 2009 50PQ30 Plasma

X BOARDS SECTION

X BOARDS SECTION

X Board Left, Center and Right (Commonly known as A--

X Board Left, Center and Right (Commonly known as A

BUS)

BUS)

The X Drive Boards deliver the Color drive signals to the Vertical Grids via TCPs.
The 50PQ30 has a Left, Center and a Right X-Drive board.
The Center X-Board has 6 connectors to a TCPs.
The Left and Right have 5 connections to TCPs.
Each TCP has 2 internal buffers.
Each buffer controls 128 vertical grids lines (256 per/TCP).

Generally speaking, there isn’t many active components on the X-Drive Boards.
So they are not very prone to failure.

In this section the X-Drive will be discussed and information given allowing the
service technician to determine if a failure has occurred in the X-Drive section.

X-BOARDS CONTROL THE VERTICAL ELECTRODES WHICH DETERMINE THE HORIZONTAL PIXEL COUNT.
TOTAL VERTICAL ELECTRODES 4096. TOTAL HORIZONTAL PIXELS 1365.

Total Buffer Count = 36

(TCPs = 16 @ 2 buffers per/TCP)

Total Output Pins = 4096

(128 per buffer X 36 total)

Total Pixels (Horizontal) 1365

(4096 / 3) Three cells per pixel (Red, Green and Blue)

100

November 2009 50PQ30 Plasma